440 lines
11 KiB
ArmAsm
440 lines
11 KiB
ArmAsm
/* Xtensa Exception (ie interrupt) Vectors & low-level handler code
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Core exception handler code is placed in the .vecbase section,
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which gets picked up specially in the linker script and placed
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at beginning of IRAM.
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The actual VecBase symbol should be the first thing in .vecbase
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(this is not strictly important as it gets set by symbol lookup not
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by hardcoded address, but having it at 0x40100000 means that the
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exception vectors have memorable offsets, which match the default
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Boot ROM vector offsets. So convenient for human understanding.
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Part of esp-open-rtos
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Original vector contents Copyright (C) 2014-2015 Espressif Systems
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Additions Copyright (C) Superhouse Automation Pty Ltd and Angus Gratton
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BSD Licensed as described in the file LICENSE
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*/
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#include "led_debug.s"
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/* Some UserException causes, see table Table 4–64 in ISA reference */
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#define CAUSE_SYSCALL 1
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#define CAUSE_LOADSTORE 3
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#define CAUSE_LVL1INT 4
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.text
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.section .vecbase.text, "x"
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.global VecBase
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.type VecBase, @function /* it's not really a function, but treat it like one */
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.org 0
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VecBase:
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/* IMPORTANT: exception vector literals will go here, but we
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can't have more than 4 otherwise we push DebugExceptionVector past
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offset 0x10 relative to VecBase. There should be ways to avoid this,
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and also keep the VecBase offsets easy to read, but this works for now.
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*/
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.literal_position
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.org 0x10
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DebugExceptionVector:
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wsr.excsave2 a0
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call0 sdk_user_fatal_exception_handler
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rfi 2
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.org 0x20
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NMIExceptionVector:
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wsr.excsave3 a0
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call0 CallNMIExceptionHandler
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rfi 3 /* CallNMIExceptionHandler should call rfi itself */
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.org 0x30
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KernelExceptionVector:
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break 1, 0
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call0 sdk_user_fatal_exception_handler
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rfe
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.org 0x50
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UserExceptionVector:
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wsr.excsave1 a0
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rsr.exccause a0
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beqi a0, CAUSE_SYSCALL, UserSyscallHandler
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beqi a0, CAUSE_LOADSTORE, UserExceptionLoadStoreHandler
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j UserExceptionHandler
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.org 0x70
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DoubleExceptionVector:
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break 1, 4
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rsr.exccause a0
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beqi a0, CAUSE_LOADSTORE, DoubleExceptionLoadStoreHandler
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call0 sdk_user_fatal_exception_handler
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/* Reset vector would go here at offset 0x80 but should be unused,
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as vecbase goes back to mask ROM vectors on reset */
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/***** end of exception vectors *****/
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.section .bss
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NMIHandlerStack: /* stack space for NMI handler */
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.skip 4*0x100
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NMIRegisterSaved: /* register space for saving NMI registers */
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.skip 4*(0x16 + 6)
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/* this symbol is _Pri_3_HandlerAddress in the RTOS SDK, appears totally
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unused (stays zero at all times) */
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.global NMIHandlerAddress
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NMIHandlerAddress:
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.long 0
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/* Save register relative to a0 */
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.macro SAVE_REG register, regnum
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s32i \register, a0, (0x20 + 4 * \regnum)
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.endm
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/* Load register relative to sp */
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.macro LOAD_REG register, regnum
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l32i \register, sp, (0x20 + 4 * \regnum)
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.endm
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.text
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.section .vecbase.text
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.literal_position
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.align 4
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.global call_user_start
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.type call_user_start, @function
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call_user_start:
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movi a2, VecBase
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wsr.vecbase a2
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call0 sdk_user_start
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.literal_position
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.align 16
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.type CallNMIExceptionHandler, @function
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CallNMIExceptionHandler:
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movi a0, NMIRegisterSaved
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SAVE_REG a2, 2
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movi a2, NMIHandlerAddress
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l32i a2, a2, 0
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SAVE_REG sp, 1
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SAVE_REG a3, 3
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xsr.excsave3 a2 /* excsave3 is now NMIHandlerAddress, a2 is former a0 */
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SAVE_REG a4, 4
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SAVE_REG a2, 0
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rsr.epc1 a3
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rsr.exccause a4
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SAVE_REG a3, -5
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SAVE_REG a4, -4
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rsr.excvaddr a3
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SAVE_REG a3, -3
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rsr.excsave1 a3
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SAVE_REG a3, -2
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SAVE_REG a5, 5
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SAVE_REG a6, 6
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SAVE_REG a7, 7
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SAVE_REG a8, 8
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SAVE_REG a9, 9
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SAVE_REG a10, 10
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SAVE_REG a11, 11
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SAVE_REG a12, 12
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SAVE_REG a13, 13
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SAVE_REG a14, 14
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SAVE_REG a15, 15
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movi sp, NMIRegisterSaved /* also top of NMIHandlerStack */
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movi a0, 0
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movi a2, 0x23 /* argument for handler */
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wsr.ps a2
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rsync
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rsr.sar a14
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s32i a14, sp, 0 /* this is also NMIRegisterSaved+0 */
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call0 sdk_wDev_ProcessFiq
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l32i a15, sp, 0
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wsr.sar a15
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movi a2, 0x33
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wsr.ps a2
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rsync
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LOAD_REG a4, 4
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LOAD_REG a5, 5
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LOAD_REG a6, 6
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LOAD_REG a7, 7
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LOAD_REG a8, 8
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LOAD_REG a9, 9
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LOAD_REG a10, 10
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LOAD_REG a11, 11
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LOAD_REG a12, 12
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LOAD_REG a13, 13
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LOAD_REG a14, 14
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LOAD_REG a15, 15
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LOAD_REG a2, -5
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LOAD_REG a3, -4
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wsr.epc1 a2
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wsr.exccause a3
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LOAD_REG a2, -3
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LOAD_REG a3, -2
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wsr.excvaddr a2
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wsr.excsave1 a3
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LOAD_REG a0, 0
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/* set dport nmi status bit 0 (wDev_ProcessFiq clears & verifies this bit stays cleared,
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see http://esp8266-re.foogod.com/wiki/WDev_ProcessFiq_%28IoT_RTOS_SDK_0.9.9%29) */
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movi a2, 0x3ff00000
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movi a3, 0x1
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s32i a3, a2, 0
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LOAD_REG a2, 2
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LOAD_REG a3, 3
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LOAD_REG a1, 1
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rfi 0x3
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.type UserExceptionHandler, @function
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UserExceptionHandler:
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mov a0, sp /* a0 was saved in UserExceptionVector */
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addi sp, sp, -0x50
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s32i a0, sp, 0x10
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rsr.ps a0
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s32i a0, sp, 0x08
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rsr.epc1 a0
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s32i a0, sp, 0x04
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rsr.excsave1 a0
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s32i a0, sp, 0x0c
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movi a0, _xt_user_exit
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s32i a0, sp, 0x0
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call0 sdk__xt_int_enter
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movi a0, 0x23
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wsr.ps a0
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rsync
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rsr.exccause a2
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beqi a2, CAUSE_LVL1INT, UserHandleInterrupt
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/* Any UserException cause other than level 1 interrupt triggers a panic */
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UserFailOtherExceptionCause:
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break 1, 1
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call0 sdk_user_fatal_exception_handler
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UserHandleInterrupt:
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rsil a0, 1
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rsr.intenable a2
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rsr.interrupt a3
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movi a4, 0x3fff
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and a2, a2, a3
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and a2, a2, a4 /* a2 = 0x3FFF & INTENABLE & INTERRUPT */
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UserHandleTimer:
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movi a3, 0xffbf
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and a3, a2, a3 /* a3 = a2 & 0xFFBF, ie remove 0x40 from a2 if set */
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bnez a3, UserTimerDone /* bits other than 0x40 are set */
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movi a3, 0x40
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sub a12, a2, a3 /* a12 - a2 - 0x40 - I think a12 _must_ be zero here? */
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call0 sdk__xt_timer_int /* tick timer interrupt */
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mov a2, a12 /* restore a2 from a12, ie zero */
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beqz a2, UserIntDone
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UserTimerDone:
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call0 _xt_isr_handler
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bnez a2, UserHandleTimer
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UserIntDone:
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beqz a2, UserIntExit
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break 1, 1 /* non-zero remnant in a2 means fail */
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call0 sdk_user_fatal_exception_handler
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UserIntExit:
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call0 sdk__xt_int_exit /* calls rfi */
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/* As far as I can tell, the syscall handler is basically a no-op */
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UserSyscallHandler:
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addi sp, sp, -0x10
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s32i a2, sp, 0x08
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s32i a3, sp, 0x0c
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rsr.epc1 a2
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addi a3, a2, 0x3
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wsr.epc1 a3
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l32i a2, sp, 0x8
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l32i a3, sp, 0xc
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addi sp, sp, 0x10
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movi a0, 0x7f
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movnez a2, a0, a2
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rsr.excsave1 a0
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rfe
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.text
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.section .vecbase.text
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.literal_position
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.align 4
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/* "Fix" LoadStoreException exceptions that are l8/l16 from an Instruction region,
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DoubleException exception variant (ie load happened in a level1 exception handler). */
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DoubleExceptionLoadStoreHandler:
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addi sp, sp, -0x18
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s32i a2, sp, 0x08
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rsr.epc2 a2
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j InnerLoadStoreExceptionHandler
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.text
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.section .vecbase.text
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.literal_position
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.align 4
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/* "Fix" LoadStoreException exceptions that are l8/l16 from an Instruction region,
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normal exception variant. */
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UserExceptionLoadStoreHandler:
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addi sp, sp, -0x18
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s32i a2, sp, 0x08
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rsr.epc1 a2
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/* Inner UserLoadStoreExceptionHandler handlers. Works for both level1 & level 2 interrupt level.
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*
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* Called from level-specific handler above which sets up stack and loads epcX into a2.
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*/
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InnerLoadStoreExceptionHandler:
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s32i a3, sp, 0x0c
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s32i a4, sp, 0x10
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s32i a5, sp, 0x14
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rsr.sar a0 // save sar in a0
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/* Examine the instruction we failed to execute (in a2) */
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ssa8l a2 // sar is now correct shift for aligned read
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movi a3, ~3
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and a2, a2, a3 // a2 now 4-byte aligned address of instruction
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l32i a3, a2, 0
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l32i a4, a2, 4
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src a2, a4, a3 // a2 now instruction that failed
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/* Check if a2 matches l8ui, l16ui or l16si opcodes */
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movi a3, 0x00F00F /* opcode mask */
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and a3, a2, a3
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beqi a3, 0x000002, .Lcan_fix_8bit /* l8ui opcode after masking */
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movi a4, 0x001002 /* l16ui opcode after masking */
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beq a3, a4, .Lcan_fix_16bit
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movi a4, 0x009002 /* l16si opcode after masking */
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beq a3, a4, .Lcan_fix_16bit_signed
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.Lcant_fix:
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/* not an opcode we can try to fix, so bomb out
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TODO: the exception dump will have some wrong values in it */
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call0 sdk_user_fatal_exception_handler
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.Lcan_fix_16bit_signed:
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movi a5, 0x7FFF
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j .Lcan_fix
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.Lcan_fix_16bit:
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movi a5, 0xFFFF
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j .Lcan_fix
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.Lcan_fix_8bit:
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movi a5, 0xFF
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.Lcan_fix:
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/* verified an 8- or 16-bit read
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a2 holds instruction, a5 holds mask to apply to read value
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*/
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rsr.excvaddr a3 // read faulting address
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ssa8l a3 /* sar is now shift to extract a3's byte */
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movi a4, ~3
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and a3, a3, a4 /* a3 now word aligned read address */
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l32i a3, a3, 0 /* perform the actual read */
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srl a3, a3 /* shift right correct distance */
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and a4, a3, a5 /* mask off bits we need for an l8/l16 */
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bbci a5, 14, .Lafter_extend_sign /* 8-bit, no sign extension */
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bbsi a5, 15, .Lafter_extend_sign /* 16-bit unsigned, no sign extension */
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bbci a3, 15, .Lafter_extend_sign /* sign bit not set, no sign extension */
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movi a3, (1<<31)
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or a4, a3, a4 /* set 32-bit sign bit */
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.Lafter_extend_sign:
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/* a2 holds instruction, a4 holds the correctly read value */
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extui a2, a2, 4, 4 /* a2 now destination register 0-15 */
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/* test if a4 needs to be written directly to a register (ie not a working register) */
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bgei a2, 6, .Lwrite_value_direct_reg
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/* test if a4 needs to be written to a0 */
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beqz a2, .Lwrite_value_a0_reg
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/* otherwise, a4 can be written to a saved working register 'slot' on the stack */
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addx4 a5, a2, sp
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s32i a4, a5, 0
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.Lafter_write_value:
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/* test PS.INTLEVEL (1=User, 2=Double) to see which interrupt level we restore from
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*/
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rsr.ps a2
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bbsi a2, 1, .Lincrement_PC_intlevel2
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.Lincrement_PC_intlevel1:
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rsr.epc1 a2
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addi a3, a2, 0x3
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wsr.epc1 a3
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wsr.sar a0 // restore saved sar
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rsr.excsave1 a0 // restore a0 saved in exception vector
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.Lafter_increment_PC:
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// Restore registers
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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l32i a5, sp, 0x14
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addi sp, sp, 0x18
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rfe
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.Lincrement_PC_intlevel2:
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rsr.epc2 a2
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addi a3, a2, 0x3
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wsr.epc2 a3
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wsr.sar a0 // restore saved sar
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rsr.excsave2 a0 // restore a0 saved in exception vector
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j .Lafter_increment_PC
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.Lextend_sign: /* apply 16-bit sign extension if necessary
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a3 holds raw value, a4 holds masked */
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bbci a3, 15, .Lafter_extend_sign /* sign bit not set, do nothing */
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movi a3, (1<<31)
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or a4, a3, a4 /* set sign bit */
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j .Lafter_extend_sign
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.Lwrite_value_direct_reg:
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/* Directly update register index a2, in range 6-15, using value in a4 */
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addi a2, a2, -6
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slli a2, a2, 3 /* offset from a6, x8 */
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movi a3, .Ldirect_reg_jumptable
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add a2, a2, a3
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jx a2
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.align 8
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.Ldirect_reg_jumptable:
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mov a6, a4
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j .Lafter_write_value
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.align 8
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mov a7, a4
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j .Lafter_write_value
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.align 8
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mov a8, a4
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j .Lafter_write_value
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.align 8
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mov a9, a4
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j .Lafter_write_value
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.align 8
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mov a10, a4
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j .Lafter_write_value
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.align 8
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mov a11, a4
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j .Lafter_write_value
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.align 8
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mov a12, a4
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j .Lafter_write_value
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.align 8
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mov a13, a4
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j .Lafter_write_value
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.align 8
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mov a14, a4
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j .Lafter_write_value
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.align 8
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mov a15, a4
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j .Lafter_write_value
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.Lwrite_value_a0_reg:
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/* a0 is saved in excsave1,so just update this with value
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TODO: This won't work with interrupt level 2
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*/
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wsr.excsave1 a4
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j .Lafter_write_value
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/* End of InnerUserLoadStoreExceptionHandler */
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.global _xt_user_exit
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.type _xt_user_exit, @function
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_xt_user_exit:
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l32i a0, sp, 0x8
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wsr.ps a0
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l32i a0, sp, 0x4
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wsr.epc1 a0
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l32i a0, sp, 0xc
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l32i sp, sp, 0x10
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rsync
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rfe
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