244 lines
9.2 KiB
C
244 lines
9.2 KiB
C
/** esp/spi.h
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*
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* Configuration of SPI registers.
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*
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* Part of esp-open-rtos
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* Copyright (C) 2015 Superhouse Automation Pty Ltd
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* BSD Licensed as described in the file LICENSE
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*/
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#ifndef _SPI_REGS_H
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#define _SPI_REGS_H
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#include "esp/types.h"
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#include "common_macros.h"
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/* Register definitions for the SPI peripherals on the ESP8266.
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*
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* There are twp SPI devices built into the ESP8266:
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* SPI(0) is at 0x60000200
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* SPI(1) is at 0x60000100
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* (note that the device number order is reversed in memory)
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*
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* Each device is allocated a block of 64 32-bit registers (256 bytes of
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* address space) to communicate with application code.
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*/
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#define SPI_BASE 0x60000200
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#define SPI(i) (*(struct SPI_REGS *)(0x60000200 - (i)*0x100))
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#define SPI0_BASE SPI_BASE
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#define SPI1_BASE (SPI_BASE - 0x100)
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struct SPI_REGS {
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uint32_t volatile CMD; // 0x00
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uint32_t volatile ADDR; // 0x04
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uint32_t volatile CTRL0; // 0x08
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uint32_t volatile CTRL1; // 0x0c
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uint32_t volatile RSTATUS; // 0x10
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uint32_t volatile CTRL2; // 0x14
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uint32_t volatile CLOCK; // 0x18
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uint32_t volatile USER0; // 0x1c
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uint32_t volatile USER1; // 0x20
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uint32_t volatile USER2; // 0x24
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uint32_t volatile WSTATUS; // 0x28
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uint32_t volatile PIN; // 0x2c
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uint32_t volatile SLAVE0; // 0x30
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uint32_t volatile SLAVE1; // 0x34
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uint32_t volatile SLAVE2; // 0x38
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uint32_t volatile SLAVE3; // 0x3c
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uint32_t volatile W0; // 0x40
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uint32_t volatile W1; // 0x44
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uint32_t volatile W2; // 0x48
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uint32_t volatile W3; // 0x4c
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uint32_t volatile W4; // 0x50
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uint32_t volatile W5; // 0x54
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uint32_t volatile W6; // 0x58
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uint32_t volatile W7; // 0x5c
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uint32_t volatile W8; // 0x60
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uint32_t volatile W9; // 0x64
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uint32_t volatile W10; // 0x68
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uint32_t volatile W11; // 0x6c
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uint32_t volatile W12; // 0x70
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uint32_t volatile W13; // 0x74
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uint32_t volatile W14; // 0x78
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uint32_t volatile W15; // 0x7c
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uint32_t volatile _unused[28]; // 0x80 - 0xec
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uint32_t volatile EXT0; // 0xf0
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uint32_t volatile EXT1; // 0xf4
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uint32_t volatile EXT2; // 0xf8
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uint32_t volatile EXT3; // 0xfc
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};
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_Static_assert(sizeof(struct SPI_REGS) == 0x100, "SPI_REGS is the wrong size");
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/* Details for CMD register */
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#define SPI_CMD_USR BIT(18)
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/* Details for CTRL0 register */
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#define SPI_CTRL0_WR_BIT_ORDER BIT(26)
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#define SPI_CTRL0_RD_BIT_ORDER BIT(25)
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#define SPI_CTRL0_QIO_MODE BIT(24)
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#define SPI_CTRL0_DIO_MODE BIT(23)
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#define SPI_CTRL0_QOUT_MODE BIT(20)
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#define SPI_CTRL0_DOUT_MODE BIT(14)
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#define SPI_CTRL0_FASTRD_MODE BIT(13)
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#define SPI_CTRL0_CLOCK_EQU_SYS_CLOCK BIT(12)
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#define SPI_CTRL0_CLOCK_NUM_M 0x0000000F
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#define SPI_CTRL0_CLOCK_NUM_S 8
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#define SPI_CTRL0_CLOCK_HIGH_M 0x0000000F
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#define SPI_CTRL0_CLOCK_HIGH_S 4
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#define SPI_CTRL0_CLOCK_LOW_M 0x0000000F
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#define SPI_CTRL0_CLOCK_LOW_S 0
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/* Mask for the CLOCK_NUM/CLOCK_HIGH/CLOCK_LOW combined, in case one wants
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* to set them all as a single value.
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*/
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#define SPI_CTRL0_CLOCK_M 0x00000FFF
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#define SPI_CTRL0_CLOCK_S 0
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/* Details for CTRL2 register */
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#define SPI_CTRL2_CS_DELAY_NUM_M 0x0000000F
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#define SPI_CTRL2_CS_DELAY_NUM_S 28
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#define SPI_CTRL2_CS_DELAY_MODE_M 0x00000003
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#define SPI_CTRL2_CS_DELAY_MODE_S 26
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#define SPI_CTRL2_MOSI_DELAY_NUM_M 0x00000007
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#define SPI_CTRL2_MOSI_DELAY_NUM_S 23
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#define SPI_CTRL2_MOSI_DELAY_MODE_M 0x00000003
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#define SPI_CTRL2_MOSI_DELAY_MODE_S 21
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#define SPI_CTRL2_MISO_DELAY_NUM_M 0x00000007
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#define SPI_CTRL2_MISO_DELAY_NUM_S 18
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#define SPI_CTRL2_MISO_DELAY_MODE_M 0x00000003
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#define SPI_CTRL2_MISO_DELAY_MODE_S 16
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/* Details for CLOCK register */
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#define SPI_CLOCK_EQU_SYS_CLOCK BIT(31)
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#define SPI_CLOCK_DIV_PRE_M 0x00001FFF
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#define SPI_CLOCK_DIV_PRE_S 18
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#define SPI_CLOCK_COUNT_NUM_M 0x0000003F
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#define SPI_CLOCK_COUNT_NUM_S 12
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#define SPI_CLOCK_COUNT_HIGH_M 0x0000003F
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#define SPI_CLOCK_COUNT_HIGH_S 6
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#define SPI_CLOCK_COUNT_LOW_M 0x0000003F
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#define SPI_CLOCK_COUNT_LOW_S 0
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/* Mask for the COUNT_NUM/COUNT_HIGH/COUNT_LOW combined, in case one wants
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* to set them all as a single value.
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*/
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#define SPI_CTRL0_COUNT_M 0x0003FFFF
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#define SPI_CTRL0_COUNT_S 0
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/* Details for USER0 register */
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#define SPI_USER0_COMMAND BIT(31)
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#define SPI_USER0_ADDR BIT(30)
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#define SPI_USER0_DUMMY BIT(29)
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#define SPI_USER0_MISO BIT(28)
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#define SPI_USER0_MOSI BIT(27)
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#define SPI_USER0_MOSI_HIGHPART BIT(25)
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#define SPI_USER0_MISO_HIGHPART BIT(24)
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#define SPI_USER0_SIO BIT(16)
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#define SPI_USER0_FWRITE_QIO BIT(15)
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#define SPI_USER0_FWRITE_DIO BIT(14)
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#define SPI_USER0_FWRITE_QUAD BIT(13)
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#define SPI_USER0_FWRITE_DUAL BIT(12)
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#define SPI_USER0_WR_BYTE_ORDER BIT(11)
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#define SPI_USER0_RD_BYTE_ORDER BIT(10)
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#define SPI_USER0_CLOCK_OUT_EDGE BIT(7)
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#define SPI_USER0_CLOCK_IN_EDGE BIT(6)
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#define SPI_USER0_CS_SETUP BIT(5)
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#define SPI_USER0_CS_HOLD BIT(4)
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#define SPI_USER0_FLASH_MODE BIT(2)
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/* Details for USER1 register */
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#define SPI_USER1_ADDR_BITLEN_M 0x0000003F
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#define SPI_USER1_ADDR_BITLEN_S 26
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#define SPI_USER1_MOSI_BITLEN_M 0x000001FF
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#define SPI_USER1_MOSI_BITLEN_S 17
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#define SPI_USER1_MISO_BITLEN_M 0x000001FF
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#define SPI_USER1_MISO_BITLEN_S 8
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#define SPI_USER1_DUMMY_CYCLELEN_M 0x000000FF
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#define SPI_USER1_DUMMY_CYCLELEN_S 0
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/* Details for USER2 register */
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#define SPI_USER2_COMMAND_BITLEN_M 0x0000000F
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#define SPI_USER2_COMMAND_BITLEN_S 28
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#define SPI_USER2_COMMAND_VALUE_M 0x0000FFFF
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#define SPI_USER2_COMMAND_VALUE_S 0
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/* Details for PIN register */
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#define SPI_PIN_CS2_DISABLE BIT(2)
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#define SPI_PIN_CS1_DISABLE BIT(1)
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#define SPI_PIN_CS0_DISABLE BIT(0)
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/* Details for SLAVE0 register */
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#define SPI_SLAVE0_SYNC_RESET BIT(31)
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#define SPI_SLAVE0_MODE BIT(30)
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#define SPI_SLAVE0_WR_RD_BUF_EN BIT(29)
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#define SPI_SLAVE0_WR_RD_STA_EN BIT(28)
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#define SPI_SLAVE0_CMD_DEFINE BIT(27)
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#define SPI_SLAVE0_TRANS_COUNT_M 0x0000000F
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#define SPI_SLAVE0_TRANS_COUNT_S 23
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#define SPI_SLAVE0_TRANS_DONE_EN BIT(9)
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#define SPI_SLAVE0_WR_STA_DONE_EN BIT(8)
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#define SPI_SLAVE0_RD_STA_DONE_EN BIT(7)
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#define SPI_SLAVE0_WR_BUF_DONE_EN BIT(6)
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#define SPI_SLAVE0_RD_BUF_DONE_EN BIT(5)
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#define SPI_SLAVE0_INT_EN_M 0x0000001f
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#define SPI_SLAVE0_INT_EN_S 5
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#define SPI_SLAVE0_TRANS_DONE BIT(4)
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#define SPI_SLAVE0_WR_STA_DONE BIT(3)
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#define SPI_SLAVE0_RD_STA_DONE BIT(2)
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#define SPI_SLAVE0_WR_BUF_DONE BIT(1)
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#define SPI_SLAVE0_RD_BUF_DONE BIT(0)
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/* Details for SLAVE1 register */
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#define SPI_SLAVE1_STATUS_BITLEN_M 0x0000001F
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#define SPI_SLAVE1_STATUS_BITLEN_S 27
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#define SPI_SLAVE1_BUF_BITLEN_M 0x000001FF
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#define SPI_SLAVE1_BUF_BITLEN_S 16
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#define SPI_SLAVE1_RD_ADDR_BITLEN_M 0x0000003F
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#define SPI_SLAVE1_RD_ADDR_BITLEN_S 10
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#define SPI_SLAVE1_WR_ADDR_BITLEN_M 0x0000003F
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#define SPI_SLAVE1_WR_ADDR_BITLEN_S 4
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#define SPI_SLAVE1_WRSTA_DUMMY_ENABLE BIT(3)
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#define SPI_SLAVE1_RDSTA_DUMMY_ENABLE BIT(2)
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#define SPI_SLAVE1_WRBUF_DUMMY_ENABLE BIT(1)
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#define SPI_SLAVE1_RDBUF_DUMMY_ENABLE BIT(0)
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/* Details for SLAVE2 register */
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#define SPI_SLAVE2_WRBUF_DUMMY_CYCLELEN_M 0x000000FF
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#define SPI_SLAVE2_WRBUF_DUMMY_CYCLELEN_S 24
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#define SPI_SLAVE2_RDBUF_DUMMY_CYCLELEN_M 0x000000FF
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#define SPI_SLAVE2_RDBUF_DUMMY_CYCLELEN_S 16
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#define SPI_SLAVE2_WRSTR_DUMMY_CYCLELEN_M 0x000000FF
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#define SPI_SLAVE2_WRSTR_DUMMY_CYCLELEN_S 8
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#define SPI_SLAVE2_RDSTR_DUMMY_CYCLELEN_M 0x000000FF
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#define SPI_SLAVE2_RDSTR_DUMMY_CYCLELEN_S 0
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/* Details for SLAVE3 register */
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#define SPI_SLAVE3_WRSTA_CMD_VALUE_M 0x000000FF
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#define SPI_SLAVE3_WRSTA_CMD_VALUE_S 24
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#define SPI_SLAVE3_RDSTA_CMD_VALUE_M 0x000000FF
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#define SPI_SLAVE3_RDSTA_CMD_VALUE_S 16
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#define SPI_SLAVE3_WRBUF_CMD_VALUE_M 0x000000FF
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#define SPI_SLAVE3_WRBUF_CMD_VALUE_S 8
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#define SPI_SLAVE3_RDBUF_CMD_VALUE_M 0x000000FF
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#define SPI_SLAVE3_RDBUF_CMD_VALUE_S 0
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/* Details for EXT3 register */
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#define SPI_EXT3_INT_HOLD_ENABLE_M 0x00000003
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#define SPI_EXT3_INT_HOLD_ENABLE_S 0
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#endif /* _SPI_REGS_H */
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