153 lines
4.3 KiB
C
153 lines
4.3 KiB
C
/* esp/registers.h
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*
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* ESP8266 register addresses and bitmasks.
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*
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* Not compatible with ESP SDK register access code.
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*
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* Based on register map documentation:
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* https://github.com/esp8266/esp8266-wiki/wiki/Memory-Map
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*
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* Part of esp-open-rtos
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* Copyright (C) 2015 Superhouse Automation Pty Ltd
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* BSD Licensed as described in the file LICENSE
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*/
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#ifndef _ESP_REGISTERS
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#define _ESP_REGISTERS
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#include "common_macros.h"
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typedef volatile uint32_t *esp_reg_t;
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/* Internal macro, only defined in header body */
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#define _REG(BASE, OFFSET) (*(esp_reg_t)((BASE)+(OFFSET)))
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/* Register base addresses
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You shouldn't need to use these directly.
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*/
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#define MMIO_BASE 0x60000000
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#define UART0_BASE (MMIO_BASE + 0)
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#define SPI1_BASE (MMIO_BASE + 0x0100)
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#define SPI_BASE (MMIO_BASE + 0x0200)
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#define GPIO0_BASE (MMIO_BASE + 0x0300)
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#define TIMER_BASE (MMIO_BASE + 0x0600)
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#define RTC_BASE (MMIO_BASE + 0x0700)
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#define IOMUX_BASE (MMIO_BASE + 0x0800)
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#define WDT_BASE (MMIO_BASE + 0x0900)
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#define I2C_BASE (MMIO_BASE + 0x0d00)
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#define UART1_BASE (MMIO_BASE + 0x0F00)
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#define RTCB_BASE (MMIO_BASE + 0x1000)
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#define RTCS_BASE (MMIO_BASE + 0x1100)
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#define RTCU_BASE (MMIO_BASE + 0x1200)
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/*
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* iomux registers, apply to pin functions.
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*
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* Note that IOMUX register order is _not_ the same as GPIO order. See
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* esp_iomux.h for programmer-friendly IOMUX configuration options
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*/
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#define IOMUX_REG(X) _REG(IOMUX_BASE,0x04+4*X)
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#define IOMUX_OE BIT(0) /* iomux Output enable bit */
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#define IOMUX_OE_SLEEP BIT(1) /* iomux Output during sleep bit */
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#define IOMUX_PD BIT(6) /* iomux soft pulldown bit */
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#define IOMUX_PD_SLEEP BIT(2) /* iomux soft pulldown during sleep bit */
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#define IOMUX_PU BIT(7) /* iomux soft pullup bit */
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#define IOMUX_PU_SLEEP BIT(3) /* iomux soft pullup during sleep bit */
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#define IOMUX_FLAG_WAKE_MASK (IOMUX_OE|IOMUX_PD|IOMUX_PU)
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#define IOMUX_FLAG_SLEEP_MASK (IOMUX_OE_SLEEP|IOMUX_PD_SLEEP|IOMUX_PU_SLEEP)
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#define IOMUX_FLAG_MASK (IOMUX_FLAG_WAKE_MASK|IOMUX_FLAG_SLEEP_MASK)
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#define IOMUX_FUNC_MASK (BIT(4)|BIT(5)|BIT(12))
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/* All pins have FUNC_A on reset (unconfirmed) */
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#define IOMUX_FUNC_A (0)
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#define IOMUX_FUNC_B BIT(4)
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#define IOMUX_FUNC_C BIT(5)
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#define IOMUX_FUNC_D BIT(4)|BIT(5)
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#define IOMUX_FUNC_E BIT(12)
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/*
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* Based on descriptions by mamalala at https://github.com/esp8266/esp8266-wiki/wiki/gpio-registers
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*/
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/** GPIO OUTPUT registers GPIO_OUT_REG, GPIO_OUT_SET, GPIO_OUT_CLEAR
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*
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* Registers for pin outputs.
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*
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* _SET and _CLEAR write-only registers set and clear bits in _REG,
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* respectively.
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*
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* ie
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* GPIO_OUT_REG |= BIT(3);
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* and
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* GPIO_OUT_SET = BIT(3);
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*
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* ... are equivalent, but latter uses less CPU cycles.
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*/
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#define GPIO_OUT_REG _REG(GPIO0_BASE, 0x00)
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#define GPIO_OUT_SET _REG(GPIO0_BASE, 0x04)
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#define GPIO_OUT_CLEAR _REG(GPIO0_BASE, 0x08)
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/* GPIO DIR registers GPIO_DIR_REG, GPIO_DIR_SET, GPIO_DIR_CLEAR
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*
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* Set bit in DIR register for output pins. Writing to _SET and _CLEAR
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* registers set and clear bits in _REG, respectively.
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*/
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#define GPIO_DIR_REG _REG(GPIO0_BASE, 0x0C)
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#define GPIO_DIR_SET _REG(GPIO0_BASE, 0x10)
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#define GPIO_DIR_CLEAR _REG(GPIO0_BASE, 0x14)
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/* GPIO IN register GPIO_IN_REG
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*
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* Reads current input values.
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*/
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#define GPIO_IN_REG _REG(GPIO0_BASE, 0x18)
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/* GPIO interrupt 'status' flag
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Bit set if interrupt has fired (see below for interrupt config
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registers.
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Lower 16 bits only are used.
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*/
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#define GPIO_STATUS_REG _REG(GPIO0_BASE,0x1c)
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#define GPIO_STATUS_SET _REG(GPIO0_BASE,0x20)
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#define GPIO_STATUS_CLEAR _REG(GPIO0_BASE,0x24)
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#define GPIO_STATUS_MASK 0x0000FFFFL
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/* GPIO pin control registers for GPIOs 0-15
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*
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*/
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#define GPIO_CTRL_REG(GPNUM) _REG(GPIO0_BASE, 0x28+(GPNUM*4))
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#define GPIO_SOURCE_GPIO 0
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#define GPIO_SOURCE_DAC BIT(0) /* "Sigma-Delta" */
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#define GPIO_SOURCE_MASK BIT(0
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#define GPIO_DRIVE_PUSH_PULL 0
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#define GPIO_DRIVE_OPEN_DRAIN BIT(2)
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#define GPIO_DRIVE_MASK BIT(2)
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#define GPIO_INT_NONE 0
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#define GPIO_INT_RISING BIT(7)
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#define GPIO_INT_FALLING BIT(8)
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#define GPIO_INT_CHANGE (BIT(7)|BIT(8))
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#define GPIO_INT_LOW BIT(9)
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#define GPIO_INT_HIGH (BIT(7)|BIT(9))
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#define GPIO_INT_MASK (BIT(7)|BIT(8)|BIT(9))
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/* WDT register(s)
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Not fully understood yet. Writing 0 here disables wdt.
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See ROM functions esp_wdt_xxx
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*/
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#define WDT_CTRL _REG(WDT_BASE, 0x00)
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#endif
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