532 lines
17 KiB
ArmAsm
532 lines
17 KiB
ArmAsm
/* Xtensa Exception (ie interrupt) Vectors & low-level handler code
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*
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* Core exception handler code is placed in the .vecbase section, which gets
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* picked up specially in the linker script and placed at beginning of IRAM.
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*
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* The actual VecBase symbol should be the first thing in .vecbase (this is not
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* strictly important as it gets set by symbol lookup not by hardcoded address,
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* but having it at 0x40100000 means that the exception vectors have memorable
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* offsets, which match the default Boot ROM vector offsets. So convenient for
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* human understanding.
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*
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* Part of esp-open-rtos
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* Original vector contents Copyright (C) 2014-2015 Espressif Systems
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* Additions Copyright (C) Superhouse Automation Pty Ltd and Angus Gratton
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* BSD Licensed as described in the file LICENSE
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*/
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#include "led_debug.s"
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/* Some UserException causes, see table Table 4–64 in ISA reference */
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#define CAUSE_SYSCALL 1
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#define CAUSE_LOADSTORE 3
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#define CAUSE_LVL1INT 4
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.section .bss
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/* Stack space for NMI handler
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NMI handler stack high water mark measured at 0x134 bytes. Any use
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of the NMI timer callback will add stack overhead as well.
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The NMI handler does a basic check for stack overflow
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*/
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.balign 16
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NMIHandlerStack:
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.skip 0x200
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.NMIHandlerStackTop:
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.balign 16
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LoadStoreErrorHandlerStack:
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.word 0 # a0
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.word 0 # (unused)
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.word 0 # a2
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.word 0 # a3
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.word 0 # a4
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/***************************** Exception Vectors *****************************/
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.section .vecbase.text, "x"
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/* Note: Exception vectors must be aligned on a 256-byte (0x100) boundary or
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* they will not function properly. (This is taken care of in the linker
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* script by ensuring .vecbase.text is aligned properly, and putting VecBase
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* right at the beginning of .vecbase.text) */
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.org 0
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VecBase:
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.global VecBase
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/* IMPORTANT: exception vector literals will go here, but we
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* can't have more than 4 otherwise we push DebugExceptionVector past
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* offset 0x10 relative to VecBase. There should be ways to avoid this,
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* and also keep the VecBase offsets easy to read, but this works for
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* now. */
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.literal_position
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.org VecBase + 0x10
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DebugExceptionVector:
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.type DebugExceptionVector, @function
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wsr a0, excsave2
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call0 sdk_user_fatal_exception_handler
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rfi 2
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.org VecBase + 0x20
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NMIExceptionVector:
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.type NMIExceptionVector, @function
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j NMIExceptionHandler
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.org VecBase + 0x30
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KernelExceptionVector:
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.type KernelExceptionVector, @function
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break 1, 0
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call0 sdk_user_fatal_exception_handler
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rfe
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.org VecBase + 0x50
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UserExceptionVector:
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.type UserExceptionVector, @function
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wsr a1, excsave1
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rsr a1, exccause
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beqi a1, CAUSE_LOADSTORE, LoadStoreErrorHandler
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j UserExceptionHandler
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.org VecBase + 0x70
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DoubleExceptionVector:
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.type DoubleExceptionVector, @function
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break 1, 4
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call0 sdk_user_fatal_exception_handler
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/* Reset vector at offset 0x80 is unused, as vecbase gets reset to mask ROM
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* vectors on chip reset. */
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/*************************** LoadStoreError Handler **************************/
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.section .vecbase.text, "x"
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/* Xtensa "Load/Store Exception" handler:
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* Completes L8/L16 load instructions from Instruction address space, for which
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* the architecture only supports 32-bit reads.
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*
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* Called from UserExceptionVector if EXCCAUSE is LoadStoreErrorCause
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*
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* (Fast path (no branches) is for L8UI)
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*/
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.literal_position
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.balign 4
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LoadStoreErrorHandler:
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.type LoadStoreErrorHandler, @function
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/* Registers are saved in the address corresponding to their register
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* number times 4. This allows a quick and easy mapping later on when
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* needing to store the value to a particular register number. */
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movi sp, LoadStoreErrorHandlerStack
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s32i a0, sp, 0
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s32i a2, sp, 0x08
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s32i a3, sp, 0x0c
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s32i a4, sp, 0x10
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rsr a0, sar # Save SAR in a0 to restore later
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/* Examine the opcode which generated the exception */
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/* Note: Instructions are in this order to avoid pipeline stalls. */
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rsr a2, epc1
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movi a3, ~3
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ssa8l a2 # sar is now correct shift for aligned read
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and a2, a2, a3 # a2 now 4-byte aligned address of instruction
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l32i a4, a2, 0
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l32i a2, a2, 4
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movi a3, 0x00700F # opcode mask for l8ui/l16si/l16ui
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src a2, a2, a4 # a2 now instruction that failed
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and a3, a2, a3 # a3 is masked instruction
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bnei a3, 0x000002, .LSE_check_l16
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/* Note: At this point, opcode could technically be one of two things:
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* xx0xx2 (L8UI)
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* xx8xx2 (Reserved (invalid) opcode)
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* It is assumed that we'll never get to this point from an illegal
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* opcode, so we don't bother to check for that case and presume this
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* is always an L8UI. */
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movi a4, ~3
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rsr a3, excvaddr # read faulting address
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and a4, a3, a4 # a4 now word aligned read address
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l32i a4, a4, 0 # perform the actual read
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ssa8l a3 # sar is now shift to extract a3's byte
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srl a3, a4 # shift right correct distance
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extui a4, a3, 0, 8 # mask off bits we need for an l8
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.LSE_post_fetch:
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/* We jump back here after either the L8UI or the L16*I routines do the
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* necessary work to read the value from memory.
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* At this point, a2 holds the faulting instruction and a4 holds the
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* correctly read value.
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* Restore original SAR value (saved in a0) and update EPC so we'll
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* return back to the instruction following the one we just emulated */
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/* Note: Instructions are in this order to avoid pipeline stalls */
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rsr a3, epc1
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wsr a0, sar
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addi a3, a3, 0x3
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wsr a3, epc1
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/* Stupid opcode tricks: The jumptable we use later on needs 16 bytes
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* per entry (so we can avoid a second jump by just doing a RFE inside
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* each entry). Unfortunately, however, Xtensa doesn't have an addx16
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* operation to make that easy for us. Luckily, all of the faulting
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* opcodes we're processing are guaranteed to have bit 3 be zero, which
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* means if we just shift the register bits of the opcode down by 3
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* instead of 4, we will get the register number multiplied by 2. This
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* combined with an addx8 will give us an effective addx16 without
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* needing any extra shift operations. */
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extui a2, a2, 3, 5 # a2 is now destination register 0-15 times 2
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bgei a2, 10, .LSE_assign_reg # a5..a15 use jumptable
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beqi a2, 2, .LSE_assign_a1 # a1 uses a special routine
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/* We're storing into a0 or a2..a4, which are all saved in our "stack"
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* area. Calculate the correct address and stick the value in there,
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* then just do our normal restore and RFE (no jumps required, which
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* actually makes a0..a4 substantially faster). */
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addx2 a2, a2, sp
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s32i a4, a2, 0
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/* Restore all regs and return */
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l32i a0, sp, 0
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr a1, excsave1 # restore a1 saved by UserExceptionVector
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rfe
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.LSE_assign_reg:
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/* At this point, a2 contains the register number times 2, a4 is the
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* read value. */
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/* Calculate the jumptable address, and restore all regs except a2 and
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* a4 so we have less to do after jumping. */
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/* Note: Instructions are in this order to avoid pipeline stalls. */
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movi a3, .LSE_jumptable_base
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l32i a0, sp, 0
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addx8 a2, a2, a3 # a2 is now the address to jump to
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l32i a3, sp, 0x0c
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jx a2
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.balign 4
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.LSE_check_l16:
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/* At this point, a2 contains the opcode, a3 is masked opcode */
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movi a4, 0x001002 # l16si or l16ui opcode after masking
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bne a3, a4, .LSE_wrong_opcode
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/* Note: At this point, the opcode could be one of two things:
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* xx1xx2 (L16UI)
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* xx9xx2 (L16SI)
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* Both of these we can handle. */
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movi a4, ~3
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rsr a3, excvaddr # read faulting address
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and a4, a3, a4 # a4 now word aligned read address
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l32i a4, a4, 0 # perform the actual read
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ssa8l a3 # sar is now shift to extract a3's bytes
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srl a3, a4 # shift right correct distance
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extui a4, a3, 0, 16 # mask off bits we need for an l16
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bbci a2, 15, .LSE_post_fetch # Not a signed op
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bbci a4, 15, .LSE_post_fetch # Value does not need sign-extension
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movi a3, 0xFFFF0000
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or a4, a3, a4 # set 32-bit sign bits
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j .LSE_post_fetch
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.LSE_wrong_opcode:
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/* If we got here it's not an opcode we can try to fix, so bomb out.
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* Restore registers so any dump the fatal exception routine produces
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* will have correct values */
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wsr a0, sar
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l32i a0, sp, 0
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr a1, excsave1
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call0 sdk_user_fatal_exception_handler
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.balign 4
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.LSE_assign_a1:
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/* a1 is saved in excsave1, so just update that with the value, */
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wsr a4, excsave1
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/* Then restore all regs and return */
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l32i a0, sp, 0
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.balign 4
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.LSE_jumptable:
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/* The first 5 entries (80 bytes) of this table are unused (registers
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* a0..a4 are handled separately above). Rather than have a whole bunch
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* of wasted space, we just pretend that the table starts 80 bytes
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* earlier in memory. */
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.set .LSE_jumptable_base, .LSE_jumptable - (16 * 5)
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.org .LSE_jumptable_base + (16 * 5)
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mov a5, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 6)
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mov a6, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 7)
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mov a7, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 8)
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mov a8, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 9)
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mov a9, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 10)
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mov a10, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 11)
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mov a11, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 12)
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mov a12, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 13)
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mov a13, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 14)
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mov a14, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 15)
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mov a15, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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/****************************** call_user_start ******************************/
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.section .vecbase.text, "x"
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/* This is the first entrypoint called from the ROM after loading the image
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* into IRAM. It just sets up the VECBASE register to point at our own
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* exception vectors and then calls sdk_user_start() */
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.literal_position
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.balign 4
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call_user_start:
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.global call_user_start
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.type call_user_start, @function
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movi a2, VecBase
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wsr a2, vecbase
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call0 sdk_user_start
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/*************************** NMI Exception Handler ***************************/
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#define NMI_STACK_CANARY 0xABBABABA
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.section .vecbase.text, "x"
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.literal_position
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.balign 16
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NMIExceptionHandler:
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.type NMIExceptionHandler, @function
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wsr sp, excsave3 # excsave3 holds user stack
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movi sp, .NMIHandlerStackTop - 0x40
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s32i a0, sp, 0x00
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s32i a2, sp, 0x04
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s32i a3, sp, 0x08
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s32i a4, sp, 0x0c
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s32i a5, sp, 0x10
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s32i a6, sp, 0x14
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s32i a7, sp, 0x18
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s32i a8, sp, 0x1c
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s32i a9, sp, 0x20
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s32i a10, sp, 0x24
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s32i a11, sp, 0x28
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rsr a0, epc1
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s32i a0, sp, 0x2c
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rsr a0, exccause
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s32i a0, sp, 0x30
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rsr a0, excsave1
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s32i a0, sp, 0x34
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rsr a0, excvaddr
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s32i a0, sp, 0x38
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rsr a0, sar
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s32i a0, sp, 0x3c
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movi a0, 0x23 # Override PS for NMI handler
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wsr a0, ps
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rsync
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/* mark the stack overflow point before we call the actual NMI handler */
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movi a0, NMIHandlerStack
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movi a2, NMI_STACK_CANARY
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s32i a2, a0, 0x00
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call0 sdk_wDev_ProcessFiq
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/* verify we didn't overflow */
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movi a0, NMIHandlerStack
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l32i a3, a0, 0
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movi a2, NMI_STACK_CANARY
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bne a3, a2, .NMIFatalStackOverflow
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l32i a0, sp, 0x3c
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wsr a0, sar
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l32i a0, sp, 0x38
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wsr a0, excvaddr
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l32i a0, sp, 0x34
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wsr a0, excsave1
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l32i a0, sp, 0x30
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wsr a0, exccause
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l32i a0, sp, 0x2c
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wsr a0, epc1
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l32i a11, sp, 0x28
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l32i a10, sp, 0x24
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l32i a9, sp, 0x20
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l32i a8, sp, 0x1c
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l32i a7, sp, 0x18
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l32i a6, sp, 0x14
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l32i a5, sp, 0x10
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l32i a4, sp, 0x0c
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l32i a3, sp, 0x08
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movi a0, 0x33 # Reset PS
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wsr a0, ps
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rsync
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/* set dport nmi status to 1 (wDev_ProcessFiq clears bit 0 and verifies it
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* stays cleared, see
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* http://esp8266-re.foogod.com/wiki/WDev_ProcessFiq_%28IoT_RTOS_SDK_0.9.9%29)
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*/
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movi a0, 0x3ff00000
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movi a2, 0x1
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s32i a2, a0, 0
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l32i a2, sp, 0x04
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l32i a0, sp, 0x00
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movi a1, 0x0
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xsr a1, excsave3 # Load stack back from excsave3, clear excsave3
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rfi 3
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.section .rodata
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.NMIStackOverflowErrorMsg:
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.string "\nFATAL: NMI Stack Overflow\n"
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.section .vecbase.text, "x"
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.NMIFatalStackOverflow:
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movi a2, .NMIStackOverflowErrorMsg
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call0 printf
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.NMIInfiniteLoop:
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j .NMIInfiniteLoop /* TODO: replace with call to abort() */
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/*********************** General UserException Handler ***********************/
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.section .vecbase.text, "x"
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/* Called by UserExceptionVector if EXCCAUSE is anything other than
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* LoadStoreCause. */
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.literal_position
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.balign 4
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UserExceptionHandler:
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.type UserExceptionHandler, @function
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xsr a0, excsave1 # a0 now contains sp
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mov sp, a0
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addi sp, sp, -0x50
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s32i a0, sp, 0x10
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rsr a0, ps
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s32i a0, sp, 0x08
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rsr a0, epc1
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s32i a0, sp, 0x04
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rsr a0, excsave1
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s32i a0, sp, 0x0c
|
||
movi a0, _xt_user_exit
|
||
s32i a0, sp, 0x0
|
||
call0 sdk__xt_int_enter
|
||
movi a0, 0x23
|
||
wsr a0, ps
|
||
rsync
|
||
rsr a2, exccause
|
||
/* Any UserException cause other than a level 1 interrupt is fatal */
|
||
bnei a2, CAUSE_LVL1INT, .LUserFailOtherExceptionCause
|
||
.LUserHandleInterrupt:
|
||
rsil a0, 1
|
||
rsr a2, intenable
|
||
rsr a3, interrupt
|
||
movi a4, 0x3fff
|
||
and a2, a2, a3
|
||
and a2, a2, a4 # a2 = 0x3FFF & INTENABLE & INTERRUPT
|
||
call0 _xt_isr_handler
|
||
call0 sdk__xt_int_exit # once finished, jumps to _xt_user_exit via stack
|
||
|
||
.literal_position
|
||
.LUserFailOtherExceptionCause:
|
||
break 1, 1
|
||
call0 sdk_user_fatal_exception_handler
|
||
|
||
/* _xt_user_exit is pushed onto the stack as part of the user exception handler,
|
||
restores same set registers which were saved there and returns from exception */
|
||
_xt_user_exit:
|
||
.global _xt_user_exit
|
||
.type _xt_user_exit, @function
|
||
l32i a0, sp, 0x8
|
||
wsr a0, ps
|
||
l32i a0, sp, 0x4
|
||
wsr a0, epc1
|
||
l32i a0, sp, 0xc
|
||
l32i sp, sp, 0x10
|
||
rsync
|
||
rfe
|