Consolidate interrupt management in core as esp/interrupts.h & esp_interrupts.c
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8 changed files with 83 additions and 98 deletions
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@ -265,60 +265,3 @@ void IRAM vPortExitCritical( void )
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portENABLE_INTERRUPTS();
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}
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/*-----------------------------------------------------------*/
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/* Main ISR handler for FreeRTOS side of the ESP libs?
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As far as I can tell, the "real" Xtensa ISRs ("Exceptions") are
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handled in libmain.a (xtensa_vectors.o) which then can call into here
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passing an interrupt mask.
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*/
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_xt_isr isr[16];
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void IRAM _xt_isr_attach(uint8_t i, _xt_isr func)
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{
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isr[i] = func;
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}
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uint16_t IRAM _xt_isr_handler(uint16_t i)
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{
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uint8_t index;
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/* I think this is implementing some kind of interrupt priority or
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short-circuiting an expensive ffs for most common interrupts - ie
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WDT And GPIO are common or high priority, then remaining flags.
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*/
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if (i & (1 << INUM_WDT)) {
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index = INUM_WDT;
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}
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else if (i & (1 << INUM_GPIO)) {
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index = INUM_GPIO;
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}else {
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index = __builtin_ffs(i) - 1;
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if (index == INUM_MAX) {
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/* I don't understand what happens here. INUM_MAX is not
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the highest interrupt number listed (and the isr array
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has 16 entries).
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Clearing that flag and then setting index to
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__builtin_ffs(i)-1 may result in index == 255 if no
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higher flags are set, unless this is guarded against
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somehow by the caller?
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I also don't understand why the code is written like
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this in esp_iot_rtos_sdk instead of just putting the i
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&= line near the top... Probably no good reason?
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*/
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i &= ~(1 << INUM_MAX);
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index = __builtin_ffs(i) - 1;
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}
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}
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_xt_clear_ints(1<<index);
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isr[index]();
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return i & ~(1 << index);
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}
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@ -73,8 +73,8 @@ extern "C" {
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#include "esp8266.h"
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#include "espressif/esp8266/ets_sys.h"
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#include <stdint.h>
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#include "xtensa_rtos.h"
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#include "xtensa_interrupts.h"
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#include "xtensa_rtos.h"
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#include <esp/interrupts.h>
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/*-----------------------------------------------------------
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* Port specific definitions for ESP8266
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60
core/esp_interrupts.c
Normal file
60
core/esp_interrupts.c
Normal file
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@ -0,0 +1,60 @@
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/* ESP8266 Xtensa interrupt management functions
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*
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*
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* Part of esp-open-rtos
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* Copyright (C) 2015 Angus Gratton
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* BSD Licensed as described in the file LICENSE
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*/
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#include <esp/interrupts.h>
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_xt_isr isr[16];
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void IRAM _xt_isr_attach(uint8_t i, _xt_isr func)
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{
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isr[i] = func;
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}
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/* This ISR handler is taken directly from the FreeRTOS port and
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probably could use a cleanup.
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*/
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uint16_t IRAM _xt_isr_handler(uint16_t i)
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{
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uint8_t index;
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/* I think this is implementing some kind of interrupt priority or
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short-circuiting an expensive ffs for most common interrupts - ie
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WDT And GPIO are common or high priority, then remaining flags.
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*/
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if (i & (1 << INUM_WDT)) {
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index = INUM_WDT;
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}
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else if (i & (1 << INUM_GPIO)) {
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index = INUM_GPIO;
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}else {
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index = __builtin_ffs(i) - 1;
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if (index == INUM_MAX) {
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/* I don't understand what happens here. INUM_MAX is not
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the highest interrupt number listed (and the isr array
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has 16 entries).
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Clearing that flag and then setting index to
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__builtin_ffs(i)-1 may result in index == 255 if no
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higher flags are set, unless this is guarded against
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somehow by the caller?
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I also don't understand why the code is written like
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this in esp_iot_rtos_sdk instead of just putting the i
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&= line near the top... Probably no good reason?
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*/
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i &= ~(1 << INUM_MAX);
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index = __builtin_ffs(i) - 1;
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}
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}
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_xt_clear_ints(1<<index);
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isr[index]();
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return i & ~(1 << index);
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}
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@ -1,33 +0,0 @@
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/* esp/cpu.h
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*
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* Details relating to the ESP8266 Xtensa core.
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*
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*/
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#ifndef _ESP_CPU_H
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#define _ESP_CPU_H
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#include <stdbool.h>
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/* Interrupt numbers for level 1 exception handler.
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*
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* Currently the UserExceptionVector calls down to _xt_isr_handler,
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* defined in port.c, for at least some of these interrupts. Some are handled
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* on the SDK side, though.
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*/
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typedef enum {
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INUM_SPI = 2,
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INUM_GPIO = 4,
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INUM_UART = 5,
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INUM_MAX = 6, /* in some places this is documented as timer0 CCOMPARE0 interrupt */
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INUM_SOFT = 7,
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INUM_WDT = 8,
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INUM_TIMER_FRC1 = 9,
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/* FRC2 default handler. Configured by sdk_ets_timer_init, which
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runs as part of default libmain.a startup code, assigns
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interrupt handler to sdk_vApplicationTickHook+0x68
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*/
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INUM_TIMER_FRC2 = 10,
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} xt_isr_num_t;
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#endif
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@ -11,8 +11,7 @@
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#include <stdbool.h>
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#include "esp/gpio_regs.h"
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#include "esp/iomux.h"
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#include "esp/cpu.h"
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#include "xtensa_interrupts.h"
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#include "esp/interrupts.h"
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typedef enum {
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GPIO_INPUT,
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@ -1,4 +1,4 @@
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/* Xtensa interrupt management functions
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/* ESP8266 Xtensa interrupt management functions
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*
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* Some (w/ sdk_ prefix) are implemented in binary libs, rest are
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* inlines replacing functions in the binary libraries.
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@ -15,6 +15,23 @@
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#include <xtensa/hal.h>
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#include <common_macros.h>
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/* Interrupt numbers for level 1 exception handler. */
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typedef enum {
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INUM_SPI = 2,
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INUM_GPIO = 4,
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INUM_UART = 5,
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INUM_MAX = 6, /* in some places this is documented as timer0 CCOMPARE0 interrupt */
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INUM_SOFT = 7,
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INUM_WDT = 8,
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INUM_TIMER_FRC1 = 9,
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/* FRC2 default handler. Configured by sdk_ets_timer_init, which
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runs as part of default libmain.a startup code, assigns
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interrupt handler to sdk_vApplicationTickHook+0x68
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*/
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INUM_TIMER_FRC2 = 10,
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} xt_isr_num_t;
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void sdk__xt_int_exit (void);
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void _xt_user_exit (void);
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void sdk__xt_tick_timer_init (void);
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@ -10,9 +10,8 @@
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#define _ESP_TIMER_H
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#include <stdbool.h>
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#include <xtensa_interrupts.h>
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#include "esp/timer_regs.h"
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#include "esp/cpu.h"
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#include "esp/interrupts.h"
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typedef enum {
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FRC1 = 0,
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@ -13,7 +13,7 @@
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#include "common_macros.h"
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#include "esp/registers.h"
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#include "esp/cpu.h"
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#include "esp/interrupts.h"
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#include "esp/iomux.h"
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#include "esp/gpio.h"
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#include "esp/timer.h"
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