Added esp/timer_regs.h and esp/dport_regs.h
This commit is contained in:
Alex Stewart
parent
3cc5d1fa86
commit
eaa090e267
6 changed files with 234 additions and 227 deletions
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@ -14,12 +14,12 @@
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* the arguments aren't known at compile time (values are evaluated at
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* compile time otherwise.)
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*/
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uint32_t _timer_freq_to_count_runtime(const timer_frc_t frc, const uint32_t freq, const timer_div_t div)
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uint32_t _timer_freq_to_count_runtime(const timer_frc_t frc, const uint32_t freq, const timer_clkdiv_t div)
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{
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return _timer_freq_to_count_impl(frc, freq, div);
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}
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uint32_t _timer_time_to_count_runtime(const timer_frc_t frc, uint32_t us, const timer_div_t div)
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uint32_t _timer_time_to_count_runtime(const timer_frc_t frc, uint32_t us, const timer_clkdiv_t div)
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{
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return _timer_time_to_count_runtime(frc, us, div);
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}
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53
core/include/esp/dport_regs.h
Normal file
53
core/include/esp/dport_regs.h
Normal file
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@ -0,0 +1,53 @@
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/* esp/dport_regs.h
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*
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* ESP8266 DPORT0 register definitions
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*
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* Not compatible with ESP SDK register access code.
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*/
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#ifndef _ESP_DPORT_REGS_H
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#define _ESP_DPORT_REGS_H
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#include "esp/types.h"
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#include "common_macros.h"
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#define DPORT_BASE 0x3ff00000
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#define DPORT (*(struct DPORT_REGS *)(DPORT_BASE))
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/* DPORT registers
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Control various aspects of core/peripheral interaction... Not well
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documented or understood.
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*/
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struct DPORT_REGS {
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uint32_t volatile _unknown0; // 0x00
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uint32_t volatile INT_ENABLE; // 0x04
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} __attribute__ (( packed ));
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_Static_assert(sizeof(struct DPORT_REGS) == 0x08, "DPORT_REGS is the wrong size");
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/* Details for INT_ENABLE register */
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/* Set flags to enable CPU interrupts from some peripherals. Read/write.
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bit 0 - Is set by RTOS SDK startup code but function is unknown.
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bit 1 - INT_ENABLE_TIMER0 allows TIMER 0 (FRC1) to trigger interrupt INUM_TIMER_FRC1.
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bit 2 - INT_ENABLE_TIMER1 allows TIMER 1 (FRC2) to trigger interrupt INUM_TIMER_FRC2.
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Espressif calls this register "EDGE_INT_ENABLE_REG". The "edge" in
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question is (I think) the interrupt line from the peripheral, as
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the interrupt status bit is set. There may be a similar register
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for enabling "level" interrupts instead of edge triggering
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- this is unknown.
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*/
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#define DPORT_INT_ENABLE_TIMER0 BIT(1)
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#define DPORT_INT_ENABLE_TIMER1 BIT(2)
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/* Aliases for the Espressif way of referring to TIMER0 (FRC1) and TIMER1
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* (FRC2).. */
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#define DPORT_INT_ENABLE_FRC1 DPORT_INT_ENABLE_TIMER0
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#define DPORT_INT_ENABLE_FRC2 DPORT_INT_ENABLE_TIMER1
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#endif /* _ESP_DPORT_REGS_H */
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@ -18,6 +18,8 @@
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#include "esp/iomux_regs.h"
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#include "esp/gpio_regs.h"
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#include "esp/timer_regs.h"
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#include "esp/dport_regs.h"
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/* Internal macro, only defined in header body */
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#define _REG(BASE, OFFSET) (*(esp_reg_t)((BASE)+(OFFSET)))
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@ -27,13 +29,13 @@
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You shouldn't need to use these directly.
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*/
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#define MMIO_BASE 0x60000000
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#define DPORT_BASE 0x3ff00000
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//#define DPORT_BASE 0x3ff00000
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#define UART0_BASE (MMIO_BASE + 0)
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#define SPI1_BASE (MMIO_BASE + 0x0100)
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#define SPI_BASE (MMIO_BASE + 0x0200)
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//#define GPIO0_BASE (MMIO_BASE + 0x0300)
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#define TIMER_BASE (MMIO_BASE + 0x0600)
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//#define TIMER_BASE (MMIO_BASE + 0x0600)
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#define RTC_BASE (MMIO_BASE + 0x0700)
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//#define IOMUX_BASE (MMIO_BASE + 0x0800)
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#define WDT_BASE (MMIO_BASE + 0x0900)
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@ -43,135 +45,6 @@
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#define RTCS_BASE (MMIO_BASE + 0x1100)
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#define RTCU_BASE (MMIO_BASE + 0x1200)
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/* TIMER registers
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*
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* ESP8266 has two hardware(?) timer counters, FRC1 and FRC2.
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*
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* FRC1 is a 24-bit countdown timer, triggers interrupt when reaches zero.
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* FRC2 is a 32-bit countup timer, can set a variable match value to trigger an interrupt.
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*
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* FreeRTOS tick timer appears to come from XTensa core tick timer0,
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* not either of these. FRC2 is used in the FreeRTOS SDK however. It
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* is set to free-run, interrupting periodically via updates to the
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* MATCH register. sdk_ets_timer_init configures FRC2 and assigns FRC2
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* interrupt handler at sdk_vApplicationTickHook+0x68
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*/
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/* Load value for FRC1, read/write.
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When TIMER_CTRL_RELOAD is cleared in TIMER_FRC1_CTRL_REG, FRC1 will
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reload to TIMER_FRC1_MAX_LOAD once overflowed (unless the load
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value is rewritten in the interrupt handler.)
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When TIMER_CTRL_RELOAD is set in TIMER_FRC1_CTRL_REG, FRC1 will reload
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from the load register value once overflowed.
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*/
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#define TIMER_FRC1_LOAD_REG _REG(TIMER_BASE, 0x00)
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#define TIMER_FRC1_MAX_LOAD 0x7fffff
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/* Current count value for FRC1, read only? */
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#define TIMER_FRC1_COUNT_REG _REG(TIMER_BASE, 0x04)
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/* Control register for FRC1, read/write.
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See the bit definitions TIMER_CTRL_xxx lower down.
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*/
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#define TIMER_FRC1_CTRL_REG _REG(TIMER_BASE, 0x08)
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/* Reading this register always returns the value in
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* TIMER_FRC1_LOAD_REG.
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*
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* Writing zero to this register clears the FRC1
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* interrupt status.
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*/
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#define TIMER_FRC1_CLEAR_INT_REG _REG(TIMER_BASE, 0x0c)
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/* FRC2 load register.
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*
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* If TIMER_CTRL_RELOAD is cleared in TIMER_FRC2_CTRL_REG, writing to
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* this register will update the FRC2 COUNT value.
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*
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* If TIMER_CTRL_RELOAD is set in TIMER_FRC2_CTRL_REG, the behaviour
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* appears to be the same except that writing 0 to the load register
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* both sets the COUNT register to 0 and disables the timer, even if
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* the TIMER_CTRL_RUN bit is set.
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*
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* Offsets 0x34, 0x38, 0x3c all seem to read back the LOAD_REG value
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* also (but have no known function.)
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*/
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#define TIMER_FRC2_LOAD_REG _REG(TIMER_BASE, 0x20)
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/* FRC2 current count value. Read only? */
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#define TIMER_FRC2_COUNT_REG _REG(TIMER_BASE, 0x24)
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/* Control register for FRC2. Read/write.
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See the bit definitions TIMER_CTRL_xxx lower down.
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*/
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#define TIMER_FRC2_CTRL_REG _REG(TIMER_BASE, 0x28)
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/* Reading this value returns the current value of
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* TIMER_FRC2_LOAD_REG.
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*
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* Writing zero to this value clears the FRC2 interrupt status.
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*/
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#define TIMER_FRC2_CLEAR_INT_REG _REG(TIMER_BASE, 0x2c)
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/* Interrupt match value for FRC2. When COUNT == MATCH,
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the interrupt fires.
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*/
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#define TIMER_FRC2_MATCH_REG _REG(TIMER_BASE, 0x30)
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/* Timer control bits to set clock divisor values.
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Divider from master 80MHz APB_CLK (unconfirmed, see esp/clocks.h).
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*/
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#define TIMER_CTRL_DIV_1 0
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#define TIMER_CTRL_DIV_16 BIT(2)
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#define TIMER_CTRL_DIV_256 BIT(3)
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#define TIMER_CTRL_DIV_MASK (BIT(2)|BIT(3))
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/* Set timer control bits to trigger interrupt on "edge" or "level"
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*
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* Observed behaviour is like this:
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*
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* * When TIMER_CTRL_INT_LEVEL is set, the interrupt status bit
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* TIMER_CTRL_INT_STATUS remains set when the timer interrupt
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* triggers, unless manually cleared by writing 0 to
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* TIMER_FRCx_CLEAR_INT. While the interrupt status bit stays set
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* the timer will continue to run normally, but the interrupt
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* (INUM_TIMER_FRC1 or INUM_TIMER_FRC2) won't trigger again.
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*
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* * When TIMER_CTRL_INT_EDGE (default) is set, there's no need to
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* manually write to TIMER_FRCx_CLEAR_INT. The interrupt status bit
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* TIMER_CTRL_INT_STATUS automatically clears after the interrupt
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* triggers, and the interrupt handler will run again
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* automatically.
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*
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*/
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#define TIMER_CTRL_INT_EDGE 0
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#define TIMER_CTRL_INT_LEVEL BIT(0)
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#define TIMER_CTRL_INT_MASK BIT(0)
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/* Timer auto-reload bit
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This bit interacts with TIMER_FRC1_LOAD_REG & TIMER_FRC2_LOAD_REG
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differently, see those registers for details.
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*/
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#define TIMER_CTRL_RELOAD BIT(6)
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/* Timer run bit */
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#define TIMER_CTRL_RUN BIT(7)
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/* Read-only timer interrupt status.
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This bit gets set on FRC1 when interrupt fires, and cleared on a
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write to TIMER_FRC1_CLEAR_INT (cleared automatically if
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TIMER_CTRL_INT_LEVEL is not set).
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*/
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#define TIMER_CTRL_INT_STATUS BIT(8)
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/* WDT register(s)
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Not fully understood yet. Writing 0 here disables wdt.
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@ -180,29 +53,4 @@
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*/
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#define WDT_CTRL _REG(WDT_BASE, 0x00)
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/* DPORT registers
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Control various aspects of core/peripheral interaction... Not well
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documented or understood.
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*/
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/* Set flags to enable CPU interrupts from some peripherals. Read/write.
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bit 0 - Is set by RTOS SDK startup code but function is unknown.
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bit 1 - INT_ENABLE_FRC1 allows TIMER FRC1 to trigger interrupt INUM_TIMER_FRC1.
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bit 2 - INT_ENABLE_FRC2 allows TIMER FRC2 to trigger interrupt INUM_TIMER_FRC2.
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Espressif calls this register "EDGE_INT_ENABLE_REG". The "edge" in
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question is (I think) the interrupt line from the peripheral, as
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the interrupt status bit is set. There may be a similar register
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for enabling "level" interrupts instead of edge triggering
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- this is unknown.
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*/
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#define DP_INT_ENABLE_REG _REG(DPORT_BASE, 0x04)
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/* Set to enable interrupts from TIMER FRC1 */
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#define INT_ENABLE_FRC1 BIT(1)
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/* Set to enable interrupts interrupts from TIMER FRC2 */
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#define INT_ENABLE_FRC2 BIT(2)
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#endif
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@ -11,12 +11,12 @@
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#include <stdbool.h>
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#include <xtensa_interrupts.h>
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#include "esp/registers.h"
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#include "esp/timer_regs.h"
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#include "esp/cpu.h"
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typedef enum {
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TIMER_FRC1,
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TIMER_FRC2,
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FRC1 = 0,
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FRC2 = 1,
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} timer_frc_t;
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/* Return current count value for timer. */
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@ -31,14 +31,8 @@ INLINED void timer_set_load(const timer_frc_t frc, const uint32_t load);
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/* Returns maximum load value for timer. */
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INLINED uint32_t timer_max_load(const timer_frc_t frc);
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typedef enum {
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TIMER_DIV1,
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TIMER_DIV16,
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TIMER_DIV256,
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} timer_div_t;
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/* Set the timer divider value */
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INLINED void timer_set_divider(const timer_frc_t frc, const timer_div_t div);
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INLINED void timer_set_divider(const timer_frc_t frc, const timer_clkdiv_t div);
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/* Enable or disable timer interrupts
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@ -62,7 +56,7 @@ INLINED bool timer_get_reload(const timer_frc_t frc);
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/* Return a suitable timer divider for the specified frequency,
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or -1 if none is found.
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*/
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INLINED timer_div_t timer_freq_to_div(uint32_t freq);
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INLINED timer_clkdiv_t timer_freq_to_div(uint32_t freq);
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/* Return the number of timer counts to achieve the specified
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* frequency with the specified divisor.
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@ -73,12 +67,12 @@ INLINED timer_div_t timer_freq_to_div(uint32_t freq);
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*
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* Compile-time evaluates if all arguments are available at compile time.
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*/
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INLINED uint32_t timer_freq_to_count(const timer_frc_t frc, uint32_t freq, const timer_div_t div);
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INLINED uint32_t timer_freq_to_count(const timer_frc_t frc, uint32_t freq, const timer_clkdiv_t div);
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/* Return a suitable timer divider for the specified duration in
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microseconds or -1 if none is found.
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*/
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INLINED timer_div_t timer_time_to_div(uint32_t us);
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INLINED timer_clkdiv_t timer_time_to_div(uint32_t us);
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/* Return the number of timer counts for the specified timer duration
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* in microseconds, when using the specified divisor.
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@ -89,7 +83,7 @@ INLINED timer_div_t timer_time_to_div(uint32_t us);
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*
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* Compile-time evaluates if all arguments are available at compile time.
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*/
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INLINED uint32_t timer_time_to_count(const timer_frc_t frc, uint32_t us, const timer_div_t div);
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INLINED uint32_t timer_time_to_count(const timer_frc_t frc, uint32_t us, const timer_clkdiv_t div);
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/* Set a target timer interrupt frequency in Hz.
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@ -10,6 +10,7 @@
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#include <limits.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include "esp/dport_regs.h"
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/* Timer divisor index to max frequency */
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#define _FREQ_DIV1 (80*1000*1000)
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@ -20,104 +21,90 @@ const static uint32_t IROM _TIMER_FREQS[] = { _FREQ_DIV1, _FREQ_DIV16, _FREQ_DIV
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/* Timer divisor index to divisor value */
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const static uint32_t IROM _TIMER_DIV_VAL[] = { 1, 16, 256 };
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/* Timer divisor to mask value */
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const static uint32_t IROM _TIMER_DIV_REG[] = { TIMER_CTRL_DIV_1, TIMER_CTRL_DIV_16, TIMER_CTRL_DIV_256 };
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INLINED esp_reg_t _timer_ctrl_reg(const timer_frc_t frc)
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{
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return (frc == TIMER_FRC1) ? &TIMER_FRC1_CTRL_REG : &TIMER_FRC2_CTRL_REG;
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}
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INLINED uint32_t timer_get_count(const timer_frc_t frc)
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{
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return (frc == TIMER_FRC1) ? TIMER_FRC1_COUNT_REG : TIMER_FRC2_COUNT_REG;
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return TIMER(frc).COUNT;
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}
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INLINED uint32_t timer_get_load(const timer_frc_t frc)
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{
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return (frc == TIMER_FRC1) ? TIMER_FRC1_LOAD_REG : TIMER_FRC2_LOAD_REG;
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return TIMER(frc).LOAD;
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}
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INLINED void timer_set_load(const timer_frc_t frc, const uint32_t load)
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{
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if(frc == TIMER_FRC1)
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TIMER_FRC1_LOAD_REG = load;
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else
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TIMER_FRC2_LOAD_REG = load;
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TIMER(frc).LOAD = load;
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}
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INLINED uint32_t timer_max_load(const timer_frc_t frc)
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{
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return (frc == TIMER_FRC1) ? TIMER_FRC1_MAX_LOAD : UINT32_MAX;
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return (frc == FRC1) ? TIMER_FRC1_MAX_LOAD : UINT32_MAX;
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}
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INLINED void timer_set_divider(const timer_frc_t frc, const timer_div_t div)
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INLINED void timer_set_divider(const timer_frc_t frc, const timer_clkdiv_t div)
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{
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if(div < TIMER_DIV1 || div > TIMER_DIV256)
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if(div < TIMER_CLKDIV_1 || div > TIMER_CLKDIV_256)
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return;
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esp_reg_t ctrl = _timer_ctrl_reg(frc);
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*ctrl = (*ctrl & ~TIMER_CTRL_DIV_MASK) | (_TIMER_DIV_REG[div] & TIMER_CTRL_DIV_MASK);
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TIMER(frc).CTRL = SET_FIELD(TIMER(frc).CTRL, TIMER_CTRL_CLKDIV, div);
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}
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INLINED void timer_set_interrupts(const timer_frc_t frc, bool enable)
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{
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const uint32_t dp_bit = (frc == TIMER_FRC1) ? INT_ENABLE_FRC1 : INT_ENABLE_FRC2;
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const uint32_t int_mask = BIT((frc == TIMER_FRC1) ? INUM_TIMER_FRC1 : INUM_TIMER_FRC2);
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const uint32_t dp_bit = (frc == FRC1) ? DPORT_INT_ENABLE_FRC1 : DPORT_INT_ENABLE_FRC2;
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const uint32_t int_mask = BIT((frc == FRC1) ? INUM_TIMER_FRC1 : INUM_TIMER_FRC2);
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if(enable) {
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DP_INT_ENABLE_REG |= dp_bit;
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DPORT.INT_ENABLE |= dp_bit;
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_xt_isr_unmask(int_mask);
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} else {
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DP_INT_ENABLE_REG &= ~dp_bit;
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DPORT.INT_ENABLE &= ~dp_bit;
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_xt_isr_mask(int_mask);
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}
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}
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INLINED void timer_set_run(const timer_frc_t frc, const bool run)
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{
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||||
esp_reg_t ctrl = _timer_ctrl_reg(frc);
|
||||
if (run)
|
||||
*ctrl |= TIMER_CTRL_RUN;
|
||||
TIMER(frc).CTRL |= TIMER_CTRL_RUN;
|
||||
else
|
||||
*ctrl &= ~TIMER_CTRL_RUN;
|
||||
TIMER(frc).CTRL &= ~TIMER_CTRL_RUN;
|
||||
}
|
||||
|
||||
INLINED bool timer_get_run(const timer_frc_t frc)
|
||||
{
|
||||
return *_timer_ctrl_reg(frc) & TIMER_CTRL_RUN;
|
||||
return TIMER(frc).CTRL & TIMER_CTRL_RUN;
|
||||
}
|
||||
|
||||
INLINED void timer_set_reload(const timer_frc_t frc, const bool reload)
|
||||
{
|
||||
esp_reg_t ctrl = _timer_ctrl_reg(frc);
|
||||
if (reload)
|
||||
*ctrl |= TIMER_CTRL_RELOAD;
|
||||
TIMER(frc).CTRL |= TIMER_CTRL_RELOAD;
|
||||
else
|
||||
*ctrl &= ~TIMER_CTRL_RELOAD;
|
||||
TIMER(frc).CTRL &= ~TIMER_CTRL_RELOAD;
|
||||
}
|
||||
|
||||
INLINED bool timer_get_reload(const timer_frc_t frc)
|
||||
{
|
||||
return *_timer_ctrl_reg(frc) & TIMER_CTRL_RELOAD;
|
||||
return TIMER(frc).CTRL & TIMER_CTRL_RELOAD;
|
||||
}
|
||||
|
||||
INLINED timer_div_t timer_freq_to_div(uint32_t freq)
|
||||
INLINED timer_clkdiv_t timer_freq_to_div(uint32_t freq)
|
||||
{
|
||||
/*
|
||||
try to maintain resolution without risking overflows.
|
||||
these values are a bit arbitrary at the moment! */
|
||||
if(freq > 100*1000)
|
||||
return TIMER_DIV1;
|
||||
return TIMER_CLKDIV_1;
|
||||
else if(freq > 100)
|
||||
return TIMER_DIV16;
|
||||
return TIMER_CLKDIV_16;
|
||||
else
|
||||
return TIMER_DIV256;
|
||||
return TIMER_CLKDIV_256;
|
||||
}
|
||||
|
||||
/* timer_timer_to_count implementation - inline if all args are constant, call normally otherwise */
|
||||
|
||||
INLINED uint32_t _timer_freq_to_count_impl(const timer_frc_t frc, const uint32_t freq, const timer_div_t div)
|
||||
INLINED uint32_t _timer_freq_to_count_impl(const timer_frc_t frc, const uint32_t freq, const timer_clkdiv_t div)
|
||||
{
|
||||
if(div < TIMER_DIV1 || div > TIMER_DIV256)
|
||||
if(div < TIMER_CLKDIV_1 || div > TIMER_CLKDIV_256)
|
||||
return 0; /* invalid divider */
|
||||
|
||||
if(freq > _TIMER_FREQS[div])
|
||||
|
|
@ -127,9 +114,9 @@ INLINED uint32_t _timer_freq_to_count_impl(const timer_frc_t frc, const uint32_t
|
|||
return counts;
|
||||
}
|
||||
|
||||
uint32_t _timer_freq_to_count_runtime(const timer_frc_t frc, const uint32_t freq, const timer_div_t div);
|
||||
uint32_t _timer_freq_to_count_runtime(const timer_frc_t frc, const uint32_t freq, const timer_clkdiv_t div);
|
||||
|
||||
INLINED uint32_t timer_freq_to_count(const timer_frc_t frc, const uint32_t freq, const timer_div_t div)
|
||||
INLINED uint32_t timer_freq_to_count(const timer_frc_t frc, const uint32_t freq, const timer_clkdiv_t div)
|
||||
{
|
||||
if(__builtin_constant_p(frc) && __builtin_constant_p(freq) && __builtin_constant_p(div))
|
||||
return _timer_freq_to_count_impl(frc, freq, div);
|
||||
|
|
@ -137,33 +124,33 @@ INLINED uint32_t timer_freq_to_count(const timer_frc_t frc, const uint32_t freq,
|
|||
return _timer_freq_to_count_runtime(frc, freq, div);
|
||||
}
|
||||
|
||||
INLINED timer_div_t timer_time_to_div(uint32_t us)
|
||||
INLINED timer_clkdiv_t timer_time_to_div(uint32_t us)
|
||||
{
|
||||
/*
|
||||
try to maintain resolution without risking overflows. Similar to
|
||||
timer_freq_to_div, these values are a bit arbitrary at the
|
||||
moment! */
|
||||
if(us < 1000)
|
||||
return TIMER_DIV1;
|
||||
return TIMER_CLKDIV_1;
|
||||
else if(us < 10*1000)
|
||||
return TIMER_DIV16;
|
||||
return TIMER_CLKDIV_16;
|
||||
else
|
||||
return TIMER_DIV256;
|
||||
return TIMER_CLKDIV_256;
|
||||
}
|
||||
|
||||
/* timer_timer_to_count implementation - inline if all args are constant, call normally otherwise */
|
||||
|
||||
INLINED uint32_t _timer_time_to_count_impl(const timer_frc_t frc, uint32_t us, const timer_div_t div)
|
||||
INLINED uint32_t _timer_time_to_count_impl(const timer_frc_t frc, uint32_t us, const timer_clkdiv_t div)
|
||||
{
|
||||
if(div < TIMER_DIV1 || div > TIMER_DIV256)
|
||||
if(div < TIMER_CLKDIV_1 || div > TIMER_CLKDIV_256)
|
||||
return 0; /* invalid divider */
|
||||
|
||||
const uint32_t TIMER_MAX = timer_max_load(frc);
|
||||
|
||||
if(div != TIMER_DIV256) /* timer tick in MHz */
|
||||
if(div != TIMER_CLKDIV_256) /* timer tick in MHz */
|
||||
{
|
||||
/* timer is either 80MHz or 5MHz, so either 80 or 5 MHz counts per us */
|
||||
const uint32_t counts_per_us = ((div == TIMER_DIV1) ? _FREQ_DIV1 : _FREQ_DIV16)/1000/1000;
|
||||
const uint32_t counts_per_us = ((div == TIMER_CLKDIV_1) ? _FREQ_DIV1 : _FREQ_DIV16)/1000/1000;
|
||||
if(us > TIMER_MAX/counts_per_us)
|
||||
return 0; /* Multiplying us by mhz_per_count will overflow TIMER_MAX */
|
||||
return us*counts_per_us;
|
||||
|
|
@ -186,9 +173,9 @@ INLINED uint32_t _timer_time_to_count_impl(const timer_frc_t frc, uint32_t us, c
|
|||
}
|
||||
}
|
||||
|
||||
uint32_t _timer_time_to_count_runtime(const timer_frc_t frc, uint32_t us, const timer_div_t div);
|
||||
uint32_t _timer_time_to_count_runtime(const timer_frc_t frc, uint32_t us, const timer_clkdiv_t div);
|
||||
|
||||
INLINED uint32_t timer_time_to_count(const timer_frc_t frc, uint32_t us, const timer_div_t div)
|
||||
INLINED uint32_t timer_time_to_count(const timer_frc_t frc, uint32_t us, const timer_clkdiv_t div)
|
||||
{
|
||||
if(__builtin_constant_p(frc) && __builtin_constant_p(us) && __builtin_constant_p(div))
|
||||
return _timer_time_to_count_impl(frc, us, div);
|
||||
|
|
@ -201,7 +188,7 @@ INLINED uint32_t timer_time_to_count(const timer_frc_t frc, uint32_t us, const t
|
|||
INLINED bool _timer_set_frequency_impl(const timer_frc_t frc, uint32_t freq)
|
||||
{
|
||||
uint32_t counts = 0;
|
||||
timer_div_t div = timer_freq_to_div(freq);
|
||||
timer_clkdiv_t div = timer_freq_to_div(freq);
|
||||
|
||||
counts = timer_freq_to_count(frc, freq, div);
|
||||
if(counts == 0)
|
||||
|
|
@ -211,7 +198,7 @@ INLINED bool _timer_set_frequency_impl(const timer_frc_t frc, uint32_t freq)
|
|||
}
|
||||
|
||||
timer_set_divider(frc, div);
|
||||
if(frc == TIMER_FRC1)
|
||||
if(frc == FRC1)
|
||||
{
|
||||
timer_set_load(frc, counts);
|
||||
timer_set_reload(frc, true);
|
||||
|
|
@ -219,7 +206,7 @@ INLINED bool _timer_set_frequency_impl(const timer_frc_t frc, uint32_t freq)
|
|||
else /* FRC2 */
|
||||
{
|
||||
/* assume that if this overflows it'll wrap, so we'll get desired behaviour */
|
||||
TIMER_FRC2_MATCH_REG = counts + TIMER_FRC2_COUNT_REG;
|
||||
TIMER(1).ALARM = counts + TIMER(1).COUNT;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
|
@ -239,20 +226,20 @@ INLINED bool timer_set_frequency(const timer_frc_t frc, uint32_t freq)
|
|||
INLINED bool _timer_set_timeout_impl(const timer_frc_t frc, uint32_t us)
|
||||
{
|
||||
uint32_t counts = 0;
|
||||
timer_div_t div = timer_time_to_div(us);
|
||||
timer_clkdiv_t div = timer_time_to_div(us);
|
||||
|
||||
counts = timer_time_to_count(frc, us, div);
|
||||
if(counts == 0)
|
||||
return false; /* can't set frequency */
|
||||
|
||||
timer_set_divider(frc, div);
|
||||
if(frc == TIMER_FRC1)
|
||||
if(frc == FRC1)
|
||||
{
|
||||
timer_set_load(frc, counts);
|
||||
}
|
||||
else /* FRC2 */
|
||||
{
|
||||
TIMER_FRC2_MATCH_REG = counts + TIMER_FRC2_COUNT_REG;
|
||||
TIMER(1).ALARM = counts + TIMER(1).COUNT;
|
||||
}
|
||||
|
||||
return true;
|
||||
|
|
|
|||
125
core/include/esp/timer_regs.h
Normal file
125
core/include/esp/timer_regs.h
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
/* esp/timer_regs.h
|
||||
*
|
||||
* ESP8266 Timer register definitions
|
||||
*
|
||||
* Not compatible with ESP SDK register access code.
|
||||
*/
|
||||
|
||||
#ifndef _ESP_TIMER_REGS_H
|
||||
#define _ESP_TIMER_REGS_H
|
||||
|
||||
#include "esp/types.h"
|
||||
#include "common_macros.h"
|
||||
|
||||
#define TIMER_BASE 0x60000600
|
||||
#define TIMER(i) (*(struct TIMER_REGS *)(TIMER_BASE + (i)*0x20))
|
||||
#define TIMER_FRC1 TIMER(0)
|
||||
#define TIMER_FRC2 TIMER(1)
|
||||
|
||||
/* TIMER registers
|
||||
*
|
||||
* ESP8266 has two hardware timer counters, FRC1 and FRC2.
|
||||
*
|
||||
* FRC1 is a 24-bit countdown timer, triggers interrupt when reaches zero.
|
||||
* FRC2 is a 32-bit countup timer, can set a variable match value to trigger an interrupt.
|
||||
*
|
||||
* FreeRTOS tick timer appears to come from XTensa core tick timer0,
|
||||
* not either of these. FRC2 is used in the FreeRTOS SDK however. It
|
||||
* is set to free-run, interrupting periodically via updates to the
|
||||
* ALARM register. sdk_ets_timer_init configures FRC2 and assigns FRC2
|
||||
* interrupt handler at sdk_vApplicationTickHook+0x68
|
||||
*/
|
||||
|
||||
struct TIMER_REGS { // FRC1 FRC2
|
||||
uint32_t volatile LOAD; // 0x00 0x20
|
||||
uint32_t volatile COUNT; // 0x04 0x24
|
||||
uint32_t volatile CTRL; // 0x08 0x28
|
||||
uint32_t volatile STATUS; // 0x0c 0x2c
|
||||
uint32_t volatile ALARM; // 0x30
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
_Static_assert(sizeof(struct TIMER_REGS) == 0x14, "TIMER_REGS is the wrong size");
|
||||
|
||||
#define TIMER_FRC1_MAX_LOAD 0x7fffff
|
||||
|
||||
/* Details for LOAD registers */
|
||||
|
||||
/* Behavior for FRC1:
|
||||
*
|
||||
* When TIMER_CTRL_RELOAD is cleared in TIMER(0).CTRL, FRC1 will
|
||||
* reload to its max value once underflowed (unless the load
|
||||
* value is rewritten in the interrupt handler.)
|
||||
*
|
||||
* When TIMER_CTRL_RELOAD is set in TIMER(0).CTRL, FRC1 will reload
|
||||
* from the load register value once underflowed.
|
||||
*
|
||||
* Behavior for FRC2:
|
||||
*
|
||||
* If TIMER_CTRL_RELOAD is cleared in TIMER(1).CTRL, writing to
|
||||
* this register will update the FRC2 COUNT value.
|
||||
*
|
||||
* If TIMER_CTRL_RELOAD is set in TIMER(1).CTRL, the behaviour
|
||||
* appears to be the same except that writing 0 to the load register
|
||||
* both sets the COUNT register to 0 and disables the timer, even if
|
||||
* the TIMER_CTRL_RUN bit is set.
|
||||
*
|
||||
* Offsets 0x34, 0x38, 0x3c all seem to read back the LOAD_REG value
|
||||
* also (but have no known function.)
|
||||
*/
|
||||
|
||||
/* Details for CTRL registers */
|
||||
|
||||
/* Observed behaviour is like this:
|
||||
*
|
||||
* * When TIMER_CTRL_INT_HOLD is set, the interrupt status bit
|
||||
* TIMER_CTRL_INT_STATUS remains set when the timer interrupt
|
||||
* triggers, unless manually cleared by writing 0 to
|
||||
* TIMER(x).STATUS. While the interrupt status bit stays set
|
||||
* the timer will continue to run normally, but the interrupt
|
||||
* (INUM_TIMER_FRC1 or INUM_TIMER_FRC2) won't trigger again.
|
||||
*
|
||||
* * When TIMER_CTRL_INT_HOLD is cleared (default), there's no need to
|
||||
* manually write to TIMER(x).STATUS. The interrupt status bit
|
||||
* TIMER_CTRL_INT_STATUS automatically clears after the interrupt
|
||||
* triggers, and the interrupt handler will run again
|
||||
* automatically.
|
||||
*/
|
||||
|
||||
/* The values for TIMER_CTRL_CLKDIV control how many CPU clock cycles amount to
|
||||
* one timer clock cycle. For valid values, see the timer_clkdiv_t enum below.
|
||||
*/
|
||||
|
||||
/* TIMER_CTRL_INT_STATUS gets set when interrupt fires, and cleared on a write
|
||||
* to TIMER(x).STATUS (or cleared automatically if TIMER_CTRL_INT_HOLD is not
|
||||
* set).
|
||||
*/
|
||||
|
||||
#define TIMER_CTRL_INT_HOLD BIT(0)
|
||||
#define TIMER_CTRL_CLKDIV_M 0x00000003
|
||||
#define TIMER_CTRL_CLKDIV_S 2
|
||||
#define TIMER_CTRL_RELOAD BIT(6)
|
||||
#define TIMER_CTRL_RUN BIT(7)
|
||||
#define TIMER_CTRL_INT_STATUS BIT(8)
|
||||
|
||||
typedef enum {
|
||||
TIMER_CLKDIV_1 = 0,
|
||||
TIMER_CLKDIV_16 = 1,
|
||||
TIMER_CLKDIV_256 = 2,
|
||||
} timer_clkdiv_t;
|
||||
|
||||
/* Details for STATUS registers */
|
||||
|
||||
/* Reading this register always returns the value in
|
||||
* TIMER(x).LOAD
|
||||
*
|
||||
* Writing zero to this register clears the FRC1
|
||||
* interrupt status.
|
||||
*/
|
||||
|
||||
/* Details for FRC2.ALARM register */
|
||||
|
||||
/* Interrupt match value for FRC2. When COUNT == ALARM,
|
||||
the interrupt fires.
|
||||
*/
|
||||
|
||||
#endif /* _ESP_TIMER_REGS_H */
|
||||
Loading…
Reference in a new issue