Clean up PendSV/SV ISR
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					 2 changed files with 39 additions and 71 deletions
				
			
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			@ -76,10 +76,6 @@
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#include "task.h"
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#include "xtensa_rtos.h"
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static char HdlMacSig = 0;
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static char SWReq = 0;
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static char PendSvIsPosted = 0;
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unsigned cpu_sr;
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char level1_int_disabled;
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			@ -111,86 +107,66 @@ pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *p
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    return sp;
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}
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enum SVC_ReqType {
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  SVC_Software = 1,
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  SVC_MACLayer = 2,
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};
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static int pending_soft_sv;
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static int pending_maclayer_sv;
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static int pending_sv_posted;
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/* PendSV is called in place of vPortYield() to request a supervisor
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   call.
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   The portYIELD macro calls pendSV if it's a software request.
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   The libpp and libudhcp libraries also call this function, assuming
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   always with arg==2 (but maybe sometimes with arg==1?)
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   In the original esp_iot_rtos_sdk implementation, arg was a char. Using an
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   enum is ABI-compatible, though.
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*/
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void PendSV( char req )
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{
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	vPortEnterCritical();
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	if(req ==1)
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	if(req == SVC_Software)
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	{
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		SWReq = 1;
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		pending_soft_sv = 1;
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	}
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	else if(req ==2)
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		HdlMacSig= 1;
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	else if(req == SVC_MACLayer)
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		pending_maclayer_sv= 1;
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	if(PendSvIsPosted == 0)
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	if(pending_sv_posted == 0)
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	{
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		PendSvIsPosted = 1;
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		pending_sv_posted = 1;
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		xthal_set_intset(1<<ETS_SOFT_INUM);
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	}
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	vPortExitCritical();
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}
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/* This ISR is defined in libpp.a, and is called after a Blob SV
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 * requests a soft interrupt. Something to do with the MAC layer?
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   External blobs can trigger a MAC layer interrupt by calling PendSV
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   with req==2 (see below), which then calls back into this function
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   from the interrupt context.
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   I _think_ this may be the function which sets NMIIrqIsOn, but I'm
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   not sure about that (see also portmacro.h).
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*/
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/* This MAC layer ISR handler is defined in libpp.a, and is called
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 * after a Blob SV requests a soft interrupt by calling
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 * PendSV(SVC_MACLayer).
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 */
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extern portBASE_TYPE MacIsrSigPostDefHdl(void);
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#if 0
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void IRAM_FUNC_ATTR
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GPIOIntrHdl(void)
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{
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//if( (GPIO_REG_READ(GPIO_STATUS_ADDRESS) & (1<<6)) == 0 )
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	//printf("i");
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	//printf("g,%08x\n",GPIO_REG_READ(GPIO_STATUS_ADDRESS));
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//SDIO_CLK GPIO interrupt
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	if( (GPIO_REG_READ(GPIO_STATUS_ADDRESS) & (1<<6)) != 0 )
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	{
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		//CloseNMI();
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		portBASE_TYPE xHigherPriorityTaskWoken=pdFALSE ;
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		if(HdlMacSig == 1)
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		{
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			HdlMacSig = 0;
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			xHigherPriorityTaskWoken = MacIsrSigPostDefHdl();
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		}
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		if( xHigherPriorityTaskWoken || (SWReq==1)) 
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		{
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			SWReq = 0;
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			_xt_timer_int1();
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		}
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		//OpenNMI();
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		GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, 0x40);
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	}
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}
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#else
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void SoftIsrHdl(void)
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void SV_ISR(void)
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{
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//if(DbgVal5==1)
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	//printf("GP_%d,",SWReq);
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	PendSvIsPosted = 0;
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	pending_sv_posted = 0;
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	portBASE_TYPE xHigherPriorityTaskWoken=pdFALSE ;
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	if(HdlMacSig == 1)
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	if(pending_maclayer_sv)
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	{
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		xHigherPriorityTaskWoken = MacIsrSigPostDefHdl();
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		HdlMacSig = 0;
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		pending_maclayer_sv = 0;
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	}
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	if( xHigherPriorityTaskWoken || (SWReq==1)) 
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	if( xHigherPriorityTaskWoken || pending_soft_sv)
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	{
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//if( DbgVal5==1 || DbgVal10==1 )
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	//printf("_x_s,");
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		_xt_timer_int1();
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		SWReq = 0;
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	    _xt_timer_int1();
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	    pending_soft_sv = 0;
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	}
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}
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#endif
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void xPortSysTickHandle (void)
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{
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			@ -211,17 +187,9 @@ void xPortSysTickHandle (void)
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portBASE_TYPE ICACHE_FLASH_ATTR
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xPortStartScheduler( void )
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{
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	//set pendsv and systemtick as lowest priority ISR.
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	//pendsv setting
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			/*******GPIO sdio_clk isr*********/
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#if 0
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    _xt_isr_attach(ETS_GPIO_INUM, GPIOIntrHdl);
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    _xt_isr_unmask(1<<ETS_GPIO_INUM);
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#else
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			/*******software isr*********/
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   	_xt_isr_attach(ETS_SOFT_INUM, SoftIsrHdl);
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    //set SV and systemtick as lowest priority ISR.
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    _xt_isr_attach(ETS_SOFT_INUM, SV_ISR);
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    _xt_isr_unmask(1<<ETS_SOFT_INUM);
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#endif
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    /* Initialize system tick timer interrupt and schedule the first tick. */
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    _xt_tick_timer_init();
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			@ -108,7 +108,7 @@ typedef unsigned int INT32U;
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#define ICACHE_FLASH_ATTR __attribute__((section(".irom0.text")))
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/* Scheduler utilities. */
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extern void PendSV(char req);
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extern void PendSV(char);
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//#define portYIELD()	vPortYield()
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#define portYIELD()	PendSV(1)
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