Simplify linker script to remove preprocessing, not check flash sizes

Memory layout is now split into two linker scripts for OTA vs
non-OTA (different starting offsets), remaining functionality in
common.ld.

As discussed in #64, progress towards #38
This commit is contained in:
Angus Gratton 2015-11-13 12:11:37 +11:00
parent fbea34b07a
commit e8eac9614d
5 changed files with 60 additions and 67 deletions

View file

@ -131,8 +131,12 @@ endif
GITSHORTREV=\"$(shell cd $(ROOT); git rev-parse --short -q HEAD)\" GITSHORTREV=\"$(shell cd $(ROOT); git rev-parse --short -q HEAD)\"
CPPFLAGS += -DGITSHORTREV=$(GITSHORTREV) -DFLASH_SIZE=$(FLASH_SIZE) CPPFLAGS += -DGITSHORTREV=$(GITSHORTREV) -DFLASH_SIZE=$(FLASH_SIZE)
# Linker scripts, all found in $(ROOT)/ld ifeq ($(OTA),0)
LINKER_SCRIPTS = eagle.app.v6.ld eagle.rom.addr.v6.ld LINKER_SCRIPTS = $(ROOT)ld/nonota.ld
else
LINKER_SCRIPTS = $(ROOT)ld/ota.ld
endif
LINKER_SCRIPTS += $(ROOT)ld/common.ld $(ROOT)ld/rom.ld
#### ####
#### no user configurable options below here #### no user configurable options below here
@ -152,19 +156,11 @@ lc = $(subst A,a,$(subst B,b,$(subst C,c,$(subst D,d,$(subst E,e,$(subst F,f,$(s
# assume the program dir is the directory the top-level makefile was run in # assume the program dir is the directory the top-level makefile was run in
PROGRAM_DIR := $(dir $(firstword $(MAKEFILE_LIST))) PROGRAM_DIR := $(dir $(firstword $(MAKEFILE_LIST)))
# linker scripts get run through the C preprocessor
ifeq ($(OTA),1)
LD_DIR = $(BUILD_DIR)ld-$(FLASH_SIZE)-ota/
else
LD_DIR = $(BUILD_DIR)ld-$(FLASH_SIZE)/
endif
LINKER_SCRIPTS_PROCESSED = $(addprefix $(LD_DIR),$(LINKER_SCRIPTS))
# derive various parts of compiler/linker arguments # derive various parts of compiler/linker arguments
SDK_LIB_ARGS = $(addprefix -l,$(SDK_LIBS)) SDK_LIB_ARGS = $(addprefix -l,$(SDK_LIBS))
LIB_ARGS = $(addprefix -l,$(LIBS)) LIB_ARGS = $(addprefix -l,$(LIBS))
PROGRAM_OUT = $(BUILD_DIR)$(PROGRAM).out PROGRAM_OUT = $(BUILD_DIR)$(PROGRAM).out
LDFLAGS += $(addprefix -T,$(LINKER_SCRIPTS_PROCESSED)) LDFLAGS += $(addprefix -T,$(LINKER_SCRIPTS))
ifeq ($(OTA),0) ifeq ($(OTA),0)
# for non-OTA, we create two different files for uploading into the flash # for non-OTA, we create two different files for uploading into the flash
@ -335,16 +331,12 @@ $(foreach component,$(COMPONENTS), \
) \ ) \
) )
## Run linker scripts via C preprocessor to evaluate macros
$(LD_DIR)%.ld: $(ROOT)ld/%.ld | $(LD_DIR)
$(Q) $(CPP) $(CPPFLAGS) -E -C -P $< > $@
# final linking step to produce .elf # final linking step to produce .elf
$(PROGRAM_OUT): $(COMPONENT_ARS) $(SDK_PROCESSED_LIBS) $(LINKER_SCRIPTS_PROCESSED) $(PROGRAM_OUT): $(COMPONENT_ARS) $(SDK_PROCESSED_LIBS) $(LINKER_SCRIPTS)
$(vecho) "LD $@" $(vecho) "LD $@"
$(Q) $(LD) $(LDFLAGS) -Wl,--start-group $(COMPONENT_ARS) $(LIB_ARGS) $(SDK_LIB_ARGS) -Wl,--end-group -o $@ $(Q) $(LD) $(LDFLAGS) -Wl,--start-group $(COMPONENT_ARS) $(LIB_ARGS) $(SDK_LIB_ARGS) -Wl,--end-group -o $@
$(BUILD_DIR) $(FW_BASE) $(BUILD_DIR)sdklib $(LD_DIR): $(BUILD_DIR) $(FW_BASE) $(BUILD_DIR)sdklib:
$(Q) mkdir -p $@ $(Q) mkdir -p $@
$(FW_FILE_1) $(FW_FILE_2): $(PROGRAM_OUT) $(FW_BASE) $(FW_FILE_1) $(FW_FILE_2): $(PROGRAM_OUT) $(FW_BASE)

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@ -1,6 +1,6 @@
/* This linker script generated from xt-genldscripts.tpp for LSP . /*
* Common (OTA and non-OTA) parts for the esp-open-rtos Linker Script
Modified for esp open RTOS, this linker script is no longer the same as the esp_iot_rtos_sdk one. *
*/ */
/* FreeRTOS memory management functions /* FreeRTOS memory management functions
@ -28,43 +28,6 @@ _lock_release_recursive = vPortExitCritical;
/* SDK compatibility */ /* SDK compatibility */
ets_printf = printf; ets_printf = printf;
/* Evaluate FLASH_SIZE to calculate irom size, etc.
*/
#ifndef OTA
/* IROM0 section sits after other sections in the "v1" non-OTA bootloader image,
so need an 128kB offset to leave room
*/
#define IROM0_OFFSET 0x20000
#else /* OTA */
/* For OTA, IROM0 becomes an actual "section" of the bootloader image,
so we only need to leave space for the second stage bootloader
(0x2000 bytes) and space for the bootloader & section headers (0x10
bytes) */
#define IROM0_OFFSET 0x2010
#if FLASH_SIZE < 16
#error "OTA support currently requires minimum 16 megabit flash"
#endif
#endif
/* Full maximum length of IROM section is length of mappable flash (ie up to 1 megabyte),
minus anything mapped at start, minus single config SDK WiFi config sector at end
*/
#define IROM0_LEN ((0x20000*MIN(FLASH_SIZE,8)) - IROM0_OFFSET - 0x1000)
/* Linker Script for ld -N */
MEMORY
{
dport0_0_seg : org = 0x3FF00000, len = 0x10
dram0_0_seg : org = 0x3FFE8000, len = 0x14000
iram1_0_seg : org = 0x40100000, len = 0x08000
irom0_0_seg : org = 0x40200000+IROM0_OFFSET, len = IROM0_LEN
}
PHDRS PHDRS
{ {
dport0_0_phdr PT_LOAD; dport0_0_phdr PT_LOAD;

15
ld/nonota.ld Normal file
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@ -0,0 +1,15 @@
/* Memory layout for esp-open-rtos when not using OTA
(ie ROM bootloader only, no second stage rboot)
*/
MEMORY
{
dport0_0_seg : org = 0x3FF00000, len = 0x10
dram0_0_seg : org = 0x3FFE8000, len = 0x14000
iram1_0_seg : org = 0x40100000, len = 0x08000
/* irom0 section, mapped from SPI flash
- Origin is offset by 0x20000 to leave space for bootloader RAM sections.
- Length is max 8Mbit of mappable flash, minus start offset
*/
irom0_0_seg : org = 0x40220000, len = (1M - 0x20000)
}

15
ld/ota.ld Normal file
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@ -0,0 +1,15 @@
/* Memory layout for esp-open-rtos when using OTA second stage bootloader */
MEMORY
{
dport0_0_seg : org = 0x3FF00000, len = 0x10
dram0_0_seg : org = 0x3FFE8000, len = 0x14000
iram1_0_seg : org = 0x40100000, len = 0x08000
/* irom0 section, mapped from SPI flash
- Origin is offset by 0x2010 to create spacer for second stage bootloader image,
header.
- Length is max 8Mbit of mappable flash, minus start offset
*/
irom0_0_seg : org = 0x40202010, len = (1M - 0x2010)
}

View file

@ -1,3 +1,11 @@
/* Linker script containing Boot ROM functions for ESP8266
For more information, see:
http://esp8266-re.foogod.com/wiki/Boot_ROM
https://github.com/jcmvbkbc/esp-elf-rom/
*/
PROVIDE ( SPI_sector_erase = 0x400040c0 ); PROVIDE ( SPI_sector_erase = 0x400040c0 );
PROVIDE ( SPI_page_program = 0x40004174 ); PROVIDE ( SPI_page_program = 0x40004174 );
PROVIDE ( SPI_read_data = 0x400042ac ); PROVIDE ( SPI_read_data = 0x400042ac );
@ -8,22 +16,22 @@ PROVIDE ( Wait_SPI_Idle = 0x4000448c );
PROVIDE ( Enable_QMode = 0x400044c0 ); PROVIDE ( Enable_QMode = 0x400044c0 );
PROVIDE ( Disable_QMode = 0x40004508 ); PROVIDE ( Disable_QMode = 0x40004508 );
/* When using OTA, Cache_Read_Enable is defined in extras/rboot-ota so
the ROM Cache_Read_Enable isn't picked up from here. However we
also provide access to the ROM function in all cases, via the name
rom_Cache_Read_Enable */
PROVIDE ( rom_Cache_Read_Enable = 0x40004678 ); PROVIDE ( rom_Cache_Read_Enable = 0x40004678 );
PROVIDE ( Cache_Read_Enable = rom_Cache_Read_Enable );
PROVIDE ( Cache_Read_Disable = 0x400047f0 ); PROVIDE ( Cache_Read_Disable = 0x400047f0 );
#ifndef OTA
/* If not building an OTA image for boot, can use the default (simple)
cache enable function from ROM.
Otherwise, we need an OTA-aware one (see extras/rboot-ota/rboot-cache.S)
*/
Cache_Read_Enable = rom_Cache_Read_Enable;
#endif
PROVIDE ( lldesc_build_chain = 0x40004f40 ); PROVIDE ( lldesc_build_chain = 0x40004f40 );
PROVIDE ( lldesc_num2link = 0x40005050 ); PROVIDE ( lldesc_num2link = 0x40005050 );
PROVIDE ( lldesc_set_owner = 0x4000507c ); PROVIDE ( lldesc_set_owner = 0x4000507c );
/* TODO: Nearly everything below here is probably provided by the
libc, so never linked in, and can therefore be removed. */
PROVIDE ( __adddf3 = 0x4000c538 ); PROVIDE ( __adddf3 = 0x4000c538 );
PROVIDE ( __addsf3 = 0x4000c180 ); PROVIDE ( __addsf3 = 0x4000c180 );
PROVIDE ( __divdf3 = 0x4000cb94 ); PROVIDE ( __divdf3 = 0x4000cb94 );