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First half of moving custom synchronisation primitive API to standard FreeRTOS

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This commit is contained in:
Angus Gratton 2015-05-06 20:41:49 +10:00
parent a63d6b61c9
commit de4855b86c
2 changed files with 32 additions and 53 deletions
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41
FreeRTOS/Source/portable/esp8266/port.c
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@ -81,6 +81,7 @@ static char SWReq = 0;
static char PendSvIsPosted = 0;
unsigned cpu_sr;
char level1_int_disabled;
/* Each task maintains its own interrupt status in the critical nesting
variable. */
@ -263,71 +264,31 @@ vPortEndScheduler( void )
/*-----------------------------------------------------------*/
static unsigned int tick_lock=0;
static char ClosedLv1Isr = 0;
void vPortEnterCritical( void )
{
if(NMIIrqIsOn == 0)
{
//if( uxCriticalNesting == 0 )
{
if( ClosedLv1Isr !=1 )
{
portDISABLE_INTERRUPTS();
ClosedLv1Isr = 1;
}
//tick_lock = WDEV_NOW();
}
uxCriticalNesting++;
}
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
if(NMIIrqIsOn == 0)
{
uxCriticalNesting--;
if( uxCriticalNesting == 0 )
{
//if( (WDEV_NOW() - tick_lock) > 2000000 )
//printf("INTR LOCK TOO LONG:%d\n",(WDEV_NOW() - tick_lock));
if( ClosedLv1Isr ==1 )
{
ClosedLv1Isr = 0;
portENABLE_INTERRUPTS();
}
}
}
}
void
PortDisableInt_NoNest( void )
{
//os_printf("ERRRRRRR\n");
if(NMIIrqIsOn == 0)
{
if( ClosedLv1Isr !=1 )
{
portDISABLE_INTERRUPTS();
ClosedLv1Isr = 1;
}
}
}
void
PortEnableInt_NoNest( void )
{
//os_printf("ERRRRR\n");
if(NMIIrqIsOn == 0)
{
if( ClosedLv1Isr ==1 )
{
ClosedLv1Isr = 0;
portENABLE_INTERRUPTS();
}
}
}
/*-----------------------------------------------------------*/

26
FreeRTOS/Source/portable/esp8266/portmacro.h
View file

@ -131,7 +131,6 @@ extern void vTaskSwitchContext( void ); \
/*-----------------------------------------------------------*/
extern unsigned cpu_sr;
/* Critical section management. */
extern void vPortEnterCritical( void );
@ -141,12 +140,31 @@ extern void vPortExitCritical( void );
void PortDisableInt_NoNest( void );
void PortEnableInt_NoNest( void );
extern char NMIIrqIsOn;
extern char level1_int_disabled;
extern unsigned cpu_sr;
inline static __attribute__((always_inline)) void _esp_disable_interrupts(void)
{
if(!NMIIrqIsOn && !level1_int_disabled) {
__asm__ volatile ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) : "=a" (cpu_sr) :: "memory");
level1_int_disabled = 1;
}
}
inline static __attribute__((always_inline)) void _esp_enable_interrupts(void)
{
if(!NMIIrqIsOn && level1_int_disabled) {
level1_int_disabled = 0;
__asm__ volatile ("wsr %0, ps" :: "a" (cpu_sr) : "memory");
}
}
/* Disable interrupts, saving previous state in cpu_sr */
#define portDISABLE_INTERRUPTS() \
__asm__ volatile ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) : "=a" (cpu_sr) :: "memory")
#define portDISABLE_INTERRUPTS() _esp_disable_interrupts()
/* Restore interrupts to previous level saved in cpu_sr */
#define portENABLE_INTERRUPTS() __asm__ volatile ("wsr %0, ps" :: "a" (cpu_sr) : "memory")
#define portENABLE_INTERRUPTS() _esp_enable_interrupts()
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()