Misc port.c cleanup, remove now-unused PortxxxInt_NoNest, comment misc bits of blob interface
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1 changed files with 25 additions and 49 deletions
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@ -63,19 +63,19 @@
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*/
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*/
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/*-----------------------------------------------------------
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the ARM CM3 port.
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* Implementation of functions defined in portable.h for ESP8266
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*
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* This is based on the version supplied in esp_iot_rtos_sdk,
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* which is in turn based on the ARM CM3 port.
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*----------------------------------------------------------*/
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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/* Scheduler includes. */
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#include <xtensa/config/core.h>
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#include <xtensa/config/core.h>
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//#include <xtensa/tie/xt_interrupt.h>
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#include "FreeRTOS.h"
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#include "FreeRTOS.h"
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#include "task.h"
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#include "task.h"
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#include "xtensa_rtos.h"
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#include "xtensa_rtos.h"
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extern char NMIIrqIsOn;
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static char HdlMacSig = 0;
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static char HdlMacSig = 0;
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static char SWReq = 0;
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static char SWReq = 0;
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static char PendSvIsPosted = 0;
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static char PendSvIsPosted = 0;
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@ -83,23 +83,17 @@ static char PendSvIsPosted = 0;
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unsigned cpu_sr;
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unsigned cpu_sr;
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char level1_int_disabled;
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char level1_int_disabled;
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/* Each task maintains its own interrupt status in the critical nesting
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variable. */
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static unsigned portBASE_TYPE uxCriticalNesting = 0;
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void vPortEnterCritical( void );
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void vPortExitCritical( void );
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/*
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/*
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* See header file for description.
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* Stack initialization
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*/
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*/
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portSTACK_TYPE * ICACHE_FLASH_ATTR
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portSTACK_TYPE *
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pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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{
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{
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#define SET_STKREG(r,v) sp[(r) >> 2] = (portSTACK_TYPE)(v)
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#define SET_STKREG(r,v) sp[(r) >> 2] = (portSTACK_TYPE)(v)
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portSTACK_TYPE *sp, *tp;
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portSTACK_TYPE *sp, *tp;
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/* Create interrupt stack frame aligned to 16 byte boundary */
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/* Create interrupt stack frame aligned to 16 byte boundary */
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sp = (portSTACK_TYPE*) (((INT32U)(pxTopOfStack+1) - XT_CP_SIZE - XT_STK_FRMSZ) & ~0xf);
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sp = (portSTACK_TYPE*) (((uint32_t)(pxTopOfStack+1) - XT_CP_SIZE - XT_STK_FRMSZ) & ~0xf);
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/* Clear the entire frame (do not use memset() because we don't depend on C library) */
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/* Clear the entire frame (do not use memset() because we don't depend on C library) */
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for (tp = sp; tp <= pxTopOfStack; ++tp)
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for (tp = sp; tp <= pxTopOfStack; ++tp)
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@ -108,33 +102,19 @@ pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *p
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/* Explicitly initialize certain saved registers */
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/* Explicitly initialize certain saved registers */
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SET_STKREG( XT_STK_PC, pxCode ); /* task entrypoint */
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SET_STKREG( XT_STK_PC, pxCode ); /* task entrypoint */
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SET_STKREG( XT_STK_A0, 0 ); /* to terminate GDB backtrace */
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SET_STKREG( XT_STK_A0, 0 ); /* to terminate GDB backtrace */
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SET_STKREG( XT_STK_A1, (INT32U)sp + XT_STK_FRMSZ ); /* physical top of stack frame */
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SET_STKREG( XT_STK_A1, (uint32_t)sp + XT_STK_FRMSZ ); /* physical top of stack frame */
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SET_STKREG( XT_STK_A2, pvParameters ); /* parameters */
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SET_STKREG( XT_STK_A2, pvParameters ); /* parameters */
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SET_STKREG( XT_STK_EXIT, _xt_user_exit ); /* user exception exit dispatcher */
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SET_STKREG( XT_STK_EXIT, _xt_user_exit ); /* user exception exit dispatcher */
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/* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
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/* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
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#ifdef __XTENSA_CALL0_ABI__
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SET_STKREG( XT_STK_PS, PS_UM | PS_EXCM );
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SET_STKREG( XT_STK_PS, PS_UM | PS_EXCM );
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#else
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return sp;
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/* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
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SET_STKREG( XT_STK_PS, PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1) );
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#endif
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return sp;
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}
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}
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void PendSV( char req )
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void PendSV( char req )
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{
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{
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char tmp=0;
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vPortEnterCritical();
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//ETS_INTR_LOCK();
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if( NMIIrqIsOn == 0 )
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{
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vPortEnterCritical();
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//PortDisableInt_NoNest();
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tmp = 1;
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}
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if(req ==1)
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if(req ==1)
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{
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{
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@ -142,19 +122,25 @@ void PendSV( char req )
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}
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}
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else if(req ==2)
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else if(req ==2)
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HdlMacSig= 1;
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HdlMacSig= 1;
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#if 0
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GPIO_REG_WRITE(GPIO_STATUS_W1TS_ADDRESS, 0x40);
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#else
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if(PendSvIsPosted == 0)
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if(PendSvIsPosted == 0)
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{
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{
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PendSvIsPosted = 1;
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PendSvIsPosted = 1;
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xthal_set_intset(1<<ETS_SOFT_INUM);
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xthal_set_intset(1<<ETS_SOFT_INUM);
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}
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}
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#endif
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vPortExitCritical();
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if(tmp == 1)
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vPortExitCritical();
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}
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}
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/* This ISR is defined in libpp.a, and is called after a Blob SV
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* requests a soft interrupt. Something to do with the MAC layer?
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External blobs can trigger a MAC layer interrupt by calling PendSV
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with req==2 (see below), which then calls back into this function
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from the interrupt context.
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I _think_ this may be the function which sets NMIIrqIsOn, but I'm
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not sure about that (see also portmacro.h).
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*/
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extern portBASE_TYPE MacIsrSigPostDefHdl(void);
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extern portBASE_TYPE MacIsrSigPostDefHdl(void);
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#if 0
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#if 0
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void IRAM_FUNC_ATTR
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void IRAM_FUNC_ATTR
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@ -263,7 +249,9 @@ vPortEndScheduler( void )
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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static unsigned int tick_lock=0;
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/* Each task maintains its own interrupt status in the critical nesting
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variable. */
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static unsigned portBASE_TYPE uxCriticalNesting = 0;
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void vPortEnterCritical( void )
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void vPortEnterCritical( void )
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{
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{
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@ -279,18 +267,6 @@ void vPortExitCritical( void )
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portENABLE_INTERRUPTS();
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portENABLE_INTERRUPTS();
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}
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}
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void
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PortDisableInt_NoNest( void )
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{
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portDISABLE_INTERRUPTS();
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}
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void
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PortEnableInt_NoNest( void )
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{
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portENABLE_INTERRUPTS();
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}
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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_xt_isr isr[16];
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_xt_isr isr[16];
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