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Merge branch 'master' into open-libmain

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This commit is contained in:
Angus Gratton 2016-06-30 09:09:27 +10:00
commit d8bcb5d702
65 changed files with 3272 additions and 739 deletions
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30
core/include/xtensa_ops.h
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@ -11,27 +11,12 @@
#ifndef _XTENSA_OPS_H
#define _XTENSA_OPS_H
// GCC macros for reading, writing, and exchanging Xtensa processor special
// registers:
#define RSR(var, reg) asm volatile ("rsr %0, " #reg : "=r" (var))
#define WSR(var, reg) asm volatile ("wsr %0, " #reg : : "r" (var))
#define XSR(var, reg) asm volatile ("xsr %0, " #reg : "+r" (var))
// GCC macros for performing associated "*sync" opcodes
#define ISYNC() asm volatile ( "isync" )
#define RSYNC() asm volatile ( "rsync" )
#define ESYNC() asm volatile ( "esync" )
#define DSYNC() asm volatile ( "dsync" )
/* Read stack pointer to variable.
*
* Note that the compiler will push a stack frame (minimum 16 bytes)
* in the prelude of a C function that calls any other functions.
*/
#define SP(var) asm volatile ("mov %0, a1" : "=r" (var));
#define SP(var) asm volatile ("mov %0, a1" : "=r" (var))
/* Read the function return address to a variable.
*
@ -40,4 +25,17 @@
*/
#define RETADDR(var) asm volatile ("mov %0, a0" : "=r" (var))
/* GCC macros for reading, writing, and exchanging Xtensa processor special
* registers:
*/
#define RSR(var, reg) asm volatile ("rsr %0, " #reg : "=r" (var));
#define WSR(var, reg) asm volatile ("wsr %0, " #reg : : "r" (var));
#define XSR(var, reg) asm volatile ("xsr %0, " #reg : "+r" (var));
// GCC macros for performing associated "*sync" opcodes
#define ISYNC() asm volatile ( "isync" )
#define RSYNC() asm volatile ( "rsync" )
#define ESYNC() asm volatile ( "esync" )
#define DSYNC() asm volatile ( "dsync" )
#endif /* _XTENSA_OPS_H */