Merge branch 'master' into open-libmain

core/include/common_macros.h

@@ -37,15 +37,71 @@
 #define VAL2FIELD_M(fieldname, value) (((value) & fieldname##_M) << fieldname##_S)
 #define SET_FIELD_M(regbits, fieldname, value) (((regbits) & ~FIELD_MASK(fieldname)) | VAL2FIELD_M(fieldname, value))
 
-/* Use this macro to store constant values in IROM flash instead
-   of having them loaded into rodata (which resides in DRAM)
+/* Use the IRAM macro to place functions into Instruction RAM (IRAM)
+   instead of flash (aka irom).
 
-   Unlike the ESP8266 SDK you don't need an attribute like this for
-   standard functions. They're stored in flash by default. But
-   variables need them.
+   (This is the opposite to the Espressif SDK, where functions default
+   to being placed in IRAM but the ICACHE_FLASH_ATTR attribute will
+   place them in flash.)
 
-   Important to note: IROM flash can only be accessed via 32-bit word
-   aligned reads. It's up to the user of this attribute to ensure this.
+   Use the IRAM attribute for functions which are called when the
+   flash may not be available (for example during NMI exceptions), or
+   for functions which are called very frequently and need high
+   performance.
+
+   Usage example:
+
+   void IRAM high_performance_function(void)
+   {
+       // do important thing here
+   }
+
+   Bear in mind IRAM is limited (32KB), compared to up to 1MB of flash.
+*/
+#define IRAM __attribute__((section(".iram1.text")))
+
+/* Use the RAM macro to place constant data (rodata) into RAM (data
+   RAM) instead of the default placement in flash. This is useful for
+   constant data which needs high performance access.
+
+   Usage example:
+
+   const RAM uint8_t constants[] = { 1, 2, 3, 7 };
+
+   When placing string literals in RAM, they need to be declared with
+   the type "const char[]" not "const char *"
+
+   Usage example:
+
+   const RAM char hello_world[] = "Hello World";
+*/
+#define RAM __attribute__((section(".data")))
+
+/* Use the IRAM_DATA macro to place data into Instruction RAM (IRAM)
+   instead of the default of flash (for constant data) or data RAM
+   (for non-constant data).
+
+   This may be useful to free up data RAM. However all data read from
+   any instruction space (either IRAM or Flash) must be 32-bit aligned
+   word reads. Reading unaligned data stored with IRAM_DATA will be
+   slower than reading data stored in RAM. You can't perform unaligned
+   writes to IRAM.
+*/
+#define IRAM_DATA __attribute__((section(".iram1.data")))
+
+/* Use the IROM macro to store constant values in IROM flash. In
+  esp-open-rtos this is already the default location for most constant
+  data (rodata), so you don't need this attribute in 99% of cases.
+
+  The exceptions are to mark data in the core & freertos libraries,
+  where the default for constant data storage is RAM.
+
+  (Unlike the Espressif SDK you don't need to use an attribute like
+  ICACHE_FLASH_ATTR for functions, they go into flash by default.)
+
+  Important to note: IROM flash is accessed via 32-bit word aligned
+  reads. esp-open-rtos does some magic to "fix" unaligned reads, but
+  performance is reduced.
 */
 #ifdef	__cplusplus
     #define IROM __attribute__((section(".irom0.literal")))
@@ -53,30 +109,5 @@
     #define IROM __attribute__((section(".irom0.literal"))) const
 #endif
 
-/* Use this macro to place functions into Instruction RAM (IRAM)
-   instead of flash memory (IROM).
-
-   This is useful for functions which are called when the flash may
-   not be available (for example during NMI exceptions), or for
-   functions which are called very frequently and need high
-   performance.
-
-   Bear in mind IRAM is limited (32KB), compared to up to 1MB of flash.
-*/
-#define IRAM __attribute__((section(".iram1.text")))
-
-/* Use this macro to place read-only data into Instruction RAM (IRAM)
-   instead of loaded into rodata which resides in DRAM.
-
-   This may be useful to free up data RAM. However all data read from
-   the instruction space must be 32-bit aligned word reads
-   (non-aligned reads will use an interrupt routine to "fix" them and
-   still work, but are very slow..
-*/
-#ifdef	__cplusplus
-    #define IRAM_DATA __attribute__((section(".iram1.rodata")))
-#else
-    #define IRAM_DATA __attribute__((section(".iram1.rodata"))) const
-#endif
 
 #endif

core/include/debug_dumps.h

@@ -10,9 +10,12 @@
 #define _DEBUG_DUMPS_H
 #include <stdint.h>
 
-/* Dump stack memory starting from stack pointer address sp. */
+/* Dump stack memory to stdout, starting from stack pointer address sp. */
 void dump_stack(uint32_t *sp);
 
+/* Dump heap statistics to stdout */
+void dump_heapinfo(void);
+
 /* Called from exception_vectors.S when a fatal exception occurs.
 
    Probably not useful to be called in other contexts.

core/include/esp/gpio.h

@@ -81,9 +81,9 @@ static inline void gpio_set_output_on_sleep(const uint8_t gpio_num, bool enabled
 static inline void gpio_write(const uint8_t gpio_num, const bool set)
 {
     if (set)
-        GPIO.OUT_SET = BIT(gpio_num);
+        GPIO.OUT_SET = BIT(gpio_num) & GPIO_OUT_PIN_MASK;
     else
-        GPIO.OUT_CLEAR = BIT(gpio_num);
+        GPIO.OUT_CLEAR = BIT(gpio_num) & GPIO_OUT_PIN_MASK;
 }
 
 /* Toggle output of a pin
@@ -102,9 +102,9 @@ static inline void gpio_toggle(const uint8_t gpio_num)
        task's pins, without needing to disable/enable interrupts.
     */
     if(GPIO.OUT & BIT(gpio_num))
-        GPIO.OUT_CLEAR = BIT(gpio_num);
+        GPIO.OUT_CLEAR = BIT(gpio_num) & GPIO_OUT_PIN_MASK;
     else
-        GPIO.OUT_SET = BIT(gpio_num);
+        GPIO.OUT_SET = BIT(gpio_num) & GPIO_OUT_PIN_MASK;
 }
 
 /* Read input value of a GPIO pin.

core/include/esp/gpio_regs.h

@@ -61,6 +61,21 @@ struct GPIO_REGS {
 
 _Static_assert(sizeof(struct GPIO_REGS) == 0x74, "GPIO_REGS is the wrong size");
 
+/* Details for additional OUT register fields */
+
+/* Bottom 16 bits of GPIO.OUT are for GPIOs 0-15, but upper 16 bits
+   are used to configure the input signalling pins for Bluetooth
+   Coexistence config (see esp/phy.h for a wrapper function).
+*/
+#define GPIO_OUT_PIN_MASK 0x0000FFFF
+#define GPIO_OUT_BT_COEXIST_MASK 0x03FF0000
+#define GPIO_OUT_BT_ACTIVE_ENABLE BIT(24)
+#define GPIO_OUT_BT_PRIORITY_ENABLE BIT(25)
+#define GPIO_OUT_BT_ACTIVE_PIN_M 0x0F
+#define GPIO_OUT_BT_ACTIVE_PIN_S 16
+#define GPIO_OUT_BT_PRIORITY_PIN_M 0x0F
+#define GPIO_OUT_BT_PRIORITY_PIN_S 20
+
 /* Details for CONF[i] registers */
 
 /* GPIO.CONF[i] control the pin behavior for the corresponding GPIO in/output.

core/include/esp/phy.h

@@ -0,0 +1,58 @@
+/** esp/phy.h
+ *
+ * PHY hardware management functions.
+ *
+ * These are not enough to configure the ESP8266 PHY by themselves
+ * (yet), but they provide utilities to modify the configuration set
+ * up via the SDK.
+ *
+ * Functions implemented here deal directly with the hardware, not the
+ * SDK software layers.
+ *
+ * Part of esp-open-rtos
+ * Copyright (C) 2016 ChefSteps, Inc
+ * BSD Licensed as described in the file LICENSE
+ */
+#ifndef _ESP_PHY_H
+#define _ESP_PHY_H
+
+#include <esp/types.h>
+#include <common_macros.h>
+
+#include <stdint.h>
+
+typedef enum {
+    BT_COEXIST_NONE,
+    BT_COEXIST_USE_BT_ACTIVE,
+    BT_COEXIST_USE_BT_ACTIVE_PRIORITY,
+} bt_coexist_mode_t;
+
+/** Override the Bluetooth Coexistence BT_ACTIVE pin setting
+    taken from the phy_info structure.
+
+    This enables other pins to be used for Bluetooth Coexistence
+    signals (rather than just the two provided for by phy_info). (Note
+    that not that not all pins are confirmed to work, GPIO 0 is
+    confirmed not usable as the SDK configures it as the WLAN_ACTIVE
+    output - even if you change the pin mode the SDK will change it
+    back.)
+
+    To change pins and have coexistence work successfully the BT
+    coexistence feature must be enabled in the phy_info configuration
+    (get_default_phy_info()). You can then modify the initial
+    configuration by calling this function from your own user_init
+    function.
+
+    (Eventually we should be able to support enough PHY registers
+    to enable coexistence without SDK support at all, but not yet.)
+
+    This function will enable bt_active_pin & bt_priority_as GPIO
+    inputs, according to the mode parameter.
+
+    Remember that the default Bluetooth Coexistence pins will be
+    configured as GPIOs by the SDK already, so you may want to
+    reconfigure/re-iomux them after calling this function.
+*/
+void bt_coexist_configure(bt_coexist_mode_t mode, uint8_t bt_active_pin, uint8_t bt_priority_pin);
+
+#endif

core/include/sdk_internal.h

@@ -4,6 +4,7 @@
 #include "espressif/esp_wifi.h"
 #include "espressif/spi_flash.h"
 #include "etstimer.h"
+#include "espressif/phy_info.h"
 #include "lwip/netif.h"
 
 ///////////////////////////////////////////////////////////////////////////////
@@ -224,7 +225,7 @@ void sdk_phy_enable_agc(void);
 void sdk_pm_attach(void);
 void sdk_pp_attach(void);
 void sdk_pp_soft_wdt_init(void);
-int sdk_register_chipv6_phy(uint8_t *);
+int sdk_register_chipv6_phy(sdk_phy_info_t *);
 void sdk_sleep_reset_analog_rtcreg_8266(void);
 uint32_t sdk_system_get_checksum(uint8_t *, uint32_t);
 void sdk_wDevEnableRx(void);

core/include/xtensa_ops.h

@@ -11,27 +11,12 @@
 #ifndef _XTENSA_OPS_H
 #define _XTENSA_OPS_H
 
-// GCC macros for reading, writing, and exchanging Xtensa processor special
-// registers:
-
-#define RSR(var, reg) asm volatile ("rsr %0, " #reg : "=r" (var))
-#define WSR(var, reg) asm volatile ("wsr %0, " #reg : : "r" (var))
-#define XSR(var, reg) asm volatile ("xsr %0, " #reg : "+r" (var))
-
-// GCC macros for performing associated "*sync" opcodes
-
-#define ISYNC() asm volatile ( "isync" )
-#define RSYNC() asm volatile ( "rsync" )
-#define ESYNC() asm volatile ( "esync" )
-#define DSYNC() asm volatile ( "dsync" )
-
-
 /* Read stack pointer to variable.
  *
  * Note that the compiler will push a stack frame (minimum 16 bytes)
  * in the prelude of a C function that calls any other functions.
  */
-#define SP(var) asm volatile ("mov %0, a1" : "=r" (var));
+#define SP(var) asm volatile ("mov %0, a1" : "=r" (var))
 
 /* Read the function return address to a variable.
  *
@@ -40,4 +25,17 @@
  */
 #define RETADDR(var) asm volatile ("mov %0, a0" : "=r" (var))
 
+/* GCC macros for reading, writing, and exchanging Xtensa processor special
+ * registers:
+ */
+#define RSR(var, reg) asm volatile ("rsr %0, " #reg : "=r" (var));
+#define WSR(var, reg) asm volatile ("wsr %0, " #reg : : "r" (var));
+#define XSR(var, reg) asm volatile ("xsr %0, " #reg : "+r" (var));
+
+// GCC macros for performing associated "*sync" opcodes
+#define ISYNC() asm volatile ( "isync" )
+#define RSYNC() asm volatile ( "rsync" )
+#define ESYNC() asm volatile ( "esync" )
+#define DSYNC() asm volatile ( "dsync" )
+
 #endif /* _XTENSA_OPS_H */