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rename fix and register

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This commit is contained in:
Zaltora 2018-04-19 11:51:48 +02:00
parent 11dc6da5b8
commit a0a0cbf2da
2 changed files with 19 additions and 19 deletions
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22
core/include/esp/gpio_regs.h
View file

@ -70,7 +70,7 @@ struct GPIO_REGS {
uint32_t volatile STATUS_SET; // 0x20
uint32_t volatile STATUS_CLEAR; // 0x24
uint32_t volatile CONF[16]; // 0x28 - 0x64
uint32_t volatile PWM; // 0x68
uint32_t volatile DSM; // 0x68
uint32_t volatile RTC_CALIB; // 0x6c
uint32_t volatile RTC_CALIB_RESULT; // 0x70
};
@ -117,9 +117,9 @@ _Static_assert(sizeof(struct GPIO_REGS) == 0x74, "GPIO_REGS is the wrong size");
* GPIO_CONF_OPEN_DRAIN does not appear to work on all pins.
*
*
* GPIO_CONF_SOURCE_PWM (boolean)
* When set, GPIO pin output will be connected to the sigma-delta PWM
* generator (controlled by the GPIO.PWM register). When cleared, pin
* GPIO_CONF_SOURCE_DSM (boolean)
* When set, GPIO pin output will be connected to the sigma-delta
* generator (controlled by the GPIO.DSM register). When cleared, pin
* output will function as a normal GPIO output (controlled by the
* GPIO.OUT* registers).
*/
@ -130,7 +130,7 @@ _Static_assert(sizeof(struct GPIO_REGS) == 0x74, "GPIO_REGS is the wrong size");
#define GPIO_CONF_INTTYPE_M 0x00000007
#define GPIO_CONF_INTTYPE_S 7
#define GPIO_CONF_OPEN_DRAIN BIT(2)
#define GPIO_CONF_SOURCE_PWM BIT(0)
#define GPIO_CONF_SOURCE_DSM BIT(0)
/* Valid values for the GPIO_CONF_INTTYPE field */
typedef enum {
@ -142,13 +142,13 @@ typedef enum {
GPIO_INTTYPE_LEVEL_HIGH = 5,
} gpio_inttype_t;
/* Details for PWM register */
/* Details for DSM register */
#define GPIO_PWM_ENABLE BIT(16)
#define GPIO_PWM_PRESCALER_M 0x000000ff
#define GPIO_PWM_PRESCALER_S 8
#define GPIO_PWM_TARGET_M 0x000000ff
#define GPIO_PWM_TARGET_S 0
#define GPIO_DSM_ENABLE BIT(16)
#define GPIO_DSM_PRESCALER_M 0x000000ff
#define GPIO_DSM_PRESCALER_S 8
#define GPIO_DSM_TARGET_M 0x000000ff
#define GPIO_DSM_TARGET_S 0
/* Details for RTC_CALIB register */

16
extras/dsm/dsm.c
View file

@ -21,7 +21,7 @@ typedef struct dsmInfoDefinition
{
uint8_t running;
uint8_t preScale;
uint8_t dutyCycle;
uint8_t target;
bool output;
/* private */
@ -36,7 +36,7 @@ void dsm_init(uint8_t npins, const uint8_t* pins)
/* Assert number of pins is correct */
if (npins > MAX_DSM_PINS)
{
debug("Incorrect number of PWM pins (%d)\n", npins);
debug("Incorrect number of DSM pins (%d)\n", npins);
return;
}
@ -70,12 +70,12 @@ void dsm_set_prescale(uint8_t prescale)
// Freq = (80,000,000/prescale) * ((256 - target) / 256) HZ (128 < target < 256)
void dsm_set_target(uint8_t target)
{
dsmInfo.dutyCycle = target;
dsmInfo.target = target;
if (target == 0 || target == UINT8_MAX)
{
dsmInfo.output = (target == UINT8_MAX);
}
debug("Duty set at %u",dsmInfo.dutyCycle);
debug("Duty set at %u",dsmInfo.target);
if (dsmInfo.running)
{
dsm_start();
@ -84,13 +84,13 @@ void dsm_set_target(uint8_t target)
void dsm_start()
{
if (dsmInfo.dutyCycle > 0 && dsmInfo.dutyCycle < UINT8_MAX)
if (dsmInfo.target > 0 && dsmInfo.target < UINT8_MAX)
{
for (uint8_t i = 0; i < dsmInfo.usedPins; ++i)
{
SET_MASK_BITS(GPIO.CONF[dsmInfo.pins[i]], GPIO_CONF_SOURCE_PWM);
SET_MASK_BITS(GPIO.CONF[dsmInfo.pins[i]], GPIO_CONF_SOURCE_DSM);
}
GPIO.PWM = GPIO_PWM_ENABLE | (dsmInfo.preScale << 8) | dsmInfo.dutyCycle;
GPIO.DSM = GPIO_DSM_ENABLE | (dsmInfo.preScale << 8) | dsmInfo.target;
}
else
{
@ -107,7 +107,7 @@ void dsm_stop()
{
for (uint8_t i = 0; i < dsmInfo.usedPins; ++i)
{
CLEAR_MASK_BITS(GPIO.CONF[dsmInfo.pins[i]], GPIO_CONF_SOURCE_PWM);
CLEAR_MASK_BITS(GPIO.CONF[dsmInfo.pins[i]], GPIO_CONF_SOURCE_DSM);
gpio_write(dsmInfo.pins[i], false);
}
debug("stop");