I-RAM memory store support for 8 and 16 stores
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Our Air Quality
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1 changed files with 191 additions and 61 deletions
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@ -44,6 +44,8 @@ LoadStoreErrorHandlerStack:
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.word 0 # a2
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.word 0 # a3
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.word 0 # a4
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.word 0 # a5
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.word 0 # a6
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.balign 4
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.global debug_saved_ctx
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@ -123,7 +125,11 @@ DoubleExceptionVector:
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*
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* Called from UserExceptionVector if EXCCAUSE is LoadStoreErrorCause
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*
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* (Fast path (no branches) is for L8UI)
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* Accesses can be assumed aligned here as unaligned accesses would have generate
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* an unaligned exception (9) before getting here.
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*
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* Fast path (no branches) is for L8UI from low registers 0, 2-5, and the fast
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* store path is S8I for low registers 0, 2-7.
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*/
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.literal_position
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@ -141,6 +147,8 @@ LoadStoreErrorHandler:
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s32i a4, sp, 0x10
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rsr a0, sar # Save SAR in a0 to restore later
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# led_on a2, a3
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/* Examine the opcode which generated the exception */
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/* Note: Instructions are in this order to avoid pipeline stalls. */
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rsr a2, epc1
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@ -185,6 +193,8 @@ LoadStoreErrorHandler:
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addi a3, a3, 0x3
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wsr a3, epc1
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# led_off a0, a3
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/* Stupid opcode tricks: The jumptable we use later on needs 16 bytes
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* per entry (so we can avoid a second jump by just doing a RFE inside
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* each entry). Unfortunately, however, Xtensa doesn't have an addx16
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@ -214,25 +224,11 @@ LoadStoreErrorHandler:
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rsr a1, excsave1 # restore a1 saved by UserExceptionVector
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rfe
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.LSE_assign_reg:
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/* At this point, a2 contains the register number times 2, a4 is the
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* read value. */
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/* Calculate the jumptable address, and restore all regs except a2 and
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* a4 so we have less to do after jumping. */
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/* Note: Instructions are in this order to avoid pipeline stalls. */
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movi a3, .LSE_jumptable_base
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l32i a0, sp, 0
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addx8 a2, a2, a3 # a2 is now the address to jump to
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l32i a3, sp, 0x0c
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jx a2
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.balign 4
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.LSE_check_l16:
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/* At this point, a2 contains the opcode, a3 is masked opcode */
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movi a4, 0x001002 # l16si or l16ui opcode after masking
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bne a3, a4, .LSE_wrong_opcode
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bne a3, a4, .LSE_check_s8i
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/* Note: At this point, the opcode could be one of two things:
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* xx1xx2 (L16UI)
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@ -255,32 +251,91 @@ LoadStoreErrorHandler:
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or a4, a3, a4 # set 32-bit sign bits
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j .LSE_post_fetch
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.LSE_wrong_opcode:
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/* If we got here it's not an opcode we can try to fix, so bomb out.
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* Restore registers so any dump the fatal exception routine produces
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* will have correct values */
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wsr a0, sar
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l32i a0, sp, 0
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/*l32i a2, sp, 0x08*/
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr a1, excsave1
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mov a2, a1
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movi a3, 0
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call0 fatal_exception_handler
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.balign 4
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.LSE_assign_a1:
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/* a1 is saved in excsave1, so just update that with the value, */
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wsr a4, excsave1
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/* Then restore all regs and return */
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.LSE_check_s8i:
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/* At this point, a2 contains the opcode */
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movi a3, 0x00F00F # opcode mask for s8i/s16i
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s32i a5, sp, 0x14 # Save a5, needed for store op
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and a3, a2, a3 # a3 is masked instruction
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movi a4, 0x004002 # s8i opcode after masking
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s32i a6, sp, 0x18 # Save a6, needed for store op
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bne a3, a4, .LSE_check_s16i
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/* Note: At this point, the opcode is s8i */
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movi a5, 0x000000ff # source mask
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.LSE_store:
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/* We jump here for either S8I or S16I to get the address and load
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* and mask the current contents. */
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movi a4, ~3
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rsr a3, excvaddr # read faulting address
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and a4, a3, a4 # a4 now word aligned address
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ssa8b a3 # sar is now left shift amount
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sll a3, a5
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movi a6, 0xffffffff
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xor a6, a6, a3 # a6 now has the word mask
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l32i a3, a4, 0 # read the current word
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and a3, a3, a6 # a3 now has the masked word
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extui a2, a2, 4, 4 # a2 is now source register 0-15
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/* At this point, a2 contains the source register 0-15, a3 contains the
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* masked memory contents, a4 contains the address, a5 contains the source
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* mask, and sar contains the left shift amount. */
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bgei a2, 7, .LSE_load_reg # a7..a15 use jumptable
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beqi a2, 1, .LSE_load_a1 # a1 uses a special routine
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/* We're loading from a0 or a2..a6, which are all saved in our "stack"
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* area. Calculate the correct address and load the value there. */
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addx4 a2, a2, sp
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l32i a2, a2, 0
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.LSE_store_apply:
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and a2, a2, a5 # mask the source
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sll a2, a2 # shift the source
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or a3, a3, a2 # combine with the masked memory contents
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s32i a3, a4, 0 # write back to memory
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/* Note: Instructions are in this order to avoid pipeline stalls */
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rsr a3, epc1
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wsr a0, sar
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addi a3, a3, 0x3
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wsr a3, epc1
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# led_off a2, a3
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/* Restore all regs and return */
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l32i a0, sp, 0
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr a1, excsave1
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l32i a5, sp, 0x14
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l32i a6, sp, 0x18
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rsr a1, excsave1 # restore a1 saved by UserExceptionVector
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rfe
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.balign 4
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.LSE_check_s16i:
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/* At this point, a2 contains the opcode */
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movi a4, 0x005002 # s16i opcode after masking
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bne a3, a4, .LSE_wrong_opcode
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/* Note: At this point, the opcode is s16i */
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movi a5, 0x0000ffff # source mask
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j .LSE_store
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.balign 4
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.LSE_assign_reg:
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/* At this point, a2 contains the register number times 2, a4 is the
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* read value. */
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/* Calculate the jumptable address, and restore all regs except a2 and
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* a4 so we have less to do after jumping. */
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/* Note: Instructions are in this order to avoid pipeline stalls. */
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movi a3, .LSE_jumptable_base
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l32i a0, sp, 0
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addx8 a2, a2, a3 # a2 is now the address to jump to
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l32i a3, sp, 0x0c
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jx a2
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.balign 4
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.LSE_jumptable:
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/* The first 5 entries (80 bytes) of this table are unused (registers
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@ -366,6 +421,81 @@ LoadStoreErrorHandler:
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rsr a1, excsave1
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rfe
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.balign 4
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.LSE_assign_a1:
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/* a1 is saved in excsave1, so just update that with the value, */
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wsr a4, excsave1
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/* Then restore all regs and return */
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l32i a0, sp, 0
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.balign 4
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.LSE_load_reg:
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/* Calculate the jumptable address. */
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movi a6, .LSE_store_jumptable_base
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addx8 a2, a2, a6 # a2 is now the address to jump to
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jx a2
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.balign 4
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.LSE_store_jumptable:
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/* The first 7 entries (56 bytes) of this table are unused (registers
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* a0..a6 are handled separately above). Rather than have a whole bunch
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* of wasted space, we just pretend that the table starts 56 bytes
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* earlier in memory. */
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.set .LSE_store_jumptable_base, .LSE_store_jumptable - (8 * 7)
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mov a2, a7
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j .LSE_store_apply
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.balign 4
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mov a2, a8
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j .LSE_store_apply
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.balign 4
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mov a2, a9
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j .LSE_store_apply
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.balign 4
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mov a2, a10
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j .LSE_store_apply
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.balign 4
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mov a2, a11
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j .LSE_store_apply
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.balign 4
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mov a2, a12
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j .LSE_store_apply
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.balign 4
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mov a2, a13
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j .LSE_store_apply
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.balign 4
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mov a2, a14
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j .LSE_store_apply
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.balign 4
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mov a2, a15
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j .LSE_store_apply
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.balign 4
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.LSE_load_a1:
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/* a1 is saved in excsave1, so just read the value, */
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rsr a2, excsave1
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j .LSE_store_apply
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.balign 4
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.LSE_wrong_opcode:
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/* If we got here it's not an opcode we can try to fix, so bomb out.
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* Restore registers so any dump the fatal exception routine produces
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* will have correct values */
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wsr a0, sar
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l32i a0, sp, 0
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/*l32i a2, sp, 0x08*/
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr a1, excsave1
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mov a2, a1
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movi a3, 0
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call0 fatal_exception_handler
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/*************************** Debug exception handler *************************/
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.section .vecbase.text, "x"
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