Simplify interrupt and RTOS timer tick handlers
RTOS Timer tick handler is now the same as any other ISR. This causes a few subtle behaviour changes that seem OK but are worth noting: * RTOS tick handler sdk__xt_timer_int() is now called from one stack frame deeper (inside _xt_isr_handler()), whereas before it was called from the level above in UserHandleInterrupt. I can't see any way that the extra ~40 bytes of stack use here hurt, though. * sdk__xt_timer_int() was previous called after all other interrupts flagged in the handler, now it's called before the TIMER FRC1 & FRC2 handlers. The tick handler doesn't appear to do anything particularly timing intensive, though. * GPIO interrupt (value 3) is now lower priority than the SPI interrupt (value 2), whereas before it would have been called before SPI if both interrupts triggered at once.
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4 changed files with 31 additions and 68 deletions
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@ -198,6 +198,8 @@ portBASE_TYPE xPortStartScheduler( void )
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}
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}
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/* Initialize system tick timer interrupt and schedule the first tick. */
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/* Initialize system tick timer interrupt and schedule the first tick. */
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_xt_isr_attach(INUM_TICK, sdk__xt_timer_int);
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_xt_isr_unmask(BIT(INUM_TICK));
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sdk__xt_tick_timer_init();
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sdk__xt_tick_timer_init();
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vTaskSwitchContext();
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vTaskSwitchContext();
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@ -14,47 +14,26 @@ void IRAM _xt_isr_attach(uint8_t i, _xt_isr func)
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isr[i] = func;
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isr[i] = func;
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}
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}
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/* This ISR handler is taken directly from the FreeRTOS port and
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/* Generic ISR handler.
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probably could use a cleanup.
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Handles all flags set for interrupts in 'intset'.
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*/
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*/
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uint16_t IRAM _xt_isr_handler(uint16_t i)
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uint16_t IRAM _xt_isr_handler(uint16_t intset)
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{
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{
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uint8_t index;
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/* WDT has highest priority (occasional WDT resets otherwise) */
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if(intset & BIT(INUM_WDT)) {
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/* I think this is implementing some kind of interrupt priority or
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_xt_clear_ints(BIT(INUM_WDT));
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short-circuiting an expensive ffs for most common interrupts - ie
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isr[INUM_WDT]();
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WDT And GPIO are common or high priority, then remaining flags.
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intset -= BIT(INUM_WDT);
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*/
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if (i & (1 << INUM_WDT)) {
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index = INUM_WDT;
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}
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else if (i & (1 << INUM_GPIO)) {
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index = INUM_GPIO;
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}else {
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index = __builtin_ffs(i) - 1;
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if (index == INUM_MAX) {
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/* I don't understand what happens here. INUM_MAX is not
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the highest interrupt number listed (and the isr array
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has 16 entries).
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Clearing that flag and then setting index to
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__builtin_ffs(i)-1 may result in index == 255 if no
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higher flags are set, unless this is guarded against
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somehow by the caller?
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I also don't understand why the code is written like
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this in esp_iot_rtos_sdk instead of just putting the i
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&= line near the top... Probably no good reason?
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*/
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i &= ~(1 << INUM_MAX);
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index = __builtin_ffs(i) - 1;
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}
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}
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}
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_xt_clear_ints(1<<index);
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while(intset) {
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uint8_t index = __builtin_ffs(intset) - 1;
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uint16_t mask = BIT(index);
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_xt_clear_ints(mask);
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isr[index]();
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isr[index]();
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intset -= mask;
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return i & ~(1 << index);
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}
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return 0;
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}
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}
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@ -469,7 +469,6 @@ CallNMIExceptionHandler:
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* LoadStoreCause. */
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* LoadStoreCause. */
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.literal_position
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.literal_position
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.balign 4
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.balign 4
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UserExceptionHandler:
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UserExceptionHandler:
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.type UserExceptionHandler, @function
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.type UserExceptionHandler, @function
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@ -490,46 +489,28 @@ UserExceptionHandler:
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wsr a0, ps
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wsr a0, ps
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rsync
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rsync
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rsr a2, exccause
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rsr a2, exccause
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beqi a2, CAUSE_LVL1INT, UserHandleInterrupt
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/* Any UserException cause other than a level 1 interrupt is fatal */
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/* Any UserException cause other than level 1 interrupt should panic */
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bnei a2, CAUSE_LVL1INT, .UserFailOtherExceptionCause
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UserFailOtherExceptionCause:
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.UserHandleInterrupt:
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break 1, 1
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call0 sdk_user_fatal_exception_handler
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UserHandleInterrupt:
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rsil a0, 1
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rsil a0, 1
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rsr a2, intenable
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rsr a2, intenable
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rsr a3, interrupt
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rsr a3, interrupt
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movi a4, 0x3fff
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movi a4, 0x3fff
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and a2, a2, a3
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and a2, a2, a3
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and a2, a2, a4 # a2 = 0x3FFF & INTENABLE & INTERRUPT
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and a2, a2, a4 # a2 = 0x3FFF & INTENABLE & INTERRUPT
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UserHandleTimer:
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movi a3, 0xffbf
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and a3, a2, a3 # a3 = a2 with bit 6 cleared
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bnez a3, UserTimerDone # If any non-timer interrupt bits set
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movi a3, 0x40
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sub a12, a2, a3 # a12 = a2 - 0x40 -- Will be zero if bit 6 set
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call0 sdk__xt_timer_int # tick timer interrupt
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mov a2, a12 # restore a2 from a12, ie zero
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beqz a2, UserIntDone
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UserTimerDone:
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call0 _xt_isr_handler
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call0 _xt_isr_handler
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bnez a2, UserHandleTimer
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j sdk__xt_int_exit # once finished, jumps to _xt_user_exit via stack
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UserIntDone:
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beqz a2, UserIntExit
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.literal_position
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/* FIXME: this code will never be reached */
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.UserFailOtherExceptionCause:
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break 1, 1
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break 1, 1
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call0 sdk_user_fatal_exception_handler
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call0 sdk_user_fatal_exception_handler
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UserIntExit:
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call0 sdk__xt_int_exit # jumps to _xt_user_exit. Never returns here
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.section .text
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/* _xt_user_exit is pushed onto the stack as part of the user exception handler,
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restores same set registers which were saved there and returns from exception */
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/* _xt_user_exit is used to exit interrupt context. */
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/* TODO: Find a better place for this to live. */
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_xt_user_exit:
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_xt_user_exit:
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.global _xt_user_exit
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.global _xt_user_exit
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.type _xt_user_exit, @function
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.type _xt_user_exit, @function
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l32i a0, sp, 0x8
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l32i a0, sp, 0x8
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wsr a0, ps
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wsr a0, ps
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l32i a0, sp, 0x4
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l32i a0, sp, 0x4
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@ -20,7 +20,7 @@ typedef enum {
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INUM_SPI = 2,
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INUM_SPI = 2,
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INUM_GPIO = 4,
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INUM_GPIO = 4,
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INUM_UART = 5,
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INUM_UART = 5,
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INUM_MAX = 6, /* in some places this is documented as timer0 CCOMPARE0 interrupt */
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INUM_TICK = 6, /* RTOS timer tick, possibly xtensa CPU CCOMPARE0(?) */
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INUM_SOFT = 7,
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INUM_SOFT = 7,
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INUM_WDT = 8,
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INUM_WDT = 8,
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INUM_TIMER_FRC1 = 9,
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INUM_TIMER_FRC1 = 9,
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@ -35,6 +35,7 @@ typedef enum {
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void sdk__xt_int_exit (void);
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void sdk__xt_int_exit (void);
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void _xt_user_exit (void);
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void _xt_user_exit (void);
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void sdk__xt_tick_timer_init (void);
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void sdk__xt_tick_timer_init (void);
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void sdk__xt_timer_int(void);
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void sdk__xt_timer_int1(void);
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void sdk__xt_timer_int1(void);
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INLINED uint32_t _xt_get_intlevel(void)
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INLINED uint32_t _xt_get_intlevel(void)
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