Code formatted, minor fixes (#466)
This commit is contained in:
Ruslan V. Uss
Johan Kanflo
parent
8a474d749d
commit
5fa48d0298
28 changed files with 623 additions and 608 deletions
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@ -19,14 +19,14 @@
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extern "C" {
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#endif
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#include "i2c/i2c.h"
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#include <i2c/i2c.h>
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#define INA3221_ADDR_0 (0x40) // A0 to GND
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#define INA3221_ADDR_1 (0x41) // A0 to Vs+
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#define INA3221_ADDR_2 (0x42) // A0 to SDA
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#define INA3221_ADDR_3 (0x43) // A0 to SCL
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#define INA3221_ADDR_0 (0x40) ///< A0 to GND
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#define INA3221_ADDR_1 (0x41) ///< A0 to Vs+
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#define INA3221_ADDR_2 (0x42) ///< A0 to SDA
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#define INA3221_ADDR_3 (0x43) ///< A0 to SCL
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#define BUS_NUMBER 3 //Number of shunt available
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#define BUS_NUMBER 3 ///< Number of shunt available
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#define INA3221_REG_CONFIG (0x00)
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#define INA3221_REG_SHUNTVOLTAGE_1 (0x01)
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@ -39,7 +39,7 @@ extern "C" {
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#define INA3221_REG_VALID_POWER_UPPER_LIMIT (0x10)
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#define INA3221_REG_VALID_POWER_LOWER_LIMIT (0x11)
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/*
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/**
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* Default register after reset
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*/
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#define INA3221_DEFAULT_CONFIG (0x7127)
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@ -48,11 +48,12 @@ extern "C" {
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#define INA3221_DEFAULT_POWER_LOWER_LIMIT (0x2328) //9V
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#define INA3221_MASK_CONFIG (0x7C00)
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/*
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* Numbrer of samples
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/**
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* Number of samples
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*/
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typedef enum {
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INA3221_AVG_1 = 0, //Default
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INA3221_AVG_1 = 0, ///< Default
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INA3221_AVG_4,
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INA3221_AVG_16,
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INA3221_AVG_64,
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@ -62,7 +63,7 @@ typedef enum {
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INA3221_AVG_1024,
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} ina3221_avg_t;
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/*
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/**
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* Channel selection list
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*/
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typedef enum {
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@ -71,7 +72,7 @@ typedef enum {
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CHANNEL_3,
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} ina3221_channel_t;
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/*
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/**
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* Conversion time in us
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*/
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typedef enum {
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@ -79,63 +80,63 @@ typedef enum {
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INA3221_CT_204,
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INA3221_CT_332,
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INA3221_CT_588,
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INA3221_CT_1100, //Default
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INA3221_CT_1100, ///< Default
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INA3221_CT_2116,
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INA3221_CT_4156,
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INA3221_CT_8244,
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} ina3221_ct_t ;
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} ina3221_ct_t;
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/*
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/**
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* Config description register
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*/
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typedef union
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{
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struct {
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uint16_t esht : 1; // Enable/Disable shunt measure // LSB
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uint16_t ebus : 1; // Enable/Disable bus measure
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uint16_t mode : 1; // Single shot measure or continious mode
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uint16_t vsht : 3; // Shunt voltage conversion time
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uint16_t vbus : 3; // Bus voltage conversion time
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uint16_t avg : 3; // number of sample collected and averaged together
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uint16_t ch3 : 1; // Enable/Disable channel 3
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uint16_t ch2 : 1; // Enable/Disable channel 2
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uint16_t ch1 : 1; // Enable/Disable channel 1
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uint16_t rst : 1; //Set this bit to 1 to reset device // MSB
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uint16_t esht : 1; ///< Enable/Disable shunt measure // LSB
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uint16_t ebus : 1; ///< Enable/Disable bus measure
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uint16_t mode : 1; ///< Single shot measure or continious mode
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uint16_t vsht : 3; ///< Shunt voltage conversion time
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uint16_t vbus : 3; ///< Bus voltage conversion time
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uint16_t avg : 3; ///< number of sample collected and averaged together
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uint16_t ch3 : 1; ///< Enable/Disable channel 3
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uint16_t ch2 : 1; ///< Enable/Disable channel 2
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uint16_t ch1 : 1; ///< Enable/Disable channel 1
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uint16_t rst : 1; ///< Set this bit to 1 to reset device // MSB
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};
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uint16_t config_register;
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} ina3221_config_t;
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/*
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/**
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* Mask/enable description register
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*/
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typedef union
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{
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struct {
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uint16_t cvrf : 1 ; // Conversion ready flag (1: ready) // LSB
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uint16_t tcf : 1 ; // Timing control flag
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uint16_t pvf : 1 ; // Power valid flag
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uint16_t wf : 3 ; // Warning alert flag (Read mask to clear) (order : Channel1:channel2:channel3)
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uint16_t sf : 1 ; // Sum alert flag (Read mask to clear)
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uint16_t cf : 3 ; // Critical alert flag (Read mask to clear) (order : Channel1:channel2:channel3)
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uint16_t cen : 1 ; // Critical alert latch (1:enable)
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uint16_t wen : 1 ; // Warning alert latch (1:enable)
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uint16_t scc3 : 1 ; // channel 3 sum (1:enable)
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uint16_t scc2 : 1 ; // channel 2 sum (1:enable)
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uint16_t scc1 : 1 ; // channel 1 sum (1:enable)
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uint16_t : 1 ; //Reserved //MSB
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uint16_t cvrf : 1; ///< Conversion ready flag (1: ready) // LSB
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uint16_t tcf : 1; ///< Timing control flag
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uint16_t pvf : 1; ///< Power valid flag
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uint16_t wf : 3; ///< Warning alert flag (Read mask to clear) (order : Channel1:channel2:channel3)
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uint16_t sf : 1; ///< Sum alert flag (Read mask to clear)
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uint16_t cf : 3; ///< Critical alert flag (Read mask to clear) (order : Channel1:channel2:channel3)
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uint16_t cen : 1; ///< Critical alert latch (1:enable)
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uint16_t wen : 1; ///< Warning alert latch (1:enable)
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uint16_t scc3 : 1; ///< channel 3 sum (1:enable)
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uint16_t scc2 : 1; ///< channel 2 sum (1:enable)
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uint16_t scc1 : 1; ///< channel 1 sum (1:enable)
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uint16_t : 1; ///< Reserved //MSB
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};
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uint16_t mask_register;
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} ina3221_mask_t;
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/*
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/**
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* Device description
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*/
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typedef struct {
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const i2c_dev_t i2c_dev; // ina3221 I2C address
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const uint16_t shunt[BUS_NUMBER]; //Memory of shunt value (mOhm)
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ina3221_config_t config; //Memory of ina3221 config
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ina3221_mask_t mask; //Memory of mask_config
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const i2c_dev_t i2c_dev; ///< ina3221 I2C address
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const uint16_t shunt[BUS_NUMBER]; ///< Memory of shunt value (mOhm)
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ina3221_config_t config; ///< Memory of ina3221 config
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ina3221_mask_t mask; ///< Memory of mask_config
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} ina3221_t;
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/**
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