Fix status with bus.

This commit is contained in:
lilian 2016-12-05 12:05:18 +01:00
parent 762f73515b
commit 47cd73ae02

View file

@ -228,16 +228,16 @@ static void _rearm_extras_bit(uint8_t bus, bool arm) {
if (arm) if (arm)
{ {
if (status & 0x01) SPI(bus).USER0 |= (SPI_USER0_ADDR) ; if (status & (0x01<<(4*bus))) SPI(bus).USER0 |= (SPI_USER0_ADDR) ;
if (status & 0x02) SPI(bus).USER0 |= (SPI_USER0_COMMAND) ; if (status & (0x02<<(4*bus))) SPI(bus).USER0 |= (SPI_USER0_COMMAND) ;
if (status & 0x04) SPI(bus).USER0 |= (SPI_USER0_DUMMY | SPI_USER0_MISO); if (status & (0x04<<(4*bus))) SPI(bus).USER0 |= (SPI_USER0_DUMMY | SPI_USER0_MISO);
status = 0 ; status &= ~(0x0F<<(4*bus));
} }
else else
{ {
if (SPI(bus).USER0 & SPI_USER0_ADDR) { SPI(bus).USER0 &= ~(SPI_USER0_ADDR) ; status |= 1 ; } if (SPI(bus).USER0 & SPI_USER0_ADDR) { SPI(bus).USER0 &= ~(SPI_USER0_ADDR) ; status |= 0x01<<(4*bus) ; }
if (SPI(bus).USER0 & SPI_USER0_COMMAND) { SPI(bus).USER0 &= ~(SPI_USER0_COMMAND) ; status |= 2 ; } if (SPI(bus).USER0 & SPI_USER0_COMMAND) { SPI(bus).USER0 &= ~(SPI_USER0_COMMAND) ; status |= 0x02<<(4*bus) ; }
if (SPI(bus).USER0 & SPI_USER0_DUMMY) { SPI(bus).USER0 &= ~(SPI_USER0_DUMMY | SPI_USER0_MISO); status |= 4 ; } if (SPI(bus).USER0 & SPI_USER0_DUMMY) { SPI(bus).USER0 &= ~(SPI_USER0_DUMMY | SPI_USER0_MISO); status |= 0x04<<(4*bus) ; }
} }
} }