From 458a6813c8fd31598e19940697dd1db20bd9d420 Mon Sep 17 00:00:00 2001 From: Paul Sokolovsky Date: Sat, 20 Aug 2016 16:06:09 +0300 Subject: [PATCH 1/2] esp/interrupts.h: Add wDev FIQ interrupt number. 40251dd9 $a2 = 0x0 40251ddb $a3 = wDev_ProcessFiq 40251dde $a4 = 0x0 40251de0 $a0 = ets_isr_attach 40251de3 call $a0 --- core/include/esp/interrupts.h | 1 + 1 file changed, 1 insertion(+) diff --git a/core/include/esp/interrupts.h b/core/include/esp/interrupts.h index a6e779a..e539aa6 100644 --- a/core/include/esp/interrupts.h +++ b/core/include/esp/interrupts.h @@ -17,6 +17,7 @@ /* Interrupt numbers for level 1 exception handler. */ typedef enum { + INUM_WDEV_FIQ = 0, INUM_SLC = 1, INUM_SPI = 2, INUM_GPIO = 4, From 0aabbea16fd4163c81572eaa28cddf7b73836b8e Mon Sep 17 00:00:00 2001 From: Paul Sokolovsky Date: Sat, 20 Aug 2016 16:13:07 +0300 Subject: [PATCH 2/2] esp/wdt_regs.h: Add "current value" register. WDT is countdown timer. Current value is accessible via VAL register. At this time it's unclear if it's RO or RW (common sense says it shoul be RO). Source: looking at the WDT registers on a running chip. --- core/include/esp/wdt_regs.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/core/include/esp/wdt_regs.h b/core/include/esp/wdt_regs.h index 66bf1d0..6e73769 100644 --- a/core/include/esp/wdt_regs.h +++ b/core/include/esp/wdt_regs.h @@ -25,7 +25,9 @@ struct WDT_REGS { uint32_t volatile CTRL; // 0x00 uint32_t volatile REG1; // 0x04 uint32_t volatile REG2; // 0x08 - uint32_t volatile _unused[2]; // 0x0c - 0x10 + // Current value, decrementing + uint32_t volatile VAL; // 0x0c + uint32_t volatile _unused[1]; // 0x10 uint32_t volatile FEED; // 0x14 };