Merge pull request #70 from DagAgren/master
Add I2S and SLC register headers
This commit is contained in:
commit
3b3d41d502
3 changed files with 463 additions and 0 deletions
137
core/include/esp/i2s_regs.h
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137
core/include/esp/i2s_regs.h
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/* esp/i2s_regs.h
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*
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* ESP8266 I2S register definitions
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*
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* Not compatible with ESP SDK register access code.
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*/
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#ifndef _ESP_I2S_REGS_H
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#define _ESP_I2S_REGS_H
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#include "esp/types.h"
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#include "common_macros.h"
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#define I2S_BASE 0x60000e00
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#define I2S (*(struct I2S_REGS *)I2S_BASE)
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struct I2S_REGS {
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uint32_t volatile TXFIFO; // 0x00
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uint32_t volatile RXFIFO; // 0x04
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uint32_t volatile CONF; // 0x08
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uint32_t volatile INT_RAW; // 0x0c
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uint32_t volatile INT_STATUS; // 0x10
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uint32_t volatile INT_ENABLE; // 0x14
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uint32_t volatile INT_CLEAR; // 0x18
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uint32_t volatile TIMING; // 0x1c
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uint32_t volatile FIFO_CONF; // 0x20
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uint32_t volatile RX_EOF_NUM; // 0x24
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uint32_t volatile CONF_SINGLE_DATA; // 0x28
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uint32_t volatile CONF_CHANNELS; // 0x2c
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};
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_Static_assert(sizeof(struct I2S_REGS) == 0x30, "I2S_REGS is the wrong size");
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/* Details for CONF register */
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#define I2S_CONF_BCK_DIV_M 0x0000003f
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#define I2S_CONF_BCK_DIV_S 22
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#define I2S_CONF_CLKM_DIV_M 0x0000003f
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#define I2S_CONF_CLKM_DIV_S 16
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#define I2S_CONF_BITS_MOD_M 0x0000000f
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#define I2S_CONF_BITS_MOD_S 12
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#define I2S_CONF_RX_MSB_SHIFT BIT(11)
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#define I2S_CONF_TX_MSB_SHIFT BIT(10)
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#define I2S_CONF_RX_START BIT(9)
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#define I2S_CONF_TX_START BIT(8)
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#define I2S_CONF_MSB_RIGHT BIT(7)
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#define I2S_CONF_RIGHT_FIRST BIT(6)
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#define I2S_CONF_RX_SLAVE_MOD BIT(5)
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#define I2S_CONF_TX_SLAVE_MOD BIT(4)
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#define I2S_CONF_RX_FIFO_RESET BIT(3)
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#define I2S_CONF_TX_FIFO_RESET BIT(2)
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#define I2S_CONF_RX_RESET BIT(1)
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#define I2S_CONF_TX_RESET BIT(0)
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#define I2S_CONF_RESET_MASK 0xf
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/* Details for INT_RAW register */
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#define I2S_INT_RAW_TX_REMPTY BIT(5)
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#define I2S_INT_RAW_TX_WFULL BIT(4)
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#define I2S_INT_RAW_RX_REMPTY BIT(3)
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#define I2S_INT_RAW_RX_WFULL BIT(2)
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#define I2S_INT_RAW_TX_PUT_DATA BIT(1)
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#define I2S_INT_RAW_RX_TAKE_DATA BIT(0)
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/* Details for INT_STATUS register */
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#define I2S_INT_STATUS_TX_REMPTY BIT(5)
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#define I2S_INT_STATUS_TX_WFULL BIT(4)
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#define I2S_INT_STATUS_RX_REMPTY BIT(3)
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#define I2S_INT_STATUS_RX_WFULL BIT(2)
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#define I2S_INT_STATUS_TX_PUT_DATA BIT(1)
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#define I2S_INT_STATUS_RX_TAKE_DATA BIT(0)
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/* Details for INT_ENABLE register */
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#define I2S_INT_ENABLE_TX_REMPTY BIT(5)
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#define I2S_INT_ENABLE_TX_WFULL BIT(4)
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#define I2S_INT_ENABLE_RX_REMPTY BIT(3)
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#define I2S_INT_ENABLE_RX_WFULL BIT(2)
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#define I2S_INT_ENABLE_TX_PUT_DATA BIT(1)
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#define I2S_INT_ENABLE_RX_TAKE_DATA BIT(0)
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/* Details for INT_CLEAR register */
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#define I2S_INT_CLEAR_TX_REMPTY BIT(5)
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#define I2S_INT_CLEAR_TX_WFULL BIT(4)
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#define I2S_INT_CLEAR_RX_REMPTY BIT(3)
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#define I2S_INT_CLEAR_RX_WFULL BIT(2)
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#define I2S_INT_CLEAR_TX_PUT_DATA BIT(1)
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#define I2S_INT_CLEAR_RX_TAKE_DATA BIT(0)
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/* Details for TIMING register */
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#define I2S_TIMING_TX_BCK_IN_INV BIT(22)
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#define I2S_TIMING_RX_DSYNC_SW BIT(21)
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#define I2S_TIMING_TX_DSYNC_SW BIT(20)
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#define I2S_TIMING_RX_BCK_OUT_DELAY_M 0x00000003
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#define I2S_TIMING_RX_BCK_OUT_DELAY_S 18
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#define I2S_TIMING_RX_WS_OUT_DELAY_M 0x00000003
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#define I2S_TIMING_RX_WS_OUT_DELAY_S 16
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#define I2S_TIMING_TX_SD_OUT_DELAY_M 0x00000003
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#define I2S_TIMING_TX_SD_OUT_DELAY_S 14
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#define I2S_TIMING_TX_WS_OUT_DELAY_M 0x00000003
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#define I2S_TIMING_TX_WS_OUT_DELAY_S 12
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#define I2S_TIMING_TX_BCK_OUT_DELAY_M 0x00000003
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#define I2S_TIMING_TX_BCK_OUT_DELAY_S 10
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#define I2S_TIMING_RX_SD_IN_DELAY_M 0x00000003
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#define I2S_TIMING_RX_SD_IN_DELAY_S 8
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#define I2S_TIMING_RX_WS_IN_DELAY 0x00000003
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#define I2S_TIMING_RX_WS_IN_DELAY_S 6
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#define I2S_TIMING_RX_BCK_IN_DELAY_M 0x00000003
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#define I2S_TIMING_RX_BCK_IN_DELAY_S 4
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#define I2S_TIMING_TX_WS_IN_DELAY_M 0x00000003
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#define I2S_TIMING_TX_WS_IN_DELAY_S 2
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#define I2S_TIMING_TX_BCK_IN_DELAY_M 0x00000003
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#define I2S_TIMING_TX_BCK_IN_DELAY_S 0
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/* Details for FIFO_CONF register */
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#define I2S_FIFO_CONF_RX_FIFO_MOD_M 0x00000007
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#define I2S_FIFO_CONF_RX_FIFO_MOD_S 16
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#define I2S_FIFO_CONF_TX_FIFO_MOD_M 0x00000007
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#define I2S_FIFO_CONF_TX_FIFO_MOD_S 13
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#define I2S_FIFO_CONF_DESCRIPTOR_ENABLE BIT(12)
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#define I2S_FIFO_CONF_TX_DATA_NUM_M 0x0000003f
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#define I2S_FIFO_CONF_TX_DATA_NUM_S 6
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#define I2S_FIFO_CONF_RX_DATA_NUM_M 0x0000003f
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#define I2S_FIFO_CONF_RX_DATA_NUM_S 0
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/* Details for CONF_CHANNEL register */
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#define I2S_CONF_CHANNELS_RX_CHANNEL_MOD_M 0x00000003
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#define I2S_CONF_CHANNELS_RX_CHANNEL_MOD_S 3
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#define I2S_CONF_CHANNELS_TX_CHANNEL_MOD_M 0x00000007
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#define I2S_CONF_CHANNELS_TX_CHANNEL_MOD_S 0
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#endif /* _ESP_I2S_REGS_H */
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37
core/include/esp/slc.h
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37
core/include/esp/slc.h
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/* esp/slc_regs.h
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*
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* ESP8266 SLC functions
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*/
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#ifndef _ESP_SLC_H
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#define _ESP_SLC_H
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#include "esp/slc_regs.h"
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/* Memory layout for DMA transfer descriptors. */
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struct SLCDescriptor
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{
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uint32_t flags;
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uint32_t buf_ptr;
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uint32_t next_link_ptr;
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};
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#define SLC_DESCRIPTOR_FLAGS_BLOCKSIZE_M 0x00000fff
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#define SLC_DESCRIPTOR_FLAGS_BLOCKSIZE_S 0
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#define SLC_DESCRIPTOR_FLAGS_DATA_LENGTH_M 0x00000fff
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#define SLC_DESCRIPTOR_FLAGS_DATA_LENGTH_S 12
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#define SLC_DESCRIPTOR_FLAGS_SUB_SOF BIT(29)
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#define SLC_DESCRIPTOR_FLAGS_EOF BIT(30)
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#define SLC_DESCRIPTOR_FLAGS_OWNER BIT(31)
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#define SLC_DESCRIPTOR_FLAGS(blocksize,datalen,sub_sof,eof,owner) ( \
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VAL2FIELD_M(SLC_DESCRIPTOR_FLAGS_BLOCKSIZE,blocksize)| \
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VAL2FIELD_M(SLC_DESCRIPTOR_FLAGS_DATA_LENGTH,datalen)| \
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((sub_sof)?SLC_DESCRIPTOR_FLAGS_SUB_SOF:0)| \
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((eof)?SLC_DESCRIPTOR_FLAGS_EOF:0)| \
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((owner)?SLC_DESCRIPTOR_FLAGS_OWNER:0) \
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)
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#endif /* _ESP_SLC_REGS_H */
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289
core/include/esp/slc_regs.h
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core/include/esp/slc_regs.h
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/* esp/slc_regs.h
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*
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* ESP8266 SLC register definitions
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*
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* Not compatible with ESP SDK register access code.
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*/
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#ifndef _ESP_SLC_REGS_H
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#define _ESP_SLC_REGS_H
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#include "esp/types.h"
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#include "common_macros.h"
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#define SLC_BASE 0x60000b00
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#define SLC (*(struct SLC_REGS *)SLC_BASE)
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struct SLC_REGS {
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uint32_t volatile CONF0; // 0x00
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uint32_t volatile INT_RAW; // 0x04
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uint32_t volatile INT_STATUS; // 0x08
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uint32_t volatile INT_ENABLE; // 0x0c
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uint32_t volatile INT_CLEAR; // 0x10
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uint32_t volatile RX_STATUS; // 0x14
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uint32_t volatile RX_FIFO_PUSH; // 0x18
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uint32_t volatile TX_STATUS; // 0x1c
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uint32_t volatile TX_FIFO_POP; // 0x20
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uint32_t volatile RX_LINK; // 0x24
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uint32_t volatile TX_LINK; // 0x28
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uint32_t volatile INTVEC_TO_HOST; // 0x2c
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uint32_t volatile TOKEN0; // 0x30
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uint32_t volatile TOKEN1; // 0x34
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uint32_t volatile CONF1; // 0x38
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uint32_t volatile STATE0; // 0x3c
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uint32_t volatile STATE1; // 0x40
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uint32_t volatile BRIDGE_CONF; // 0x44
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uint32_t volatile RX_EOF_DESCRIPTOR_ADDR; // 0x48
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uint32_t volatile TX_EOF_DESCRIPTOR_ADDR; // 0x4c
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uint32_t volatile RX_EOF_BUFFER_DESCRIPTOR_ADDR; // 0x50 - Naming uncertain
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uint32_t volatile AHB_TEST; // 0x54
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uint32_t volatile SDIO_STATUS; // 0x58
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uint32_t volatile RX_DESCRIPTOR_CONF; // 0x5c
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uint32_t volatile TX_LINK_DESCRIPTOR; // 0x60
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uint32_t volatile TX_LINK_DESCRIPTOR_BF0; // 0x64
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uint32_t volatile TX_LINK_DESCRIPTOR_BF1; // 0x68
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uint32_t volatile RX_LINK_DESCRIPTOR; // 0x6c
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uint32_t volatile RX_LINK_DESCRIPTOR_BF0; // 0x70
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uint32_t volatile RX_LINK_DESCRIPTOR_BF1; // 0x74
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uint32_t volatile DATE; // 0x78
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uint32_t volatile ID; // 0x7c
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uint32_t volatile UNKNOWN_80; // 0x80
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uint32_t volatile UNKNOWN_84; // 0x84
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uint32_t volatile HOST_INT_RAW; // 0x88
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uint32_t volatile UNKNOWN_8C; // 0x8c
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uint32_t volatile UNKNOWN_90; // 0x90
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uint32_t volatile HOST_CONF_W0; // 0x94
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uint32_t volatile HOST_CONF_W1; // 0x98
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uint32_t volatile HOST_INT_STATUS; // 0x9c
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uint32_t volatile HOST_CONF_W2; // 0xa0
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uint32_t volatile HOST_CONF_W3; // 0xa4
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uint32_t volatile HOST_CONF_W4; // 0xa8
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uint32_t volatile UNKNOWN_AC; // 0xac
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uint32_t volatile HOST_INT_CLEAR; // 0xb0
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uint32_t volatile HOST_INT_ENABLE; // 0xb4
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uint32_t volatile UNKNOWN_B8; // 0xb8
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uint32_t volatile HOST_CONF_W5; // 0xbc
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};
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_Static_assert(sizeof(struct SLC_REGS) == 0xc0, "SLC_REGS is the wrong size");
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/* Details for CONF0 register */
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#define SLC_CONF0_MODE_M 0x00000003
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#define SLC_CONF0_MODE_S 12
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#define SLC_CONF0_DATA_BURST_ENABLE BIT(9)
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#define SLC_CONF0_DESCRIPTOR_BURST_ENABLE BIT(8)
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#define SLC_CONF0_RX_NO_RESTART_CLEAR BIT(7)
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#define SLC_CONF0_RX_AUTO_WRITE_BACK BIT(6)
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#define SLC_CONF0_RX_LOOP_TEST BIT(5)
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#define SLC_CONF0_TX_LOOP_TEST BIT(4)
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#define SLC_CONF0_AHBM_RESET BIT(3)
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#define SLC_CONF0_AHBM_FIFO_RESET BIT(2)
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#define SLC_CONF0_RX_LINK_RESET BIT(1)
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#define SLC_CONF0_TX_LINK_RESET BIT(0)
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/* Details for INT_RAW register */
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#define SLC_INT_RAW_TX_DSCR_EMPTY BIT(21)
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#define SLC_INT_RAW_RX_DSCR_ERROR BIT(20)
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#define SLC_INT_RAW_TX_DSCR_ERROR BIT(19)
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#define SLC_INT_RAW_TO_HOST BIT(18)
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#define SLC_INT_RAW_RX_EOF BIT(17)
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#define SLC_INT_RAW_RX_DONE BIT(16)
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#define SLC_INT_RAW_TX_EOF BIT(15)
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#define SLC_INT_RAW_TX_DONE BIT(14)
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#define SLC_INT_RAW_TOKEN1_1TO0 BIT(13)
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#define SLC_INT_RAW_TOKEN0_1TO0 BIT(12)
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#define SLC_INT_RAW_TX_OVERFLOW BIT(11)
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#define SLC_INT_RAW_RX_UNDEFLOW BIT(10)
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#define SLC_INT_RAW_TX_START BIT(9)
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#define SLC_INT_RAW_RX_START BIT(8)
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#define SLC_INT_RAW_FROM_HOST_BIT7 BIT(7)
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#define SLC_INT_RAW_FROM_HOST_BIT6 BIT(6)
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#define SLC_INT_RAW_FROM_HOST_BIT5 BIT(5)
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#define SLC_INT_RAW_FROM_HOST_BIT4 BIT(4)
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#define SLC_INT_RAW_FROM_HOST_BIT3 BIT(3)
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#define SLC_INT_RAW_FROM_HOST_BIT2 BIT(2)
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#define SLC_INT_RAW_FROM_HOST_BIT1 BIT(1)
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#define SLC_INT_RAW_FROM_HOST_BIT0 BIT(0)
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/* Details for INT_STATUS register */
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#define SLC_INT_STATUS_TX_DSCR_EMPTY BIT(21)
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#define SLC_INT_STATUS_RX_DSCR_ERROR BIT(20)
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#define SLC_INT_STATUS_TX_DSCR_ERROR BIT(19)
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#define SLC_INT_STATUS_TO_HOST BIT(18)
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#define SLC_INT_STATUS_RX_EOF BIT(17)
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#define SLC_INT_STATUS_RX_DONE BIT(16)
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#define SLC_INT_STATUS_TX_EOF BIT(15)
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#define SLC_INT_STATUS_TX_DONE BIT(14)
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#define SLC_INT_STATUS_TOKEN1_1TO0 BIT(13)
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#define SLC_INT_STATUS_TOKEN0_1TO0 BIT(12)
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#define SLC_INT_STATUS_TX_OVERFLOW BIT(11)
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#define SLC_INT_STATUS_RX_UNDEFLOW BIT(10)
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#define SLC_INT_STATUS_TX_START BIT(9)
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#define SLC_INT_STATUS_RX_START BIT(8)
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#define SLC_INT_STATUS_FROM_HOST_BIT7 BIT(7)
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#define SLC_INT_STATUS_FROM_HOST_BIT6 BIT(6)
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#define SLC_INT_STATUS_FROM_HOST_BIT5 BIT(5)
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#define SLC_INT_STATUS_FROM_HOST_BIT4 BIT(4)
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#define SLC_INT_STATUS_FROM_HOST_BIT3 BIT(3)
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#define SLC_INT_STATUS_FROM_HOST_BIT2 BIT(2)
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#define SLC_INT_STATUS_FROM_HOST_BIT1 BIT(1)
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#define SLC_INT_STATUS_FROM_HOST_BIT0 BIT(0)
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/* Details for INT_ENABLE register */
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#define SLC_INT_ENABLE_TX_DSCR_EMPTY BIT(21)
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#define SLC_INT_ENABLE_RX_DSCR_ERROR BIT(20)
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#define SLC_INT_ENABLE_TX_DSCR_ERROR BIT(19)
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#define SLC_INT_ENABLE_TO_HOST BIT(18)
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#define SLC_INT_ENABLE_RX_EOF BIT(17)
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#define SLC_INT_ENABLE_RX_DONE BIT(16)
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#define SLC_INT_ENABLE_TX_EOF BIT(15)
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#define SLC_INT_ENABLE_TX_DONE BIT(14)
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#define SLC_INT_ENABLE_TOKEN1_1TO0 BIT(13)
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#define SLC_INT_ENABLE_TOKEN0_1TO0 BIT(12)
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#define SLC_INT_ENABLE_TX_OVERFLOW BIT(11)
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#define SLC_INT_ENABLE_RX_UNDEFLOW BIT(10)
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#define SLC_INT_ENABLE_TX_START BIT(9)
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#define SLC_INT_ENABLE_RX_START BIT(8)
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#define SLC_INT_ENABLE_FROM_HOST_BIT7 BIT(7)
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#define SLC_INT_ENABLE_FROM_HOST_BIT6 BIT(6)
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#define SLC_INT_ENABLE_FROM_HOST_BIT5 BIT(5)
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#define SLC_INT_ENABLE_FROM_HOST_BIT4 BIT(4)
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#define SLC_INT_ENABLE_FROM_HOST_BIT3 BIT(3)
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#define SLC_INT_ENABLE_FROM_HOST_BIT2 BIT(2)
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#define SLC_INT_ENABLE_FROM_HOST_BIT1 BIT(1)
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#define SLC_INT_ENABLE_FROM_HOST_BIT0 BIT(0)
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#define SLC_INT_ENABLE_FROM_HOST_BIT_ALL 0xff
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/* Details for INT_CLEAR register */
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#define SLC_INT_CLEAR_TX_DSCR_EMPTY BIT(21)
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#define SLC_INT_CLEAR_RX_DSCR_ERROR BIT(20)
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#define SLC_INT_CLEAR_TX_DSCR_ERROR BIT(19)
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#define SLC_INT_CLEAR_TO_HOST BIT(18)
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#define SLC_INT_CLEAR_RX_EOF BIT(17)
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#define SLC_INT_CLEAR_RX_DONE BIT(16)
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#define SLC_INT_CLEAR_TX_EOF BIT(15)
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#define SLC_INT_CLEAR_TX_DONE BIT(14)
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#define SLC_INT_CLEAR_TOKEN1_1TO0 BIT(13)
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#define SLC_INT_CLEAR_TOKEN0_1TO0 BIT(12)
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#define SLC_INT_CLEAR_TX_OVERFLOW BIT(11)
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#define SLC_INT_CLEAR_RX_UNDEFLOW BIT(10)
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#define SLC_INT_CLEAR_TX_START BIT(9)
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#define SLC_INT_CLEAR_RX_START BIT(8)
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#define SLC_INT_CLEAR_FROM_HOST_BIT7 BIT(7)
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#define SLC_INT_CLEAR_FROM_HOST_BIT6 BIT(6)
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#define SLC_INT_CLEAR_FROM_HOST_BIT5 BIT(5)
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#define SLC_INT_CLEAR_FROM_HOST_BIT4 BIT(4)
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#define SLC_INT_CLEAR_FROM_HOST_BIT3 BIT(3)
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#define SLC_INT_CLEAR_FROM_HOST_BIT2 BIT(2)
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#define SLC_INT_CLEAR_FROM_HOST_BIT1 BIT(1)
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#define SLC_INT_CLEAR_FROM_HOST_BIT0 BIT(0)
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/* Details for RX_STATUS register */
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#define SLC_RX_STATUS_EMPTY BIT(1)
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#define SLC_RX_STATUS_FULL BIT(0)
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||||
/* Details for RX_FIFO_PUSH register */
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#define SLC_RX_FIFO_PUSH_FLAG BIT(16)
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#define SLC_RX_FIFO_PUSH_DATA_M 0x000001ff
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#define SLC_RX_FIFO_PUSH_DATA_S 0
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|
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/* Details for TX_STATUS register */
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|
||||
#define SLC_TX_STATUS_EMPTY BIT(1)
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#define SLC_TX_STATUS_FULL BIT(0)
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||||
|
||||
/* Details for TX_FIFO_POP register */
|
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|
||||
#define SLC_TX_FIFO_POP_FLAG BIT(16)
|
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#define SLC_TX_FIFO_POP_DATA_M 0x000007ff
|
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#define SLC_TX_FIFO_POP_DATA_S 0
|
||||
|
||||
/* Details for RX_LINK register */
|
||||
|
||||
#define SLC_RX_LINK_PARK BIT(31)
|
||||
#define SLC_RX_LINK_RESTART BIT(30)
|
||||
#define SLC_RX_LINK_START BIT(29)
|
||||
#define SLC_RX_LINK_STOP BIT(28)
|
||||
#define SLC_RX_LINK_DESCRIPTOR_ADDR_M 0x000fffff
|
||||
#define SLC_RX_LINK_DESCRIPTOR_ADDR_S 0
|
||||
|
||||
/* Details for TX_LINK register */
|
||||
|
||||
#define SLC_TX_LINK_PARK BIT(31)
|
||||
#define SLC_TX_LINK_RESTART BIT(30)
|
||||
#define SLC_TX_LINK_START BIT(29)
|
||||
#define SLC_TX_LINK_STOP BIT(28)
|
||||
#define SLC_TX_LINK_DESCRIPTOR_ADDR_M 0x000fffff
|
||||
#define SLC_TX_LINK_DESCRIPTOR_ADDR_S 0
|
||||
|
||||
/* Details for INTVEC_TO_HOST register */
|
||||
|
||||
#define SLC_INTVEC_TO_HOST_INTVEC_M 0x000000ff
|
||||
#define SLC_INTVEC_TO_HOST_INTVEC_S 0
|
||||
|
||||
/* Details for TOKEN0 register */
|
||||
|
||||
#define SLC_TOKEN0_M 0x00000fff
|
||||
#define SLC_TOKEN0_S 16
|
||||
#define SLC_TOKEN0_LOCAL_INC_MORE BIT(14)
|
||||
#define SLC_TOKEN0_LOCAL_INC BIT(13)
|
||||
#define SLC_TOKEN0_LOCAL_WRITE BIT(12)
|
||||
#define SLC_TOKEN0_LOCAL_DATA_M 0x00000FFF
|
||||
#define SLC_TOKEN0_LOCAL_DATA_S 0
|
||||
|
||||
/* Details for TOKEN1 register */
|
||||
|
||||
#define SLC_TOKEN1_MASK 0x00000fff
|
||||
#define SLC_TOKEN1_S 16
|
||||
#define SLC_TOKEN1_LOCAL_INC_MORE BIT(14)
|
||||
#define SLC_TOKEN1_LOCAL_INC BIT(13)
|
||||
#define SLC_TOKEN1_LOCAL_WRITE BIT(12)
|
||||
#define SLC_TOKEN1_LOCAL_DATA_M 0x00000fff
|
||||
#define SLC_TOKEN1_LOCAL_DATA_S 0
|
||||
|
||||
/* Details for BRIDGE_CONF register */
|
||||
|
||||
#define SLC_BRIDGE_CONF_TX_PUSH_IDLE_M 0x0000ffff
|
||||
#define SLC_BRIDGE_CONF_TX_PUSH_IDLE_S 16
|
||||
#define SLC_BRIDGE_CONF_TX_DUMMY_MODE BIT(12)
|
||||
#define SLC_BRIDGE_CONF_FIFO_MAP_ENABLE_M 0x0000000f
|
||||
#define SLC_BRIDGE_CONF_FIFO_MAP_ENABLE_S 8
|
||||
#define SLC_BRIDGE_CONF_TX_EOF_ENABLE_M 0x0000003f
|
||||
#define SLC_BRIDGE_CONF_TX_EOF_ENABLE_S 0
|
||||
|
||||
/* Details for AHB_TEST register */
|
||||
|
||||
#define SLC_AHB_TEST_ADDR_M 0x00000003
|
||||
#define SLC_AHB_TEST_ADDR_S 4
|
||||
#define SLC_AHB_TEST_MODE_M 0x00000007
|
||||
#define SLC_AHB_TEST_MODE_S 0
|
||||
|
||||
/* Details for SDIO_STATUS register */
|
||||
|
||||
#define SLC_SDIO_STATUS_BUS_M 0x00000007
|
||||
#define SLC_SDIO_STATUS_BUS_S 12
|
||||
#define SLC_SDIO_STATUS_WAKEUP BIT(8)
|
||||
#define SLC_SDIO_STATUS_FUNC_M 0x0000000f
|
||||
#define SLC_SDIO_STATUS_FUNC_S 4
|
||||
#define SLC_SDIO_STATUS_COMMAND_M 0x00000007
|
||||
#define SLC_SDIO_STATUS_COMMAND_S 0
|
||||
|
||||
/* Details for RX_DESCRIPTOR_CONF register */
|
||||
|
||||
#define SLC_RX_DESCRIPTOR_CONF_RX_FILL_ENABLE BIT(20)
|
||||
#define SLC_RX_DESCRIPTOR_CONF_RX_EOF_MODE BIT(19)
|
||||
#define SLC_RX_DESCRIPTOR_CONF_RX_FILL_MODE BIT(18)
|
||||
#define SLC_RX_DESCRIPTOR_CONF_INFOR_NO_REPLACE BIT(17)
|
||||
#define SLC_RX_DESCRIPTOR_CONF_TOKEN_NO_REPLACE BIT(16)
|
||||
#define SLC_RX_DESCRIPTOR_CONF_POP_IDLE_COUNT_M 0x0000ffff
|
||||
#define SLC_RX_DESCRIPTOR_CONF_POP_IDLE_COUNT_S 0
|
||||
|
||||
#endif /* _ESP_SLC_REGS_H */
|
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Reference in a new issue