Timer FRC1 & FRC2 registers
Mostly determined from reverse engineering and poking around. Includes first "experiments" program with random bits and pieces for poking at registers, may be useful to keep in source control but not useful for writing actual programs.
This commit is contained in:
Angus Gratton
parent
8f3111c5e1
commit
1b0124cf05
6 changed files with 456 additions and 2 deletions
26
core/include/esp/clocks.h
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26
core/include/esp/clocks.h
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@ -0,0 +1,26 @@
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/* esp/clocks.h
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*
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* ESP8266 internal clock values
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*
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* At the moment there's not a lot known about varying clock speeds
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* apart from doubling the CPU clock. It may be possible to set clock
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* domains differently somehow.
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*
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* Part of esp-open-rtos
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* Copyright (C) 2015 Superhouse Automation Pty Ltd
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* BSD Licensed as described in the file LICENSE
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*/
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#ifndef _ESP_CLOCKS_H
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#define _ESP_CLOCKS_H
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/* CPU clock, can be overclocked to 160MHz via a dport register setting */
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#define CPU_CLK_FREQ 80*1000000
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/* Main peripheral clock
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This is also the master frequency for the UART and the TIMER module
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(before divisors applied to either.)
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*/
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#define APB_CLK_FREQ CPU_CLK_FREQ
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#endif
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@ -16,10 +16,16 @@ typedef enum {
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INUM_SPI = 2,
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INUM_SPI = 2,
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INUM_GPIO = 4,
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INUM_GPIO = 4,
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INUM_UART = 5,
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INUM_UART = 5,
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INUM_MAX = 6,
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INUM_MAX = 6, /* in some places this is documented as timer0 CCOMPARE0 interrupt */
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INUM_SOFT = 7,
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INUM_SOFT = 7,
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INUM_WDT = 8,
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INUM_WDT = 8,
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INUM_FRC_TIMER1 = 9,
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INUM_TIMER_FRC1 = 9,
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/* FRC2 default handler. Configured by sdk_ets_timer_init, which
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runs as part of default libmain.a startup code, assigns
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interrupt handler to sdk_vApplicationTickHook+0x68
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*/
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INUM_TIMER_FRC2 = 10,
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} xt_isr_num_t;
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} xt_isr_num_t;
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#endif
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#endif
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@ -25,6 +25,7 @@ typedef volatile uint32_t *esp_reg_t;
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You shouldn't need to use these directly.
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You shouldn't need to use these directly.
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*/
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*/
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#define MMIO_BASE 0x60000000
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#define MMIO_BASE 0x60000000
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#define DPORT_BASE 0x3ff00000
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#define UART0_BASE (MMIO_BASE + 0)
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#define UART0_BASE (MMIO_BASE + 0)
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#define SPI1_BASE (MMIO_BASE + 0x0100)
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#define SPI1_BASE (MMIO_BASE + 0x0100)
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@ -142,6 +143,133 @@ typedef volatile uint32_t *esp_reg_t;
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#define GPIO_INT_HIGH (BIT(7)|BIT(9))
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#define GPIO_INT_HIGH (BIT(7)|BIT(9))
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#define GPIO_INT_MASK (BIT(7)|BIT(8)|BIT(9))
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#define GPIO_INT_MASK (BIT(7)|BIT(8)|BIT(9))
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/* TIMER registers
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*
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* ESP8266 has two hardware(?) timer counters, FRC1 and FRC2.
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*
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* FRC1 is a 24-bit countdown timer, triggers interrupt when reaches zero.
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* FRC2 is a 32-bit countup timer, can set a variable match value to trigger an interrupt.
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*
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* FreeRTOS tick timer appears to come from XTensa core tick timer0,
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* not either of these. FRC2 is used in the FreeRTOS SDK however. It
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* is set to free-run, interrupting periodically via updates to the
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* MATCH register. sdk_ets_timer_init configures FRC2 and assigns FRC2
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* interrupt handler at sdk_vApplicationTickHook+0x68
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*/
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/* Load value for FRC1, read/write.
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When TIMER_CTRL_RELOAD is cleared in TIMER_FRC1_CTRL_REG, FRC1
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will reload to 0x7fffff once overflowed (unless the load value is
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rewritten in the interrupt handler.)
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When TIMER_CTRL_RELOAD is set in TIMER_FRC1_CTRL_REG, FRC1 will reload
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from the load register value once overflowed.
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*/
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#define TIMER_FRC1_LOAD_REG _REG(TIMER_BASE, 0x00)
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/* Current count value for FRC1, read only? */
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#define TIMER_FRC1_COUNT_REG _REG(TIMER_BASE, 0x04)
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/* Control register for FRC1, read/write.
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See the bit definitions TIMER_CTRL_xxx lower down.
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*/
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#define TIMER_FRC1_CTRL_REG _REG(TIMER_BASE, 0x08)
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/* Reading this register always returns the value in
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* TIMER_FRC1_LOAD_REG.
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*
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* Writing zero to this register clears the FRC1
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* interrupt status.
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*/
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#define TIMER_FRC1_CLEAR_INT_REG _REG(TIMER_BASE, 0x0c)
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/* FRC2 load register.
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*
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* If TIMER_CTRL_RELOAD is cleared in TIMER_FRC2_CTRL_REG, writing to
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* this register will update the FRC2 COUNT value.
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*
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* If TIMER_CTRL_RELOAD is set in TIMER_FRC2_CTRL_REG, the behaviour
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* appears to be the same except that writing 0 to the load register
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* both sets the COUNT register to 0 and disables the timer, even if
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* the TIMER_CTRL_RUN bit is set.
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*
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* Offsets 0x34, 0x38, 0x3c all seem to read back the LOAD_REG value
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* also (but have no known function.)
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*/
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#define TIMER_FRC2_LOAD_REG _REG(TIMER_BASE, 0x20)
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/* FRC2 current count value. Read only? */
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#define TIMER_FRC2_COUNT_REG _REG(TIMER_BASE, 0x24)
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/* Control register for FRC2. Read/write.
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See the bit definitions TIMER_CTRL_xxx lower down.
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*/
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#define TIMER_FRC2_CTRL_REG _REG(TIMER_BASE, 0x28)
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/* Reading this value returns the current value of
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* TIMER_FRC2_LOAD_REG.
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*
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* Writing zero to this value clears the FRC2 interrupt status.
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*/
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#define TIMER_FRC2_CLEAR_INT_REG _REG(TIMER_BASE, 0x2c)
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/* Interrupt match value for FRC2. When COUNT == MATCH,
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the interrupt fires.
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*/
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#define TIMER_FRC2_MATCH_REG _REG(TIMER_BASE, 0x30)
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/* Timer control bits to set clock divisor values.
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Divider from master 80MHz APB_CLK (unconfirmed, see esp/clocks.h).
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*/
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#define TIMER_CTRL_DIV_1 0
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#define TIMER_CTRL_DIV_16 BIT(2)
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#define TIMER_CTRL_DIV_256 BIT(3)
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#define TIMER_CTRL_DIV_MASK (BIT(2)|BIT(3))
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/* Set timer control bits to trigger interrupt on "edge" or "level"
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*
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* Observed behaviour is like this:
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*
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* * When TIMER_CTRL_INT_LEVEL is set, the interrupt status bit
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* TIMER_CTRL_INT_STATUS remains set when the timer interrupt
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* triggers, unless manually cleared by writing 0 to
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* TIMER_FRCx_CLEAR_INT. While the interrupt status bit stays set
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* the timer will continue to run normally, but the interrupt
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* (INUM_TIMER_FRC1 or INUM_TIMER_FRC2) won't trigger again.
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*
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* * When TIMER_CTRL_INT_EDGE (default) is set, there's no need to
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* manually write to TIMER_FRCx_CLEAR_INT. The interrupt status bit
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* TIMER_CTRL_INT_STATUS automatically clears after the interrupt
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* triggers, and the interrupt handler will run again
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* automatically.
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*
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*/
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#define TIMER_CTRL_INT_EDGE 0
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#define TIMER_CTRL_INT_LEVEL BIT(0)
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#define TIMER_CTRL_INT_MASK BIT(0)
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/* Timer auto-reload bit
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This bit interacts with TIMER_FCR1_LOAD_REG & TIMER_FCR2_LOAD_REG
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differently, see those registers for details.
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*/
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#define TIMER_CTRL_RELOAD BIT(6)
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/* Timer run bit */
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#define TIMER_CTRL_RUN BIT(7)
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/* Read-only timer interrupt status.
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This bit gets set on FRC1 when interrupt fires, and cleared on a
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write to TIMER_FRC1_CLEAR_INT (cleared automatically if
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TIMER_CTRL_INT_LEVEL is not set).
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*/
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#define TIMER_CTRL_INT_STATUS BIT(8)
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/* WDT register(s)
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/* WDT register(s)
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Not fully understood yet. Writing 0 here disables wdt.
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Not fully understood yet. Writing 0 here disables wdt.
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@ -150,4 +278,29 @@ typedef volatile uint32_t *esp_reg_t;
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*/
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*/
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#define WDT_CTRL _REG(WDT_BASE, 0x00)
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#define WDT_CTRL _REG(WDT_BASE, 0x00)
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/* DPORT registers
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Control various aspects of core/peripheral interaction... Not well
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documented or understood.
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*/
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/* Set flags to enable CPU interrupts from some peripherals. Read/write.
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bit 0 - Is set by RTOS SDK startup code but function is unknown.
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bit 1 - INT_ENABLE_FRC1 allows TIMER FRC1 to trigger interrupt INUM_TIMER_FRC1.
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bit 2 - INT_ENABLE_FRC2 allows TIMER FRC2 to trigger interrupt INUM_TIMER_FRC2.
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Espressif calls this register "EDGE_INT_ENABLE_REG". The "edge" in
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question is (I think) the interrupt line from the peripheral, as
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the interrupt status bit is set. There may be a similar register
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for enabling "level" interrupts instead of edge triggering
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- this is unknown.
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*/
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#define DP_INT_ENABLE_REG _REG(DPORT_BASE, 0x04)
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/* Set to enable interrupts from TIMER FRC1 */
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#define INT_ENABLE_FRC1 BIT(1)
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/* Set to enable interrupts interrupts from TIMER FRC2 */
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#define INT_ENABLE_FRC2 BIT(2)
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#endif
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#endif
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127
examples/experiments/timers/FreeRTOSConfig.h
Normal file
127
examples/experiments/timers/FreeRTOSConfig.h
Normal file
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@ -0,0 +1,127 @@
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/*
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FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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***************************************************************************
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* *
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* FreeRTOS provides completely free yet professionally developed, *
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* robust, strictly quality controlled, supported, and cross *
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* platform software that has become a de facto standard. *
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* *
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* Help yourself get started quickly and support the FreeRTOS *
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* project by purchasing a FreeRTOS tutorial book, reference *
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* manual, or both from: http://www.FreeRTOS.org/Documentation *
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* *
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* Thank you! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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|
the terms of the GNU General Public License (version 2) as published by the
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|
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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|
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>>! NOTE: The modification to the GPL is included to allow you to distribute
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>>! a combined work that includes FreeRTOS without being obliged to provide
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>>! the source code for proprietary components outside of the FreeRTOS
|
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>>! kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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|
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. Full license text is available from the following
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link: http://www.freertos.org/a00114.html
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1 tab == 4 spaces!
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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* not run, what could be wrong?" *
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* *
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* http://www.FreeRTOS.org/FAQHelp.html *
|
||||||
|
* *
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|
***************************************************************************
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||||||
|
|
||||||
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
|
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|
license and Real Time Engineers Ltd. contact details.
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|
|
||||||
|
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
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|
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||||
|
compatible FAT file system, and our tiny thread aware UDP/IP stack.
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||||||
|
|
||||||
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
|
||||||
|
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||||
|
licenses offer ticketed support, indemnification and middleware.
|
||||||
|
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||||||
|
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||||
|
engineered and independently SIL3 certified version for use in safety and
|
||||||
|
mission critical applications that require provable dependability.
|
||||||
|
|
||||||
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1 tab == 4 spaces!
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*/
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#ifndef FREERTOS_CONFIG_H
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#define FREERTOS_CONFIG_H
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||||||
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/*-----------------------------------------------------------
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||||||
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* Application specific definitions.
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||||||
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*
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* These definitions should be adjusted for your particular hardware and
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||||||
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* application requirements.
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*
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* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||||
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* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
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||||||
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*
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||||||
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* See http://www.freertos.org/a00110.html.
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*----------------------------------------------------------*/
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#define configUSE_PREEMPTION 1
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#define configUSE_IDLE_HOOK 0
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#define configUSE_TICK_HOOK 0
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#define configCPU_CLOCK_HZ ( ( unsigned long ) 80000000 )
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#define configTICK_RATE_HZ ( ( portTickType ) 100 )
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#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 15 )
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#define configMINIMAL_STACK_SIZE ( ( unsigned short )156 )
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#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) )
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#define configMAX_TASK_NAME_LEN ( 16 )
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#define configUSE_TRACE_FACILITY 0
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#define configUSE_STATS_FORMATTING_FUNCTIONS 0
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#define configUSE_16_BIT_TICKS 0
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#define configIDLE_SHOULD_YIELD 1
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#define INCLUDE_xTaskGetIdleTaskHandle 1
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#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1
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#define configCHECK_FOR_STACK_OVERFLOW 2
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#define configUSE_MUTEXES 1
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#define configUSE_TIMERS 1
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#if configUSE_TIMERS
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#define configTIMER_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
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#define configTIMER_QUEUE_LENGTH (10)
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#define configTIMER_TASK_STACK_DEPTH ( ( unsigned short ) 512 )
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#endif
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/* Co-routine definitions. */
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#define configUSE_CO_ROUTINES 0
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#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
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/* Set the following definitions to 1 to include the API function, or zero
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to exclude the API function. */
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#define INCLUDE_vTaskPrioritySet 1
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#define INCLUDE_uxTaskPriorityGet 1
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#define INCLUDE_vTaskDelete 1
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#define INCLUDE_vTaskCleanUpResources 0
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#define INCLUDE_vTaskSuspend 1
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#define INCLUDE_vTaskDelayUntil 1
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#define INCLUDE_vTaskDelay 1
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/*set the #define for debug info*/
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#define INCLUDE_xTaskGetCurrentTaskHandle 1
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#define INCLUDE_uxTaskGetStackHighWaterMark 1
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#endif /* FREERTOS_CONFIG_H */
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2
examples/experiments/timers/Makefile
Normal file
2
examples/experiments/timers/Makefile
Normal file
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@ -0,0 +1,2 @@
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PROGRAM=timers
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include ../../../common.mk
|
||||||
140
examples/experiments/timers/timers.c
Normal file
140
examples/experiments/timers/timers.c
Normal file
|
|
@ -0,0 +1,140 @@
|
||||||
|
/* Experiments to dump timer registers at various points, mess around
|
||||||
|
* with timer registers.
|
||||||
|
*
|
||||||
|
* NOT good code, not example code, nothing something you probably
|
||||||
|
* want to mess with.
|
||||||
|
*
|
||||||
|
* This experimental reverse engineering code is in the public domain.
|
||||||
|
*/
|
||||||
|
#include "espressif/esp_common.h"
|
||||||
|
#include "espressif/sdk_private.h"
|
||||||
|
#include "FreeRTOS.h"
|
||||||
|
#include "task.h"
|
||||||
|
#include "esp8266.h"
|
||||||
|
|
||||||
|
#define DUMP_SZ 0x10 /* number of regs not size of buffer */
|
||||||
|
|
||||||
|
IRAM void dump_frc1_seq(void)
|
||||||
|
{
|
||||||
|
uint32_t f1_a = TIMER_FRC1_COUNT_REG;
|
||||||
|
uint32_t f1_b = TIMER_FRC1_COUNT_REG;
|
||||||
|
uint32_t f1_c = TIMER_FRC1_COUNT_REG;
|
||||||
|
printf("FRC1 sequence 0x%08x 0x%08x 0x%08x\r\n", f1_a, f1_b, f1_c);
|
||||||
|
printf("FRC1 deltas %d %d \r\n", f1_b-f1_a, f1_c-f1_b);
|
||||||
|
}
|
||||||
|
|
||||||
|
IRAM void dump_frc2_seq(void)
|
||||||
|
{
|
||||||
|
/* this sequence of reads compiles down to sequence of l32is with
|
||||||
|
* memw instructions in between.
|
||||||
|
*
|
||||||
|
* counts at various divisor values:
|
||||||
|
* /1 = 13
|
||||||
|
* /16 = 0 or 1 (usually 1)
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
uint32_t f2_a = TIMER_FRC2_COUNT_REG;
|
||||||
|
uint32_t f2_b = TIMER_FRC2_COUNT_REG;
|
||||||
|
uint32_t f2_c = TIMER_FRC2_COUNT_REG;
|
||||||
|
printf("FRC2 sequence 0x%08x 0x%08x 0x%08x\r\n", f2_a, f2_b, f2_c);
|
||||||
|
printf("FRC2 deltas %d %d \r\n", f2_b-f2_a, f2_c-f2_b);
|
||||||
|
}
|
||||||
|
|
||||||
|
IRAM void dump_timer_regs(const char *msg)
|
||||||
|
{
|
||||||
|
esp_reg_t reg = (esp_reg_t)TIMER_BASE;
|
||||||
|
static uint32_t chunk[DUMP_SZ];
|
||||||
|
|
||||||
|
/* load everything as quickly as possible to get a "snapshot" */
|
||||||
|
for(int i = 0; i < DUMP_SZ; i++) {
|
||||||
|
chunk[i] = reg[i];
|
||||||
|
}
|
||||||
|
|
||||||
|
printf("%s:\r\n", msg);
|
||||||
|
/* print the chunk we loaded */
|
||||||
|
for(int i = 0; i < DUMP_SZ; i++) {
|
||||||
|
if(i % 4 == 0)
|
||||||
|
printf("%s0x%02x: ", i ? "\r\n" : "", i*4);
|
||||||
|
printf("%08x ", chunk[i]);
|
||||||
|
}
|
||||||
|
printf("\r\n");
|
||||||
|
|
||||||
|
dump_frc1_seq();
|
||||||
|
dump_frc2_seq();
|
||||||
|
}
|
||||||
|
|
||||||
|
extern uint32_t isr[16];
|
||||||
|
extern uint32_t seen_isr[16];
|
||||||
|
extern uint32_t max_count;
|
||||||
|
|
||||||
|
static volatile uint32_t frc2_handler_call_count;
|
||||||
|
static volatile uint32_t frc2_last_count_val;
|
||||||
|
|
||||||
|
static volatile uint32_t frc1_handler_call_count;
|
||||||
|
static volatile uint32_t frc1_last_count_val;
|
||||||
|
|
||||||
|
void timerRegTask(void *pvParameters)
|
||||||
|
{
|
||||||
|
while(1) {
|
||||||
|
printf("state at task tick count %d:\r\n", xTaskGetTickCount());
|
||||||
|
dump_timer_regs("");
|
||||||
|
|
||||||
|
/*
|
||||||
|
for(int i = 0; i < 16; i++) {
|
||||||
|
printf("int 0x%02x: 0x%08x (%d)\r\n", i, isr[i], seen_isr[i]);
|
||||||
|
}
|
||||||
|
printf("INUM_MAX count %d\r\n", max_count);
|
||||||
|
*/
|
||||||
|
|
||||||
|
printf("frc1 handler called %d times, last value 0x%08x\r\n", frc1_handler_call_count,
|
||||||
|
frc1_last_count_val);
|
||||||
|
|
||||||
|
printf("frc2 handler called %d times, last value 0x%08x\r\n", frc2_handler_call_count,
|
||||||
|
frc2_last_count_val);
|
||||||
|
|
||||||
|
vTaskDelay(500 / portTICK_RATE_MS);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
IRAM void frc1_handler(void)
|
||||||
|
{
|
||||||
|
frc1_handler_call_count++;
|
||||||
|
frc1_last_count_val = TIMER_FRC1_COUNT_REG;
|
||||||
|
//TIMER_FRC1_LOAD_REG = 0x300000;
|
||||||
|
//TIMER_FRC1_CLEAR_INT = 0;
|
||||||
|
//TIMER_FRC1_MATCH_REG = frc1_last_count_val + 0x100000;
|
||||||
|
}
|
||||||
|
|
||||||
|
void frc2_handler(void)
|
||||||
|
{
|
||||||
|
frc2_handler_call_count++;
|
||||||
|
frc2_last_count_val = TIMER_FRC2_COUNT_REG;
|
||||||
|
TIMER_FRC2_MATCH_REG = frc2_last_count_val + 0x100000;
|
||||||
|
//TIMER_FRC2_LOAD_REG = 0;
|
||||||
|
//TIMER_FRC2_LOAD_REG = 0x2000000;
|
||||||
|
//TIMER_FRC2_CLEAR_INT_REG = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void user_init(void)
|
||||||
|
{
|
||||||
|
sdk_uart_div_modify(0, UART_CLK_FREQ / 115200);
|
||||||
|
xTaskCreate(timerRegTask, (signed char *)"timerRegTask", 1024, NULL, 2, NULL);
|
||||||
|
|
||||||
|
TIMER_FRC1_CTRL_REG = TIMER_CTRL_DIV_256|TIMER_CTRL_INT_EDGE|TIMER_CTRL_RELOAD;
|
||||||
|
TIMER_FRC1_LOAD_REG = 0x200000;
|
||||||
|
|
||||||
|
TIMER_FRC2_CTRL_REG = TIMER_CTRL_DIV_256|TIMER_CTRL_INT_EDGE;
|
||||||
|
|
||||||
|
DP_INT_ENABLE_REG |= INT_ENABLE_FRC1|INT_ENABLE_FRC2;
|
||||||
|
_xt_isr_attach(INUM_TIMER_FRC1, frc1_handler);
|
||||||
|
_xt_isr_unmask(1<<INUM_TIMER_FRC1);
|
||||||
|
_xt_isr_attach(INUM_TIMER_FRC2, frc2_handler);
|
||||||
|
_xt_isr_unmask(1<<INUM_TIMER_FRC2);
|
||||||
|
|
||||||
|
TIMER_FRC1_CTRL_REG |= TIMER_CTRL_RUN;
|
||||||
|
TIMER_FRC2_CTRL_REG |= TIMER_CTRL_RUN;
|
||||||
|
|
||||||
|
dump_timer_regs("timer regs during user_init");
|
||||||
|
dump_timer_regs("#2 timer regs during user_init");
|
||||||
|
dump_timer_regs("#3 timer regs during user_init");
|
||||||
|
}
|
||||||
Loading…
Reference in a new issue