Flush the uart tx fifo before a restart. (#274)

Also comment the point at which the bus clock that drives the uart changes on startup and comment out the change in the uart divisor. This at least allows a consistent uart baud rate during a restart if using the rate 115200.

core/app_main.c

@@ -254,12 +254,25 @@ static void zero_bss(void) {
 
 // .Lfunc006 -- .irom0.text+0x70
 static void init_networking(sdk_phy_info_t *phy_info, uint8_t *mac_addr) {
+    // The call to sdk_register_chipv6_phy appears to change the bus clock,
+    // perhaps from 40MHz to 26MHz, at least it has such an effect on the uart
+    // baud rate. The caller flushes the TX fifos.
     if (sdk_register_chipv6_phy(phy_info)) {
         printf("FATAL: sdk_register_chipv6_phy failed");
         abort();
     }
-    uart_set_baud(0, 74906);
+
-    uart_set_baud(1, 74906);
+    // The boot rom initializes uart0 for a 115200 baud rate but the bus clock
+    // does not appear to be as expected so the initial baud rate is actually
+    // 74906. On a cold boot, to keep the 74906 baud rate the uart0 divisor
+    // would need to changed here to 74906. On a warm boot the bus clock is
+    // expected to have already been set so the boot baud rate is 115200.
+    // Reset the rate here and settle on a 115200 baud rate.
+    if (sdk_rst_if.reason > 0) {
+        uart_set_baud(0, 115200);
+        uart_set_baud(1, 115200);
+    }
+
     sdk_phy_disable_agc();
     sdk_ieee80211_phy_init(sdk_g_ic.s.phy_mode);
     sdk_lmacInit();

open_esplibs/libmain/user_interface.c

@@ -20,6 +20,7 @@
 #include "esp/iomux_regs.h"
 #include "esp/sar_regs.h"
 #include "esp/wdev_regs.h"
+#include "esp/uart.h"
 
 #include "etstimer.h"
 #include "espressif/sdk_private.h"
@@ -79,16 +80,23 @@ void IRAM sdk_system_restart_in_nmi(void) {
         buf[0] = 3;
         sdk_system_rtc_mem_write(0, buf, 32);
     }
+
+    uart_flush_txfifo(0);
+    uart_flush_txfifo(1);
+
     if (!sdk_NMIIrqIsOn) {
         portENTER_CRITICAL();
         do {
             DPORT.DPORT0 = SET_FIELD(DPORT.DPORT0, DPORT_DPORT0_FIELD0, 0);
         } while (DPORT.DPORT0 & 1);
     }
+
     ESPSAR.UNKNOWN_48 |= 3;
     DPORT.CLOCKGATE_WATCHDOG |= DPORT_CLOCKGATE_WATCHDOG_UNKNOWN_8;
     ESPSAR.UNKNOWN_48 &= ~3;
     DPORT.CLOCKGATE_WATCHDOG &= ~DPORT_CLOCKGATE_WATCHDOG_UNKNOWN_8;
+
+    Wait_SPI_Idle(&sdk_flashchip);
     Cache_Read_Disable();
     DPORT.SPI_CACHE_RAM &= ~(DPORT_SPI_CACHE_RAM_BANK0 | DPORT_SPI_CACHE_RAM_BANK1);
     // This calls directly to 0x40000080, the "reset" exception vector address.
@@ -559,8 +567,8 @@ enum sdk_dhcp_status sdk_wifi_station_dhcpc_status(void) {
 
 void sdk_system_uart_swap()
 {
-    while (FIELD2VAL(UART_STATUS_TXFIFO_COUNT, UART(0).STATUS)) {};
+    uart_flush_txfifo(0);
-    while (FIELD2VAL(UART_STATUS_TXFIFO_COUNT, UART(1).STATUS)) {};
+    uart_flush_txfifo(1);
 
     /* Disable pullup IO_MUX_MTDO, Alt TX. GPIO15. */
     iomux_set_pullup_flags(3, 0);
@@ -576,8 +584,8 @@ void sdk_system_uart_swap()
 
 void sdk_system_uart_de_swap()
 {
-    while (FIELD2VAL(UART_STATUS_TXFIFO_COUNT, UART(0).STATUS)) {};
+    uart_flush_txfifo(0);
-    while (FIELD2VAL(UART_STATUS_TXFIFO_COUNT, UART(1).STATUS)) {};
+    uart_flush_txfifo(1);
 
     /* Disable pullup IO_MUX_U0TXD, TX. GPIO 1. */
     iomux_set_pullup_flags(5, 0);