Merge pull request #528 from UncleRus/extras/f-ram
Driver for Cypress serial F-RAM
This commit is contained in:
Ruslan V. Uss
GitHub
commit
126fbc20a7
5 changed files with 361 additions and 0 deletions
9
extras/fram/component.mk
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9
extras/fram/component.mk
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# Component makefile for extras/fram
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# expected anyone using ADC driver includes it as 'fram/fram.h'
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INC_DIRS += $(fram_ROOT)..
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# args for passing into compile rule generation
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fram_SRC_DIR = $(fram_ROOT)
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$(eval $(call component_compile_rules,fram))
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183
extras/fram/fram.c
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183
extras/fram/fram.c
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/**
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* Driver for serial nonvolatile ferroelectric random access
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* memory or F-RAM.
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*
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* Part of esp-open-rtos
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* Copyright (C) 2017 Ruslan V. Uss <unclerus@gmail.com>
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* BSD Licensed as described in the file LICENSE
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*/
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#include "fram.h"
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#include <esp/gpio.h>
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#define CMD_WRSR 0x01 // 0b00000001
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#define CMD_WRITE 0x02 // 0b00000010
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#define CMD_READ 0x03 // 0b00000011
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#define CMD_WRDI 0x04 // 0b00000100
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#define CMD_RDSR 0x05 // 0b00000101
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#define CMD_WREN 0x06 // 0b00000110
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#define CMD_FSTRD 0x0b // 0b00001011
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#define CMD_RDID 0x9f // 0b10011111
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#define CMD_SLEEP 0xb9 // 0b10111001
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#define CMD_SNR 0xc3 // 0b11000011
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#define SR_BIT_WEL 1
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#define SR_BIT_BP0 2
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#define SR_BIT_BP1 3
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#define SR_BIT_WPEN 7
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#define SR_MASK_BP (0x03 << SR_BIT_BP0)
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static const spi_settings_t defaults = {
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.endianness = SPI_BIG_ENDIAN,
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.msb = true,
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.mode = SPI_MODE0,
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.minimal_pins = true,
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.freq_divider = SPI_FREQ_DIV_40M
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};
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inline static void chip_select(const fram_t *dev)
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{
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gpio_write(dev->cs_gpio, false);
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}
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inline static void chip_unselect(const fram_t *dev)
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{
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gpio_write(dev->cs_gpio, true);
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}
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static uint8_t read_status_reg(const fram_t *dev)
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{
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chip_select(dev);
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spi_transfer_8(dev->spi_bus, CMD_RDSR);
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uint8_t res = spi_transfer_8(dev->spi_bus, 0xff);
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chip_unselect(dev);
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return res;
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}
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static void write_status_reg(const fram_t *dev, uint8_t val)
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{
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chip_select(dev);
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spi_transfer_8(dev->spi_bus, CMD_WREN);
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chip_unselect(dev);
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chip_select(dev);
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spi_transfer_8(dev->spi_bus, CMD_WRSR);
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spi_transfer_8(dev->spi_bus, val);
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}
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void fram_init(const fram_t *dev)
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{
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gpio_enable(dev->cs_gpio, GPIO_OUTPUT);
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gpio_set_pullup(dev->cs_gpio, true, true);
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chip_unselect(dev);
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}
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static void begin(const fram_t *dev, spi_settings_t *s, spi_settings_t *old)
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{
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spi_get_settings(dev->spi_bus, &old);
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memcpy(&s, &defaults, sizeof(spi_settings_t));
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s->freq_divider = dev->spi_freq_div;
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spi_set_settings(dev->spi_bus, &s);
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chip_select(dev);
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}
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static void end(const fram_t *dev, spi_settings_t *old)
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{
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chip_unselect(dev);
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spi_set_settings(dev->spi_bus, &old);
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}
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void fram_read(const fram_t *dev, void *to, void *from, size_t size)
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{
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spi_settings_t s, old;
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begin(dev, &s, &old);
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uint32_t header = ((uint32_t)CMD_READ << 24) | ((uint32_t)from & 0x00ffffff);
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spi_transfer_32(dev->spi_bus, header);
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spi_set_endianness(dev->spi_bus, SPI_LITTLE_ENDIAN);
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spi_read(dev->spi_bus, 0xff, to, size, SPI_8BIT);
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end(dev, &old);
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}
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void fram_write(const fram_t *dev, void *from, void *to, size_t size)
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{
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spi_settings_t s, old;
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begin(dev, &s, &old);
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spi_transfer_8(dev->spi_bus, CMD_WREN);
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chip_unselect(dev);
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chip_select(dev);
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uint32_t header = ((uint32_t)CMD_WRITE << 24) | ((uint32_t)to & 0x00ffffff);
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spi_transfer_32(dev->spi_bus, header);
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spi_set_endianness(dev->spi_bus, SPI_LITTLE_ENDIAN);
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spi_transfer(dev->spi_bus, from, NULL, size, SPI_8BIT);
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end(dev, &old);
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}
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void fram_sleep(const fram_t *dev, bool sleep)
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{
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if (!sleep)
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{
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chip_select(dev);
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chip_unselect(dev);
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return;
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}
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spi_settings_t s, old;
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begin(dev, &s, &old);
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spi_transfer_8(dev->spi_bus, CMD_SLEEP);
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end(dev, &old);
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}
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bool fram_busy(const fram_t *dev)
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{
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gpio_enable(dev->cs_gpio, GPIO_INPUT);
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bool res = !gpio_read(dev->cs_gpio);
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fram_init(dev);
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return res;
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}
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void fram_id(const fram_t *dev, fram_id_t *id)
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{
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spi_settings_t s, old;
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begin(dev, &s, &old);
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spi_transfer_8(dev->spi_bus, CMD_RDID);
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for (uint8_t i = 0; i < FRAM_ID_LEN; i ++)
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id->data[FRAM_ID_LEN - i - 1] = spi_transfer_8(dev->spi_bus, 0xff);
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end(dev, &old);
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}
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void fram_set_wp_mode(const fram_t *dev, fram_wp_mode_t mode)
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{
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spi_settings_t s, old;
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begin(dev, &s, &old);
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write_status_reg(dev, (read_status_reg(dev) & ~SR_MASK_BP) | ((mode & 0x03) << SR_BIT_BP0));
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end(dev, &old);
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}
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fram_wp_mode_t fram_get_wp_mode(const fram_t *dev)
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{
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spi_settings_t s, old;
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begin(dev, &s, &old);
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fram_wp_mode_t res = (fram_wp_mode_t)((read_status_reg(dev) & SR_MASK_BP) >> SR_BIT_BP0);
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end(dev, &old);
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return res;
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}
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124
extras/fram/fram.h
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124
extras/fram/fram.h
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@ -0,0 +1,124 @@
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/**
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* Driver for serial nonvolatile ferroelectric random access
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* memory or F-RAM.
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*
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* Part of esp-open-rtos
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* Copyright (C) 2017 Ruslan V. Uss <unclerus@gmail.com>
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* BSD Licensed as described in the file LICENSE
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*/
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#ifndef EXTRAS_FRAM_H_
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#define EXTRAS_FRAM_H_
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#include <esp/spi.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define FRAM_ID_LEN 9
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/**
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* F-RAM device descriptor
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*/
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typedef struct
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{
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uint8_t spi_bus; //!< SPI bus
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uint8_t cs_gpio; //!< chip select GPIO
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uint32_t spi_freq_div; //!< SPI bus frequency divider
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} fram_t;
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/**
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* F-RAM device ID
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*/
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typedef struct
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{
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uint8_t data[FRAM_ID_LEN];
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union
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{
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uint8_t rsvd: 3;
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uint8_t rev: 3;
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uint8_t sub: 2;
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uint8_t density: 5;
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uint8_t family: 3;
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uint8_t manufacturer[FRAM_ID_LEN - 2];
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};
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} fram_id_t;
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/**
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* Write protection mode
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*/
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typedef enum
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{
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FRAM_WP_NONE = 0, //!< No write protection
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FRAM_WP_UPPER_QUARTER,//!< Upper 1/4 write protection
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FRAM_WP_UPPER_HALF, //!< Upper 1/2 write protection
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FRAM_WP_ALL //!< All memory write protection
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} fram_wp_mode_t;
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/**
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* Prepare to read/write F-RAM
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* @param dev Pointer to device descriptor
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*/
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void fram_init(const fram_t *dev);
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/**
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* Read data from F-RAM
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* @param dev Pointer to device descriptor
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* @param to Buffer to store data
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* @param from F-RAM address
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* @param size Bytes to read
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*/
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void fram_read(const fram_t *dev, void *to, void *from, size_t size);
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/**
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* Write data to F-RAM
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* @param dev Pointer to device descriptor
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* @param from Data buffer
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* @param to F-RAM address
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* @param size Bytes to write
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*/
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void fram_write(const fram_t *dev, void *from, void *to, size_t size);
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/**
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* Set device to sleep mode or wake up
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* @param dev Pointer to device descriptor
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* @param sleep Set to sleep mode when true, wake up otherwise
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*/
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void fram_sleep(const fram_t *dev, bool sleep);
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/**
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* Check if F-RAM busy with another SPI master.
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* To use this method of sharing F-RAM between two masters
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* you'll need to pull up CS GPIO line
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* @param dev Pointer to device descriptor
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* @return true when device is busy
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*/
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bool fram_busy(const fram_t *dev);
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/**
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* Read the device ID
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* @param dev Pointer to device descriptor
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* @param id Poiner to device ID structure
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*/
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void fram_id(const fram_t *dev, fram_id_t *id);
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/**
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* Set block write protection mode
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* @param dev Pointer to device descriptor
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* @param mode Write protection mode
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*/
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void fram_set_wp_mode(const fram_t *dev, fram_wp_mode_t mode);
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/**
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* Get current write protection mode
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* @param dev Pointer to device descriptor
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* @return Write protection mode
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*/
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fram_wp_mode_t fram_get_wp_mode(const fram_t *dev);
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#ifdef __cplusplus
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}
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#endif
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#endif /* EXTRAS_FRAM_H_ */
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