54 lines
1.6 KiB
C
54 lines
1.6 KiB
C
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/* esp/dport_regs.h
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*
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* ESP8266 DPORT0 register definitions
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*
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* Not compatible with ESP SDK register access code.
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*/
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#ifndef _ESP_DPORT_REGS_H
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#define _ESP_DPORT_REGS_H
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#include "esp/types.h"
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#include "common_macros.h"
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#define DPORT_BASE 0x3ff00000
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#define DPORT (*(struct DPORT_REGS *)(DPORT_BASE))
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/* DPORT registers
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Control various aspects of core/peripheral interaction... Not well
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documented or understood.
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*/
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struct DPORT_REGS {
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uint32_t volatile _unknown0; // 0x00
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uint32_t volatile INT_ENABLE; // 0x04
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} __attribute__ (( packed ));
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_Static_assert(sizeof(struct DPORT_REGS) == 0x08, "DPORT_REGS is the wrong size");
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/* Details for INT_ENABLE register */
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/* Set flags to enable CPU interrupts from some peripherals. Read/write.
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bit 0 - Is set by RTOS SDK startup code but function is unknown.
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bit 1 - INT_ENABLE_TIMER0 allows TIMER 0 (FRC1) to trigger interrupt INUM_TIMER_FRC1.
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bit 2 - INT_ENABLE_TIMER1 allows TIMER 1 (FRC2) to trigger interrupt INUM_TIMER_FRC2.
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Espressif calls this register "EDGE_INT_ENABLE_REG". The "edge" in
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question is (I think) the interrupt line from the peripheral, as
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the interrupt status bit is set. There may be a similar register
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for enabling "level" interrupts instead of edge triggering
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- this is unknown.
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*/
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#define DPORT_INT_ENABLE_TIMER0 BIT(1)
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#define DPORT_INT_ENABLE_TIMER1 BIT(2)
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/* Aliases for the Espressif way of referring to TIMER0 (FRC1) and TIMER1
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* (FRC2).. */
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#define DPORT_INT_ENABLE_FRC1 DPORT_INT_ENABLE_TIMER0
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#define DPORT_INT_ENABLE_FRC2 DPORT_INT_ENABLE_TIMER1
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#endif /* _ESP_DPORT_REGS_H */
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