2015-04-30 04:00:03 +00:00
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/*
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* Copyright (c) Espressif System 2010 - 2012
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*
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*/
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#ifndef _EAGLE_SOC_H_
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#define _EAGLE_SOC_H_
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//Register Bits{{
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#define BIT31 0x80000000
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#define BIT30 0x40000000
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#define BIT29 0x20000000
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#define BIT28 0x10000000
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#define BIT27 0x08000000
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#define BIT26 0x04000000
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#define BIT25 0x02000000
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#define BIT24 0x01000000
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#define BIT23 0x00800000
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#define BIT22 0x00400000
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#define BIT21 0x00200000
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#define BIT20 0x00100000
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#define BIT19 0x00080000
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#define BIT18 0x00040000
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#define BIT17 0x00020000
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#define BIT16 0x00010000
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#define BIT15 0x00008000
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#define BIT14 0x00004000
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#define BIT13 0x00002000
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#define BIT12 0x00001000
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#define BIT11 0x00000800
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#define BIT10 0x00000400
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#define BIT9 0x00000200
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#define BIT8 0x00000100
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#define BIT7 0x00000080
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#define BIT6 0x00000040
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#define BIT5 0x00000020
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#define BIT4 0x00000010
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#define BIT3 0x00000008
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#define BIT2 0x00000004
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#define BIT1 0x00000002
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#define BIT0 0x00000001
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//}}
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
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#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
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#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
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#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
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#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
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#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|((value)<<(shift)) ))
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//}}
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//Periheral Clock {{
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#define CPU_CLK_FREQ 80*1000000 // unit: Hz
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#define APB_CLK_FREQ CPU_CLK_FREQ
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#define UART_CLK_FREQ APB_CLK_FREQ
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#define TIMER_CLK_FREQ (APB_CLK_FREQ>>8) // divided by 256
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//}}
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//Peripheral device base address define{{
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#define PERIPHS_DPORT_BASEADDR 0x3ff00000
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#define PERIPHS_RTC_BASEADDR 0x60000700
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//}}
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//DPORT{{
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2016-05-31 19:10:14 +00:00
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#define HOST_INF_SEL (PERIPHS_DPORT_BASEADDR + 0x28)
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2015-04-30 04:00:03 +00:00
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#define DPORT_LINK_DEVICE_SEL 0x000000FF
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#define DPORT_LINK_DEVICE_SEL_S 8
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#define DPORT_PERI_IO_SWAP 0x000000FF
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#define DPORT_PERI_IO_SWAP_S 0
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#define PERI_IO_CSPI_OVERLAP (BIT(7)) // two spi masters on cspi
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#define PERI_IO_HSPI_OVERLAP (BIT(6)) // two spi masters on hspi
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#define PERI_IO_HSPI_PRIO (BIT(5)) // hspi is with the higher prior
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#define PERI_IO_UART1_PIN_SWAP (BIT(3)) // swap uart1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts)
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#define PERI_IO_UART0_PIN_SWAP (BIT(2)) // swap uart0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts)
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#define PERI_IO_SPI_PORT_SWAP (BIT(1)) // swap two spi
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#define PERI_IO_UART_PORT_SWAP (BIT(0)) // swap two uart
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//}}
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//Interrupt remap control registers define{{
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#define EDGE_INT_ENABLE_REG (PERIPHS_DPORT_BASEADDR+0x04)
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#define TM1_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
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#define TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
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//}}
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//RTC reg {{
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#define REG_RTC_BASE PERIPHS_RTC_BASEADDR
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#define RTC_SLP_VAL (REG_RTC_BASE + 0x004) // the target value of RTC_COUNTER for wakeup from light-sleep/deep-sleep
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#define RTC_SLP_CNT_VAL (REG_RTC_BASE + 0x01C) // the current value of RTC_COUNTER
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#define RTC_SCRATCH0 (REG_RTC_BASE + 0x030) // the register for software to save some values for watchdog reset
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#define RTC_SCRATCH1 (REG_RTC_BASE + 0x034) // the register for software to save some values for watchdog reset
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#define RTC_SCRATCH2 (REG_RTC_BASE + 0x038) // the register for software to save some values for watchdog reset
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#define RTC_SCRATCH3 (REG_RTC_BASE + 0x03C) // the register for software to save some values for watchdog reset
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#define RTC_GPIO_OUT (REG_RTC_BASE + 0x068) // used by gpio16
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#define RTC_GPIO_ENABLE (REG_RTC_BASE + 0x074)
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#define RTC_GPIO_IN_DATA (REG_RTC_BASE + 0x08C)
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#define RTC_GPIO_CONF (REG_RTC_BASE + 0x090)
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#define PAD_XPD_DCDC_CONF (REG_RTC_BASE + 0x0A0)
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//}}
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#endif //_EAGLE_SOC_H_
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