483 lines
17 KiB
C
483 lines
17 KiB
C
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/** Internal Espressif SDK "PHY info" data structure
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The data structure (sdk_phy_info_t) is used to configure the
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ESP8266 PHY layer via the SDK. The fields here are not written
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directly to hardware, the SDK code (mostly in libphy) parses this
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structure and configures the hardware.
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The structure loaded at reset time from a flash configuration
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sector (see read_saved_phy_info()) (Espressif's SDK sources this
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from a file "esp_init_data_default.bin"). If no valid structure is
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found in the flash config sector then the SDK loads default values
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(see get_default_phy_info()). It is possible to implement a custom
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get_default_phy_info() to change the PHY default settings (see the
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'version' field below).
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@note It is possible that the SDK will quietly write a new
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configuration sector to flash itself following internal
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calibration, etc. However this does not seem to happen, you need to
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flash it explicitly if you want it stored there.
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@note Most of what is below is unconfirmed, except where a @note
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says that it has been confirmed to work as expected. Please
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consider submitting notes if you find behaviour here that works or
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doesn't work as expected.
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Information on the meaning/offset of fields comes from Espressif's
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flash download tool, which uses an Excel spreadsheet (in the
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init_data directory of the ZIP file) to configure and a Python
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script to convert an esp_init_data_custom.bin file to flash:
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http://bbs.espressif.com/viewtopic.php?f=5&t=433
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Many fields remain undocumented (& disassembly of libphy suggests
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that some documented fields supported undocumented values.)
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A few additional notes about the phy_info fields can be found
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in the ESP Arduino ESP8266 phy_init_data structure (however most of
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that content is verbatim from Espressif's spreadsheet):
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https://github.com/esp8266/Arduino/blob/master/cores/esp8266/core_esp8266_phy.c#L29
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Part of esp-open-rtos. Copyright (C) 2016 Angus Gratton,
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BSD Licensed as described in the file LICENSE.
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*/
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#ifndef _ESPRESSIF_PHY_INFO_H
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#define _ESPRESSIF_PHY_INFO_H
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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/* CRYSTAL_FREQ_xx values as used by sdk_phy_info_t.crystal_freq */
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#define CRYSTAL_FREQ_40M 0
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#define CRYSTAL_FREQ_26M 1
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#define CRYSTAL_FREQ_24M 2
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/* SDIO_CONFIG_xx values as used by sdk_phy_info_t.sdio_config */
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#define SDIO_CONFIG_AUTO 0 /* Uses pin strapping to determine */
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#define SDIO_CONFIG_SDIOV1_1 /* Data output on negative edge */
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#define SDIO_CONFIG_SDIOV2_0 /* data output on positive edge */
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/* BT_COEXIST_CONFIG_xx values as used by sdk_phy_info_t.bt_coexist */
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/* No bluetooth */
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#define BT_COEXIST_CONFIG_NONE 0
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/* Coexistence configuration A:
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GPIO 0 - WLAN_ACTIVE
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GPIO 14 - BT_ACTIVE
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GPIO 13 - BT_PRIORITY
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GPIO 3 - ANT_SEL_BT
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*/
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#define BT_COEXIST_CONFIG_A 1
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/* No coexistence, but Bluetooth enabled?
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Unsure how this works?
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*/
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#define BT_COEXIST_CONFIG_PRESENT 2
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/* Coexistence configuration B:
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GPIO 0 - WLAN_ACTIVE
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GPIO 14 - BT_PRIORITY
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GPIO 13 - BT_ACTIVE
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GPIO 3 - ANT_SEL_BT
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*/
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#define BT_COEXIST_CONFIG_B 3
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/* BT_COEXIST_PROTOCOL_xx values for coexistence protocol,
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field sdk_phy_info_t.bt_coexist_protocol
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*/
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#define BT_COEXIST_PROTOCOL_WIFI_ONLY 0
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#define BT_COEXIST_PROTOCOL_BT_ONLY 1
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/* Coexistence is enabled, Bluetooth has its own antenna */
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#define BT_COEXIST_PROTOCOL_FLAG_SEPARATE_ANT 2
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/* Coexistence is enabled, Bluetooth shares WiFi antenna */
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#define BT_COEXIST_PROTOCOL_FLAG_SHARE_ANT 4
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/* Coexistence is enabled, use only BT_ACTIVE signal */
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#define BT_COEXIST_PROTOCOL_FLAG_BT_ACTIVE_ONLY 0
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/* Coexistence is enabled, use both BT_ACTIVE and BT_PRIORITY signals */
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#define BT_COEXIST_PROTOCOL_FLAG_BT_ACTIVE_PRIORITY 1
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/* DUAL_ANT_CONFIG_xx values for dual antenna config,
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field sdk_phy_info_t.dual_ant_config
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(Not really clear how this feature works, if at all.)
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*/
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#define DUAL_ANT_CONFIG_NONE 0
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/* antenna diversity for WiFi, use GPIO0 + U0RXD (?) */
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#define DUAL_ANT_CONFIG_DUAL 1
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/* TX/RX switch for external PA & LNA: GPIO 0 high, GPIO 3 low during TX */
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#define DUAL_ANT_CONFIG_TX_GPIO0_HIGH_GPIO3_LOW
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/* TX/RX switch for external PA & LNA: GPIO 0 low, GPIO 3 high during TX */
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#define DUAL_ANT_CONFIG_TX_GPIO0_LOW_GPIO3_HIGH
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/* CRYSTAL_SLEEP_xx values used for sdk_phy_info_t.crystal_sleep
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*/
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#define CRYSTAL_SLEEP_OFF 0
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#define CRYSTAL_SLEEP_ON 1
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#define CRYSTAL_SLEEP_GPIO16 2
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#define CRYSTAL_SLEEP_GPIO2 3
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/* RF Stage 0 & 1 attenuation constants. Use for sdk_phy_info_t.lp_atten_stage01
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@note These values have been tested and are confirmed to work as
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expected by measuring RSSI w/ rt73 USB adapter in monitor mode
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(some values also checked on spectrum analyzer) - provided
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low_power_en is set then the signal is attenuated as per this
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setting.
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(It may look like LP_ATTEN_STAGE01_11_5DB is out of order, but
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according to monitor mode captures this is the correct ordering of
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these constants.)
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Setting the numeric values in between these constants appears to
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also attenuate the signal, but not necessarily by the amount you'd
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expect.
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*/
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#define LP_ATTEN_STAGE01_0DB 0x0f /* 0dB */
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#define LP_ATTEN_STAGE01_2_5DB 0x0e /* -2.5dB */
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#define LP_ATTEN_STAGE01_6DB 0x0d /* -6dB */
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#define LP_ATTEN_STAGE01_8_5DB 0x09 /* -8.5dB */
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#define LP_ATTEN_STAGE01_11_5DB 0x0c /* -11.5dB */
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#define LP_ATTEN_STAGE01_14DB 0x08 /* -14dB */
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#define LP_ATTEN_STAGE01_17_5DB 0x04 /* -17.5dB */
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#define LP_ATTEN_STAGE01_23DB 0x00 /* -23dB */
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/* Constant for sdk_phy_info_t.pa_vdd */
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#define PA_VDD_MEASURE_VCC 0xFF
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/* Bitmask flags for sdk_phy_info_t.freq_correct_mode */
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/* Set this flag to disable frequency offset correction */
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#define FREQ_CORRECT_DISABLE 0
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/* Set this flag to enable frequency offset correction */
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#define FREQ_CORRECT_ENABLE BIT(0)
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/* Set = Baseband PLL frequency is 160MHz (can only apply +ve offset)
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* Unset = Baseband PLL frequency is 168MHz (can apply +ve/-ve offset */
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#define FREQ_CORRECT_BB_160M BIT(1)
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/* Set = use force_freq_offset field to correct, Unset = automatically
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measure & correct offset
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*/
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#define FREQ_CORRECT_FORCE BIT(2)
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/* RF_CAL_MODE_xx fields used for sdk_phy_info_t.rf_cal_mode
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*/
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/* Use saved RF CAL data from flash, only. RF init takes 2ms. */
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#define RF_CAL_MODE_SAVED 0
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/* Calibrate TX power control only, use saved RF CAL data for others.
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RF init takes 20ms. */
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#define RF_CAL_MODE_TXPOWER_ONLY 1
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/* Unclear if/how this mode is different to 2? */
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#define RF_CAL_MODE_SAVED_2 2
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/* Run full RF CAL routine. RF init takes approx 200ms. */
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#define RF_CAL_MODE_FULL 3
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/* Data structure that maps to the phy_info configuration block */
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typedef struct __attribute__((packed)) {
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uint8_t _reserved00[0x05]; /* 0x00 - 0x04 */
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/* This "version" field was set to 5 in the SDK phy_info,
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and the original SDK startup code checks it is 5 and then loads
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default PHY configuration otherwise.
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esp-open-rtos will load phy_info from get_default_phy_info() if
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the value stored in flash has a different value to the value
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returned in get_default_phy_info(). This means you can
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increment the version return by get_default_phy_info() (to any
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value but 0xFF), and know that the new defaults will replace
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any older stored values.
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@notes It's not clear whether this is actually a version field
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(the other 24 bytes here have equally arbitrary numbers in
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them.) Changing the "version" to other values does not seem to
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effect WiFi performance at all, neither does zeroing out the
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first 5 reserved bytes in _reserved00. However zeroing bytes in
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the _reserved06 region will break WiFi entirely.
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*/
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uint8_t version; /* 0x05 */
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int8_t _reserved06[0x14]; /* 0x06 - 0x19 */
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/* spur_freq = spur_freq_primary / spur_freq_divisor */
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uint8_t spur_freq_primary; /* 0x1a */
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uint8_t spur_freq_divisor; /* 0x1b */
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/* Bitmask to enable spur_freq for each channel
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Appears to be a big endian short word?
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*/
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uint8_t spur_freq_en_h; /* 0x1c */
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uint8_t spur_freq_en_l; /* 0x1d */
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uint8_t _reserved1e[4]; /* 0x1e - 0x21 */
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/* Each value is a target power level.
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Units are 1/4 dBm ie value 64 = 16dBm.
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SDK defaults to using these transmit powers:
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20.5dBm, 19.5dBm, 18.5dBm, 17dBm, 16dBm, 14dBm
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@note Adjusting these values is confirmed to reduce
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transmit power accordingly.
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*/
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uint8_t target_power[6]; /* 0x22 - 0x27 */
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/* Maps 8 MCS (modulation & coding schemes) types for 802.11b, g &
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* n to a target_power level index (0-5), set above.
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This mapping of MCS slot to MCS type is derived from the
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spreadsheet and also a table sent by Espressif, but is untested
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and may be SDK version dependendent (especially any 802.11n
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rates). However the general relationship is confirmed to hold
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(higher MCS index = higher bit rate).
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MCS 0: 1Mbps/2Mbps/5.5Mbps/11Mbps (802.11b) / 6Mbps/9Mbps (802.11g)
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default target_power 0 (default 20.5dBm)
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(see also pwr_ind_11b_en)
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MCS 1: 12Mbps (802.11g)
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default target_power 0 (default 20.5dBm)
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MCS 2: 18Mbps (802.11g)
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default target_power 1 (19.5dBm)
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MCS 3: 24Mbps (802.11g)
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default target_power 1 (19.5dBm)
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MCS 4: 36Mbps (802.11g)
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default target_power 2 (18.5dBm)
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MCS 5: 48Mbps (802.11g)
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default target_power 3 (17dBm)
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MCS 6: 54Mbps (802.11g)
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default target_power 4 (16dBm)
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MCS 7: 65Mbps (802.11n) - unclear if ever used?
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default target_power 5 (14dBm)
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*/
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uint8_t target_power_index_mcs[8]; /* 0x28 - 0x2f */
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/* One of CRYSTAL_FREQ_40M / CRYSTAL_FREQ_26M / CRYSTAL_FREQ_24M
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The crystal configured here is the input to the PLL setting
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calculations which are used to derive the CPU & APB peripheral
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clock frequency, and probably the WiFi PLLs (unconfirmed.)
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*/
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uint8_t crystal_freq; /* 0x30 */
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uint8_t _unused31; /* 0x31: Possibly high byte of crystal freq? */
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/* One of SDIO_CONFIG_AUTO, SDIO_CONFIG_SDIOV1_1, SDIO_CONFIG_SDIOV2_0 */
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uint8_t sdio_config; /* 0x32 */
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/* BT coexistence pin configuration.
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One of BT_COEXIST_CONFIG_NONE, BT_COEXIST_CONFIG_A,
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BT_COEXIST_CONFIG_PRESENT, BT_COEXIST_CONFIG_B
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*/
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uint8_t bt_coexist_config; /* 0x33 */
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/* BT coexistence pin protocol.
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If no coexistence:
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Either BT_COEXIST_PROTOCOL_WIFI_ONLY, or
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BT_COEXIST_PROTOCOL_BT_ONLY.
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If coexistence:
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Combine one of
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BT_COEXIST_PROTOCOL_FLAG_SEPARATE_ANT or
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BT_COEXIST_PROTOCOL_FLAG_SHARE_ANT
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with one of
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BT_COEXIST_PROTOCOL_FLAG_BT_ACTIVE_ONLY or
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BT_COEXIST_PROTOCOL_FLAG_BT_ACTIVE_BT_PRIORITY
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*/
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uint8_t bt_coexist_protocol; /* 0x34 */
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/* Dual antenna configuration
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One of DUAL_ANT_CONFIG_NONE, DUAL_ANT_CONFIG_DUAL,
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DUAL_ANT_CONFIG_TX_GPIO0_HIGH_GPIO3_LOW,
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DUAL_ANT_CONFIG_TX_GPIO0_LOW_GPIO3_HIGH
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*/
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uint8_t dual_ant_config; /* 0x35 */
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uint8_t _reserved34; /* 0x36 */
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/* For sharing crystal clock with other devices:
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one of CRYSTAL_SLEEP_OFF, CRYSTAL_SLEEP_ON,
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CRYSTAL_SLEEP_GPIO16, CRYSTAL_SLEEP_GPIO2
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*/
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uint8_t crystal_sleep; /* 0x37 */
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uint8_t _unused38[8];
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/* spur_freq_2 = spur_freq_2_primary / spur_freq_2_divisor */
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uint8_t spur_freq_2_primary; /* 0x40 */
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uint8_t spur_freq_2_divisor; /* 0x41 */
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/* Bitmask to enable spur_freq_2 for each channel?
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Appears to be a big endian short word?
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*/
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uint8_t spur_freq_2_en_h; /* 0x42 */
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uint8_t spur_freq_2_en_l; /* 0x43 */
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/* Not really clear what these do */
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uint8_t spur_freq_cfg_msb; /* 0x44 */
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uint8_t spur_freq_2_cfg_msb; /* 0x45 */
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uint16_t spur_freq_3_cfg; /* 0x46 - 0x47 */
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uint16_t spur_freq_4_cfg; /* 0x48 - 0x49 */
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uint8_t _reserved4a[4]; /* 0x4a - 0x4d */
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uint8_t _unused78[15]; /* 0x4e - 0x5c */
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|
|
|
||
|
|
/* Flag to enable low power mode */
|
||
|
|
uint8_t low_power_en; /* 0x5d */
|
||
|
|
|
||
|
|
/* Low Power attenuation of RF gain stages 0 & 1
|
||
|
|
|
||
|
|
Attenuates transmit power if/when low_power_en is set.
|
||
|
|
|
||
|
|
Use one of the constants LP_ATTEN_STAGE01_0DB,
|
||
|
|
LP_ATTEN_STAGE01_2_5DB, LP_ATTEN_STAGE01_6DB,
|
||
|
|
LP_ATTEN_STAGE01_8_5DB, LP_ATTEN_STAGE01_11_5DB,
|
||
|
|
LP_ATTEN_STAGE01_14DB, LP_ATTEN_STAGE01_17_5DB,
|
||
|
|
LP_ATTEN_STAGE01_23DB.
|
||
|
|
*/
|
||
|
|
uint8_t lp_atten_stage01; /* 0x5e */
|
||
|
|
|
||
|
|
/* Low Power(?) attenuation of baseband gain
|
||
|
|
|
||
|
|
Units are minus 1/4 dB, ie value 4 == -1dB.
|
||
|
|
|
||
|
|
Maximum value is 24 (0x18) == -6dB
|
||
|
|
*/
|
||
|
|
uint8_t lp_atten_bb; /* 0x5f */
|
||
|
|
|
||
|
|
/* I believe this means, when pwr_ind_11b_en == 0 then the 802.11g
|
||
|
|
MCS 0 level from target_power_index_mcs are used to
|
||
|
|
determine 802.11b transmit power level.
|
||
|
|
|
||
|
|
However, when pwr_ind_11b_en == 1 then the index values in
|
||
|
|
pwr_ind_11b_0 & pwr_ind_11b_1 are used for 802.11b instead.
|
||
|
|
|
||
|
|
This is all unconfirmed, if you can confirm then please update
|
||
|
|
this comment.
|
||
|
|
*/
|
||
|
|
uint8_t pwr_ind_11b_en; /* 0x60 */
|
||
|
|
|
||
|
|
/* 802.11b low data rate power index (0~5).
|
||
|
|
Sets the power level index for operation at 1 & 2Mbps
|
||
|
|
*/
|
||
|
|
uint8_t pwr_ind_11b_0; /* 0x61 */
|
||
|
|
|
||
|
|
/* 802.11b high data rate power index (0~5)
|
||
|
|
Sets the power level index for operation at 5.5 & 11Mbps
|
||
|
|
*/
|
||
|
|
uint8_t pwr_ind_11b_1; /* 0x62 */
|
||
|
|
|
||
|
|
uint8_t _unused63[8]; /* 0x63 - 0x6a */
|
||
|
|
|
||
|
|
/* Set the voltage of PA_VDD, which appears to be an internal analog
|
||
|
|
reference voltage(?)
|
||
|
|
|
||
|
|
This field is called vdd33_const in the Arduino phy fields,
|
||
|
|
and relates to usage of the TOUT pin (ADC pin).
|
||
|
|
|
||
|
|
Set to PA_VDD_MEASURE_VCC (0xFF) and leave TOUT (ADC) pin
|
||
|
|
floating in order to use the ADC to measure the 3.3V input
|
||
|
|
voltage.
|
||
|
|
|
||
|
|
Set to value in the range 18-36 (1.8V to 3.6V) to set a
|
||
|
|
reference voltage(?) when using TOUT pin as an ADC input. I
|
||
|
|
think this is the reference voltage used to scale the 0-1V
|
||
|
|
which is allowed on the pin, in order to get an accurate
|
||
|
|
reading. So it should be set to a value that matches system
|
||
|
|
VCC... I think!
|
||
|
|
*/
|
||
|
|
uint8_t pa_vdd; /* 0x6b */
|
||
|
|
|
||
|
|
/* Disable RF calibration cycle for this many times */
|
||
|
|
uint8_t disable_rfcal_count; /* 0x6c */
|
||
|
|
|
||
|
|
uint8_t _unused6d[3];
|
||
|
|
|
||
|
|
/* Flags for frequency correction
|
||
|
|
|
||
|
|
A bitmask combination of any of: FREQ_CORRECT_DISABLE,
|
||
|
|
FREQ_CORRECT_ENABLE, FREQ_CORRECT_BB_160M, FREQ_CORRECT_FORCE
|
||
|
|
*/
|
||
|
|
uint8_t freq_correct_mode; /* 0x70 */
|
||
|
|
|
||
|
|
/* Force frequency offset adjustment (instead of auto measuring)
|
||
|
|
units are 1 = 8kHz, full range +/- 1016kHz.
|
||
|
|
|
||
|
|
Only used if FREQ_CORRECT_ENABLE and FREQ_CORRECT_FORCE are
|
||
|
|
set in freq_correct_mode.
|
||
|
|
|
||
|
|
Unclear whether setting FREQ_CORRECT_BB_160M (which allows only positive offsets) changes the usable range.
|
||
|
|
*/
|
||
|
|
int8_t force_freq_offset; /* 0x71 */
|
||
|
|
|
||
|
|
/* Use stored data in flash for RF calibration.
|
||
|
|
|
||
|
|
This field was previously called rf_cal_use_flash.
|
||
|
|
|
||
|
|
Acceptable values one of RF_CAL_MODE_SAVED, RF_CAL_MODE_TXPOWER_ONLY, RF_CAL_MODE_SAVED_2, RF_CAL_MODE_FULL.
|
||
|
|
*/
|
||
|
|
uint8_t rf_cal_mode; /* 0x72 */
|
||
|
|
|
||
|
|
uint8_t _unused73[13];
|
||
|
|
} sdk_phy_info_t;
|
||
|
|
|
||
|
|
/* Some sanity check static assertions. These can probably be
|
||
|
|
removed after this structure has been better tested.
|
||
|
|
*/
|
||
|
|
_Static_assert(sizeof(sdk_phy_info_t) == 128, "sdk_phy_info_t is wrong size!");
|
||
|
|
_Static_assert(offsetof(sdk_phy_info_t, version) == 5, "version at wrong offset");
|
||
|
|
_Static_assert(offsetof(sdk_phy_info_t, target_power) == 34, "target_power_qdb at wrong offset");
|
||
|
|
_Static_assert(offsetof(sdk_phy_info_t, bt_coexist_protocol) == 52, "bt_coexist_protocol at wrong offset");
|
||
|
|
_Static_assert(offsetof(sdk_phy_info_t, spur_freq_2_primary) == 64, "spur_freq_2_primary at wrong offset");
|
||
|
|
_Static_assert(offsetof(sdk_phy_info_t, lp_atten_stage01) == 94, "lp_atten_stage01 at wrong offset");
|
||
|
|
_Static_assert(offsetof(sdk_phy_info_t, pa_vdd) == 107, "pa_vdd aka vdd33_const at wrong offset");
|
||
|
|
_Static_assert(offsetof(sdk_phy_info_t, rf_cal_mode) == 114, "rf_cal_use_flash at wrong offset!");
|
||
|
|
|
||
|
|
/* Read the default PHY info into the supplied structure.
|
||
|
|
|
||
|
|
This function is weak-aliased to get_sdk_default_phy_info() so you
|
||
|
|
can replace it with your own if you want to vary the default values
|
||
|
|
- suggested way to do this is to call get_sdk_default_phy_info()
|
||
|
|
and then only update the fields you care about.
|
||
|
|
|
||
|
|
The default PHY info is used at startup whenever the version field
|
||
|
|
in the default sdk_phy_info_t does not match the version field
|
||
|
|
stored in flash. So you can increment the version field to force a
|
||
|
|
reset to defaults, regardless of what values are in flash.
|
||
|
|
*/
|
||
|
|
void get_default_phy_info(sdk_phy_info_t *info);
|
||
|
|
|
||
|
|
/* Read the "SDK default" PHY info as used by the Espressif SDK */
|
||
|
|
void get_sdk_default_phy_info(sdk_phy_info_t *info);
|
||
|
|
|
||
|
|
/* Read the PHY info currently stored in the SPI flash SDK configuration sector.
|
||
|
|
|
||
|
|
This PHY info is updated by the SDK following RF calibration, etc.
|
||
|
|
|
||
|
|
Note that the saved data may be corrupt - read the 'version' field to verify.
|
||
|
|
*/
|
||
|
|
void read_saved_phy_info(sdk_phy_info_t *info);
|
||
|
|
|
||
|
|
/* Update the saved PHY info in the SPI flash. A reset is necessary to use these values.
|
||
|
|
|
||
|
|
Note that the SDK may clobber these values, so it's recommended you reset ASAP after updating them.
|
||
|
|
*/
|
||
|
|
void write_saved_phy_info(const sdk_phy_info_t *info);
|
||
|
|
|
||
|
|
/* Dump known fields in the phy info structure to stdout,
|
||
|
|
if 'raw' flag is set then the raw hex values are also dumped.
|
||
|
|
*/
|
||
|
|
void dump_phy_info(const sdk_phy_info_t *info, bool raw);
|
||
|
|
|
||
|
|
#endif
|