279 lines
12 KiB
C
279 lines
12 KiB
C
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/*******************************************************************************
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Copyright (c) 2006-2008 by Tensilica Inc. ALL RIGHTS RESERVED.
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These coded instructions, statements, and computer programs are the
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copyrighted works and confidential proprietary information of Tensilica Inc.
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They may not be modified, copied, reproduced, distributed, or disclosed to
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third parties in any manner, medium, or form, in whole or in part, without
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the prior written consent of Tensilica Inc.
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--------------------------------------------------------------------------------
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XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
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This header contains definitions and macros for use primarily by Xtensa
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RTOS assembly coded source files. It includes and uses the Xtensa hardware
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abstraction layer (HAL) to deal with config specifics. It may also be
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included in C source files.
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!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
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NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
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*******************************************************************************/
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#ifndef XTENSA_CONTEXT_H
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#define XTENSA_CONTEXT_H
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#ifdef __ASSEMBLER__
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#include <xtensa/coreasm.h>
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#endif
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#include <xtensa/config/tie.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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/*
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Align a value up to nearest n-byte boundary, where n is a power of 2.
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*/
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#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
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/*******************************************************************************
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INTERRUPT STACK FRAME FOR A THREAD OR NESTED INTERRUPT
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A stack frame of this structure is allocated for any interrupt or exception.
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It goes on the current stack. If the RTOS has a system stack for handling
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interrupts, every thread stack must allow space for just one interrupt stack
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frame, then nested interrupt stack frames go on the system stack.
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The frame includes basic registers (explicit) and "extra" registers introduced
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by user TIE or the use of the MAC16 option in the user's Xtensa config.
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The frame size is minimized by omitting regs not applicable to user's config.
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For Windowed ABI, this stack frame includes the interruptee's base save area,
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another base save area to manage gcc nested functions, and a little temporary
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space to help manage the spilling of the register windows.
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*******************************************************************************/
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#define XT_STK_EXIT 0x00 /* (offset 0) exit point for dispatch */
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#define XT_STK_PC 0x04 /* return address */
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#define XT_STK_PS 0x08 /* at level 1 PS.EXCM is set here */
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#define XT_STK_A0 0x0C
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#define XT_STK_A1 0x10 /* stack ptr before interrupt */
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#define XT_STK_A2 0x14
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#define XT_STK_A3 0x18
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#define XT_STK_A4 0x1C
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#define XT_STK_A5 0x20
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#define XT_STK_A6 0x24
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#define XT_STK_A7 0x28
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#define XT_STK_A8 0x2C
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#define XT_STK_A9 0x30
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#define XT_STK_A10 0x34
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#define XT_STK_A11 0x38
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#define XT_STK_A12 0x3C /* Call0 callee-save */
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#define XT_STK_A13 0x40 /* Call0 callee-save */
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#define XT_STK_A14 0x44 /* Call0 callee-save */
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#define XT_STK_A15 0x48 /* Call0 callee-save */
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#define XT_STK_SAR 0x4C
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#if XCHAL_HAVE_LOOPS
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#define XT_STK_LBEG 0x50
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#define XT_STK_LEND 0x54
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#define XT_STK_LCOUNT 0x58
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#define XT_STK_NEXT1 0x5C /* next unused offset */
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#else
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#define XT_STK_NEXT1 0x50 /* next unused offset */
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#endif
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/* there may be some unused space here */
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#if XCHAL_EXTRA_SA_SIZE != 0
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#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
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#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
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#else
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#define XT_STK_NEXT2 XT_STK_NEXT1
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#endif
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/* next unused offset */
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/* there may be some unused space here */
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#ifdef __XTENSA_CALL0_ABI__
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/* Call0 - no more stack frame needed */
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#define XT_STK_FRMSZ ALIGNUP(0x10, XT_STK_NEXT2)
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#else
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/*
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Windowed -
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Need some temp space for saving stuff during window spill.
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Also add 16 bytes to skip over interruptee's base save area
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and another 16 bytes in case of gcc nested functions: these
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must be at physical top (logical base) of frame.
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*/
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#define XT_STK_N_TMP 3 /* # of 4-byte temp. slots */
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#define XT_STK_TMP XT_STK_NEXT2
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#define XT_STK_NEXT3 XT_STK_TMP + (4 * XT_STK_N_TMP)
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#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT3) + 0x20)
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#endif
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/*******************************************************************************
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SOLICTED STACK FRAME FOR A THREAD
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A stack frame of this structure is allocated whenever a thread enters the
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RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
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It goes on the current thread's stack.
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The solicted frame only includes registers that are required to be preserved
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by the callee according to the compiler's ABI conventions, some space to save
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the return address for returning to the caller, and the caller's PS register.
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For Windowed ABI, this stack frame includes the caller's base save area.
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Note on XT_SOL_EXIT field:
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It is necessary to distinguish a solicited from an interrupt stack frame.
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This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
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always at the same offset (0). It can be written with a code (usually 0)
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to distinguish a solicted frame from an interrupt frame. An RTOS port may
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opt to ignore this field if it has another way of distinguishing frames.
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*******************************************************************************/
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#ifdef __XTENSA_CALL0_ABI__
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/* Call0 ABI: room to save callee-save regs and return address. */
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#define XT_SOL_EXIT XT_STK_EXIT /* code indicates solicited frame */
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#define XT_SOL_PC 0x04 /* return address */
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#define XT_SOL_PS 0x08
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#define XT_SOL_NEXT 0x0c /* next unused offset */
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/* there may be some unused space here */
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#define XT_SOL_A12 ALIGNUP(0x10, XT_SOL_NEXT)
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#define XT_SOL_A13 XT_SOL_A12 + 4
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#define XT_SOL_A14 XT_SOL_A13 + 4
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#define XT_SOL_A15 XT_SOL_A14 + 4
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#define XT_SOL_FRMSZ ALIGNUP(0x10, XT_SOL_A15)
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#else
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/* Windowed ABI: room to spill base-save area and save return address. */
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#define XT_SOL_EXIT XT_STK_EXIT /* code indicates solicited frame */
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#define XT_SOL_PC 0x04 /* return address (b30-31=callinc) */
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#define XT_SOL_PS 0x08
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#define XT_SOL_NEXT 0x0c /* next unused offset */
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/* there may be some unused space here */
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#define XT_SOL_A0 ALIGNUP(0x10, XT_SOL_NEXT)
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#define XT_SOL_A1 XT_SOL_A0 + 4
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#define XT_SOL_A2 XT_SOL_A1 + 4
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#define XT_SOL_A3 XT_SOL_A2 + 4
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#define XT_SOL_FRMSZ ALIGNUP(0x10, XT_SOL_A3)
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#endif
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/*******************************************************************************
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CO-PROCESSOR STATE SAVE AREA FOR A THREAD
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The RTOS must provide an area per thread to save the state of co-processors
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when that thread does not have control. Co-processors are context-switched
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lazily (on demand) only when a new thread uses a co-processor instruction,
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otherwise a thread retains ownership of the co-processor even when it loses
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control of the processor. An Xtensa co-processor exception is triggered when
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any co-processor instruction is executed by a thread that is not the owner,
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and the context switch of that co-processor is then peformed by the handler.
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Ownership represents which thread's state is currently in the co-processor.
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Co-processors may not be used by interrupt or exception handlers. If an
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co-processor instruction is executed by an interrupt or exception handler,
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the co-processor exception handler will trigger a kernel panic and freeze.
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This restriction is introduced to reduce the overhead of saving and restoring
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co-processor state (which can be quite large) and in particular remove that
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overhead from interrupt handlers.
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The co-processor state save area may be in any convenient per-thread location
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such as in the thread control block or above the thread stack area. It need
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not be in the interrupt stack frame since interrupts don't use co-processors.
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Along with the save area for each co-processor, two bitmasks with flags per
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co-processor (laid out as in the CPENABLE reg) help manage context-switching
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co-processors as efficiently as possible:
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XT_CPENABLE
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The contents of a non-running thread's CPENABLE register.
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It represents the co-processors owned (and whose state is still needed)
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by the thread. When a thread is preempted, its CPENABLE is saved here.
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When a thread solicits a context-swtich, its CPENABLE is cleared - the
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compiler has saved the (caller-saved) co-proc state if it needs to.
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When a non-running thread loses ownership of a CP, its bit is cleared.
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When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
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Avoids co-processor exceptions when no change of ownership is needed.
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XT_CPSTORED
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A bitmask with the same layout as CPENABLE, a bit per co-processor.
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Indicates whether the state of each co-processor is saved in the state
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save area. When a thread enters the kernel, only the state of co-procs
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still enabled in CPENABLE is saved. When the co-processor exception
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handler assigns ownership of a co-processor to a thread, it restores
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the saved state only if this bit is set, and clears this bit.
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*******************************************************************************/
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#if XCHAL_CP_NUM > 0
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#define XT_CPENABLE 0
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#define XT_CPSTORED (XT_CPENABLE + 1)
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#define XT_CP0_SA ALIGNUP(XCHAL_CP0_SA_ALIGN, XT_CPSTORED + 1)
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#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
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#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
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#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
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#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
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#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
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#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
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#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
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#define XT_CP_SIZE ALIGNUP(4 , XT_CP7_SA + XCHAL_CP7_SA_SIZE)
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#else
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#define XT_CP_SIZE 0
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#endif
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/*******************************************************************************
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MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
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Convenient where the frame size requirements are the same for both ABIs.
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ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
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ENTRY0, RET0 are for frameless functions (no locals, no calls).
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where size = size of stack frame in bytes (must be >0 and aligned to 16).
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For framed functions the frame is created and the return address saved at
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base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
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For frameless functions, there is no frame and return address remains in a0.
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Note: Because CPP macros expand to a single line, macros requiring multi-line
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expansions are implemented as assembler macros.
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*******************************************************************************/
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#ifdef __ASSEMBLER__
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#ifdef __XTENSA_CALL0_ABI__
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/* Call0 */
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#define ENTRY(sz) entry1 sz
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.macro entry1 size=0x10
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addi sp, sp, -\size
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s32i a0, sp, 0
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.endm
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#define ENTRY0
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#define RET(sz) ret1 sz
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.macro ret1 size=0x10
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l32i a0, sp, 0
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addi sp, sp, \size
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ret
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.endm
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#define RET0 ret
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#else
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/* Windowed */
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#define ENTRY(sz) entry sp, sz
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#define ENTRY0 entry sp, 0x10
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#define RET(sz) retw
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#define RET0 retw
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#endif
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#endif
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#endif /* XTENSA_CONTEXT_H */
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