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first commit
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jeffrey
parent
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1181 changed files with 784669 additions and 0 deletions
380
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_adc.c
Normal file
380
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_adc.c
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@ -0,0 +1,380 @@
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#include "platform_autoconf.h"
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#include "diag.h"
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#include "rtl8195a_adc.h"
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#include "hal_adc.h"
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//---------------------------------------------------------------------------------------------------
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//Function Name:
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// HalI2CInit8195a
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//
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// Description:
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// To initialize I2C module by using the given data.
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//
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// Arguments:
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// [in] VOID *Data -
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// The I2C parameter data struct.
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//
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// Return:
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// The status of the DeInit process.
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// _EXIT_SUCCESS if the initialization succeeded.
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// _EXIT_FAILURE if the initialization failed.
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//
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// Note:
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// None
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//
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// See Also:
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// NA
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//
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// Author:
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// By Jason Deng, 2014-04-02.
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//
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//---------------------------------------------------------------------------------------------------
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RTK_STATUS
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HalADCInit8195a(
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IN VOID *Data
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)
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{
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PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
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u32 AdcTempDat;
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u8 AdcTempIdx = pHalAdcInitData->ADCIdx;
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/* Enable ADC power cut */
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/*
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AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
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AdcTempDat |= BIT_ADC_PWR_AUTO;
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HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
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*/
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/* ADC Control register set-up*/
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AdcTempDat = 0;
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AdcTempDat |= (BIT_CTRL_ADC_COMP_ONLY(pHalAdcInitData->ADCCompOnly) |
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BIT_CTRL_ADC_ONESHOT(pHalAdcInitData->ADCOneShotEn) |
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BIT_CTRL_ADC_OVERWRITE(pHalAdcInitData->ADCOverWREn) |
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BIT_CTRL_ADC_ENDIAN(pHalAdcInitData->ADCEndian) |
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BIT_CTRL_ADC_BURST_SIZE(pHalAdcInitData->ADCBurstSz) |
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BIT_CTRL_ADC_THRESHOLD(pHalAdcInitData->ADCOneShotTD) |
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BIT_CTRL_ADC_DBG_SEL(pHalAdcInitData->ADCDbgSel));
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HAL_ADC_WRITE32(REG_ADC_CONTROL,AdcTempDat);
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DBG_8195A_ADC_LVL(HAL_ADC_LVL,"REG_ADC_CONTROL:%x\n", HAL_ADC_READ32(REG_ADC_CONTROL));
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/* ADC compare value and compare method setting*/
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switch (AdcTempIdx) {
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case ADC0_SEL:
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AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
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AdcTempDat &= ~(BIT_ADC_COMP_TH_0(0xFFFF));
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AdcTempDat |= BIT_CTRL_ADC_COMP_TH_0(pHalAdcInitData->ADCCompTD);
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HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
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break;
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case ADC1_SEL:
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AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
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AdcTempDat &= ~(BIT_ADC_COMP_TH_1(0xFFFF));
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AdcTempDat |= BIT_CTRL_ADC_COMP_TH_1(pHalAdcInitData->ADCCompTD);
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HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
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break;
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case ADC2_SEL:
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AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
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AdcTempDat &= ~(BIT_ADC_COMP_TH_2(0xFFFF));
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AdcTempDat |= BIT_CTRL_ADC_COMP_TH_2(pHalAdcInitData->ADCCompTD);
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HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
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break;
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case ADC3_SEL:
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AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
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AdcTempDat &= ~(BIT_ADC_COMP_TH_3(0xFFFF));
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AdcTempDat |= BIT_CTRL_ADC_COMP_TH_3(pHalAdcInitData->ADCCompTD);
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HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
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break;
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default:
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return _EXIT_FAILURE;
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}
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/* ADC compare mode setting */
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AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_SET);
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AdcTempDat &= (~(0x01 << pHalAdcInitData->ADCIdx));
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AdcTempDat |= (BIT_CTRL_ADC_COMP_0_EN(pHalAdcInitData->ADCCompCtrl) <<
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pHalAdcInitData->ADCIdx);
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HAL_ADC_WRITE32(REG_ADC_COMP_SET, AdcTempDat);
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/* ADC audio mode set-up */
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
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AdcTempDat &= ~(BIT_ADC_AUDIO_EN);
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AdcTempDat |= BIT_CTRL_ADC_AUDIO_EN(pHalAdcInitData->ADCAudioEn);
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
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/* ADC enable manually setting */
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
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AdcTempDat &= ~(BIT_ADC_EN_MANUAL);
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AdcTempDat |= BIT_CTRL_ADC_EN_MANUAL(pHalAdcInitData->ADCEnManul);
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
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/* ADC analog parameter 0 */
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
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DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
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AdcTempDat |= (BIT0);
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if (pHalAdcInitData->ADCInInput == 1){
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AdcTempDat &= (~BIT14);
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}
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else {
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AdcTempDat |= (BIT14);
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}
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AdcTempDat &= (~(BIT3|BIT2));
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/* Adjust VCM for C-Cut*/
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#ifdef CONFIG_CHIP_C_CUT
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AdcTempDat |= (BIT22);
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#endif
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
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DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
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/* ADC analog parameter 1 */
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
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AdcTempDat &= (~BIT1);
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AdcTempDat |= (BIT2|BIT0);
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, AdcTempDat);
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
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DBG_ADC_INFO("AD1:%x\n", AdcTempDat);
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/* ADC analog parameter 2 */
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
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DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
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AdcTempDat = 0x67884400;
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD2, AdcTempDat);
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
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DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
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/* ADC analog parameter 3 */
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
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DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
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AdcTempDat = 0x77780039;
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD3, AdcTempDat);
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
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DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
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/* ADC analog parameter 4 */
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
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DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
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AdcTempDat = 0x0004d501;
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD4, AdcTempDat);
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
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DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
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/* ADC analog parameter 5 */
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
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DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
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AdcTempDat = 0x1E010800;
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD5, AdcTempDat);
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AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
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DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
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return _EXIT_SUCCESS;
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}
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//---------------------------------------------------------------------------------------------------
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//Function Name:
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// HalI2CInit8195a
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//
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// Description:
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// To initialize I2C module by using the given data.
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//
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// Arguments:
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// [in] VOID *Data -
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// The I2C parameter data struct.
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//
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// Return:
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// The status of the DeInit process.
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// _EXIT_SUCCESS if the initialization succeeded.
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// _EXIT_FAILURE if the initialization failed.
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//
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// Note:
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// None
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//
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// See Also:
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// NA
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//
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// Author:
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// By Jason Deng, 2014-04-02.
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//
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//---------------------------------------------------------------------------------------------------
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RTK_STATUS
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HalADCDeInit8195a(
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IN VOID *Data
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)
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{
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u32 AdcTempDat;
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AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
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AdcTempDat &= ~(BIT_ADC_PWR_AUTO);
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HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
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return _EXIT_SUCCESS;
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}
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//---------------------------------------------------------------------------------------------------
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//Function Name:
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// HalI2CIntrCtrl8195a
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//
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// Description:
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// Modify the I2C interrupt mask according to the given value
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//
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// Arguments:
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// [in] VOID *Data -
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// The I2C parameter data struct.
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//
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// Return:
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// The status of the enable process.
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// _EXIT_SUCCESS if the de-initialization succeeded.
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// _EXIT_FAILURE if the de-initialization failed.
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//
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// Note:
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// None
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//
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// See Also:
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// NA
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//
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// Author:
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// By Jason Deng, 2014-02-18.
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//
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//---------------------------------------------------------------------------------------------------
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RTK_STATUS
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HalADCEnableRtl8195a(
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IN VOID *Data
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){
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PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
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u32 AdcTempDat;
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AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
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AdcTempDat &= (~BIT_ADC_PWR_AUTO);
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AdcTempDat |= BIT_CTRL_ADC_PWR_AUTO(pHalAdcInitData->ADCEn);
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HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
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return _EXIT_SUCCESS;
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}
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//---------------------------------------------------------------------------------------------------
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//Function Name:
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// HalI2CIntrCtrl8195a
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//
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// Description:
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// Modify the I2C interrupt mask according to the given value
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//
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// Arguments:
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// [in] VOID *Data -
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// The I2C parameter data struct.
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//
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// Return:
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// The status of the enable process.
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// _EXIT_SUCCESS if the de-initialization succeeded.
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// _EXIT_FAILURE if the de-initialization failed.
|
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//
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// Note:
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// None
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//
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// See Also:
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// NA
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//
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// Author:
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// By Jason Deng, 2014-02-18.
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//
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//---------------------------------------------------------------------------------------------------
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RTK_STATUS
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HalADCIntrCtrl8195a(
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IN VOID *Data
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){
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PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
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HAL_ADC_WRITE32(REG_ADC_INTR_EN, pHalAdcInitData->ADCIntrMSK);
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return _EXIT_SUCCESS;
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}
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//---------------------------------------------------------------------------------------------------
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//Function Name:
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// HalI2CReceiveRtl8195a
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//
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// Description:
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// Directly read one data byte a I2C data fifo.
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//
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// Arguments:
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// [in] VOID *Data -
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// The I2C parameter data struct.
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//
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// Return:
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// The first data fifo content.
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//
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// Note:
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// None
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//
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// See Also:
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// NA
|
||||
//
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// Author:
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// By Jason Deng, 2014-02-18.
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//
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//---------------------------------------------------------------------------------------------------
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u32
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HalADCReceiveRtl8195a(
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IN VOID *Data
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){
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u32 AdcTempDat;
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AdcTempDat = HAL_ADC_READ32(REG_ADC_FIFO_READ);
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return (AdcTempDat);
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}
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//---------------------------------------------------------------------------------------------------
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//Function Name:
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// HalI2CReadRegRtl8195a
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//
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// Description:
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// Directly read a I2C register according to the register offset.
|
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//
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// Arguments:
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// [in] VOID *Data -
|
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// The I2C parameter data struct.
|
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// [in] I2CReg -
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// The I2C register offset.
|
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//
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// Return:
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// The register content in u32 format.
|
||||
//
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// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
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//
|
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//---------------------------------------------------------------------------------------------------
|
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u32
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HalADCReadRegRtl8195a(
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IN VOID *Data,
|
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IN u8 I2CReg
|
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){
|
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u32 AdcTempDat;
|
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|
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AdcTempDat = HAL_ADC_READ32(I2CReg);
|
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return (AdcTempDat);
|
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}
|
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|
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269
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_dac.c
Normal file
269
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_dac.c
Normal file
|
|
@ -0,0 +1,269 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
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#include "rtl8195a_dac.h"
|
||||
#include "hal_dac.h"
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalDACInit8195a
|
||||
//
|
||||
// Description:
|
||||
// To initialize DAC module by using the given data.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The DAC parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the DeInit process.
|
||||
// _EXIT_SUCCESS if the initialization succeeded.
|
||||
// _EXIT_FAILURE if the initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-04-15.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
RTK_STATUS
|
||||
HalDACInit8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
|
||||
u32 DacTempDat;
|
||||
u8 DacTempIdx = pHalDacInitData->DACIdx;
|
||||
|
||||
/* Enable DAC power cut */
|
||||
DacTempDat = HAL_DAC_READ32(0, REG_DAC_PWR_CTRL);
|
||||
DacTempDat |= BIT_DAC_PWR_AUTO;
|
||||
|
||||
HAL_DAC_WRITE32(0, REG_DAC_PWR_CTRL, DacTempDat);
|
||||
|
||||
/* Disable DAC module first */
|
||||
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, 0);
|
||||
|
||||
/* Setup DAC module */
|
||||
DacTempDat = 0;
|
||||
DacTempDat |= (BIT_CTRL_DAC_SPEED(pHalDacInitData->DACDataRate) |
|
||||
BIT_CTRL_DAC_ENDIAN(pHalDacInitData->DACEndian) |
|
||||
BIT_CTRL_DAC_FILTER_SETTLE(pHalDacInitData->DACFilterSet) |
|
||||
BIT_CTRL_DAC_BURST_SIZE(pHalDacInitData->DACBurstSz) |
|
||||
BIT_CTRL_DAC_DBG_SEL(pHalDacInitData->DACDbgSel) |
|
||||
BIT_CTRL_DAC_DSC_DBG_SEL(pHalDacInitData->DACDscDbgSel) |
|
||||
BIT_CTRL_DAC_BYPASS_DSC(pHalDacInitData->DACBPDsc) |
|
||||
BIT_CTRL_DAC_DELTA_SIGMA(pHalDacInitData->DACDeltaSig));
|
||||
|
||||
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CInit8195a
|
||||
//
|
||||
// Description:
|
||||
// To initialize I2C module by using the given data.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the DeInit process.
|
||||
// _EXIT_SUCCESS if the initialization succeeded.
|
||||
// _EXIT_FAILURE if the initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-04-02.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
RTK_STATUS
|
||||
HalDACDeInit8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
|
||||
u32 DacTempDat;
|
||||
|
||||
DacTempDat = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL);
|
||||
DacTempDat &= (~BIT_DAC_FIFO_EN);
|
||||
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL ,DacTempDat);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CIntrCtrl8195a
|
||||
//
|
||||
// Description:
|
||||
// Modify the I2C interrupt mask according to the given value
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the enable process.
|
||||
// _EXIT_SUCCESS if the de-initialization succeeded.
|
||||
// _EXIT_FAILURE if the de-initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
RTK_STATUS
|
||||
HalDACEnableRtl8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
|
||||
u32 DacTempDat;
|
||||
u8 DacTempIdx = pHalDacInitData->DACIdx;
|
||||
|
||||
DacTempDat = HAL_DAC_READ32(DacTempIdx, REG_DAC_CTRL);
|
||||
DacTempDat &= (~BIT_DAC_FIFO_EN);
|
||||
|
||||
DacTempDat |= BIT_CTRL_DAC_FIFO_EN(pHalDacInitData->DACEn);
|
||||
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CIntrCtrl8195a
|
||||
//
|
||||
// Description:
|
||||
// Modify the I2C interrupt mask according to the given value
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the enable process.
|
||||
// _EXIT_SUCCESS if the de-initialization succeeded.
|
||||
// _EXIT_FAILURE if the de-initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
RTK_STATUS
|
||||
HalDACIntrCtrl8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
|
||||
|
||||
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL, pHalDacInitData->DACIntrMSK);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CReceiveRtl8195a
|
||||
//
|
||||
// Description:
|
||||
// Directly read one data byte a I2C data fifo.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The first data fifo content.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
u8
|
||||
HalDACSendRtl8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalDACReadRegRtl8195a
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The DAC parameter data struct.
|
||||
// [in] I2CReg -
|
||||
// The DAC register offset.
|
||||
//
|
||||
// Return:
|
||||
// The DAC register content in u32 format.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-04-15.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
u32
|
||||
HalDACReadRegRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 I2CReg
|
||||
){
|
||||
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
|
||||
|
||||
//DBG_8195A_DAC("dac read reg idx:%x\n",pHalDacInitData->DACIdx);
|
||||
//DBG_8195A_DAC("dac read reg offset:%x\n",I2CReg);
|
||||
|
||||
return (u32)HAL_DAC_READ32(pHalDacInitData->DACIdx, I2CReg);
|
||||
}
|
||||
|
||||
243
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c
Normal file
243
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c
Normal file
|
|
@ -0,0 +1,243 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "rtl8195a_gdma.h"
|
||||
#include "hal_gdma.h"
|
||||
|
||||
#ifndef CONFIG_CHIP_D_CUT
|
||||
BOOL
|
||||
HalGdmaChBlockSetingRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
PGDMA_CH_LLI_ELE pLliEle;
|
||||
struct GDMA_CH_LLI *pGdmaChLli;
|
||||
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
|
||||
u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
|
||||
u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
|
||||
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
|
||||
u8 ChNum = pHalGdmaAdapter->ChNum;
|
||||
u32 ChEn = pHalGdmaAdapter->ChEn;
|
||||
u8 GdmaChIsrBitmap = (ChEn & 0xFF);
|
||||
u8 PendingIsrIndex;
|
||||
|
||||
|
||||
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
|
||||
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
|
||||
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
|
||||
|
||||
|
||||
//4 1) Check chanel is avaliable
|
||||
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
|
||||
//4 Disable Channel
|
||||
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
|
||||
|
||||
HalGdmaChDisRtl8195a(Data);
|
||||
|
||||
}
|
||||
|
||||
//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
|
||||
for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
|
||||
|
||||
u32 PendRaw, PendStstus;
|
||||
PendRaw = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
|
||||
PendStstus = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
|
||||
|
||||
if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
|
||||
//4 Clear Pending Isr
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
|
||||
(PendStstus & (GdmaChIsrBitmap))
|
||||
);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
//4 Fill in SARx register
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
|
||||
(pHalGdmaAdapter->ChSar)
|
||||
);
|
||||
|
||||
|
||||
//4 Fill in DARx register
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
|
||||
(pHalGdmaAdapter->ChDar)
|
||||
);
|
||||
|
||||
|
||||
|
||||
//4 3) Process CTLx
|
||||
CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
|
||||
|
||||
//4 Clear Config low register bits
|
||||
CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
|
||||
BIT_INVC_CTLX_LO_DST_TR_WIDTH &
|
||||
BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
|
||||
BIT_INVC_CTLX_LO_DINC &
|
||||
BIT_INVC_CTLX_LO_SINC &
|
||||
BIT_INVC_CTLX_LO_DEST_MSIZE &
|
||||
BIT_INVC_CTLX_LO_SRC_MSIZE &
|
||||
BIT_INVC_CTLX_LO_TT_FC &
|
||||
BIT_INVC_CTLX_LO_LLP_DST_EN &
|
||||
BIT_INVC_CTLX_LO_LLP_SRC_EN);
|
||||
|
||||
CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
|
||||
|
||||
//4 Clear Config upper register bits
|
||||
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
|
||||
BIT_INVC_CTLX_UP_DONE);
|
||||
|
||||
|
||||
CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
|
||||
BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
|
||||
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
|
||||
BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
|
||||
BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
|
||||
BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
|
||||
BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
|
||||
BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
|
||||
BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
|
||||
BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
|
||||
CtlxLow;
|
||||
|
||||
CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
|
||||
BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
|
||||
CtlxUp;
|
||||
|
||||
//4 Fill in CTLx register
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
|
||||
CtlxLow
|
||||
);
|
||||
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
|
||||
CtlxUp
|
||||
);
|
||||
|
||||
//4 4) Program CFGx
|
||||
|
||||
CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
|
||||
|
||||
CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
|
||||
BIT_INVC_CFGX_LO_CH_SUSP &
|
||||
BIT_INVC_CFGX_LO_HS_SEL_DST &
|
||||
BIT_INVC_CFGX_LO_HS_SEL_SRC &
|
||||
BIT_INVC_CFGX_LO_LOCK_CH_L &
|
||||
BIT_INVC_CFGX_LO_LOCK_B_L &
|
||||
BIT_INVC_CFGX_LO_LOCK_CH &
|
||||
BIT_INVC_CFGX_LO_LOCK_B &
|
||||
BIT_INVC_CFGX_LO_RELOAD_SRC &
|
||||
BIT_INVC_CFGX_LO_RELOAD_DST);
|
||||
|
||||
CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
|
||||
|
||||
CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
|
||||
BIT_INVC_CFGX_UP_DS_UPD_EN &
|
||||
BIT_INVC_CFGX_UP_SS_UPD_EN &
|
||||
BIT_INVC_CFGX_UP_SRC_PER &
|
||||
BIT_INVC_CFGX_UP_DEST_PER);
|
||||
|
||||
CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
|
||||
BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
|
||||
BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
|
||||
BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
|
||||
BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
|
||||
BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
|
||||
BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
|
||||
BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
|
||||
BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
|
||||
BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
|
||||
CfgxLow;
|
||||
|
||||
CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
|
||||
BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
|
||||
BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
|
||||
BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
|
||||
BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
|
||||
CfgxUp;
|
||||
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
|
||||
CfgxLow
|
||||
);
|
||||
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
|
||||
CfgxUp
|
||||
);
|
||||
|
||||
|
||||
|
||||
//4 Check 4 Bytes Alignment
|
||||
if ((u32)(pLliEle) & 0x3) {
|
||||
DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n",
|
||||
pHalGdmaAdapter->pLli);
|
||||
return _FALSE;
|
||||
}
|
||||
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
|
||||
pLliEle
|
||||
);
|
||||
|
||||
//4 Update the first llp0
|
||||
pLliEle->CtlxLow = CtlxLow;
|
||||
pLliEle->CtlxUp = CtlxUp;
|
||||
pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
|
||||
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
|
||||
|
||||
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
|
||||
|
||||
while (MultiBlockCount > 1) {
|
||||
MultiBlockCount--;
|
||||
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
|
||||
pLliEle = pGdmaChLli->pLliEle;
|
||||
|
||||
if (NULL == pLliEle) {
|
||||
DBG_8195A("pLliEle Null Point!!!!!\n");
|
||||
return _FALSE;
|
||||
}
|
||||
|
||||
//4 Clear the last element llp enable bit
|
||||
if (1 == MultiBlockCount) {
|
||||
if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 0){
|
||||
CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
|
||||
BIT_INVC_CTLX_LO_LLP_SRC_EN);
|
||||
}
|
||||
}
|
||||
//4 Update block size for transfer
|
||||
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
|
||||
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
|
||||
|
||||
//4 Update tje Lli and Block size list point to next llp
|
||||
pGdmaChLli = pGdmaChLli->pNextLli;
|
||||
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
|
||||
|
||||
//4 Updatethe Llpx context
|
||||
pLliEle->CtlxLow = CtlxLow;
|
||||
pLliEle->CtlxUp = CtlxUp;
|
||||
pLliEle->Llpx = pGdmaChLli->pLliEle;
|
||||
|
||||
}
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "hal_gpio.h"
|
||||
#include "rtl8195a_gpio.h"
|
||||
#include "gpio_irq_api.h"
|
||||
|
||||
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
|
||||
|
||||
/**
|
||||
* @brief Clear the pending interrupt of a specified pin
|
||||
*
|
||||
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
HAL_Status
|
||||
HAL_GPIO_ClearISR_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
)
|
||||
{
|
||||
u8 port_num;
|
||||
u8 pin_num;
|
||||
HAL_GPIO_PIN_MODE pin_mode;
|
||||
|
||||
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
|
||||
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
|
||||
pin_mode = GPIO_Pin->pin_mode;
|
||||
|
||||
if ((pin_mode & HAL_GPIO_PIN_INT_MODE)==0 || (port_num != GPIO_PORT_A)) {
|
||||
DBG_GPIO_ERR("HAL_GPIO_ClearISR_8195a: This pin(%x:%x) is'nt an interrupt pin\n", GPIO_Pin->pin_name, GPIO_Pin->pin_mode);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
if (GPIO_Lock() != HAL_OK) {
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
// Clear pending interrupt before unmask it
|
||||
HAL_WRITE32(GPIO_REG_BASE, GPIO_PORTA_EOI, (1<<pin_num));
|
||||
|
||||
GPIO_UnLock();
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
394
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_i2s.c
Normal file
394
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_i2s.c
Normal file
|
|
@ -0,0 +1,394 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "rtl8195a_i2s.h"
|
||||
#include "hal_i2s.h"
|
||||
|
||||
extern void *
|
||||
_memset( void *s, int c, SIZE_T n );
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SInitRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
|
||||
u8 I2SIdx;
|
||||
u8 I2SEn;
|
||||
u8 I2SMaster;
|
||||
u8 I2SWordLen;
|
||||
u8 I2SChNum;
|
||||
u8 I2SPageNum;
|
||||
u16 I2SPageSize;
|
||||
u16 I2SRate;
|
||||
u32 I2STxIntrMSK;
|
||||
u32 I2SRxIntrMSK;
|
||||
u8 I2STRxAct;
|
||||
u8 *I2STxData;
|
||||
u8 *I2SRxData;
|
||||
|
||||
u32 Tmp;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
I2SEn = pHalI2SInitData->I2SEn;
|
||||
I2SMaster = pHalI2SInitData->I2SMaster;
|
||||
I2SWordLen = pHalI2SInitData->I2SWordLen;
|
||||
I2SChNum = pHalI2SInitData->I2SChNum;
|
||||
I2SPageNum = pHalI2SInitData->I2SPageNum;
|
||||
I2SPageSize = pHalI2SInitData->I2SPageSize;
|
||||
I2SRate = pHalI2SInitData->I2SRate;
|
||||
I2STRxAct = pHalI2SInitData->I2STRxAct;
|
||||
I2STxData = pHalI2SInitData->I2STxData;
|
||||
I2SRxData = pHalI2SInitData->I2SRxData;
|
||||
|
||||
|
||||
/* Disable the I2S first, and reset to default */
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
|
||||
BIT_CTRL_CTLX_I2S_SW_RSTN(1));
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
|
||||
BIT_CTRL_CTLX_I2S_SW_RSTN(0));
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
|
||||
BIT_CTRL_CTLX_I2S_SW_RSTN(1));
|
||||
|
||||
Tmp = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
|
||||
Tmp |= BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(1);
|
||||
|
||||
if (I2SRate&0x10)
|
||||
{
|
||||
Tmp |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
|
||||
}
|
||||
|
||||
Tmp |= (BIT_CTRL_CTLX_I2S_WL(I2SWordLen) | BIT_CTRL_CTLX_I2S_CH_NUM(I2SChNum) |
|
||||
BIT_CTRL_CTLX_I2S_SLAVE_MODE(I2SMaster) | BIT_CTRL_CTLX_I2S_TRX_ACT(I2STRxAct));
|
||||
/* set 44.1khz clock source, word length, channel number, master or slave, trx act */
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, Tmp);
|
||||
|
||||
Tmp = BIT_CTRL_SETTING_I2S_PAGE_SZ(I2SPageSize) | BIT_CTRL_SETTING_I2S_PAGE_NUM(I2SPageNum) |
|
||||
BIT_CTRL_SETTING_I2S_SAMPLE_RATE(I2SRate);
|
||||
/* set page size, page number, sample rate */
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, Tmp);
|
||||
|
||||
/* need tx rx buffer? need rx page own bit */
|
||||
if (I2STxData != NULL) {
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (u32)I2STxData);
|
||||
}
|
||||
|
||||
if (I2SRxData != NULL) {
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (u32)I2SRxData);
|
||||
}
|
||||
|
||||
pHalI2SInitData->I2STxIdx = 0;
|
||||
pHalI2SInitData->I2SRxIdx = 0;
|
||||
pHalI2SInitData->I2SHWTxIdx = 0;
|
||||
pHalI2SInitData->I2SHWRxIdx = 0;
|
||||
/* I2S Clear all interrupts first */
|
||||
HalI2SClrAllIntrRtl8195a(pHalI2SInitData);
|
||||
|
||||
/* I2S Disable all interrupts first */
|
||||
I2STxIntrMSK = pHalI2SInitData->I2STxIntrMSK;
|
||||
I2SRxIntrMSK = pHalI2SInitData->I2SRxIntrMSK;
|
||||
pHalI2SInitData->I2STxIntrMSK = 0;
|
||||
pHalI2SInitData->I2SRxIntrMSK = 0;
|
||||
HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
|
||||
pHalI2SInitData->I2STxIntrMSK = I2STxIntrMSK;
|
||||
pHalI2SInitData->I2SRxIntrMSK = I2SRxIntrMSK;
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetRateRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
|
||||
reg_value &= ~(BIT_MASK_CTLX_I2S_CLK_SRC << BIT_SHIFT_CTLX_I2S_CLK_SRC);
|
||||
if (pHalI2SInitData->I2SRate&0x10)
|
||||
{
|
||||
reg_value |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
|
||||
}
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
|
||||
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
|
||||
reg_value &= ~(BIT_MASK_SETTING_I2S_SAMPLE_RATE << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE);
|
||||
reg_value |= BIT_CTRL_SETTING_I2S_SAMPLE_RATE(pHalI2SInitData->I2SRate);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetWordLenRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
|
||||
reg_value &= ~(BIT_MASK_CTLX_I2S_WL << BIT_SHIFT_CTLX_I2S_WL);
|
||||
reg_value |= BIT_CTRL_CTLX_I2S_WL(pHalI2SInitData->I2SWordLen);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetChNumRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
|
||||
reg_value &= ~(BIT_MASK_CTLX_I2S_CH_NUM << BIT_SHIFT_CTLX_I2S_CH_NUM);
|
||||
reg_value |= BIT_CTRL_CTLX_I2S_CH_NUM(pHalI2SInitData->I2SChNum);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetPageNumRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
|
||||
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
|
||||
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetPageSizeRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
|
||||
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
|
||||
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetDirectionRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
|
||||
reg_value &= ~(BIT_MASK_CTLX_I2S_TRX_ACT << BIT_SHIFT_CTLX_I2S_TRX_ACT);
|
||||
reg_value |= BIT_CTRL_CTLX_I2S_TRX_ACT(pHalI2SInitData->I2STRxAct);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetDMABufRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
u32 page_num;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
|
||||
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
|
||||
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
|
||||
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
|
||||
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
|
||||
|
||||
page_num = pHalI2SInitData->I2SPageNum + 1;
|
||||
if (pHalI2SInitData->I2STxData) {
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2STxData);
|
||||
pHalI2SInitData->I2STxIntrMSK = (1<<page_num) - 1;
|
||||
} else {
|
||||
pHalI2SInitData->I2STxIntrMSK = 0;
|
||||
}
|
||||
|
||||
if (pHalI2SInitData->I2SRxData) {
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2SRxData);
|
||||
pHalI2SInitData->I2SRxIntrMSK = (1<<page_num) - 1;
|
||||
} else {
|
||||
pHalI2SInitData->I2SRxIntrMSK = 0;
|
||||
|
||||
}
|
||||
|
||||
// According to the page number to modify the ISR mask
|
||||
HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
u8
|
||||
HalI2SGetTxPageRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
|
||||
u8 I2SIdx;
|
||||
u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
|
||||
u32 reg;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(I2STxIdx<<2));
|
||||
if ((reg & (1<<31)) == 0) {
|
||||
return I2STxIdx;
|
||||
} else {
|
||||
return 0xFF;
|
||||
}
|
||||
}
|
||||
|
||||
u8
|
||||
HalI2SGetRxPageRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
|
||||
u8 I2SIdx;
|
||||
u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
|
||||
u32 reg;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
|
||||
if ((reg & (1<<31)) == 0) {
|
||||
return I2SRxIdx;
|
||||
} else {
|
||||
return 0xFF;
|
||||
}
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SPageSendRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 PageIdx
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
|
||||
u8 I2SPageNum = pHalI2SInitData->I2SPageNum;
|
||||
u8 I2SIdx;
|
||||
|
||||
if (I2STxIdx != PageIdx) {
|
||||
DBG_I2S_ERR("HalI2SPageSendRtl8195a: UnExpected Page Index. TxPage=%d, Expected:%d\r\n",
|
||||
PageIdx, I2STxIdx);
|
||||
}
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+4*PageIdx, 1<<31);
|
||||
I2STxIdx = PageIdx+1;
|
||||
if (I2STxIdx > I2SPageNum) {
|
||||
I2STxIdx = 0;
|
||||
}
|
||||
pHalI2SInitData->I2STxIdx = I2STxIdx;
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SPageRecvRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
|
||||
u8 I2SPageNum = pHalI2SInitData->I2SPageNum;
|
||||
u32 reg;
|
||||
u8 I2SIdx;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
|
||||
if ((reg & (1<<31)) != 0) {
|
||||
DBG_I2S_ERR("HalI2SPageRecvRtl8195a: No Idle Rx Page\r\n");
|
||||
return _EXIT_FAILURE;
|
||||
}
|
||||
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx<<2), 1<<31);
|
||||
I2SRxIdx += 1;
|
||||
if (I2SRxIdx > I2SPageNum) {
|
||||
I2SRxIdx = 0;
|
||||
}
|
||||
pHalI2SInitData->I2SRxIdx = I2SRxIdx;
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SClearAllOwnBitRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 i;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
for (i=0;i<4;i++) {
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(i<<2), 0);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(i<<2), 0);
|
||||
}
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SDMACtrlRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
411
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_mii.c
Normal file
411
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_mii.c
Normal file
|
|
@ -0,0 +1,411 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "rtl8195a_mii.h"
|
||||
#include "hal_mii.h"
|
||||
|
||||
|
||||
|
||||
VOID MiiIrqHandle (IN VOID *Data);
|
||||
|
||||
VOID MiiIrqHandle (IN VOID *Data) {
|
||||
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
|
||||
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
|
||||
u32 RegValue = HalMiiGmacGetInterruptStatusRtl8195a();
|
||||
#ifdef CONFIG_MII_VERIFY
|
||||
extern u8 isRxOK;
|
||||
extern u8 isTxOK;
|
||||
extern u8 RxIntCnt;
|
||||
|
||||
|
||||
// DBG_8195A("ISR = 0x%08X\n", RegValue);
|
||||
if(RegValue & GMAC_ISR_ROK) {
|
||||
HalMiiGmacClearInterruptStatusRtl8195a(0x00410001);
|
||||
isRxOK = 1;
|
||||
RxIntCnt++;
|
||||
}
|
||||
|
||||
if(RegValue & GMAC_ISR_TOK_TI) {
|
||||
HalMiiGmacClearInterruptStatusRtl8195a(0x00410040);
|
||||
isTxOK = 1;
|
||||
}
|
||||
#else
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ConfigDebugPort_E4(u32 DebugSelect) {
|
||||
u32 RegValue;
|
||||
BOOL DebugMsg = _FALSE;
|
||||
|
||||
if (DebugMsg) {
|
||||
LOGI(ANSI_COLOR_YELLOW"Debug Port Select (0xE4)\n"ANSI_COLOR_RESET);
|
||||
LOGD2("[P] PERI_ON_010: %X\n", HAL_READ32(PERI_ON_BASE, REG_SOC_FUNC_EN));
|
||||
LOGD2("[P] PERI_ON_014: %X\n", HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN));
|
||||
}
|
||||
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_CCR);
|
||||
if (DebugMsg) {
|
||||
LOGD2("[B] 0x00E4: %X\n", RegValue);
|
||||
}
|
||||
|
||||
RegValue |= DebugSelect << 2;
|
||||
if (DebugMsg) {
|
||||
LOGD2("[B] RegValue: %X\n", RegValue);
|
||||
}
|
||||
|
||||
HAL_MII_WRITE32(REG_RTL_MII_CCR, RegValue);
|
||||
if (DebugMsg) {
|
||||
LOGD2("[A] 0x00E4: %X\n", HAL_MII_READ32(REG_RTL_MII_CCR));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* MII Initialize.
|
||||
*
|
||||
* MII Initialize.
|
||||
*
|
||||
* Initialization Steps:
|
||||
* I. Rtl8195A Board Configurations:
|
||||
* 1. MII Function Enable & AHB mux
|
||||
*
|
||||
* @return runtime status value.
|
||||
*/
|
||||
BOOL
|
||||
HalMiiGmacInitRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
|
||||
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
|
||||
u32 RegValue;
|
||||
|
||||
|
||||
/* 1. enable MII Pinmux & disable SDIO Host/Device mode Pinmux */
|
||||
RegValue = HAL_READ32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL);
|
||||
RegValue |= BIT24;
|
||||
RegValue &= ~(BIT0 | BIT1); // Important!
|
||||
HAL_WRITE32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL, RegValue);
|
||||
|
||||
/* 2. enable MII IP block (214, 12) */
|
||||
RegValue = HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN);
|
||||
RegValue |= BIT12;
|
||||
HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, RegValue);
|
||||
|
||||
/* 3. Lexra2AHB Function Enable (304, 11) */
|
||||
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL);
|
||||
RegValue |= BIT11;
|
||||
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue);
|
||||
|
||||
/* 4. enable MII bus clock (240, 24|25) */
|
||||
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0);
|
||||
RegValue |= (BIT24 | BIT25);
|
||||
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0, RegValue);
|
||||
|
||||
/* 5. */
|
||||
RegValue = HAL_READ32(SYSTEM_CTRL_BASE, 0x74) & 0xFFFFC7FF;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, 0x74, (RegValue | 0x00003000));
|
||||
|
||||
/* 6. AHB mux: select MII (214, 13) */
|
||||
RegValue = HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN);
|
||||
RegValue |= BIT13;
|
||||
HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, RegValue);
|
||||
|
||||
/* 7. Vendor Register Clock Enable (230, 6|7) */
|
||||
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_CTRL);
|
||||
RegValue |= (BIT6 | BIT7);
|
||||
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_CLK_CTRL, RegValue);
|
||||
|
||||
/* 8. Enable GMAC Lexra Timeout (090, 16|17|18) */
|
||||
RegValue = HAL_READ32(VENDOR_REG_BASE, 0x0090);
|
||||
RegValue |= (BIT16 | BIT17 | BIT18);
|
||||
HAL_WRITE32(VENDOR_REG_BASE, 0x0090, RegValue);
|
||||
|
||||
/* 9. Endian Swap Control (304, 12|13) */
|
||||
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL);
|
||||
RegValue |= (BIT12 | BIT13);
|
||||
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue);
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
|
||||
BOOL
|
||||
HalMiiInitRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
DBG_ENTRANCE;
|
||||
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
|
||||
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
|
||||
u32 RegValue;
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
|
||||
BOOL
|
||||
HalMiiGmacResetRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
HAL_MII_WRITE32(REG_RTL_MII_CR, (HAL_MII_READ32(REG_RTL_MII_CR) | BIT0));
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
|
||||
BOOL
|
||||
HalMiiGmacEnablePhyModeRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
|
||||
u32
|
||||
HalMiiGmacXmitRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalMiiGmacCleanTxRingRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalMiiGmacFillTxInfoRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
DBG_ENTRANCE;
|
||||
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
|
||||
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
|
||||
PTX_INFO pTx_Info = pMiiAdapter->pTx_Info;
|
||||
VOID* TxBuffer = pMiiAdapter->TxBuffer;
|
||||
u32 RegValue;
|
||||
|
||||
LOGI(ANSI_COLOR_GREEN"==[ Tx Descriptor Configuration ]======\n"ANSI_COLOR_RESET);
|
||||
|
||||
pTx_Info->opts1.dw = 0xBC8001FE;
|
||||
/* pTx_Info->opts1.dw = 0xBC800080; // size: 128 */
|
||||
|
||||
pTx_Info->addr = (u32)TxBuffer;
|
||||
pTx_Info->opts2.dw = 0x0400279F;
|
||||
pTx_Info->opts3.dw = 0x00000000;
|
||||
/* pTx_Info->opts4.dw = 0x57800000; */
|
||||
pTx_Info->opts4.dw = 0x1FE00000;
|
||||
LOGI("pTx_Info->addr: %X\n", pTx_Info->addr);
|
||||
|
||||
LOGI(ANSI_COLOR_YELLOW"TxFDP1 Register(0x%04X) (W: 0x%X)\n"ANSI_COLOR_RESET, REG_RTL_MII_TXFDP1, pTx_Info);
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_TXFDP1);
|
||||
LOGD2("[B] REG_RTL_MII_TXFDP1: %X\n", RegValue);
|
||||
HAL_MII_WRITE32(REG_RTL_MII_TXFDP1, pTx_Info);
|
||||
LOGD2("[A] REG_RTL_MII_TXFDP1: %X\n", HAL_MII_READ32(REG_RTL_MII_TXFDP1));
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalMiiGmacFillRxInfoRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
DBG_ENTRANCE;
|
||||
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
|
||||
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
|
||||
PRX_INFO pRx_Info = pMiiAdapter->pRx_Info;
|
||||
VOID* RxBuffer = pMiiAdapter->RxBuffer;
|
||||
u32 RegValue;
|
||||
|
||||
LOGI(ANSI_COLOR_GREEN"==[ Rx Descriptor Configuration ]======\n"ANSI_COLOR_RESET);
|
||||
|
||||
/* pRx_Info->opts1.dw = 0x80000200; //Data Length: 4095(FFF), 512(200) */
|
||||
pRx_Info->opts1.dw = 0x800001FC; //Data Length: 4095(FFF), 512(200)
|
||||
/* pRx_Info->opts1.dw = 0x8000007F; */
|
||||
|
||||
pRx_Info->addr = (u32)RxBuffer;
|
||||
pRx_Info->opts2.dw = 0x00000000;
|
||||
pRx_Info->opts3.dw = 0x00000000;
|
||||
|
||||
LOGI(ANSI_COLOR_YELLOW"RxFDP1 Register(0x%04X) (W: 0x%X)\n"ANSI_COLOR_RESET, REG_RTL_MII_RXFDP1, pRx_Info);
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_RXFDP1);
|
||||
LOGD2("[B] REG_RTL_MII_RXFDP1: %X\n", RegValue);
|
||||
HAL_MII_WRITE32(REG_RTL_MII_RXFDP1, pRx_Info);
|
||||
LOGD2("[A] REG_RTL_MII_RXFDP1: %X\n", HAL_MII_READ32(REG_RTL_MII_RXFDP1));
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalMiiGmacTxRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
DBG_ENTRANCE;
|
||||
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
|
||||
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
|
||||
PTX_INFO pTx_Info = pMiiAdapter->pTx_Info;
|
||||
u32 RegValue;
|
||||
|
||||
LOGI(ANSI_COLOR_GREEN"==[ Tx ]===============================\n"ANSI_COLOR_RESET);
|
||||
|
||||
LOGI(ANSI_COLOR_YELLOW"REG_RTL_MII_IOCMD Register(0x%04X): Enable Tx (W: 0x10, BIT4)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD);
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
|
||||
LOGD2("[B] REG_RTL_MII_IOCMD: %X\n", RegValue);
|
||||
RegValue |= BIT_IOCMD_TXENABLE(1);
|
||||
HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue);
|
||||
LOGD2("[A] REG_RTL_MII_IOCMD: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD));
|
||||
LOGD4("--> Tx Descriptor opts1: %X\n", HAL_READ32(pTx_Info, 0));
|
||||
|
||||
LOGI(ANSI_COLOR_YELLOW"REG_RTL_MII_IOCMD Register(0x%04X): Enable 1st Tx (W: 0x1, BIT0)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD);
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
|
||||
LOGD2("[B] REG_RTL_MII_IOCMD: %X\n", RegValue);
|
||||
RegValue |= BIT_IOCMD_FIRST_DMATX_ENABLE(1);
|
||||
HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue);
|
||||
LOGD2("[A] REG_RTL_MII_IOCMD: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD));
|
||||
LOGD4("--> Tx Descriptor opts1: %X\n", HAL_READ32(pTx_Info, 0));
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalMiiGmacRxRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
DBG_ENTRANCE;
|
||||
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
|
||||
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
|
||||
u32 RegValue;
|
||||
|
||||
LOGI(ANSI_COLOR_GREEN"==[ Rx ]===============================\n"ANSI_COLOR_RESET);
|
||||
LOGI(ANSI_COLOR_YELLOW"Transmit (Tx) Configuration Register (0x%04X) (W: 0x00000C00)\n"ANSI_COLOR_RESET, REG_RTL_MII_TCR);
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_TCR);
|
||||
LOGD2("[B] REG_RTL_MII_TCR: %X\n", RegValue);
|
||||
|
||||
HAL_MII_WRITE32(REG_RTL_MII_TCR, 0x00000D00); // loopback R2T mode
|
||||
LOGD2("[A] REG_RTL_MII_TCR: %X\n", HAL_MII_READ32(REG_RTL_MII_TCR));
|
||||
|
||||
LOGI(ANSI_COLOR_YELLOW"Receive (Rx) Configuration Register (0x%04X) (W: 0x0000007F)\n"ANSI_COLOR_RESET, REG_RTL_MII_RCR);
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_RCR);
|
||||
LOGD2("[B] REG_RTL_MII_RCR: %X\n", RegValue);
|
||||
HAL_MII_WRITE32(REG_RTL_MII_RCR, 0x0000007F);
|
||||
LOGD2("[A] REG_RTL_MII_RCR: %X\n", HAL_MII_READ32(REG_RTL_MII_RCR));
|
||||
|
||||
LOGI(ANSI_COLOR_YELLOW"EhtrntRxCPU_Des_Num1 (0x%04X) (W: 0x1F0A0F00)\n"ANSI_COLOR_RESET, REG_RTL_MII_ETNRXCPU1);
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_ETNRXCPU1);
|
||||
LOGD2("[B] REG_RTL_MII_ETNRXCPU1: %X\n", RegValue);
|
||||
HAL_MII_WRITE32(REG_RTL_MII_ETNRXCPU1, 0x1F0A0F00);
|
||||
LOGD2("[A] REG_RTL_MII_ETNRXCPU1: %X\n", HAL_MII_READ32(REG_RTL_MII_ETNRXCPU1));
|
||||
|
||||
LOGI(ANSI_COLOR_YELLOW"Rx_Pse_Des_Thres_1_h (0x%04X) (W: 0x00000022)\n"ANSI_COLOR_RESET, REG_RTL_MII_RX_PSE1);
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_RX_PSE1);
|
||||
LOGD2("[B] REG_RTL_MII_RX_PSE1: %X\n", RegValue);
|
||||
HAL_MII_WRITE32(REG_RTL_MII_RX_PSE1, 0x00000022);
|
||||
LOGD2("[A] REG_RTL_MII_RX_PSE1: %X\n", HAL_MII_READ32(REG_RTL_MII_RX_PSE1));
|
||||
|
||||
LOGI(ANSI_COLOR_YELLOW"Ethernet_IO_CMD1 Register(0x%04X): Enable Rx Ring1 (W: 0x10000, BIT16)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD1);
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1);
|
||||
LOGD2("[B] REG_RTL_MII_IOCMD1: %X\n", RegValue);
|
||||
RegValue |= BIT_IOCMD1_FIRST_DMARX_ENABLE(1);
|
||||
HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, RegValue);
|
||||
LOGD2("[A] REG_RTL_MII_IOCMD1: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD1));
|
||||
|
||||
LOGI(ANSI_COLOR_YELLOW"REG_RTL_MII_IOCMD Register(0x%04X): Enable Rx (W: 0x20, BIT5)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD);
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
|
||||
LOGD2("[B] REG_RTL_MII_IOCMD: %X\n", RegValue);
|
||||
RegValue |= BIT_IOCMD_RXENABLE(1);
|
||||
HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue);
|
||||
LOGD2("[A] REG_RTL_MII_IOCMD: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD));
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalMiiGmacSetDefaultEthIoCmdRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
DBG_ENTRANCE;
|
||||
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
|
||||
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
|
||||
u32 RegValue;
|
||||
|
||||
LOGI(ANSI_COLOR_YELLOW"REG_RTL_MII_IOCMD Register(0x%04X) (W: CMD_CONFIG)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD);
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
|
||||
LOGD2("[B] REG_RTL_MII_IOCMD: %X\n", RegValue);
|
||||
HAL_MII_WRITE32(REG_RTL_MII_IOCMD, CMD_CONFIG);
|
||||
LOGD2("[A] REG_RTL_MII_IOCMD: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD));
|
||||
|
||||
LOGI(ANSI_COLOR_YELLOW"Ethernet_IO_CMD1 Register(0x%04X) (W: CMD1_CONFIG)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD1);
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1);
|
||||
LOGD2("[B] REG_RTL_MII_IOCMD1: %X\n", RegValue);
|
||||
HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, CMD1_CONFIG);
|
||||
LOGD2("[A] REG_RTL_MII_IOCMD1: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD1));
|
||||
|
||||
//2014-04-29 yclin (disable 0x40051438[27] r_en_precise_dma) {
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1);
|
||||
RegValue = RegValue & 0xF7FFFFFF;
|
||||
HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, RegValue);
|
||||
// }
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalMiiGmacInitIrqRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
IRQ_HANDLE MiiIrqHandle_Master;
|
||||
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
|
||||
|
||||
|
||||
MiiIrqHandle_Master.Data = (u32) (pMiiAdapter);
|
||||
MiiIrqHandle_Master.IrqNum = GMAC_IRQ;
|
||||
MiiIrqHandle_Master.IrqFun = (IRQ_FUN) MiiIrqHandle;
|
||||
MiiIrqHandle_Master.Priority = 0;
|
||||
InterruptRegister(&MiiIrqHandle_Master);
|
||||
InterruptEn(&MiiIrqHandle_Master);
|
||||
}
|
||||
|
||||
|
||||
u32
|
||||
HalMiiGmacGetInterruptStatusRtl8195a(
|
||||
VOID
|
||||
)
|
||||
{
|
||||
DBG_ENTRANCE;
|
||||
u32 RegValue;
|
||||
|
||||
RegValue = HAL_MII_READ32(REG_RTL_MII_IMRISR);
|
||||
LOGD("REG_RTL_MII_IMRISR: %X\n", RegValue);
|
||||
return RegValue;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalMiiGmacClearInterruptStatusRtl8195a(
|
||||
u32 IsrStatus
|
||||
)
|
||||
{
|
||||
DBG_ENTRANCE;
|
||||
HAL_MII_WRITE32(REG_RTL_MII_IMRISR, IsrStatus);
|
||||
}
|
||||
|
||||
|
||||
1919
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_nfc.c
Normal file
1919
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_nfc.c
Normal file
File diff suppressed because it is too large
Load diff
360
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c
Normal file
360
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c
Normal file
|
|
@ -0,0 +1,360 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "platform_autoconf.h"
|
||||
#include "diag.h"
|
||||
#include "rtl8195a_pcm.h"
|
||||
#include "hal_pcm.h"
|
||||
|
||||
extern void *
|
||||
_memset( void *s, int c, SIZE_T n );
|
||||
|
||||
VOID
|
||||
HalPcmOnOffRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
|
||||
//todo on off pcm
|
||||
|
||||
}
|
||||
|
||||
//default sampling rate 8khz, linear, 10ms frame size, time slot 0 , tx+rx
|
||||
// master mode, enable endian swap
|
||||
// Question: need local tx/rx page?
|
||||
BOOL
|
||||
HalPcmInitRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
|
||||
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
|
||||
_memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER));
|
||||
|
||||
//4 1) Initial PcmChCNR03 Register
|
||||
pHalPcmAdapter->PcmChCNR03.CH0MuA = 0;
|
||||
pHalPcmAdapter->PcmChCNR03.CH0Band = 0;
|
||||
|
||||
|
||||
//4 1) Initial PcmTSR03 Register
|
||||
pHalPcmAdapter->PcmTSR03.CH0TSA = 0;
|
||||
|
||||
//4 1) Initial PcmBSize03 Register
|
||||
pHalPcmAdapter->PcmBSize03.CH0BSize = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte
|
||||
|
||||
|
||||
//4 2) Initial Ctl Register
|
||||
|
||||
pHalPcmAdapter->PcmCtl.Pcm_En = 1;
|
||||
pHalPcmAdapter->PcmCtl.SlaveMode = 0;
|
||||
pHalPcmAdapter->PcmCtl.FsInv = 0;
|
||||
pHalPcmAdapter->PcmCtl.LinearMode = 0;
|
||||
pHalPcmAdapter->PcmCtl.LoopBack = 0;
|
||||
pHalPcmAdapter->PcmCtl.EndianSwap = 1;
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
|
||||
BOOL
|
||||
HalPcmSettingRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
|
||||
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
|
||||
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
|
||||
u8 PcmCh = pHalPcmAdapter->PcmCh;
|
||||
u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03;
|
||||
u32 Isr03;
|
||||
|
||||
PcmCh=0;
|
||||
//4 1) Check Pcm index is avaliable
|
||||
if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) {
|
||||
//4 Pcm index is running, stop first
|
||||
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
|
||||
|
||||
return _FALSE;
|
||||
}
|
||||
|
||||
//4 2) Check if there are the pending isr
|
||||
|
||||
|
||||
Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03);
|
||||
Isr03 &= 0xff000000;
|
||||
//4 Clear Pending Isr
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03);
|
||||
//}
|
||||
|
||||
|
||||
//4 3) Process RegCtl
|
||||
RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL);
|
||||
|
||||
//4 Clear Ctl register bits
|
||||
RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL &
|
||||
BIT_INV_CTLX_FSINV &
|
||||
BIT_INV_CTLX_PCM_EN &
|
||||
BIT_INV_CTLX_LINEARMODE &
|
||||
BIT_INV_CTLX_LOOP_BACK &
|
||||
BIT_INV_CTLX_ENDIAN_SWAP);
|
||||
|
||||
RegCtl = BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) |
|
||||
BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) |
|
||||
BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) |
|
||||
BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) |
|
||||
BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) |
|
||||
BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) |
|
||||
RegCtl;
|
||||
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl);
|
||||
//4 4) Program ChCNR03 Register
|
||||
|
||||
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
|
||||
|
||||
RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE &
|
||||
BIT_INV_CHCNR03_CH0TE &
|
||||
BIT_INV_CHCNR03_CH0MUA &
|
||||
BIT_INV_CHCNR03_CH0BAND);
|
||||
|
||||
RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) |
|
||||
BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) |
|
||||
BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) |
|
||||
BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) |
|
||||
RegChCNR03;
|
||||
|
||||
DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03);
|
||||
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03);
|
||||
// time slot
|
||||
RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03);
|
||||
|
||||
RegTSR03 &= (BIT_INV_TSR03_CH0TSA);
|
||||
RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) |
|
||||
RegTSR03;
|
||||
|
||||
DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03);
|
||||
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03);
|
||||
|
||||
// buffer size
|
||||
RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03);
|
||||
|
||||
RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE);
|
||||
RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) |
|
||||
RegBSize03;
|
||||
|
||||
DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03);
|
||||
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03);
|
||||
|
||||
|
||||
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
BOOL
|
||||
HalPcmEnRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
|
||||
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
|
||||
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
|
||||
u8 PcmCh = pHalPcmAdapter->PcmCh;
|
||||
u32 RegChCNR03;
|
||||
|
||||
PcmCh=0;
|
||||
pHalPcmAdapter->Enable = 1;
|
||||
|
||||
|
||||
//4 1) Check Pcm index is avaliable
|
||||
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
|
||||
if (RegChCNR03 & (BIT24|BIT25)) {
|
||||
//4 Pcm index is running, stop first
|
||||
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
|
||||
|
||||
return _FALSE;
|
||||
}
|
||||
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25);
|
||||
pHalPcmAdapter->PcmChCNR03.CH0RE = 1;
|
||||
pHalPcmAdapter->PcmChCNR03.CH0TE = 1;
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
BOOL
|
||||
HalPcmDisRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
|
||||
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
|
||||
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
|
||||
u8 PcmCh = pHalPcmAdapter->PcmCh;
|
||||
u32 RegChCNR03;
|
||||
|
||||
PcmCh=0;
|
||||
pHalPcmAdapter->Enable = 0;
|
||||
|
||||
|
||||
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
|
||||
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25)));
|
||||
pHalPcmAdapter->PcmChCNR03.CH0RE = 0;
|
||||
pHalPcmAdapter->PcmChCNR03.CH0TE = 0;
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
BOOL
|
||||
HalPcmIsrEnAndDisRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
/*
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
u32 IsrMask, Addr, IsrCtrl;
|
||||
u8 IsrTypeIndex = 0;
|
||||
|
||||
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
|
||||
|
||||
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
|
||||
Addr = (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8);
|
||||
|
||||
IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr);
|
||||
|
||||
IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask):
|
||||
((~pHalGdmaAdapter->ChEn) & IsrMask));
|
||||
|
||||
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
|
||||
Addr,
|
||||
IsrCtrl
|
||||
);
|
||||
|
||||
}
|
||||
}
|
||||
*/
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
BOOL
|
||||
HalPcmDumpRegRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
/*
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
|
||||
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
|
||||
REG_GDMA_CH_EN,
|
||||
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
|
||||
(pHalGdmaAdapter->ChEn))
|
||||
);
|
||||
*/
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
BOOL
|
||||
HalPcmRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
|
||||
REG_GDMA_CH_EN,
|
||||
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
|
||||
~(pHalGdmaAdapter->ChEn))
|
||||
);
|
||||
*/
|
||||
return _TRUE;
|
||||
}
|
||||
/*
|
||||
u8
|
||||
HalGdmaChIsrCleanRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
u32 IsrStatus;
|
||||
u8 IsrTypeIndex = 0, IsrActBitMap = 0;
|
||||
|
||||
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
|
||||
|
||||
IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
|
||||
(REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8));
|
||||
|
||||
// DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus);
|
||||
|
||||
IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF));
|
||||
|
||||
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
|
||||
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
|
||||
(REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)),
|
||||
(IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF))
|
||||
);
|
||||
IsrActBitMap |= BIT_(IsrTypeIndex);
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
return IsrActBitMap;
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalGdmaChCleanAutoSrcRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
u32 CfgxLow;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
|
||||
|
||||
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC;
|
||||
|
||||
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
|
||||
CfgxLow
|
||||
);
|
||||
|
||||
DBG_8195A_DMA("CFG Low data:0x%x\n",
|
||||
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
|
||||
}
|
||||
|
||||
VOID
|
||||
HalGdmaChCleanAutoDstRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
u32 CfgxLow;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
|
||||
|
||||
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST;
|
||||
|
||||
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
|
||||
CfgxLow
|
||||
);
|
||||
DBG_8195A_DMA("CFG Low data:0x%x\n",
|
||||
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
|
||||
|
||||
}
|
||||
*/
|
||||
|
||||
|
||||
219
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pwm.c
Normal file
219
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pwm.c
Normal file
|
|
@ -0,0 +1,219 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "hal_peri_on.h"
|
||||
|
||||
#ifdef CONFIG_PWM_EN
|
||||
#include "rtl8195a_pwm.h"
|
||||
#include "hal_pwm.h"
|
||||
|
||||
extern HAL_PWM_ADAPTER PWMPin[];
|
||||
|
||||
extern HAL_TIMER_OP HalTimerOp;
|
||||
|
||||
/**
|
||||
* @brief Configure a G-Timer to generate a tick with certain time.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
* @param tick_time: the time (micro-second) of a tick
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void
|
||||
Pwm_SetTimerTick_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt,
|
||||
u32 tick_time
|
||||
)
|
||||
{
|
||||
TIMER_ADAPTER TimerAdapter;
|
||||
|
||||
|
||||
if (tick_time <= MIN_GTIMER_TIMEOUT) {
|
||||
tick_time = MIN_GTIMER_TIMEOUT;
|
||||
}
|
||||
else {
|
||||
tick_time = (((tick_time-1)/TIMER_TICK_US)+1) * TIMER_TICK_US;
|
||||
}
|
||||
|
||||
// Initial a G-Timer for the PWM pin
|
||||
if (pPwmAdapt->tick_time != tick_time) {
|
||||
TimerAdapter.IrqDis = 1; // Disable Irq
|
||||
TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) NULL;
|
||||
TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ;
|
||||
TimerAdapter.IrqHandle.Priority = 0;
|
||||
TimerAdapter.IrqHandle.Data = (u32)NULL;
|
||||
TimerAdapter.TimerId = pPwmAdapt->gtimer_id;
|
||||
TimerAdapter.TimerIrqPriority = 0;
|
||||
TimerAdapter.TimerLoadValueUs = tick_time-1;
|
||||
TimerAdapter.TimerMode = 1; // auto-reload with user defined value
|
||||
|
||||
HalTimerOp.HalTimerInit((VOID*) &TimerAdapter);
|
||||
pPwmAdapt->tick_time = tick_time;
|
||||
DBG_PWM_INFO("%s: Timer_Id=%d Count=%d\n", __FUNCTION__, pPwmAdapt->gtimer_id, tick_time);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the duty ratio of the PWM pin.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
* @param period: the period time, in micro-second.
|
||||
* @param pulse_width: the pulse width time, in micro-second.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void
|
||||
HAL_Pwm_SetDuty_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt,
|
||||
u32 period,
|
||||
u32 pulse_width
|
||||
)
|
||||
{
|
||||
u32 RegAddr;
|
||||
u32 RegValue;
|
||||
u32 period_tick;
|
||||
u32 pulsewidth_tick;
|
||||
u32 tick_time;
|
||||
u8 timer_id;
|
||||
u8 pwm_id;
|
||||
|
||||
pwm_id = pPwmAdapt->pwm_id;
|
||||
// Adjust the tick time to a proper value
|
||||
if (period < (MIN_GTIMER_TIMEOUT*2)) {
|
||||
DBG_PWM_ERR ("HAL_Pwm_SetDuty_8195a: Invalid PWM period(%d), too short!!\n", period);
|
||||
tick_time = MIN_GTIMER_TIMEOUT;
|
||||
period = MIN_GTIMER_TIMEOUT*2;
|
||||
}
|
||||
else {
|
||||
tick_time = period / 0x3fc;
|
||||
if (tick_time < MIN_GTIMER_TIMEOUT) {
|
||||
tick_time = MIN_GTIMER_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
Pwm_SetTimerTick_8195a(pPwmAdapt, tick_time);
|
||||
tick_time = pPwmAdapt->tick_time;
|
||||
#if 0
|
||||
// Check if current tick time needs adjustment
|
||||
if ((pPwmAdapt->tick_time << 12) <= period) {
|
||||
// need a longger tick time
|
||||
}
|
||||
else if ((pPwmAdapt->tick_time >> 2) >= period) {
|
||||
// need a shorter tick time
|
||||
}
|
||||
#endif
|
||||
period_tick = period/tick_time;
|
||||
if (period_tick == 0) {
|
||||
period_tick = 1;
|
||||
}
|
||||
|
||||
if (pulse_width >= period) {
|
||||
// pulse_width = period-1;
|
||||
pulse_width = period;
|
||||
}
|
||||
pulsewidth_tick = pulse_width/tick_time;
|
||||
if (pulsewidth_tick == 0) {
|
||||
// pulsewidth_tick = 1;
|
||||
}
|
||||
|
||||
timer_id = pPwmAdapt->gtimer_id;
|
||||
|
||||
pPwmAdapt->period = period_tick & 0x3ff;
|
||||
pPwmAdapt->pulsewidth = pulsewidth_tick & 0x3ff;
|
||||
|
||||
RegAddr = REG_PERI_PWM0_CTRL + (pwm_id*4);
|
||||
RegValue = BIT31 | (timer_id<<24) | (pulsewidth_tick<<12) | period_tick;
|
||||
|
||||
HAL_WRITE32(PERI_ON_BASE, RegAddr, RegValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes and enable a PWM control pin.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
* @param sel: pin mux selection
|
||||
* @param timer_id: the G-timer index assigned to this PWM
|
||||
*
|
||||
* @retval HAL_Status
|
||||
*/
|
||||
HAL_Status
|
||||
HAL_Pwm_Init_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt
|
||||
)
|
||||
{
|
||||
u32 pwm_id;
|
||||
u32 pin_sel;
|
||||
|
||||
pwm_id = pPwmAdapt->pwm_id;
|
||||
pin_sel = pPwmAdapt->sel;
|
||||
// Initial a G-Timer for the PWM pin
|
||||
Pwm_SetTimerTick_8195a(pPwmAdapt, MIN_GTIMER_TIMEOUT);
|
||||
|
||||
// Set default duty ration
|
||||
HAL_Pwm_SetDuty_8195a(pPwmAdapt, 20000, 10000);
|
||||
|
||||
// Configure the Pin Mux
|
||||
PinCtrl((PWM0+pwm_id), pin_sel, 1);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable a PWM control pin.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void
|
||||
HAL_Pwm_Enable_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt
|
||||
)
|
||||
{
|
||||
u32 pwm_id;
|
||||
|
||||
pwm_id = pPwmAdapt->pwm_id;
|
||||
// Configure the Pin Mux
|
||||
if (!pPwmAdapt->enable) {
|
||||
PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 1);
|
||||
HalTimerOp.HalTimerEn(pPwmAdapt->gtimer_id);
|
||||
pPwmAdapt->enable = 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable a PWM control pin.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void
|
||||
HAL_Pwm_Disable_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt
|
||||
)
|
||||
{
|
||||
u32 pwm_id;
|
||||
|
||||
pwm_id = pPwmAdapt->pwm_id;
|
||||
// Configure the Pin Mux
|
||||
if (pPwmAdapt->enable) {
|
||||
PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 0);
|
||||
HalTimerOp.HalTimerDis(pPwmAdapt->gtimer_id);
|
||||
pPwmAdapt->enable = 0;
|
||||
}
|
||||
}
|
||||
|
||||
#endif //CONFIG_PWM_EN
|
||||
File diff suppressed because it is too large
Load diff
1188
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
Normal file
1188
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
Normal file
File diff suppressed because it is too large
Load diff
317
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_timer.c
Normal file
317
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_timer.c
Normal file
|
|
@ -0,0 +1,317 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
#include "rtl8195a.h"
|
||||
#include "rtl8195a_timer.h"
|
||||
|
||||
extern u32 gTimerRecord;
|
||||
extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM];
|
||||
|
||||
#ifdef CONFIG_CHIP_C_CUT
|
||||
extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
|
||||
#else
|
||||
u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
|
||||
#endif
|
||||
|
||||
VOID
|
||||
HalTimerIrq2To7Handle_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
u32 TimerIrqStatus = 0, CheckIndex;
|
||||
IRQ_FUN pHandler;
|
||||
|
||||
TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF);
|
||||
|
||||
DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus);
|
||||
|
||||
for (CheckIndex = 2; CheckIndex<8; CheckIndex++) {
|
||||
|
||||
//3 Check IRQ status bit and Timer X IRQ enable bit
|
||||
if ((TimerIrqStatus & BIT_(CheckIndex)) &&
|
||||
(HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) {
|
||||
//3 Execute Timer callback function
|
||||
pHandler = Timer2To7VectorTable[CheckIndex-2];
|
||||
if (pHandler != NULL) {
|
||||
pHandler((void*)Timer2To7HandlerData[CheckIndex-2]);
|
||||
}
|
||||
//3 Clear Timer ISR
|
||||
HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalTimerIrqRegisterRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
|
||||
IRQ_HANDLE TimerIrqHandle;
|
||||
IRQ_FUN BackUpIrqFun = NULL;
|
||||
|
||||
if (pHalTimerAdap->TimerId > 7) {
|
||||
DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
else {
|
||||
if (pHalTimerAdap->TimerId > 1) {
|
||||
|
||||
TimerIrqHandle.IrqNum = TIMER2_7_IRQ;
|
||||
TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch;
|
||||
|
||||
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] =
|
||||
(IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
|
||||
Timer2To7HandlerData[pHalTimerAdap->TimerId-2] =
|
||||
(uint32_t) pHalTimerAdap->IrqHandle.Data;
|
||||
}
|
||||
else {
|
||||
TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
|
||||
TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
|
||||
}
|
||||
TimerIrqHandle.Data = (u32)pHalTimerAdap;
|
||||
InterruptRegister(&TimerIrqHandle);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalTimerInitRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
|
||||
HAL_Status ret=HAL_OK;
|
||||
u32 ControlReg = 0, LoadCount = 0;
|
||||
u32 LoadUsX4;
|
||||
|
||||
if ((gTimerRecord & (1<<pHalTimerAdap->TimerId)) != 0) {
|
||||
DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2);
|
||||
|
||||
if (pHalTimerAdap->TimerMode) {
|
||||
//User-defined Mode
|
||||
LoadUsX4 = pHalTimerAdap->TimerLoadValueUs << 2;
|
||||
if (LoadUsX4 < TIMER_TICK_US_X4) {
|
||||
DBG_TIMER_WARN("%s : Timer Load Count = 1!\r\n", __FUNCTION__);
|
||||
LoadCount = 1;
|
||||
}
|
||||
else {
|
||||
LoadCount = (LoadUsX4-(TIMER_TICK_US_X4>>1))/TIMER_TICK_US_X4; // to get the most closed integer
|
||||
if (LoadCount == 0) {
|
||||
LoadCount = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
LoadCount = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
|
||||
//4 1) Config Timer Setting
|
||||
/*
|
||||
set TimerControlReg
|
||||
0: Timer enable (0,disable; 1,enable)
|
||||
1: Timer Mode (0, free-running mode; 1, user-defined count mode)
|
||||
2: Timer Interrupt Mask (0, not masked; 1,masked)
|
||||
*/
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
|
||||
ControlReg);
|
||||
|
||||
// set TimerLoadCount Register
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF),
|
||||
LoadCount);
|
||||
|
||||
//4 2) Setting Timer IRQ
|
||||
if (!pHalTimerAdap->IrqDis) {
|
||||
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
|
||||
//4 2.1) Initial TimerIRQHandle
|
||||
ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap);
|
||||
if (HAL_OK != ret) {
|
||||
DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
|
||||
return ret;
|
||||
}
|
||||
//4 2.2) Enable TimerIRQ for Platform
|
||||
InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
|
||||
|
||||
}
|
||||
else {
|
||||
DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//4 4) Enable Timer
|
||||
// HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
|
||||
// (ControlReg|0x1));
|
||||
|
||||
gTimerRecord |= (1<<pHalTimerAdap->TimerId);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
HAL_Status
|
||||
HalTimerIrqUnRegisterRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
|
||||
PIRQ_HANDLE pTimerIrqHandle;
|
||||
u32 i;
|
||||
|
||||
pTimerIrqHandle = &pHalTimerAdap->IrqHandle;
|
||||
|
||||
if (pHalTimerAdap->TimerId > 7) {
|
||||
DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
else {
|
||||
if (pHalTimerAdap->TimerId > 1) {
|
||||
pTimerIrqHandle->IrqNum = TIMER2_7_IRQ;
|
||||
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL;
|
||||
for (i=0;i<MAX_TIMER_VECTOR_TABLE_NUM;i++) {
|
||||
if (Timer2To7VectorTable[i] != NULL) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i == MAX_TIMER_VECTOR_TABLE_NUM) {
|
||||
// All timer UnRegister Interrupt
|
||||
InterruptDis((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
|
||||
InterruptUnRegister(pTimerIrqHandle);
|
||||
}
|
||||
}
|
||||
else {
|
||||
pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
|
||||
InterruptUnRegister(pTimerIrqHandle);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalTimerDeInitRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
|
||||
u32 timer_id;
|
||||
|
||||
timer_id = pHalTimerAdap->TimerId;
|
||||
HalTimerDisRtl8195a (timer_id);
|
||||
if (!pHalTimerAdap->IrqDis) {
|
||||
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
|
||||
HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap);
|
||||
}
|
||||
}
|
||||
|
||||
gTimerRecord &= ~(1<<pHalTimerAdap->TimerId);
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTimerReLoadRtl8195a_Patch(
|
||||
IN u32 TimerId,
|
||||
IN u32 LoadUs
|
||||
)
|
||||
{
|
||||
u32 LoadCount = 0;
|
||||
u32 LoadUsX4;
|
||||
|
||||
//User-defined Mode
|
||||
LoadUsX4 = LoadUs << 2; // time 4
|
||||
if (LoadUsX4 < TIMER_TICK_US_X4) {
|
||||
DBG_TIMER_WARN("HalTimerReLoadRtl8195a Warning : Timer Load Count = 1!!!!!!!\n");
|
||||
LoadCount = 1;
|
||||
}
|
||||
else {
|
||||
LoadCount = (LoadUsX4-(TIMER_TICK_US_X4>>1))/TIMER_TICK_US_X4; // to get the most closed integer
|
||||
if (LoadCount == 0) {
|
||||
LoadCount = 1;
|
||||
}
|
||||
}
|
||||
|
||||
DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount);
|
||||
// set TimerLoadCount Register
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF),
|
||||
LoadCount);
|
||||
}
|
||||
|
||||
u32
|
||||
HalTimerReadCountRtl8195a_Patch(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
u32 TimerCountOld;
|
||||
u32 TimerCountNew;
|
||||
u32 TimerRDCnt;
|
||||
|
||||
TimerRDCnt = 0;
|
||||
TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
|
||||
while(1) {
|
||||
TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
|
||||
|
||||
if (TimerCountOld == TimerCountNew) {
|
||||
return (u32)TimerCountOld;
|
||||
}
|
||||
else {
|
||||
TimerRDCnt++;
|
||||
TimerCountOld = TimerCountNew;
|
||||
|
||||
if (TimerRDCnt >= 2){
|
||||
return (u32)TimerCountOld;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTimerIrqEnRtl8195a(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
|
||||
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~(BIT2)));
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTimerIrqDisRtl8195a(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
|
||||
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT2));
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTimerEnRtl8195a_Patch(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
|
||||
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT0));
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTimerDisRtl8195a_Patch(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
// Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
|
||||
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~BIT0));
|
||||
}
|
||||
|
||||
399
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c
Normal file
399
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c
Normal file
|
|
@ -0,0 +1,399 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "rtl8195a_uart.h"
|
||||
#include "hal_uart.h"
|
||||
#include "hal_gdma.h"
|
||||
|
||||
#if (CONFIG_CHIP_A_CUT | CONFIG_CHIP_B_CUT)
|
||||
|
||||
const u32 BAUDRATE_PATCH[] = {
|
||||
1200, 2400, 4800, 9600,
|
||||
14400, 19200, 28800, 38400,
|
||||
57600, 76800, 115200, 128000,
|
||||
153600, 230400, 460800, 500000,
|
||||
921600, 1000000, 1382400, 1444400,
|
||||
1500000, 1843200, 2000000, 2100000,
|
||||
2764800, 3000000, 3250000, 3692300,
|
||||
3750000, 4000000, 6000000,
|
||||
|
||||
// For UART to IR Carrier
|
||||
66000, 72000, 73400, 76000,
|
||||
80000, 112000
|
||||
};
|
||||
|
||||
#if 0
|
||||
const u32 OVSR_PATCH[] = {
|
||||
11, 13, 19, 10,
|
||||
20, 10, 20, 17,
|
||||
11, 10, 17, 10,
|
||||
10, 13, 18, 13,
|
||||
20, 19, 13, 15,
|
||||
13, 13, 15, 13,
|
||||
12, 11, 11, 20,
|
||||
13
|
||||
};
|
||||
|
||||
const u32 DIV_PATCH[] = {
|
||||
6105, 643, 293, 434,
|
||||
142, 217, 71, 62,
|
||||
65, 62, 31, 34,
|
||||
17, 12, 5, 6,
|
||||
3, 3, 4, 3,
|
||||
3, 3, 2, 2,
|
||||
2, 2, 2, 1,
|
||||
1
|
||||
};
|
||||
|
||||
const u32 OVSR_ADJ_PATCH[] = {
|
||||
0x24A, 0x555, 0x3BB, 0x000,
|
||||
0x24A, 0x000, 0x24A, 0x555,
|
||||
0x008, 0x555, 0x555, 0x5AD,
|
||||
0x5AD, 0x7EF, 0x020, 0x7EF,
|
||||
0x020, 0x444, 0x7EF, 0x080,
|
||||
0x7EF, 0x444, 0x080, 0x7EF,
|
||||
0x6FB, 0x122, 0x010, 0x5F7,
|
||||
0x7EF
|
||||
};
|
||||
#else
|
||||
const u8 OVSR_PATCH[] = {
|
||||
10, 10, 10, 15,
|
||||
10, 13, 15, 11,
|
||||
12, 11, 12, 11,
|
||||
11, 18, 11, 18,
|
||||
11, 10, 11, 11,
|
||||
18, 11, 10, 13,
|
||||
14, 13, 12, 11,
|
||||
10, 10, 13,
|
||||
|
||||
// For UART to IR Carrier
|
||||
11, 18, 14, 10,
|
||||
10, 11
|
||||
};
|
||||
|
||||
const u16 DIV_PATCH[] = {
|
||||
6516, 3258, 1629, 543,
|
||||
543, 311, 181, 188,
|
||||
114, 94, 57, 57,
|
||||
47, 19, 15, 9,
|
||||
8, 8, 5, 5,
|
||||
3, 4, 4, 3,
|
||||
2, 2, 2, 2,
|
||||
2, 2, 1,
|
||||
|
||||
// For UART to IR Carrier
|
||||
111, 63, 79, 102,
|
||||
98, 64
|
||||
};
|
||||
|
||||
const u16 OVSR_ADJ_PATCH[] = {
|
||||
0x555, 0x555, 0x555, 0x3BB,
|
||||
0x555, 0x5DD, 0x3BB, 0x252,
|
||||
0x555, 0x252, 0x555, 0x222,
|
||||
0x252, 0x3BB, 0x7EF, 0x444,
|
||||
0x008, 0x222, 0x7EF, 0x252,
|
||||
0x444, 0x008, 0x222, 0x000,
|
||||
0x5F7, 0x76D, 0x5AD, 0x010,
|
||||
0x5FF, 0x222, 0x76D,
|
||||
|
||||
// For UART to IR Carrier
|
||||
0x24A, 0x252, 0x252, 0x5DD,
|
||||
0x5AD, 0x5AD
|
||||
};
|
||||
#endif
|
||||
#if 0
|
||||
static s32
|
||||
FindElementIndex(
|
||||
u32 Element, ///< RUART Baudrate
|
||||
u32* Array ///< Pre-defined Baudrate Array
|
||||
)
|
||||
{
|
||||
/* DBG_ENTRANCE; */
|
||||
u32 BaudRateNumber = 29;
|
||||
s32 Result = -1;
|
||||
u32 Index = 0;
|
||||
|
||||
for (Index = 0; Index < BaudRateNumber && Result == -1; Index++) {
|
||||
if (Element == Array[Index])
|
||||
Result = Index;
|
||||
}
|
||||
return Result; //TODO: Error handling
|
||||
}
|
||||
#endif
|
||||
s32
|
||||
FindElementIndex_Patch(
|
||||
u32 Element, ///< RUART Baudrate
|
||||
u32* Array, ///< Pre-defined Baudrate Array
|
||||
u32 ElementNo
|
||||
)
|
||||
{
|
||||
/* DBG_ENTRANCE; */
|
||||
s32 Result = -1;
|
||||
u32 Index = 0;
|
||||
|
||||
for (Index = 0; Index < ElementNo && Result == -1; Index++) {
|
||||
if (Element == Array[Index])
|
||||
Result = Index;
|
||||
}
|
||||
return Result; //TODO: Error handling
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalRuartInitRtl8195a_Patch(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
)
|
||||
{
|
||||
/* DBG_ENTRANCE; */
|
||||
u32 RegValue;
|
||||
u32 Divisor;
|
||||
u32 Dll;
|
||||
u32 Dlm;
|
||||
u8 UartIndex;
|
||||
s32 ElementIndex;
|
||||
RUART_SPEED_SETTING RuartSpeedSetting;
|
||||
u8 PinmuxSelect;
|
||||
|
||||
PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data;
|
||||
|
||||
UartIndex = pHalRuartAdapter->UartIndex;
|
||||
PinmuxSelect = pHalRuartAdapter->PinmuxSelect;
|
||||
|
||||
if (UartIndex > 2) {
|
||||
DBG_UART_ERR(ANSI_COLOR_MAGENTA"HalRuartInitRtl8195a: Invalid UART Index\n"ANSI_COLOR_RESET);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
DBG_UART_INFO("%s==>\n", __FUNCTION__);
|
||||
DBG_UART_INFO("HalRuartInitRtl8195a: [UART %d] PinSel=%d\n", UartIndex, PinmuxSelect);
|
||||
if(( PinmuxSelect == RUART0_MUX_TO_GPIOE ) && ((UartIndex == 0) || (UartIndex == 1))) {
|
||||
DBG_UART_WARN(ANSI_COLOR_MAGENTA"UART Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
|
||||
}
|
||||
|
||||
// switch Pin from EEPROM to UART0
|
||||
if(( PinmuxSelect == RUART0_MUX_TO_GPIOC ) && (UartIndex == 0)) {
|
||||
RegValue = HAL_READ32(SYSTEM_CTRL_BASE, 0xa4);
|
||||
if (RegValue & 0x10) {
|
||||
DBG_UART_WARN("Disable EEPROM Pin for UART 0\n");
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, 0xa4, (RegValue & (~0x10)));
|
||||
}
|
||||
}
|
||||
|
||||
switch (UartIndex) {
|
||||
case 0:
|
||||
/* UART 0 */
|
||||
ACTCK_UART0_CCTRL(ON);
|
||||
SLPCK_UART0_CCTRL(ON);
|
||||
PinCtrl(UART0, PinmuxSelect, ON);
|
||||
UART0_FCTRL(ON);
|
||||
UART0_BD_FCTRL(ON);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
/* UART 1 */
|
||||
ACTCK_UART1_CCTRL(ON);
|
||||
SLPCK_UART1_CCTRL(ON);
|
||||
PinCtrl(UART1, PinmuxSelect, ON);
|
||||
UART1_FCTRL(ON);
|
||||
UART1_BD_FCTRL(ON);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
/* UART 1 */
|
||||
ACTCK_UART2_CCTRL(ON);
|
||||
SLPCK_UART2_CCTRL(ON);
|
||||
PinCtrl(UART2, PinmuxSelect, ON);
|
||||
UART2_FCTRL(ON);
|
||||
UART2_BD_FCTRL(ON);
|
||||
break;
|
||||
|
||||
default:
|
||||
DBG_UART_ERR("Invalid UART Index(%d)\n", UartIndex);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
/* Reset RX FIFO */
|
||||
HalRuartResetRxFifoRtl8195a(Data);
|
||||
DBG_UART_INFO(ANSI_COLOR_CYAN"HAL UART Init[UART %d]\n"ANSI_COLOR_RESET, UartIndex);
|
||||
|
||||
/* Disable all interrupts */
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_INTERRUPT_EN_REG_OFF, 0x00);
|
||||
|
||||
/* Set DLAB bit to 1 to access DLL/DLM */
|
||||
RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF);
|
||||
RegValue |= RUART_LINE_CTL_REG_DLAB_ENABLE;
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue);
|
||||
DBG_UART_INFO("[R] RUART_LINE_CTL_REG_OFF(0x0C) = %x\n", HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
|
||||
|
||||
/* Set Baudrate Division */
|
||||
#if 1
|
||||
ElementIndex = FindElementIndex_Patch(pHalRuartAdapter->BaudRate, (uint32_t*)BAUDRATE_PATCH, sizeof(BAUDRATE_PATCH)/sizeof(u32));
|
||||
if (ElementIndex < 0) {
|
||||
ElementIndex = 5;
|
||||
DBG_UART_ERR("Invalid BaudRate(%d), Force it as default(%d)\n", pHalRuartAdapter->BaudRate, BAUDRATE_PATCH[ElementIndex]);
|
||||
}
|
||||
|
||||
RuartSpeedSetting.BaudRate = BAUDRATE_PATCH[ElementIndex];
|
||||
RuartSpeedSetting.Ovsr = OVSR_PATCH[ElementIndex];
|
||||
RuartSpeedSetting.Div = DIV_PATCH[ElementIndex];
|
||||
RuartSpeedSetting.Ovsr_adj = OVSR_ADJ_PATCH[ElementIndex];
|
||||
#else
|
||||
RuartSpeedSetting.BaudRate = 38400;
|
||||
RuartSpeedSetting.Ovsr = 10;
|
||||
RuartSpeedSetting.Div = 217;
|
||||
RuartSpeedSetting.Ovsr_adj = 0x0;
|
||||
#endif
|
||||
|
||||
DBG_UART_INFO("Baud %d, Ovsr %d, Div %d, OvsrAdj 0x%X\n",
|
||||
RuartSpeedSetting.BaudRate,
|
||||
RuartSpeedSetting.Ovsr,
|
||||
RuartSpeedSetting.Div,
|
||||
RuartSpeedSetting.Ovsr_adj
|
||||
);
|
||||
/* Divisor = (SYSTEM_CLK / ((ovsr + 5 + ovsr_adj/11) * (UartAdapter.BaudRate))); */
|
||||
|
||||
/* Set Divisor */
|
||||
Divisor = RuartSpeedSetting.Div;
|
||||
|
||||
Dll = Divisor & 0xFF;
|
||||
Dlm = (Divisor & 0xFF00) >> 8;
|
||||
|
||||
// DBG_UART_INFO("Calculated Dll, Dlm = %02x, %02x\n", Dll, Dlm);
|
||||
// DBG_UART_INFO("---- Before setting baud rate ----\n");
|
||||
// DBG_UART_INFO(" [R] RUART_DLL_OFF(0x00) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLL_OFF));
|
||||
// DBG_UART_INFO(" [R] RUART_DLM_OFF(0x04) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLM_OFF));
|
||||
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_DLL_OFF, Dll);
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_DLM_OFF, Dlm);
|
||||
|
||||
// DBG_UART_INFO("---- After setting baud rate ----\n");
|
||||
// DBG_UART_INFO(" [R] RUART_DLL_OFF(0x00) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLL_OFF));
|
||||
// DBG_UART_INFO(" [R] RUART_DLM_OFF(0x04) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLM_OFF));
|
||||
|
||||
// DBG_UART_INFO(ANSI_COLOR_CYAN"---- Befor OVSR & OVSR_ADJ ----\n"ANSI_COLOR_RESET);
|
||||
// RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
|
||||
// DBG_UART_INFO("UART%d SPR(0x1C) = %X\n", UartIndex, RegValue);
|
||||
// RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF);
|
||||
// DBG_UART_INFO("UART%d SIS(0x20) = %X\n", UartIndex, RegValue);
|
||||
|
||||
/**
|
||||
* Clean Rx break signal interrupt status at initial stage.
|
||||
*/
|
||||
RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
|
||||
RegValue |= RUART_SP_REG_RXBREAK_INT_STATUS;
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_SCRATCH_PAD_REG_OFF, RegValue);
|
||||
|
||||
/* Set OVSR(xfactor) */
|
||||
RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF);
|
||||
RegValue &= ~(RUART_STS_REG_XFACTOR);
|
||||
RegValue |= (((RuartSpeedSetting.Ovsr - 5) << 4) & RUART_STS_REG_XFACTOR);
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_STS_REG_OFF, RegValue);
|
||||
|
||||
/* Set OVSR_ADJ[10:0] (xfactor_adj[26:16]) */
|
||||
RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
|
||||
RegValue &= ~(RUART_SP_REG_XFACTOR_ADJ);
|
||||
RegValue |= ((RuartSpeedSetting.Ovsr_adj << 16) & RUART_SP_REG_XFACTOR_ADJ);
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_SCRATCH_PAD_REG_OFF, RegValue);
|
||||
|
||||
// DBG_UART_INFO(ANSI_COLOR_CYAN"---- After OVSR & OVSR_ADJ ----\n"ANSI_COLOR_RESET);
|
||||
// RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
|
||||
// DBG_UART_INFO("UART%d SPR(0x1C) = %X\n", UartIndex, RegValue);
|
||||
// RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF);
|
||||
// DBG_UART_INFO("UART%d SIS(0x20) = %X\n", UartIndex, RegValue);
|
||||
|
||||
/* clear DLAB bit */
|
||||
RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF);
|
||||
RegValue &= ~(RUART_LINE_CTL_REG_DLAB_ENABLE);
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue);
|
||||
// DBG_UART_INFO("[R] RUART_LINE_CTL_REG_OFF(0x0C) = %x\n", HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
|
||||
// DBG_UART_INFO("[R] UART%d INT_EN(0x04) = %x\n", UartIndex, pHalRuartAdapter->Interrupts);
|
||||
RegValue = ((pHalRuartAdapter->Interrupts) & 0xFF);
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_INTERRUPT_EN_REG_OFF, RegValue);
|
||||
// DBG_UART_INFO("[W] UART%d INT_EN(0x04) = %x\n", UartIndex, RegValue);
|
||||
|
||||
/* Configure FlowControl */
|
||||
if (pHalRuartAdapter->FlowControl == AUTOFLOW_ENABLE) {
|
||||
RegValue = HAL_RUART_READ32(UartIndex, RUART_MODEM_CTL_REG_OFF);
|
||||
RegValue |= RUART_MCL_AUTOFLOW_ENABLE;
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_MODEM_CTL_REG_OFF, RegValue);
|
||||
}
|
||||
|
||||
/* RUART DMA Initialization */
|
||||
HalRuartDmaInitRtl8195a(pHalRuartAdapter);
|
||||
|
||||
DBG_UART_INFO("[R] UART%d LCR(0x%02X): %X\n", UartIndex, RUART_LINE_CTL_REG_OFF, HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
|
||||
RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF);
|
||||
|
||||
/* PARITY CONTROL */
|
||||
RegValue &= BIT_CLR_LCR_WLS;
|
||||
RegValue |= BIT_LCR_WLS(pHalRuartAdapter->WordLen);
|
||||
|
||||
RegValue &= BIT_INVC_LCR_STB_EN;
|
||||
RegValue |= BIT_LCR_STB_EN(pHalRuartAdapter->StopBit);
|
||||
|
||||
RegValue &= BIT_INVC_LCR_PARITY_EN;
|
||||
RegValue |= BIT_LCR_PARITY_EN(pHalRuartAdapter->Parity);
|
||||
|
||||
/* PARITY TYPE SELECT */
|
||||
RegValue &= BIT_INVC_LCR_PARITY_TYPE;
|
||||
RegValue |= BIT_LCR_PARITY_TYPE(pHalRuartAdapter->ParityType);
|
||||
|
||||
/* STICK PARITY CONTROL */
|
||||
RegValue &= BIT_INVC_LCR_STICK_PARITY_EN;
|
||||
RegValue |= BIT_LCR_STICK_PARITY_EN(pHalRuartAdapter->StickParity);
|
||||
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue);
|
||||
DBG_UART_INFO("[W] UART%d LCR(0x%02X): %X\n", UartIndex, RUART_LINE_CTL_REG_OFF, HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
|
||||
|
||||
/* Need to assert RTS during initial stage. */
|
||||
if (pHalRuartAdapter->FlowControl == AUTOFLOW_ENABLE) {
|
||||
HalRuartRTSCtrlRtl8195a(Data, 1);
|
||||
}
|
||||
pHalRuartAdapter->State = HAL_UART_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Reset RUART Tx FIFO.
|
||||
*
|
||||
* Reset RUART Receiver and Rx FIFO wrapper function.
|
||||
* It will check LINE_STATUS_REG until reset action completion.
|
||||
*
|
||||
* @return BOOL
|
||||
*/
|
||||
HAL_Status
|
||||
HalRuartResetTxFifoRtl8195a(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
)
|
||||
{
|
||||
PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data;
|
||||
u8 UartIndex = pHalRuartAdapter->UartIndex;
|
||||
u32 rx_trigger_lv;
|
||||
u32 RegValue;
|
||||
|
||||
// Backup the RX FIFO trigger Level setting
|
||||
rx_trigger_lv = HAL_RUART_READ32(UartIndex, RUART_FIFO_CTL_REG_OFF);
|
||||
rx_trigger_lv &= 0xC0; // only keep the bit[7:6]
|
||||
|
||||
/* Step 2: Enable clear_txfifo */
|
||||
RegValue = (FIFO_CTL_DEFAULT_WITH_FIFO_DMA | RUART_FIFO_CTL_REG_CLEAR_TXFIFO) & (~0xC0);
|
||||
RegValue |= rx_trigger_lv;
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_FIFO_CTL_REG_OFF, RegValue);
|
||||
|
||||
//TODO: Check Defautl Value
|
||||
RegValue = (FIFO_CTL_DEFAULT_WITH_FIFO_DMA & (~0xC0)) | rx_trigger_lv;
|
||||
HAL_RUART_WRITE32(UartIndex, RUART_FIFO_CTL_REG_OFF, RegValue);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue