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jeffrey 2015-11-17 10:30:14 +08:00
parent 48de61fed7
commit 28cd8da44d
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155
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_8195A_H_
#define _HAL_8195A_H_
#include "platform_autoconf.h"
#include "basic_types.h"
#include "section_config.h"
#include "rtl8195a_sys_on.h"
#include "rtl8195a_peri_on.h"
#include "hal_platform.h"
#include "hal_pinmux.h"
#include "hal_api.h"
#include "hal_peri_on.h"
#include "hal_misc.h"
#include "hal_irqn.h"
#include "hal_vector_table.h"
#include "hal_diag.h"
#include "hal_spi_flash.h"
#include "hal_timer.h"
#include "hal_util.h"
#include "hal_efuse.h"
#include "hal_soc_ps_monitor.h"
#include "diag.h"
#include "hal_common.h"
/* ----------------------------------------------------------------------------
-- Cortex M3 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
* @{
*/
#define __CM3_REV 0x0200 /**< Core revision r0p0 */
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 1 /**< Vendor specific implementation of SysTickConfig is defined */
#include "core_cm3.h"
#ifdef CONFIG_TIMER_EN
#include "hal_timer.h"
#endif
#ifdef CONFIG_GDMA_EN
#include "hal_gdma.h"
#include "rtl8195a_gdma.h"
#endif
#ifdef CONFIG_GPIO_EN
#include "hal_gpio.h"
#include "rtl8195a_gpio.h"
#endif
#ifdef CONFIG_SPI_COM_EN
#include "hal_ssi.h"
#include "rtl8195a_ssi.h"
#endif
#ifdef CONFIG_UART_EN
#include "hal_uart.h"
#include "rtl8195a_uart.h"
#endif
#ifdef CONFIG_I2C_EN
#include "hal_i2c.h"
#include "rtl8195a_i2c.h"
#endif
#ifdef CONFIG_PCM_EN
#include "hal_pcm.h"
#include "rtl8195a_pcm.h"
#endif
#ifdef CONFIG_PWM_EN
#include "hal_pwm.h"
#include "rtl8195a_pwm.h"
#endif
#ifdef CONFIG_I2S_EN
#include "hal_i2s.h"
#include "rtl8195a_i2s.h"
#endif
#ifdef CONFIG_DAC_EN
#include "hal_dac.h"
#include "rtl8195a_dac.h"
#endif
#ifdef CONFIG_ADC_EN
#include "hal_adc.h"
#include "rtl8195a_adc.h"
#endif
#ifdef CONFIG_SDR_EN
#endif
#ifdef CONFIG_SPIC_EN
#endif
#ifdef CONFIG_SDIO_DEVICE_EN
#include "hal_sdio.h"
#endif
#ifdef CONFIG_NFC_EN
#include "hal_nfc.h"
#include "rtl8195a_nfc.h"
#endif
#if CONFIG_WDG
#include "rtl8195a_wdt.h"
#endif
#ifdef CONFIG_USB_EN
#include "hal_usb.h"
#include "rtl8195a_usb.h"
#endif
// firmware information, located at the header of Image2
#define FW_VERSION (0x0100)
#define FW_SUBVERSION (0x0001)
#define FW_CHIP_ID (0x8195)
#define FW_CHIP_VER (0x01)
#define FW_BUS_TYPE (0x01) // the iNIC firmware type: USB/SDIO
#define FW_INFO_RSV1 (0x00) // the firmware information reserved
#define FW_INFO_RSV2 (0x00) // the firmware information reserved
#define FW_INFO_RSV3 (0x00) // the firmware information reserved
#define FW_INFO_RSV4 (0x00) // the firmware information reserved
#define FLASH_RESERVED_DATA_BASE 0x8000 // reserve 32K for Image1
#define FLASH_SYSTEM_DATA_ADDR 0x9000 // reserve 32K+4K for Image1 + Reserved data
// Flash Map for Calibration data
#define FLASH_CAL_DATA_BASE 0xA000
#define FLASH_CAL_DATA_ADDR(_offset) (FLASH_CAL_DATA_BASE + _offset)
#define FLASH_CAL_DATA_SIZE 0x1000
#define FLASH_SECTOR_SIZE 0x1000
// SPIC Calibration Data
#define FLASH_SPIC_PARA_OFFSET 0x80
#define FLASH_SPIC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET)
// SDRC Calibration Data
#define FLASH_SDRC_PARA_OFFSET 0x180
#define FLASH_SDRC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET)
// ADC Calibration Data
#define FLASH_ADC_PARA_OFFSET 0x200
#define FLASH_ADC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET)
#endif //_HAL_8195A_H_

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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_adc.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_ADC_H_
#define _RTL8195A_ADC_H_
//================ Register Bit Field ==========================
//2 REG_ADC_FIFO_READ
#define BIT_SHIFT_ADC_FIFO_RO 0
#define BIT_MASK_ADC_FIFO_RO 0xffffffffL
#define BIT_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
#define BIT_CTRL_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
#define BIT_GET_ADC_FIFO_RO(x) (((x) >> BIT_SHIFT_ADC_FIFO_RO) & BIT_MASK_ADC_FIFO_RO)
//2 REG_ADC_CONTROL
#define BIT_SHIFT_ADC_DBG_SEL 24
#define BIT_MASK_ADC_DBG_SEL 0x7
#define BIT_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
#define BIT_CTRL_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
#define BIT_GET_ADC_DBG_SEL(x) (((x) >> BIT_SHIFT_ADC_DBG_SEL) & BIT_MASK_ADC_DBG_SEL)
#define BIT_SHIFT_ADC_THRESHOLD 16
#define BIT_MASK_ADC_THRESHOLD 0x3f
#define BIT_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
#define BIT_CTRL_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
#define BIT_GET_ADC_THRESHOLD(x) (((x) >> BIT_SHIFT_ADC_THRESHOLD) & BIT_MASK_ADC_THRESHOLD)
#define BIT_SHIFT_ADC_BURST_SIZE 8
#define BIT_MASK_ADC_BURST_SIZE 0x1f
#define BIT_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
#define BIT_CTRL_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
#define BIT_GET_ADC_BURST_SIZE(x) (((x) >> BIT_SHIFT_ADC_BURST_SIZE) & BIT_MASK_ADC_BURST_SIZE)
#define BIT_ADC_ENDIAN BIT(3)
#define BIT_SHIFT_ADC_ENDIAN 3
#define BIT_MASK_ADC_ENDIAN 0x1
#define BIT_CTRL_ADC_ENDIAN(x) (((x) & BIT_MASK_ADC_ENDIAN) << BIT_SHIFT_ADC_ENDIAN)
#define BIT_ADC_OVERWRITE BIT(2)
#define BIT_SHIFT_ADC_OVERWRITE 2
#define BIT_MASK_ADC_OVERWRITE 0x1
#define BIT_CTRL_ADC_OVERWRITE(x) (((x) & BIT_MASK_ADC_OVERWRITE) << BIT_SHIFT_ADC_OVERWRITE)
#define BIT_ADC_ONESHOT BIT(1)
#define BIT_SHIFT_ADC_ONESHOT 1
#define BIT_MASK_ADC_ONESHOT 0x1
#define BIT_CTRL_ADC_ONESHOT(x) (((x) & BIT_MASK_ADC_ONESHOT) << BIT_SHIFT_ADC_ONESHOT)
#define BIT_ADC_COMP_ONLY BIT(0)
#define BIT_SHIFT_ADC_COMP_ONLY 0
#define BIT_MASK_ADC_COMP_ONLY 0x1
#define BIT_CTRL_ADC_COMP_ONLY(x) (((x) & BIT_MASK_ADC_COMP_ONLY) << BIT_SHIFT_ADC_COMP_ONLY)
//2 REG_ADC_INTR_EN
#define BIT_ADC_AWAKE_CPU_EN BIT(7)
#define BIT_SHIFT_ADC_AWAKE_CPU_EN 7
#define BIT_MASK_ADC_AWAKE_CPU_EN 0x1
#define BIT_CTRL_ADC_AWAKE_CPU_EN(x) (((x) & BIT_MASK_ADC_AWAKE_CPU_EN) << BIT_SHIFT_ADC_AWAKE_CPU_EN)
#define BIT_ADC_FIFO_RD_ERROR_EN BIT(6)
#define BIT_SHIFT_ADC_FIFO_RD_ERROR_EN 6
#define BIT_MASK_ADC_FIFO_RD_ERROR_EN 0x1
#define BIT_CTRL_ADC_FIFO_RD_ERROR_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_EN) << BIT_SHIFT_ADC_FIFO_RD_ERROR_EN)
#define BIT_ADC_FIFO_RD_REQ_EN BIT(5)
#define BIT_SHIFT_ADC_FIFO_RD_REQ_EN 5
#define BIT_MASK_ADC_FIFO_RD_REQ_EN 0x1
#define BIT_CTRL_ADC_FIFO_RD_REQ_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_EN) << BIT_SHIFT_ADC_FIFO_RD_REQ_EN)
#define BIT_ADC_FIFO_FULL_EN BIT(4)
#define BIT_SHIFT_ADC_FIFO_FULL_EN 4
#define BIT_MASK_ADC_FIFO_FULL_EN 0x1
#define BIT_CTRL_ADC_FIFO_FULL_EN(x) (((x) & BIT_MASK_ADC_FIFO_FULL_EN) << BIT_SHIFT_ADC_FIFO_FULL_EN)
#define BIT_ADC_COMP_3_EN BIT(3)
#define BIT_SHIFT_ADC_COMP_3_EN 3
#define BIT_MASK_ADC_COMP_3_EN 0x1
#define BIT_CTRL_ADC_COMP_3_EN(x) (((x) & BIT_MASK_ADC_COMP_3_EN) << BIT_SHIFT_ADC_COMP_3_EN)
#define BIT_ADC_COMP_2_EN BIT(2)
#define BIT_SHIFT_ADC_COMP_2_EN 2
#define BIT_MASK_ADC_COMP_2_EN 0x1
#define BIT_CTRL_ADC_COMP_2_EN(x) (((x) & BIT_MASK_ADC_COMP_2_EN) << BIT_SHIFT_ADC_COMP_2_EN)
#define BIT_ADC_COMP_1_EN BIT(1)
#define BIT_SHIFT_ADC_COMP_1_EN 1
#define BIT_MASK_ADC_COMP_1_EN 0x1
#define BIT_CTRL_ADC_COMP_1_EN(x) (((x) & BIT_MASK_ADC_COMP_1_EN) << BIT_SHIFT_ADC_COMP_1_EN)
#define BIT_ADC_COMP_0_EN BIT(0)
#define BIT_SHIFT_ADC_COMP_0_EN 0
#define BIT_MASK_ADC_COMP_0_EN 0x1
#define BIT_CTRL_ADC_COMP_0_EN(x) (((x) & BIT_MASK_ADC_COMP_0_EN) << BIT_SHIFT_ADC_COMP_0_EN)
//2 REG_ADC_INTR_STS
#define BIT_ADC_FIFO_THRESHOLD BIT(7)
#define BIT_SHIFT_ADC_FIFO_THRESHOLD 7
#define BIT_MASK_ADC_FIFO_THRESHOLD 0x1
#define BIT_CTRL_ADC_FIFO_THRESHOLD(x) (((x) & BIT_MASK_ADC_FIFO_THRESHOLD) << BIT_SHIFT_ADC_FIFO_THRESHOLD)
#define BIT_ADC_FIFO_RD_ERROR_ST BIT(6)
#define BIT_SHIFT_ADC_FIFO_RD_ERROR_ST 6
#define BIT_MASK_ADC_FIFO_RD_ERROR_ST 0x1
#define BIT_CTRL_ADC_FIFO_RD_ERROR_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_ST) << BIT_SHIFT_ADC_FIFO_RD_ERROR_ST)
#define BIT_ADC_FIFO_RD_REQ_ST BIT(5)
#define BIT_SHIFT_ADC_FIFO_RD_REQ_ST 5
#define BIT_MASK_ADC_FIFO_RD_REQ_ST 0x1
#define BIT_CTRL_ADC_FIFO_RD_REQ_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_ST) << BIT_SHIFT_ADC_FIFO_RD_REQ_ST)
#define BIT_ADC_FIFO_FULL_ST BIT(4)
#define BIT_SHIFT_ADC_FIFO_FULL_ST 4
#define BIT_MASK_ADC_FIFO_FULL_ST 0x1
#define BIT_CTRL_ADC_FIFO_FULL_ST(x) (((x) & BIT_MASK_ADC_FIFO_FULL_ST) << BIT_SHIFT_ADC_FIFO_FULL_ST)
#define BIT_ADC_COMP_3_ST BIT(3)
#define BIT_SHIFT_ADC_COMP_3_ST 3
#define BIT_MASK_ADC_COMP_3_ST 0x1
#define BIT_CTRL_ADC_COMP_3_ST(x) (((x) & BIT_MASK_ADC_COMP_3_ST) << BIT_SHIFT_ADC_COMP_3_ST)
#define BIT_ADC_COMP_2_ST BIT(2)
#define BIT_SHIFT_ADC_COMP_2_ST 2
#define BIT_MASK_ADC_COMP_2_ST 0x1
#define BIT_CTRL_ADC_COMP_2_ST(x) (((x) & BIT_MASK_ADC_COMP_2_ST) << BIT_SHIFT_ADC_COMP_2_ST)
#define BIT_ADC_COMP_1_ST BIT(1)
#define BIT_SHIFT_ADC_COMP_1_ST 1
#define BIT_MASK_ADC_COMP_1_ST 0x1
#define BIT_CTRL_ADC_COMP_1_ST(x) (((x) & BIT_MASK_ADC_COMP_1_ST) << BIT_SHIFT_ADC_COMP_1_ST)
#define BIT_ADC_COMP_0_ST BIT(0)
#define BIT_SHIFT_ADC_COMP_0_ST 0
#define BIT_MASK_ADC_COMP_0_ST 0x1
#define BIT_CTRL_ADC_COMP_0_ST(x) (((x) & BIT_MASK_ADC_COMP_0_ST) << BIT_SHIFT_ADC_COMP_0_ST)
//2 REG_ADC_COMP_VALUE_L
#define BIT_SHIFT_ADC_COMP_TH_1 16
#define BIT_MASK_ADC_COMP_TH_1 0xffff
#define BIT_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
#define BIT_CTRL_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
#define BIT_GET_ADC_COMP_TH_1(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_1) & BIT_MASK_ADC_COMP_TH_1)
#define BIT_SHIFT_ADC_COMP_TH_0 0
#define BIT_MASK_ADC_COMP_TH_0 0xffff
#define BIT_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
#define BIT_CTRL_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
#define BIT_GET_ADC_COMP_TH_0(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_0) & BIT_MASK_ADC_COMP_TH_0)
//2 REG_ADC_COMP_VALUE_H
#define BIT_SHIFT_ADC_COMP_TH_3 16
#define BIT_MASK_ADC_COMP_TH_3 0xffff
#define BIT_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
#define BIT_CTRL_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
#define BIT_GET_ADC_COMP_TH_3(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_3) & BIT_MASK_ADC_COMP_TH_3)
#define BIT_SHIFT_ADC_COMP_TH_2 0
#define BIT_MASK_ADC_COMP_TH_2 0xffff
#define BIT_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
#define BIT_CTRL_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
#define BIT_GET_ADC_COMP_TH_2(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_2) & BIT_MASK_ADC_COMP_TH_2)
//2 REG_ADC_COMP_SET
#define BIT_SHIFT_ADC_GREATER_THAN 0
#define BIT_MASK_ADC_GREATER_THAN 0xf
#define BIT_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
#define BIT_CTRL_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
#define BIT_GET_ADC_GREATER_THAN(x) (((x) >> BIT_SHIFT_ADC_GREATER_THAN) & BIT_MASK_ADC_GREATER_THAN)
//2 REG_ADC_POWER
#define BIT_SHIFT_ADC_PWR_CUT_CNTR 16
#define BIT_MASK_ADC_PWR_CUT_CNTR 0xff
#define BIT_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
#define BIT_CTRL_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
#define BIT_GET_ADC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_ADC_PWR_CUT_CNTR) & BIT_MASK_ADC_PWR_CUT_CNTR)
#define BIT_ADC_FIFO_ON_ST BIT(11)
#define BIT_SHIFT_ADC_FIFO_ON_ST 11
#define BIT_MASK_ADC_FIFO_ON_ST 0x1
#define BIT_CTRL_ADC_FIFO_ON_ST(x) (((x) & BIT_MASK_ADC_FIFO_ON_ST) << BIT_SHIFT_ADC_FIFO_ON_ST)
#define BIT_ADC_ISO_ON_ST BIT(10)
#define BIT_SHIFT_ADC_ISO_ON_ST 10
#define BIT_MASK_ADC_ISO_ON_ST 0x1
#define BIT_CTRL_ADC_ISO_ON_ST(x) (((x) & BIT_MASK_ADC_ISO_ON_ST) << BIT_SHIFT_ADC_ISO_ON_ST)
#define BIT_ADC_PWR33_ON_ST BIT(9)
#define BIT_SHIFT_ADC_PWR33_ON_ST 9
#define BIT_MASK_ADC_PWR33_ON_ST 0x1
#define BIT_CTRL_ADC_PWR33_ON_ST(x) (((x) & BIT_MASK_ADC_PWR33_ON_ST) << BIT_SHIFT_ADC_PWR33_ON_ST)
#define BIT_ADC_PWR12_ON_ST BIT(8)
#define BIT_SHIFT_ADC_PWR12_ON_ST 8
#define BIT_MASK_ADC_PWR12_ON_ST 0x1
#define BIT_CTRL_ADC_PWR12_ON_ST(x) (((x) & BIT_MASK_ADC_PWR12_ON_ST) << BIT_SHIFT_ADC_PWR12_ON_ST)
#define BIT_ADC_ISO_MANUAL BIT(3)
#define BIT_SHIFT_ADC_ISO_MANUAL 3
#define BIT_MASK_ADC_ISO_MANUAL 0x1
#define BIT_CTRL_ADC_ISO_MANUAL(x) (((x) & BIT_MASK_ADC_ISO_MANUAL) << BIT_SHIFT_ADC_ISO_MANUAL)
#define BIT_ADC_PWR33_MANUAL BIT(2)
#define BIT_SHIFT_ADC_PWR33_MANUAL 2
#define BIT_MASK_ADC_PWR33_MANUAL 0x1
#define BIT_CTRL_ADC_PWR33_MANUAL(x) (((x) & BIT_MASK_ADC_PWR33_MANUAL) << BIT_SHIFT_ADC_PWR33_MANUAL)
#define BIT_ADC_PWR12_MANUAL BIT(1)
#define BIT_SHIFT_ADC_PWR12_MANUAL 1
#define BIT_MASK_ADC_PWR12_MANUAL 0x1
#define BIT_CTRL_ADC_PWR12_MANUAL(x) (((x) & BIT_MASK_ADC_PWR12_MANUAL) << BIT_SHIFT_ADC_PWR12_MANUAL)
#define BIT_ADC_PWR_AUTO BIT(0)
#define BIT_SHIFT_ADC_PWR_AUTO 0
#define BIT_MASK_ADC_PWR_AUTO 0x1
#define BIT_CTRL_ADC_PWR_AUTO(x) (((x) & BIT_MASK_ADC_PWR_AUTO) << BIT_SHIFT_ADC_PWR_AUTO)
//2 REG_ADC_ANAPAR_AD0
#define BIT_SHIFT_ADC_ANAPAR_AD0 2
#define BIT_MASK_ADC_ANAPAR_AD0 0x3fffffff
#define BIT_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
#define BIT_CTRL_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
#define BIT_GET_ADC_ANAPAR_AD0(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD0) & BIT_MASK_ADC_ANAPAR_AD0)
#define BIT_ADC_AUDIO_EN BIT(1)
#define BIT_SHIFT_ADC_AUDIO_EN 1
#define BIT_MASK_ADC_AUDIO_EN 0x1
#define BIT_CTRL_ADC_AUDIO_EN(x) (((x) & BIT_MASK_ADC_AUDIO_EN) << BIT_SHIFT_ADC_AUDIO_EN)
#define BIT_ADC_EN_MANUAL BIT(0)
#define BIT_SHIFT_ADC_EN_MANUAL 0
#define BIT_MASK_ADC_EN_MANUAL 0x1
#define BIT_CTRL_ADC_EN_MANUAL(x) (((x) & BIT_MASK_ADC_EN_MANUAL) << BIT_SHIFT_ADC_EN_MANUAL)
//2 REG_ADC_ANAPAR_AD1
#define BIT_SHIFT_ADC_ANAPAR_AD1 0
#define BIT_MASK_ADC_ANAPAR_AD1 0xffffffffL
#define BIT_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
#define BIT_CTRL_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
#define BIT_GET_ADC_ANAPAR_AD1(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD1) & BIT_MASK_ADC_ANAPAR_AD1)
//2 REG_ADC_ANAPAR_AD2
#define BIT_SHIFT_ADC_ANAPAR_AD2 0
#define BIT_MASK_ADC_ANAPAR_AD2 0xffffffffL
#define BIT_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
#define BIT_CTRL_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
#define BIT_GET_ADC_ANAPAR_AD2(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD2) & BIT_MASK_ADC_ANAPAR_AD2)
//2 REG_ADC_ANAPAR_AD3
#define BIT_SHIFT_ADC_ANAPAR_AD3 0
#define BIT_MASK_ADC_ANAPAR_AD3 0xffffffffL
#define BIT_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
#define BIT_CTRL_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
#define BIT_GET_ADC_ANAPAR_AD3(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD3) & BIT_MASK_ADC_ANAPAR_AD3)
//2 REG_ADC_ANAPAR_AD4
#define BIT_SHIFT_ADC_ANAPAR_AD4 0
#define BIT_MASK_ADC_ANAPAR_AD4 0xffffffffL
#define BIT_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
#define BIT_CTRL_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
#define BIT_GET_ADC_ANAPAR_AD4(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD4) & BIT_MASK_ADC_ANAPAR_AD4)
//2 REG_ADC_ANAPAR_AD5
#define BIT_SHIFT_ADC_ANAPAR_AD5 0
#define BIT_MASK_ADC_ANAPAR_AD5 0xffffffffL
#define BIT_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
#define BIT_CTRL_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
#define BIT_GET_ADC_ANAPAR_AD5(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD5) & BIT_MASK_ADC_ANAPAR_AD5)
//2 REG_ADC_CALI_DATA
#define BIT_SHIFT_ADC_CALI_DATA_6 16
#define BIT_MASK_ADC_CALI_DATA_6 0xffff
#define BIT_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
#define BIT_CTRL_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
#define BIT_GET_ADC_CALI_DATA_6(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_6) & BIT_MASK_ADC_CALI_DATA_6)
#define BIT_SHIFT_ADC_CALI_DATA_0 0
#define BIT_MASK_ADC_CALI_DATA_0 0xffff
#define BIT_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
#define BIT_CTRL_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
#define BIT_GET_ADC_CALI_DATA_0(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_0) & BIT_MASK_ADC_CALI_DATA_0)
//================ Register Reg Field =========================
#define REG_ADC_FIFO_READ 0x0000
#define REG_ADC_CONTROL 0x0004
#define REG_ADC_INTR_EN 0x0008
#define REG_ADC_INTR_STS 0x000C
#define REG_ADC_COMP_VALUE_L 0x0010
#define REG_ADC_COMP_VALUE_H 0x0014
#define REG_ADC_COMP_SET 0x0018
#define REG_ADC_POWER 0x001C
#define REG_ADC_ANAPAR_AD0 0x0020
#define REG_ADC_ANAPAR_AD1 0x0024
#define REG_ADC_ANAPAR_AD2 0x0028
#define REG_ADC_ANAPAR_AD3 0x002C
#define REG_ADC_ANAPAR_AD4 0x0030
#define REG_ADC_ANAPAR_AD5 0x0034
#define REG_ADC_CALI_DATA 0x0038
//================ ADC HAL related enumeration ==================
//================ ADC Function Prototypes =====================
#define HAL_ADC_WRITE32(addr, value) HAL_WRITE32(ADC_REG_BASE,addr,value)
#define HAL_ADC_READ32(addr) HAL_READ32(ADC_REG_BASE,addr)
RTK_STATUS HalADCInit8195a(IN VOID *Data);
RTK_STATUS HalADCDeInit8195a(IN VOID *Data);
RTK_STATUS HalADCEnableRtl8195a(IN VOID *Data);
RTK_STATUS HalADCIntrCtrl8195a(IN VOID *Data);
u32 HalADCReceiveRtl8195a(IN VOID *Data);
u32 HalADCReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg);
#endif

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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_dac.h Normal file
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#ifndef _RTL8195A_DAC_H_
#define _RTL8195A_DAC_H_
//================ Register Bit Field ==========================
//2 REG_DAC0_FIFO_WR
#define BIT_SHIFT_DAC0_FIFO_WO 0
#define BIT_MASK_DAC0_FIFO_WO 0xffffffffL
#define BIT_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
#define BIT_CTRL_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
#define BIT_GET_DAC0_FIFO_WO(x) (((x) >> BIT_SHIFT_DAC0_FIFO_WO) & BIT_MASK_DAC0_FIFO_WO)
//2 REG_DAC_CTRL
#define BIT_SHIFT_DAC_DELTA_SIGMA 25
#define BIT_MASK_DAC_DELTA_SIGMA 0x7
#define BIT_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
#define BIT_CTRL_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
#define BIT_GET_DAC_DELTA_SIGMA(x) (((x) >> BIT_SHIFT_DAC_DELTA_SIGMA) & BIT_MASK_DAC_DELTA_SIGMA)
#define BIT_DAC_BYPASS_DSC BIT(24)
#define BIT_SHIFT_DAC_BYPASS_DSC 24
#define BIT_MASK_DAC_BYPASS_DSC 0x1
#define BIT_CTRL_DAC_BYPASS_DSC(x) (((x) & BIT_MASK_DAC_BYPASS_DSC) << BIT_SHIFT_DAC_BYPASS_DSC)
#define BIT_SHIFT_DAC_DSC_DBG_SEL 19
#define BIT_MASK_DAC_DSC_DBG_SEL 0x3
#define BIT_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
#define BIT_CTRL_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
#define BIT_GET_DAC_DSC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DSC_DBG_SEL) & BIT_MASK_DAC_DSC_DBG_SEL)
#define BIT_SHIFT_DAC_DBG_SEL 16
#define BIT_MASK_DAC_DBG_SEL 0x7
#define BIT_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
#define BIT_CTRL_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
#define BIT_GET_DAC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DBG_SEL) & BIT_MASK_DAC_DBG_SEL)
#define BIT_SHIFT_DAC_BURST_SIZE 8
#define BIT_MASK_DAC_BURST_SIZE 0xf
#define BIT_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
#define BIT_CTRL_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
#define BIT_GET_DAC_BURST_SIZE(x) (((x) >> BIT_SHIFT_DAC_BURST_SIZE) & BIT_MASK_DAC_BURST_SIZE)
#define BIT_DAC_FILTER_SETTLE BIT(4)
#define BIT_SHIFT_DAC_FILTER_SETTLE 4
#define BIT_MASK_DAC_FILTER_SETTLE 0x1
#define BIT_CTRL_DAC_FILTER_SETTLE(x) (((x) & BIT_MASK_DAC_FILTER_SETTLE) << BIT_SHIFT_DAC_FILTER_SETTLE)
#define BIT_DAC_OV_OPTION BIT(3)
#define BIT_SHIFT_DAC_OV_OPTION 3
#define BIT_MASK_DAC_OV_OPTION 0x1
#define BIT_CTRL_DAC_OV_OPTION(x) (((x) & BIT_MASK_DAC_OV_OPTION) << BIT_SHIFT_DAC_OV_OPTION)
#define BIT_DAC_ENDIAN BIT(2)
#define BIT_SHIFT_DAC_ENDIAN 2
#define BIT_MASK_DAC_ENDIAN 0x1
#define BIT_CTRL_DAC_ENDIAN(x) (((x) & BIT_MASK_DAC_ENDIAN) << BIT_SHIFT_DAC_ENDIAN)
#define BIT_DAC_SPEED BIT(1)
#define BIT_SHIFT_DAC_SPEED 1
#define BIT_MASK_DAC_SPEED 0x1
#define BIT_CTRL_DAC_SPEED(x) (((x) & BIT_MASK_DAC_SPEED) << BIT_SHIFT_DAC_SPEED)
#define BIT_DAC_FIFO_EN BIT(0)
#define BIT_SHIFT_DAC_FIFO_EN 0
#define BIT_MASK_DAC_FIFO_EN 0x1
#define BIT_CTRL_DAC_FIFO_EN(x) (((x) & BIT_MASK_DAC_FIFO_EN) << BIT_SHIFT_DAC_FIFO_EN)
//2 REG_DAC_INTR_CTRL
#define BIT_DAC_DSC_OVERFLOW1_EN BIT(6)
#define BIT_SHIFT_DAC_DSC_OVERFLOW1_EN 6
#define BIT_MASK_DAC_DSC_OVERFLOW1_EN 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW1_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW1_EN)
#define BIT_DAC_DSC_OVERFLOW0_EN BIT(5)
#define BIT_SHIFT_DAC_DSC_OVERFLOW0_EN 5
#define BIT_MASK_DAC_DSC_OVERFLOW0_EN 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW0_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW0_EN)
#define BIT_DAC__WRITE_ERROR_EN BIT(4)
#define BIT_SHIFT_DAC__WRITE_ERROR_EN 4
#define BIT_MASK_DAC__WRITE_ERROR_EN 0x1
#define BIT_CTRL_DAC__WRITE_ERROR_EN(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_EN) << BIT_SHIFT_DAC__WRITE_ERROR_EN)
#define BIT_DAC_FIFO_STOP_EN BIT(3)
#define BIT_SHIFT_DAC_FIFO_STOP_EN 3
#define BIT_MASK_DAC_FIFO_STOP_EN 0x1
#define BIT_CTRL_DAC_FIFO_STOP_EN(x) (((x) & BIT_MASK_DAC_FIFO_STOP_EN) << BIT_SHIFT_DAC_FIFO_STOP_EN)
#define BIT_DAC_FIFO_OVERFLOW_EN BIT(2)
#define BIT_SHIFT_DAC_FIFO_OVERFLOW_EN 2
#define BIT_MASK_DAC_FIFO_OVERFLOW_EN 0x1
#define BIT_CTRL_DAC_FIFO_OVERFLOW_EN(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_EN) << BIT_SHIFT_DAC_FIFO_OVERFLOW_EN)
#define BIT_DAC_FIFO_WR_REQ_EN BIT(1)
#define BIT_SHIFT_DAC_FIFO_WR_REQ_EN 1
#define BIT_MASK_DAC_FIFO_WR_REQ_EN 0x1
#define BIT_CTRL_DAC_FIFO_WR_REQ_EN(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_EN) << BIT_SHIFT_DAC_FIFO_WR_REQ_EN)
#define BIT_DAC_FIFO_FULL_EN BIT(0)
#define BIT_SHIFT_DAC_FIFO_FULL_EN 0
#define BIT_MASK_DAC_FIFO_FULL_EN 0x1
#define BIT_CTRL_DAC_FIFO_FULL_EN(x) (((x) & BIT_MASK_DAC_FIFO_FULL_EN) << BIT_SHIFT_DAC_FIFO_FULL_EN)
//2 REG_DAC_INTR_STS
#define BIT_DAC_DSC_OVERFLOW1_ST BIT(6)
#define BIT_SHIFT_DAC_DSC_OVERFLOW1_ST 6
#define BIT_MASK_DAC_DSC_OVERFLOW1_ST 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW1_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW1_ST)
#define BIT_DAC_DSC_OVERFLOW0_ST BIT(5)
#define BIT_SHIFT_DAC_DSC_OVERFLOW0_ST 5
#define BIT_MASK_DAC_DSC_OVERFLOW0_ST 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW0_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW0_ST)
#define BIT_DAC__WRITE_ERROR_ST BIT(4)
#define BIT_SHIFT_DAC__WRITE_ERROR_ST 4
#define BIT_MASK_DAC__WRITE_ERROR_ST 0x1
#define BIT_CTRL_DAC__WRITE_ERROR_ST(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_ST) << BIT_SHIFT_DAC__WRITE_ERROR_ST)
#define BIT_DAC_FIFO_STOP_ST BIT(3)
#define BIT_SHIFT_DAC_FIFO_STOP_ST 3
#define BIT_MASK_DAC_FIFO_STOP_ST 0x1
#define BIT_CTRL_DAC_FIFO_STOP_ST(x) (((x) & BIT_MASK_DAC_FIFO_STOP_ST) << BIT_SHIFT_DAC_FIFO_STOP_ST)
#define BIT_DAC_FIFO_OVERFLOW_ST BIT(2)
#define BIT_SHIFT_DAC_FIFO_OVERFLOW_ST 2
#define BIT_MASK_DAC_FIFO_OVERFLOW_ST 0x1
#define BIT_CTRL_DAC_FIFO_OVERFLOW_ST(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_ST) << BIT_SHIFT_DAC_FIFO_OVERFLOW_ST)
#define BIT_DAC_FIFO_WR_REQ_ST BIT(1)
#define BIT_SHIFT_DAC_FIFO_WR_REQ_ST 1
#define BIT_MASK_DAC_FIFO_WR_REQ_ST 0x1
#define BIT_CTRL_DAC_FIFO_WR_REQ_ST(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_ST) << BIT_SHIFT_DAC_FIFO_WR_REQ_ST)
#define BIT_DAC_FIFO_FULL_ST BIT(0)
#define BIT_SHIFT_DAC_FIFO_FULL_ST 0
#define BIT_MASK_DAC_FIFO_FULL_ST 0x1
#define BIT_CTRL_DAC_FIFO_FULL_ST(x) (((x) & BIT_MASK_DAC_FIFO_FULL_ST) << BIT_SHIFT_DAC_FIFO_FULL_ST)
//2 REG_DAC_PWR_CTRL
#define BIT_SHIFT_DAC_PWR_CUT_CNTR 16
#define BIT_MASK_DAC_PWR_CUT_CNTR 0xff
#define BIT_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
#define BIT_CTRL_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
#define BIT_GET_DAC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_DAC_PWR_CUT_CNTR) & BIT_MASK_DAC_PWR_CUT_CNTR)
#define BIT_ST_DAC_FIFO_ON BIT(11)
#define BIT_SHIFT_ST_DAC_FIFO_ON 11
#define BIT_MASK_ST_DAC_FIFO_ON 0x1
#define BIT_CTRL_ST_DAC_FIFO_ON(x) (((x) & BIT_MASK_ST_DAC_FIFO_ON) << BIT_SHIFT_ST_DAC_FIFO_ON)
#define BIT_ST_DAC_ISO_ON BIT(10)
#define BIT_SHIFT_ST_DAC_ISO_ON 10
#define BIT_MASK_ST_DAC_ISO_ON 0x1
#define BIT_CTRL_ST_DAC_ISO_ON(x) (((x) & BIT_MASK_ST_DAC_ISO_ON) << BIT_SHIFT_ST_DAC_ISO_ON)
#define BIT_ST_DAC_PWR33_ON BIT(9)
#define BIT_SHIFT_ST_DAC_PWR33_ON 9
#define BIT_MASK_ST_DAC_PWR33_ON 0x1
#define BIT_CTRL_ST_DAC_PWR33_ON(x) (((x) & BIT_MASK_ST_DAC_PWR33_ON) << BIT_SHIFT_ST_DAC_PWR33_ON)
#define BIT_ST_DAC_PWR12_ON BIT(8)
#define BIT_SHIFT_ST_DAC_PWR12_ON 8
#define BIT_MASK_ST_DAC_PWR12_ON 0x1
#define BIT_CTRL_ST_DAC_PWR12_ON(x) (((x) & BIT_MASK_ST_DAC_PWR12_ON) << BIT_SHIFT_ST_DAC_PWR12_ON)
#define BIT_DAC_ISO_MANU BIT(3)
#define BIT_SHIFT_DAC_ISO_MANU 3
#define BIT_MASK_DAC_ISO_MANU 0x1
#define BIT_CTRL_DAC_ISO_MANU(x) (((x) & BIT_MASK_DAC_ISO_MANU) << BIT_SHIFT_DAC_ISO_MANU)
#define BIT_DAC_PWR33_MANU BIT(2)
#define BIT_SHIFT_DAC_PWR33_MANU 2
#define BIT_MASK_DAC_PWR33_MANU 0x1
#define BIT_CTRL_DAC_PWR33_MANU(x) (((x) & BIT_MASK_DAC_PWR33_MANU) << BIT_SHIFT_DAC_PWR33_MANU)
#define BIT_DAC_PWR12_MANU BIT(1)
#define BIT_SHIFT_DAC_PWR12_MANU 1
#define BIT_MASK_DAC_PWR12_MANU 0x1
#define BIT_CTRL_DAC_PWR12_MANU(x) (((x) & BIT_MASK_DAC_PWR12_MANU) << BIT_SHIFT_DAC_PWR12_MANU)
#define BIT_DAC_PWR_AUTO BIT(0)
#define BIT_SHIFT_DAC_PWR_AUTO 0
#define BIT_MASK_DAC_PWR_AUTO 0x1
#define BIT_CTRL_DAC_PWR_AUTO(x) (((x) & BIT_MASK_DAC_PWR_AUTO) << BIT_SHIFT_DAC_PWR_AUTO)
//2 REG_DAC_ANAPAR_DA0
#define BIT_SHIFT_PWR_ALL_CNTR 12
#define BIT_MASK_PWR_ALL_CNTR 0xfffff
#define BIT_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
#define BIT_CTRL_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
#define BIT_GET_PWR_ALL_CNTR(x) (((x) >> BIT_SHIFT_PWR_ALL_CNTR) & BIT_MASK_PWR_ALL_CNTR)
#define BIT_SHIFT_PWR_FUP_CNTR 0
#define BIT_MASK_PWR_FUP_CNTR 0xfff
#define BIT_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
#define BIT_CTRL_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
#define BIT_GET_PWR_FUP_CNTR(x) (((x) >> BIT_SHIFT_PWR_FUP_CNTR) & BIT_MASK_PWR_FUP_CNTR)
//2 REG_DAC_ANAPAR_DA1
#define BIT_FUP_EN BIT(31)
#define BIT_SHIFT_FUP_EN 31
#define BIT_MASK_FUP_EN 0x1
#define BIT_CTRL_FUP_EN(x) (((x) & BIT_MASK_FUP_EN) << BIT_SHIFT_FUP_EN)
#define BIT_SHIFT_ANAPAR_DA 8
#define BIT_MASK_ANAPAR_DA 0x7fffff
#define BIT_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
#define BIT_CTRL_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
#define BIT_GET_ANAPAR_DA(x) (((x) >> BIT_SHIFT_ANAPAR_DA) & BIT_MASK_ANAPAR_DA)
#define BIT_D_POW_DACVREF BIT(7)
#define BIT_SHIFT_D_POW_DACVREF 7
#define BIT_MASK_D_POW_DACVREF 0x1
#define BIT_CTRL_D_POW_DACVREF(x) (((x) & BIT_MASK_D_POW_DACVREF) << BIT_SHIFT_D_POW_DACVREF)
#define BIT_D_POW_VREF2 BIT(6)
#define BIT_SHIFT_D_POW_VREF2 6
#define BIT_MASK_D_POW_VREF2 0x1
#define BIT_CTRL_D_POW_VREF2(x) (((x) & BIT_MASK_D_POW_VREF2) << BIT_SHIFT_D_POW_VREF2)
#define BIT_D_POW_MBIAS BIT(5)
#define BIT_SHIFT_D_POW_MBIAS 5
#define BIT_MASK_D_POW_MBIAS 0x1
#define BIT_CTRL_D_POW_MBIAS(x) (((x) & BIT_MASK_D_POW_MBIAS) << BIT_SHIFT_D_POW_MBIAS)
#define BIT_D_POW_DIV4 BIT(4)
#define BIT_SHIFT_D_POW_DIV4 4
#define BIT_MASK_D_POW_DIV4 0x1
#define BIT_CTRL_D_POW_DIV4(x) (((x) & BIT_MASK_D_POW_DIV4) << BIT_SHIFT_D_POW_DIV4)
#define BIT_D_POW_DF1SE_R BIT(3)
#define BIT_SHIFT_D_POW_DF1SE_R 3
#define BIT_MASK_D_POW_DF1SE_R 0x1
#define BIT_CTRL_D_POW_DF1SE_R(x) (((x) & BIT_MASK_D_POW_DF1SE_R) << BIT_SHIFT_D_POW_DF1SE_R)
#define BIT_D_POW_DF2SE_L BIT(2)
#define BIT_SHIFT_D_POW_DF2SE_L 2
#define BIT_MASK_D_POW_DF2SE_L 0x1
#define BIT_CTRL_D_POW_DF2SE_L(x) (((x) & BIT_MASK_D_POW_DF2SE_L) << BIT_SHIFT_D_POW_DF2SE_L)
#define BIT_D_POW_DAC_R BIT(1)
#define BIT_SHIFT_D_POW_DAC_R 1
#define BIT_MASK_D_POW_DAC_R 0x1
#define BIT_CTRL_D_POW_DAC_R(x) (((x) & BIT_MASK_D_POW_DAC_R) << BIT_SHIFT_D_POW_DAC_R)
#define BIT_D_POW_DAC_L BIT(0)
#define BIT_SHIFT_D_POW_DAC_L 0
#define BIT_MASK_D_POW_DAC_L 0x1
#define BIT_CTRL_D_POW_DAC_L(x) (((x) & BIT_MASK_D_POW_DAC_L) << BIT_SHIFT_D_POW_DAC_L)
//================ Register Reg Field =========================
#define REG_DAC0_FIFO_WR 0x0000
#define REG_DAC_CTRL 0x0004
#define REG_DAC_INTR_CTRL 0x0008
#define REG_DAC_INTR_STS 0x000C
#define REG_DAC_PWR_CTRL 0x0010
#define REG_DAC_ANAPAR_DA0 0x0014
#define REG_DAC_ANAPAR_DA1 0x0018
//================ DAC HAL related enumeration ==================
//================ DAC HAL Macro ===========================
#define HAL_DAC_WRITE32(dacidx, addr, value) HAL_WRITE32(DAC_REG_BASE+dacidx*0x800 \
,addr,value)
#define HAL_DAC_READ32(dacidx, addr) HAL_READ32(DAC_REG_BASE+dacidx*0x800,addr)
//================ DAC Function Prototypes =====================
RTK_STATUS HalDACInit8195a(IN VOID *Data);
RTK_STATUS HalDACDeInit8195a(IN VOID *Data);
RTK_STATUS HalDACEnableRtl8195a(IN VOID *Data);
RTK_STATUS HalDACIntrCtrl8195a(IN VOID *Data);
u8 HalDACSendRtl8195a(IN VOID *Data);
u32 HalDACReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_GDMA_H_
#define _RTL8195A_GDMA_H_
// Define GDMA Handshake interface with peripheral, 0 -> GDMA0, 1-> GDMA1
// Set this Hnadshake interface map to register REG_PESOC_SOC_CTRL
#define GDMA_HANDSHAKE_UART0_TX 0
#define GDMA_HANDSHAKE_UART0_RX 1
#define GDMA_HANDSHAKE_UART1_TX 2
#define GDMA_HANDSHAKE_UART1_RX 3
#define GDMA_HANDSHAKE_UART2_TX 14 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_UART2_RX 14 // Only on GDMA 1, hardware fixed
#define GDMA_HANDSHAKE_SSI0_TX 4
#define GDMA_HANDSHAKE_SSI0_RX 5
#define GDMA_HANDSHAKE_SSI1_TX 6
#define GDMA_HANDSHAKE_SSI1_RX 7
#define GDMA_HANDSHAKE_SSI2_TX 15 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_SSI2_RX 15 // Only on GDMA 1, hardware fixed
#define GDMA_HANDSHAKE_I2C0_TX 8
#define GDMA_HANDSHAKE_I2C0_RX 9
#define GDMA_HANDSHAKE_I2C1_TX 10
#define GDMA_HANDSHAKE_I2C1_RX 11
#define GDMA_HANDSHAKE_ADC 12
#define GDMA_HANDSHAKE_DAC0 13 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_DAC1 13 // Only on GDMA 1, hardware fixed
#define HAL_GDMAX_READ32(GdmaIndex, addr) \
HAL_READ32(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE32(GdmaIndex, addr, value) \
HAL_WRITE32((GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF)), addr, value)
#define HAL_GDMAX_READ16(GdmaIndex, addr) \
HAL_READ16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE16(GdmaIndex, addr, value) \
HAL_WRITE16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
#define HAL_GDMAX_READ8(GdmaIndex, addr) \
HAL_READ8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE8(GdmaIndex, addr, value) \
HAL_WRITE8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
#define GDMA_CH_MAX 0x06
#define REG_GDMA_CH_OFF 0x058
#define REG_GDMA_CH_SAR 0x000
#define REG_GDMA_CH_DAR 0x008
#define REG_GDMA_CH_LLP 0x010
#define REG_GDMA_CH_CTL 0x018
#define REG_GDMA_CH_SSTAT 0x020
#define REG_GDMA_CH_DSTAT 0x028
#define REG_GDMA_CH_SSTATAR 0x030
#define REG_GDMA_CH_DSTATAR 0x038
#define REG_GDMA_CH_CFG 0x040
#define REG_GDMA_CH_SGR 0x048
#define REG_GDMA_CH_DSR 0x050
//3 Interrupt Registers
#define REG_GDMA_RAW_INT_BASE 0x2C0
#define REG_GDMA_RAW_INT_TFR 0x2C0
#define REG_GDMA_RAW_INT_BLOCK 0x2c8
#define REG_GDMA_RAW_INT_SRC_TRAN 0x2D0
#define REG_GDMA_RAW_INT_DST_TRAN 0x2D8
#define REG_GDMA_RAW_INT_ERR 0x2E0
#define REG_GDMA_STATUS_INT_BASE 0x2E8
#define REG_GDMA_STATUS_INT_TFR 0x2E8
#define REG_GDMA_STATUS_INT_BLOCK 0x2F0
#define REG_GDMA_STATUS_INT_SRC_TRAN 0x2F8
#define REG_GDMA_STATUS_INT_DST_TRAN 0x300
#define REG_GDMA_STATUS_INT_ERR 0x308
#define REG_GDMA_MASK_INT_BASE 0x310
#define REG_GDMA_MASK_INT_TFR 0x310
#define REG_GDMA_MASK_INT_BLOCK 0x318
#define REG_GDMA_MASK_INT_SRC_TRAN 0x320
#define REG_GDMA_MASK_INT_DST_TRAN 0x328
#define REG_GDMA_MASK_INT_INT_ERR 0x330
#define REG_GDMA_CLEAR_INT_BASE 0x338
#define REG_GDMA_CLEAR_INT_TFR 0x338
#define REG_GDMA_CLEAR_INT_BLOCK 0x340
#define REG_GDMA_CLEAR_INT_SRC_TRAN 0x348
#define REG_GDMA_CLEAR_INT_DST_TRAN 0x350
#define REG_GDMA_CLEAR_INT_ERR 0x358
#define REG_GDMA_STATUS_INT 0x360
//3 Software handshaking Registers
#define REG_GDMA_REQ_SRC 0x368
#define REG_GDMA_REQ_DST 0x370
#define REG_GDMA_REQ_SGL_REQ 0x378
#define REG_GDMA_REQ_DST_REQ 0x380
#define REG_GDMA_REQ_LST_SRC 0x388
#define REG_GDMA_REQ_LST_DST 0x390
//3 Miscellaneous Registers
#define REG_GDMA_DMAC_CFG 0x398
#define REG_GDMA_CH_EN 0x3A0
#define REG_GDMA_DMA_ID 0x3A8
#define REG_GDMA_DMA_TEST 0x3B0
#define REG_GDMA_DMA_COM_PARAMS6 0x3C8
#define REG_GDMA_DMA_COM_PARAMS5 0x3D0
#define REG_GDMA_DMA_COM_PARAMS4 0x3D8
#define REG_GDMA_DMA_COM_PARAMS3 0x3E0
#define REG_GDMA_DMA_COM_PARAMS2 0x3E8
#define REG_GDMA_DMA_COM_PARAMS1 0x3F0
#define REG_GDMA_DMA_COM_PARAMS0 0x3F8
//3 CTL Register Bit Control
#define BIT_SHIFT_CTLX_LO_INT_EN 0
#define BIT_MASK_CTLX_LO_INT_EN 0x1
#define BIT_CTLX_LO_INT_EN(x)(((x) & BIT_MASK_CTLX_LO_INT_EN) << BIT_SHIFT_CTLX_LO_INT_EN)
#define BIT_INVC_CTLX_LO_INT_EN (~(BIT_MASK_CTLX_LO_INT_EN << BIT_SHIFT_CTLX_LO_INT_EN))
#define BIT_SHIFT_CTLX_LO_DST_TR_WIDTH 1
#define BIT_MASK_CTLX_LO_DST_TR_WIDTH 0x7
#define BIT_CTLX_LO_DST_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_DST_TR_WIDTH) << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH)
#define BIT_INVC_CTLX_LO_DST_TR_WIDTH (~(BIT_MASK_CTLX_LO_DST_TR_WIDTH << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH))
#define BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH 4
#define BIT_MASK_CTLX_LO_SRC_TR_WIDTH 0x7
#define BIT_CTLX_LO_SRC_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_SRC_TR_WIDTH) << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH)
#define BIT_INVC_CTLX_LO_SRC_TR_WIDTH (~(BIT_MASK_CTLX_LO_SRC_TR_WIDTH << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH))
#define BIT_SHIFT_CTLX_LO_DINC 7
#define BIT_MASK_CTLX_LO_DINC 0x3
#define BIT_CTLX_LO_DINC(x)(((x) & BIT_MASK_CTLX_LO_DINC) << BIT_SHIFT_CTLX_LO_DINC)
#define BIT_INVC_CTLX_LO_DINC (~(BIT_MASK_CTLX_LO_DINC << BIT_SHIFT_CTLX_LO_DINC))
#define BIT_SHIFT_CTLX_LO_SINC 9
#define BIT_MASK_CTLX_LO_SINC 0x3
#define BIT_CTLX_LO_SINC(x)(((x) & BIT_MASK_CTLX_LO_SINC) << BIT_SHIFT_CTLX_LO_SINC)
#define BIT_INVC_CTLX_LO_SINC (~(BIT_MASK_CTLX_LO_SINC << BIT_SHIFT_CTLX_LO_SINC))
#define BIT_SHIFT_CTLX_LO_DEST_MSIZE 11
#define BIT_MASK_CTLX_LO_DEST_MSIZE 0x7
#define BIT_CTLX_LO_DEST_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_DEST_MSIZE) << BIT_SHIFT_CTLX_LO_DEST_MSIZE)
#define BIT_INVC_CTLX_LO_DEST_MSIZE (~(BIT_MASK_CTLX_LO_DEST_MSIZE << BIT_SHIFT_CTLX_LO_DEST_MSIZE))
#define BIT_SHIFT_CTLX_LO_SRC_MSIZE 14
#define BIT_MASK_CTLX_LO_SRC_MSIZE 0x7
#define BIT_CTLX_LO_SRC_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_SRC_MSIZE) << BIT_SHIFT_CTLX_LO_SRC_MSIZE)
#define BIT_INVC_CTLX_LO_SRC_MSIZE (~(BIT_MASK_CTLX_LO_SRC_MSIZE << BIT_SHIFT_CTLX_LO_SRC_MSIZE))
#define BIT_SHIFT_CTLX_LO_SRC_GATHER_EN 17
#define BIT_MASK_CTLX_LO_SRC_GATHER_EN 0x1
#define BIT_CTLX_LO_SRC_GATHER_EN(x)(((x) & BIT_MASK_CTLX_LO_SRC_GATHER_EN) << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN)
#define BIT_INVC_CTLX_LO_SRC_GATHER_EN (~(BIT_MASK_CTLX_LO_SRC_GATHER_EN << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN))
#define BIT_SHIFT_CTLX_LO_DST_SCATTER_EN 18
#define BIT_MASK_CTLX_LO_DST_SCATTER_EN 0x1
#define BIT_CTLX_LO_DST_SCATTER_EN(x)(((x) & BIT_MASK_CTLX_LO_DST_SCATTER_EN) << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN)
#define BIT_INVC_CTLX_LO_DST_SCATTER_EN (~(BIT_MASK_CTLX_LO_DST_SCATTER_EN << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN))
#define BIT_SHIFT_CTLX_LO_TT_FC 20
#define BIT_MASK_CTLX_LO_TT_FC 0x7
#define BIT_CTLX_LO_TT_FC(x)(((x) & BIT_MASK_CTLX_LO_TT_FC) << BIT_SHIFT_CTLX_LO_TT_FC)
#define BIT_INVC_CTLX_LO_TT_FC (~(BIT_MASK_CTLX_LO_TT_FC << BIT_SHIFT_CTLX_LO_TT_FC))
#define BIT_SHIFT_CTLX_LO_DMS 23
#define BIT_MASK_CTLX_LO_DMS 0x3
#define BIT_CTLX_LO_DMS(x)(((x) & BIT_MASK_CTLX_LO_DMS) << BIT_MASK_CTLX_LO_DMS)
#define BIT_INVC_CTLX_LO_DMS (~(BIT_MASK_CTLX_LO_DMS << BIT_SHIFT_CTLX_LO_DMS))
#define BIT_SHIFT_CTLX_LO_SMS 25
#define BIT_MASK_CTLX_LO_SMS 0x3
#define BIT_CTLX_LO_SMS(x)(((x) & BIT_MASK_CTLX_LO_SMS) << BIT_SHIFT_CTLX_LO_SMS)
#define BIT_INVC_CTLX_LO_SMS (~(BIT_MASK_CTLX_LO_SMS << BIT_SHIFT_CTLX_LO_SMS))
#define BIT_SHIFT_CTLX_LO_LLP_DST_EN 27
#define BIT_MASK_CTLX_LO_LLP_DST_EN 0x1
#define BIT_CTLX_LO_LLP_DST_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_DST_EN) << BIT_SHIFT_CTLX_LO_LLP_DST_EN)
#define BIT_INVC_CTLX_LO_LLP_DST_EN (~(BIT_MASK_CTLX_LO_LLP_DST_EN << BIT_SHIFT_CTLX_LO_LLP_DST_EN))
#define BIT_SHIFT_CTLX_LO_LLP_SRC_EN 28
#define BIT_MASK_CTLX_LO_LLP_SRC_EN 0x1
#define BIT_CTLX_LO_LLP_SRC_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_SRC_EN) << BIT_SHIFT_CTLX_LO_LLP_SRC_EN)
#define BIT_INVC_CTLX_LO_LLP_SRC_EN (~(BIT_MASK_CTLX_LO_LLP_SRC_EN << BIT_SHIFT_CTLX_LO_LLP_SRC_EN))
#define BIT_SHIFT_CTLX_UP_BLOCK_BS 0
#define BIT_MASK_CTLX_UP_BLOCK_BS 0xFFF
#define BIT_CTLX_UP_BLOCK_BS(x)(((x) & BIT_MASK_CTLX_UP_BLOCK_BS) << BIT_SHIFT_CTLX_UP_BLOCK_BS)
#define BIT_INVC_CTLX_UP_BLOCK_BS (~(BIT_MASK_CTLX_UP_BLOCK_BS << BIT_SHIFT_CTLX_UP_BLOCK_BS))
#define BIT_SHIFT_CTLX_UP_DONE 12
#define BIT_MASK_CTLX_UP_DONE 0x1
#define BIT_CTLX_UP_DONE(x)(((x) & BIT_MASK_CTLX_UP_DONE) << BIT_SHIFT_CTLX_UP_DONE)
#define BIT_INVC_CTLX_UP_DONE (~(BIT_MASK_CTLX_UP_DONE << BIT_SHIFT_CTLX_UP_DONE))
//3 CFG Register Bit Control
#define BIT_SHIFT_CFGX_LO_CH_PRIOR 5
#define BIT_MASK_CFGX_LO_CH_PRIOR 0x7
#define BIT_CFGX_LO_CH_PRIOR(x)(((x) & BIT_MASK_CFGX_LO_CH_PRIOR) << BIT_SHIFT_CFGX_LO_CH_PRIOR)
#define BIT_INVC_CFGX_LO_CH_PRIOR (~(BIT_MASK_CFGX_LO_CH_PRIOR << BIT_SHIFT_CFGX_LO_CH_PRIOR))
#define BIT_SHIFT_CFGX_LO_CH_SUSP 8
#define BIT_MASK_CFGX_LO_CH_SUSP 0x1
#define BIT_CFGX_LO_CH_SUSP(x)(((x) & BIT_MASK_CFGX_LO_CH_SUSP) << BIT_SHIFT_CFGX_LO_CH_SUSP)
#define BIT_INVC_CFGX_LO_CH_SUSP (~(BIT_MASK_CFGX_LO_CH_SUSP << BIT_SHIFT_CFGX_LO_CH_SUSP))
#define BIT_SHIFT_CFGX_LO_FIFO_EMPTY 9
#define BIT_MASK_CFGX_LO_FIFO_EMPTY 0x1
#define BIT_CFGX_LO_FIFO_EMPTY(x)(((x) & BIT_MASK_CFGX_LO_FIFO_EMPTY) << BIT_SHIFT_CFGX_LO_FIFO_EMPTY)
#define BIT_INVC_CFGX_LO_FIFO_EMPTY (~(BIT_MASK_CFGX_LO_FIFO_EMPTY << BIT_SHIFT_CFGX_LO_FIFO_EMPTY))
#define BIT_SHIFT_CFGX_LO_HS_SEL_DST 10
#define BIT_MASK_CFGX_LO_HS_SEL_DST 0x1
#define BIT_CFGX_LO_HS_SEL_DST(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_DST) << BIT_SHIFT_CFGX_LO_HS_SEL_DST)
#define BIT_INVC_CFGX_LO_HS_SEL_DST (~(BIT_MASK_CFGX_LO_HS_SEL_DST << BIT_SHIFT_CFGX_LO_HS_SEL_DST))
#define BIT_SHIFT_CFGX_LO_HS_SEL_SRC 11
#define BIT_MASK_CFGX_LO_HS_SEL_SRC 0x1
#define BIT_CFGX_LO_HS_SEL_SRC(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_SRC) << BIT_SHIFT_CFGX_LO_HS_SEL_SRC)
#define BIT_INVC_CFGX_LO_HS_SEL_SRC (~(BIT_MASK_CFGX_LO_HS_SEL_SRC << BIT_SHIFT_CFGX_LO_HS_SEL_SRC))
#define BIT_SHIFT_CFGX_LO_LOCK_CH_L 12
#define BIT_MASK_CFGX_LO_LOCK_CH_L 0x3
#define BIT_CFGX_LO_LOCK_CH_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH_L) << BIT_SHIFT_CFGX_LO_LOCK_CH_L)
#define BIT_INVC_CFGX_LO_LOCK_CH_L (~(BIT_MASK_CFGX_LO_LOCK_CH_L << BIT_SHIFT_CFGX_LO_LOCK_CH_L))
#define BIT_SHIFT_CFGX_LO_LOCK_B_L 14
#define BIT_MASK_CFGX_LO_LOCK_B_L 0x3
#define BIT_CFGX_LO_LOCK_B_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B_L) << BIT_SHIFT_CFGX_LO_LOCK_B_L)
#define BIT_INVC_CFGX_LO_LOCK_B_L (~(BIT_MASK_CFGX_LO_LOCK_B_L << BIT_SHIFT_CFGX_LO_LOCK_B_L))
#define BIT_SHIFT_CFGX_LO_LOCK_CH 16
#define BIT_MASK_CFGX_LO_LOCK_CH 0x1
#define BIT_CFGX_LO_LOCK_CH(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH) << BIT_SHIFT_CFGX_LO_LOCK_CH)
#define BIT_INVC_CFGX_LO_LOCK_CH (~(BIT_MASK_CFGX_LO_LOCK_CH << BIT_SHIFT_CFGX_LO_LOCK_CH))
#define BIT_SHIFT_CFGX_LO_LOCK_B 17
#define BIT_MASK_CFGX_LO_LOCK_B 0x1
#define BIT_CFGX_LO_LOCK_B(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B) << BIT_SHIFT_CFGX_LO_LOCK_B)
#define BIT_INVC_CFGX_LO_LOCK_B (~(BIT_MASK_CFGX_LO_LOCK_B << BIT_SHIFT_CFGX_LO_LOCK_B))
#define BIT_SHIFT_CFGX_LO_DST_HS_POL 18
#define BIT_MASK_CFGX_LO_DST_HS_POL 0x1
#define BIT_CFGX_LO_DST_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_DST_HS_POL) << BIT_SHIFT_CFGX_LO_DST_HS_POL)
#define BIT_INVC_CFGX_LO_DST_HS_POL (~(BIT_MASK_CFGX_LO_DST_HS_POL << BIT_SHIFT_CFGX_LO_DST_HS_POL))
#define BIT_SHIFT_CFGX_LO_SRC_HS_POL 19
#define BIT_MASK_CFGX_LO_SRC_HS_POL 0x1
#define BIT_CFGX_LO_SRC_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_SRC_HS_POL) << BIT_SHIFT_CFGX_LO_SRC_HS_POL)
#define BIT_INVC_CFGX_LO_SRC_HS_POL (~(BIT_MASK_CFGX_LO_SRC_HS_POL << BIT_SHIFT_CFGX_LO_SRC_HS_POL))
#define BIT_SHIFT_CFGX_LO_MAX_ABRST 20
#define BIT_MASK_CFGX_LO_MAX_ABRST 0x3FF
#define BIT_CFGX_LO_MAX_ABRST(x)(((x) & BIT_MASK_CFGX_LO_MAX_ABRST) << BIT_SHIFT_CFGX_LO_MAX_ABRST)
#define BIT_INVC_CFGX_LO_MAX_ABRST (~(BIT_MASK_CFGX_LO_MAX_ABRST << BIT_SHIFT_CFGX_LO_MAX_ABRST))
#define BIT_SHIFT_CFGX_LO_RELOAD_SRC 30
#define BIT_MASK_CFGX_LO_RELOAD_SRC 0x1
#define BIT_CFGX_LO_RELOAD_SRC(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_SRC) << BIT_SHIFT_CFGX_LO_RELOAD_SRC)
#define BIT_INVC_CFGX_LO_RELOAD_SRC (~(BIT_MASK_CFGX_LO_RELOAD_SRC << BIT_SHIFT_CFGX_LO_RELOAD_SRC))
#define BIT_SHIFT_CFGX_LO_RELOAD_DST 31
#define BIT_MASK_CFGX_LO_RELOAD_DST 0x1
#define BIT_CFGX_LO_RELOAD_DST(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_DST) << BIT_SHIFT_CFGX_LO_RELOAD_DST)
#define BIT_INVC_CFGX_LO_RELOAD_DST (~(BIT_MASK_CFGX_LO_RELOAD_DST << BIT_SHIFT_CFGX_LO_RELOAD_DST))
#define BIT_SHIFT_CFGX_UP_FCMODE 0
#define BIT_MASK_CFGX_UP_FCMODE 0x1
#define BIT_CFGX_UP_FCMODE(x)(((x) & BIT_MASK_CFGX_UP_FCMODE) << BIT_SHIFT_CFGX_UP_FCMODE)
#define BIT_INVC_CFGX_UP_FCMODE (~(BIT_MASK_CFGX_UP_FCMODE << BIT_SHIFT_CFGX_UP_FCMODE))
#define BIT_SHIFT_CFGX_UP_FIFO_MODE 1
#define BIT_MASK_CFGX_UP_FIFO_MODE 0x1
#define BIT_CFGX_UP_FIFO_MODE(x)(((x) & BIT_MASK_CFGX_UP_FIFO_MODE) << BIT_SHIFT_CFGX_UP_FIFO_MODE)
#define BIT_INVC_CFGX_UP_FIFO_MODE (~(BIT_MASK_CFGX_UP_FIFO_MODE << BIT_SHIFT_CFGX_UP_FIFO_MODE))
#define BIT_SHIFT_CFGX_UP_PROTCTL 2
#define BIT_MASK_CFGX_UP_PROTCTL 0x7
#define BIT_CFGX_UP_PROTCTL(x)(((x) & BIT_MASK_CFGX_UP_PROTCTL) << BIT_SHIFT_CFGX_UP_PROTCTL)
#define BIT_INVC_CFGX_UP_PROTCTL (~(BIT_MASK_CFGX_UP_PROTCTL << BIT_SHIFT_CFGX_UP_PROTCTL))
#define BIT_SHIFT_CFGX_UP_DS_UPD_EN 5
#define BIT_MASK_CFGX_UP_DS_UPD_EN 0x1
#define BIT_CFGX_UP_DS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_DS_UPD_EN) << BIT_SHIFT_CFGX_UP_DS_UPD_EN)
#define BIT_INVC_CFGX_UP_DS_UPD_EN (~(BIT_MASK_CFGX_UP_DS_UPD_EN << BIT_SHIFT_CFGX_UP_DS_UPD_EN))
#define BIT_SHIFT_CFGX_UP_SS_UPD_EN 6
#define BIT_MASK_CFGX_UP_SS_UPD_EN 0x1
#define BIT_CFGX_UP_SS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_SS_UPD_EN) << BIT_SHIFT_CFGX_UP_SS_UPD_EN)
#define BIT_INVC_CFGX_UP_SS_UPD_EN (~(BIT_MASK_CFGX_UP_SS_UPD_EN << BIT_SHIFT_CFGX_UP_SS_UPD_EN))
#define BIT_SHIFT_CFGX_UP_SRC_PER 7
#define BIT_MASK_CFGX_UP_SRC_PER 0xF
#define BIT_CFGX_UP_SRC_PER(x)(((x) & BIT_MASK_CFGX_UP_SRC_PER) << BIT_SHIFT_CFGX_UP_SRC_PER)
#define BIT_INVC_CFGX_UP_SRC_PER (~(BIT_MASK_CFGX_UP_SRC_PER << BIT_SHIFT_CFGX_UP_SRC_PER))
#define BIT_SHIFT_CFGX_UP_DEST_PER 11
#define BIT_MASK_CFGX_UP_DEST_PER 0xF
#define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER)
#define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER))
typedef enum _GDMA_CHANNEL_NUM_ {
GdmaNoCh = 0x0000,
GdmaCh0 = 0x0101,
GdmaCh1 = 0x0202,
GdmaCh2 = 0x0404,
GdmaCh3 = 0x0808,
GdmaCh4 = 0x1010,
GdmaCh5 = 0x2020,
GdmaCh6 = 0x4040,
GdmaCh7 = 0x8080,
GdmaAllCh = 0xffff
}GDMA_CHANNEL_NUM, *PGDMA_CHANNEL_NUM;
//3 CTL register struct
typedef enum _GDMA_CTL_TT_FC_TYPE_ {
TTFCMemToMem = 0x00,
TTFCMemToPeri = 0x01,
TTFCPeriToMem = 0x02
}GDMA_CTL_TT_FC_TYPE, *PGDMA_CTL_TT_FC_TYPE;
//Max type = Bus Width
typedef enum _GDMA_CTL_TR_WIDTH_ {
TrWidthOneByte = 0x00,
TrWidthTwoBytes = 0x01,
TrWidthFourBytes = 0x02
}GDMA_CTL_TR_WIDTH, *PGDMA_CTL_TR_WIDTH;
typedef enum _GDMA_CTL_MSIZE_ {
MsizeOne = 0x00,
MsizeFour = 0x01,
MsizeEight = 0x02
}GDMA_CTL_MSIZE, *PGDMA_CTL_MSIZE;
typedef enum _GDMA_INC_TYPE_ {
IncType = 0x00,
DecType = 0x01,
NoChange = 0x02
}GDMA_INC_TYPE, *PGDMA_INC_TYPE;
typedef struct _GDMA_CTL_REG_ {
GDMA_CTL_TT_FC_TYPE TtFc;
GDMA_CTL_TR_WIDTH DstTrWidth;
GDMA_CTL_TR_WIDTH SrcTrWidth;
GDMA_INC_TYPE Dinc;
GDMA_INC_TYPE Sinc;
GDMA_CTL_MSIZE DestMsize;
GDMA_CTL_MSIZE SrcMsize;
u8 IntEn :1; // Bit 0
u8 SrcGatherEn :1; // Bit 1
u8 DstScatterEn :1; // Bit 2
u8 LlpDstEn :1; // Bit 3
u8 LlpSrcEn :1; // Bit 4
u8 Done :1; // Bit 5
u8 Rsvd6To7 :2; //Bit 6 -7
u16 BlockSize;
}GDMA_CTL_REG, *PGDMA_CTL_REG;
//3 CFG Register Structure
typedef enum _GDMA_CH_PRIORITY_ {
Prior0 = 0,
Prior1 = 1,
Prior2 = 2,
Prior3 = 3,
Prior4 = 4,
Prior5 = 5,
Prior6 = 6,
Prior7 = 7
}GDMA_CH_PRIORITY, *PGDMA_CH_PRIORITY;
typedef enum _GDMA_LOCK_LEVEL_ {
OverComplDmaTransfer = 0x00,
OverComplDmaBlockTransfer = 0x01,
OverComplDmaTransation = 0x02
}GDMA_LOCK_LEVEL, *PGDMA_LOCK_LEVEL;
typedef struct _GDMA_CFG_REG_ {
GDMA_CH_PRIORITY ChPrior;
GDMA_LOCK_LEVEL LockBL;
GDMA_LOCK_LEVEL LockChL;
u16 MaxAbrst;
u8 SrcPer;
u8 DestPer;
u16 ChSusp :1; //Bit 0
u16 FifoEmpty :1; //Bit 1
u16 HsSelDst :1; //Bit 2
u16 HsSelSrc :1; //Bit 3
u16 LockCh :1; //Bit 4
u16 LockB :1; //Bit 5
u16 DstHsPol :1; //Bit 6
u16 SrcHsPol :1; //Bit 7
u16 ReloadSrc :1; //Bit 8
u16 ReloadDst :1; //Bit 9
u16 FifoMode :1; //Bit 10
u16 DsUpdEn :1; //Bit 11
u16 SsUpdEn :1; //Bit 12
u16 Rsvd13To15 :3;
}GDMA_CFG_REG, *PGDMA_CFG_REG;
typedef enum _GDMA_ISR_TYPE_ {
TransferType = 0x1,
BlockType = 0x2,
SrcTransferType = 0x4,
DstTransferType = 0x8,
ErrType = 0x10
}GDMA_ISR_TYPE, *PGDMA_ISR_TYPE;
VOID
HalGdmaOnOffRtl8195a (
IN VOID *Data
);
BOOL
HalGdamChInitRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaChSetingRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaChBlockSetingRtl8195a(
IN VOID *Data
);
VOID
HalGdmaChDisRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChEnRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChIsrEnAndDisRtl8195a (
IN VOID *Data
);
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
);
#endif

352
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gpio.h Normal file
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@ -0,0 +1,352 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_GPIO_H_
#define _RTL8195A_GPIO_H_
#include "hal_api.h"
#include "hal_gpio.h"
#define GPIO_PORTA_DR 0x00 // data register
#define GPIO_PORTA_DDR 0x04 // data direction
#define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
#define GPIO_PORTB_DR 0x0c // data register
#define GPIO_PORTB_DDR 0x10 // data direction
#define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
#define GPIO_PORTC_DR 0x18 // data register
#define GPIO_PORTC_DDR 0x1c // data direction
#define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
//1 Only the PORTA can be configured to generate interrupts
#define GPIO_INT_EN 0x30 // Interrupt enable register
#define GPIO_INT_MASK 0x34 // Interrupt mask
#define GPIO_INT_TYPE 0x38 // Interrupt type(level/edge) register
#define GPIO_INT_POLARITY 0x3C // Interrupt polarity(Active low/high) register
#define GPIO_INT_STATUS 0x40 // Interrupt status
#define GPIO_INT_RAWSTATUS 0x44 // Interrupt status without mask
#define GPIO_DEBOUNCE 0x48 // Interrupt signal debounce
#define GPIO_PORTA_EOI 0x4c // Clear interrupt
#define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back
#define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back
#define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back
#define GPIO_INT_SYNC 0x60 // Is level-sensitive interrupt being sync sith PCLK
enum {
HAL_GPIO_HIGHZ = 0,
HAL_GPIO_PULL_LOW = 1,
HAL_GPIO_PULL_HIGH = 2
};
//======================================================
// ROM Function prototype
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
static __inline HAL_Status
GPIO_Lock (
VOID
)
{
HAL_Status Status;
if (_pHAL_Gpio_Adapter->EnterCritical) {
_pHAL_Gpio_Adapter->EnterCritical();
}
if(_pHAL_Gpio_Adapter->Locked) {
Status = HAL_BUSY;
}
else {
_pHAL_Gpio_Adapter->Locked = 1;
Status = HAL_OK;
}
if (_pHAL_Gpio_Adapter->ExitCritical) {
_pHAL_Gpio_Adapter->ExitCritical();
}
return Status;
}
static __inline VOID
GPIO_UnLock (
VOID
)
{
if (_pHAL_Gpio_Adapter->EnterCritical) {
_pHAL_Gpio_Adapter->EnterCritical();
}
_pHAL_Gpio_Adapter->Locked = 0;
if (_pHAL_Gpio_Adapter->ExitCritical) {
_pHAL_Gpio_Adapter->ExitCritical();
}
}
_LONG_CALL_ extern u32
HAL_GPIO_IrqHandler_8195a(
IN VOID *pData
);
_LONG_CALL_ extern u32
HAL_GPIO_MbedIrqHandler_8195a(
IN VOID *pData
);
_LONG_CALL_ HAL_Status
HAL_GPIO_IntCtrl_8195a(
HAL_GPIO_PIN *GPIO_Pin,
u32 En
);
_LONG_CALL_ HAL_Status
HAL_GPIO_Init_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_DeInit_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_GPIO_PIN_STATE
HAL_GPIO_ReadPin_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_WritePin_8195a(
HAL_GPIO_PIN *GPIO_Pin,
HAL_GPIO_PIN_STATE Pin_State
);
_LONG_CALL_ HAL_Status
HAL_GPIO_RegIrq_8195a(
IN PIRQ_HANDLE pIrqHandle
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UnRegIrq_8195a(
IN PIRQ_HANDLE pIrqHandle
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UserRegIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin,
VOID *IrqHandler,
VOID *IrqData
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UserUnRegIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_MaskIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UnMaskIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_IntDebounce_8195a(
HAL_GPIO_PIN *GPIO_Pin,
u8 Enable
);
_LONG_CALL_ u32
HAL_GPIO_GetIPPinName_8195a(
u32 chip_pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_PullCtrl_8195a(
u32 chip_pin,
u8 pull_type
);
_LONG_CALL_ u32
GPIO_GetChipPinName_8195a(
u32 port,
u32 pin
);
_LONG_CALL_ VOID
GPIO_PullCtrl_8195a(
u32 chip_pin,
u8 pull_type
);
_LONG_CALL_ VOID
GPIO_Int_SetType_8195a(
u8 pin_num,
u8 int_mode
);
_LONG_CALL_ HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN *GPIO_Pin, u32 En);
_LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr);
HAL_Status
HAL_GPIO_ClearISR_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
/********** HAL In-Line Functions **********/
/**
* @brief De-Initializes a GPIO Pin, reset it as default setting.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval HAL_Status
*/
static __inline VOID
HAL_GPIO_DeInit(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_DeInit_8195a(GPIO_Pin);
}
/**
* @brief Reads the specified input port pin.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval The input port pin current status(High or Low).
*/
static __inline s32
HAL_GPIO_ReadPin(
HAL_GPIO_PIN *GPIO_Pin
)
{
return (s32)HAL_GPIO_ReadPin_8195a(GPIO_Pin);
}
/**
* @brief Write the specified output port pin.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @param Pin_State: The state going to be set to the assigned GPIO pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_WritePin(
HAL_GPIO_PIN *GPIO_Pin,
u32 Value
)
{
HAL_GPIO_WritePin_8195a(GPIO_Pin, (HAL_GPIO_PIN_STATE)Value);
}
/**
* @brief To register a user interrupt handler for a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @param IrqHandler: The IRQ handler to be assigned to the specified pin
*
* @param IrqData: The pointer will be pass the the IRQ handler
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UserRegIrq(
HAL_GPIO_PIN *GPIO_Pin,
VOID *IrqHandler,
VOID *IrqData
)
{
HAL_GPIO_UserRegIrq_8195a(GPIO_Pin, IrqHandler, IrqData);
}
/**
* @brief To un-register a user interrupt handler for a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UserUnRegIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_UserUnRegIrq_8195a(GPIO_Pin);
}
/**
* @brief Enable/Disable GPIO interrupt
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
*
* @param En: Enable (1) or Disable (0)
*
* @retval HAL_Status
*/
static __inline VOID
HAL_GPIO_IntCtrl(
HAL_GPIO_PIN *GPIO_Pin,
u32 En
)
{
HAL_GPIO_IntCtrl_8195a(GPIO_Pin, En);
}
/**
* @brief Mask the interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_MaskIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
}
/**
* @brief UnMask the interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UnMaskIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_ClearISR_8195a(GPIO_Pin);
HAL_GPIO_UnMaskIrq_8195a(GPIO_Pin);
}
#endif // end of "#define _RTL8195A_GPIO_H_"

844
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h Normal file
View file

@ -0,0 +1,844 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_I2C_H_
#define _RTL8195A_I2C_H_
#include "hal_api.h"
//================ Register Bit Field ==================
//2 REG_DW_I2C_IC_CON
#define BIT_IC_CON_IC_SLAVE_DISABLE BIT(6)
#define BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE 6
#define BIT_MASK_IC_CON_IC_SLAVE_DISABLE 0x1
#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(x) (((x) & BIT_MASK_IC_CON_IC_SLAVE_DISABLE) << BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE)
#define BIT_IC_CON_IC_RESTART_EN BIT(5)
#define BIT_SHIFT_IC_CON_IC_RESTART_EN 5
#define BIT_MASK_IC_CON_IC_RESTART_EN 0x1
#define BIT_CTRL_IC_CON_IC_RESTART_EN(x) (((x) & BIT_MASK_IC_CON_IC_RESTART_EN) << BIT_SHIFT_IC_CON_IC_RESTART_EN)
#define BIT_IC_CON_IC_10BITADDR_MASTER BIT(4)
#define BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER 4
#define BIT_MASK_IC_CON_IC_10BITADDR_MASTER 0x1
#define BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER)
#define BIT_IC_CON_IC_10BITADDR_SLAVE BIT(3)
#define BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE 3
#define BIT_MASK_IC_CON_IC_10BITADDR_SLAVE 0x1
#define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_SLAVE) << BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE)
#define BIT_SHIFT_IC_CON_SPEED 1
#define BIT_MASK_IC_CON_SPEED 0x3
#define BIT_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
#define BIT_CTRL_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
#define BIT_GET_IC_CON_SPEED(x) (((x) >> BIT_SHIFT_IC_CON_SPEED) & BIT_MASK_IC_CON_SPEED)
#define BIT_IC_CON_MASTER_MODE BIT(0)
#define BIT_SHIFT_IC_CON_MASTER_MODE 0
#define BIT_MASK_IC_CON_MASTER_MODE 0x1
#define BIT_CTRL_IC_CON_MASTER_MODE(x) (((x) & BIT_MASK_IC_CON_MASTER_MODE) << BIT_SHIFT_IC_CON_MASTER_MODE)
//2 REG_DW_I2C_IC_TAR
#define BIT_IC_TAR_IC_10BITADDR_MASTER BIT(12)
#define BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER 12
#define BIT_MASK_IC_TAR_IC_10BITADDR_MASTER 0x1
#define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_TAR_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER)
#define BIT_IC_TAR_SPECIAL BIT(11)
#define BIT_SHIFT_IC_TAR_SPECIAL 11
#define BIT_MASK_IC_TAR_SPECIAL 0x1
#define BIT_CTRL_IC_TAR_SPECIAL(x) (((x) & BIT_MASK_IC_TAR_SPECIAL) << BIT_SHIFT_IC_TAR_SPECIAL)
#define BIT_IC_TAR_GC_OR_START BIT(10)
#define BIT_SHIFT_IC_TAR_GC_OR_START 10
#define BIT_MASK_IC_TAR_GC_OR_START 0x1
#define BIT_CTRL_IC_TAR_GC_OR_START(x) (((x) & BIT_MASK_IC_TAR_GC_OR_START) << BIT_SHIFT_IC_TAR_GC_OR_START)
#define BIT_SHIFT_IC_TAR 0
#define BIT_MASK_IC_TAR 0x3ff
#define BIT_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
#define BIT_CTRL_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
#define BIT_GET_IC_TAR(x) (((x) >> BIT_SHIFT_IC_TAR) & BIT_MASK_IC_TAR)
//2 REG_DW_I2C_IC_SAR
#define BIT_SHIFT_IC_SAR 0
#define BIT_MASK_IC_SAR 0x3ff
#define BIT_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
#define BIT_CTRL_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
#define BIT_GET_IC_SAR(x) (((x) >> BIT_SHIFT_IC_SAR) & BIT_MASK_IC_SAR)
//2 REG_DW_I2C_IC_HS_MADDR
#define BIT_SHIFT_IC_HS_MADDR 0
#define BIT_MASK_IC_HS_MADDR 0x7
#define BIT_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
#define BIT_CTRL_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
#define BIT_GET_IC_HS_MADDR(x) (((x) >> BIT_SHIFT_IC_HS_MADDR) & BIT_MASK_IC_HS_MADDR)
//2 REG_DW_I2C_IC_DATA_CMD
#define BIT_IC_DATA_CMD_RESTART BIT(10)
#define BIT_SHIFT_IC_DATA_CMD_RESTART 10
#define BIT_MASK_IC_DATA_CMD_RESTART 0x1
#define BIT_CTRL_IC_DATA_CMD_RESTART(x) (((x) & BIT_MASK_IC_DATA_CMD_RESTART) << BIT_SHIFT_IC_DATA_CMD_RESTART)
#define BIT_IC_DATA_CMD_STOP BIT(9)
#define BIT_SHIFT_IC_DATA_CMD_STOP 9
#define BIT_MASK_IC_DATA_CMD_STOP 0x1
#define BIT_CTRL_IC_DATA_CMD_STOP(x) (((x) & BIT_MASK_IC_DATA_CMD_STOP) << BIT_SHIFT_IC_DATA_CMD_STOP)
#define BIT_IC_DATA_CMD_CMD BIT(8)
#define BIT_SHIFT_IC_DATA_CMD_CMD 8
#define BIT_MASK_IC_DATA_CMD_CMD 0x1
#define BIT_CTRL_IC_DATA_CMD_CMD(x) (((x) & BIT_MASK_IC_DATA_CMD_CMD) << BIT_SHIFT_IC_DATA_CMD_CMD)
#define BIT_SHIFT_IC_DATA_CMD_DAT 0
#define BIT_MASK_IC_DATA_CMD_DAT 0xff
#define BIT_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
#define BIT_CTRL_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
#define BIT_GET_IC_DATA_CMD_DAT(x) (((x) >> BIT_SHIFT_IC_DATA_CMD_DAT) & BIT_MASK_IC_DATA_CMD_DAT)
//2 REG_DW_I2C_IC_SS_SCL_HCNT
#define BIT_SHIFT_IC_SS_SCL_HCNT 0
#define BIT_MASK_IC_SS_SCL_HCNT 0xffff
#define BIT_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
#define BIT_CTRL_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
#define BIT_GET_IC_SS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_HCNT) & BIT_MASK_IC_SS_SCL_HCNT)
//2 REG_DW_I2C_IC_SS_SCL_LCNT
#define BIT_SHIFT_IC_SS_SCL_LCNT 0
#define BIT_MASK_IC_SS_SCL_LCNT 0xffff
#define BIT_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
#define BIT_CTRL_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
#define BIT_GET_IC_SS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_LCNT) & BIT_MASK_IC_SS_SCL_LCNT)
//2 REG_DW_I2C_IC_FS_SCL_HCNT
#define BIT_SHIFT_IC_FS_SCL_HCNT 0
#define BIT_MASK_IC_FS_SCL_HCNT 0xffff
#define BIT_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
#define BIT_CTRL_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
#define BIT_GET_IC_FS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_HCNT) & BIT_MASK_IC_FS_SCL_HCNT)
//2 REG_DW_I2C_IC_FS_SCL_LCNT
#define BIT_SHIFT_IC_FS_SCL_LCNT 0
#define BIT_MASK_IC_FS_SCL_LCNT 0xffff
#define BIT_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
#define BIT_CTRL_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
#define BIT_GET_IC_FS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_LCNT) & BIT_MASK_IC_FS_SCL_LCNT)
//2 REG_DW_I2C_IC_HS_SCL_HCNT
#define BIT_SHIFT_IC_HS_SCL_HCNT 0
#define BIT_MASK_IC_HS_SCL_HCNT 0xffff
#define BIT_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
#define BIT_CTRL_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
#define BIT_GET_IC_HS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_HCNT) & BIT_MASK_IC_HS_SCL_HCNT)
//2 REG_DW_I2C_IC_HS_SCL_LCNT
#define BIT_SHIFT_IC_HS_SCL_LCNT 0
#define BIT_MASK_IC_HS_SCL_LCNT 0xffff
#define BIT_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
#define BIT_CTRL_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
#define BIT_GET_IC_HS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_LCNT) & BIT_MASK_IC_HS_SCL_LCNT)
//2 REG_DW_I2C_IC_INTR_STAT
#define BIT_IC_INTR_STAT_R_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL 11
#define BIT_MASK_IC_INTR_STAT_R_GEN_CALL 0x1
#define BIT_CTRL_IC_INTR_STAT_R_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_GEN_CALL) << BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL)
#define BIT_IC_INTR_STAT_R_START_DET BIT(10)
#define BIT_SHIFT_IC_INTR_STAT_R_START_DET 10
#define BIT_MASK_IC_INTR_STAT_R_START_DET 0x1
#define BIT_CTRL_IC_INTR_STAT_R_START_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_START_DET) << BIT_SHIFT_IC_INTR_STAT_R_START_DET)
#define BIT_IC_INTR_STAT_R_STOP_DET BIT(9)
#define BIT_SHIFT_IC_INTR_STAT_R_STOP_DET 9
#define BIT_MASK_IC_INTR_STAT_R_STOP_DET 0x1
#define BIT_CTRL_IC_INTR_STAT_R_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_STOP_DET) << BIT_SHIFT_IC_INTR_STAT_R_STOP_DET)
#define BIT_IC_INTR_STAT_R_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY 8
#define BIT_MASK_IC_INTR_STAT_R_ACTIVITY 0x1
#define BIT_CTRL_IC_INTR_STAT_R_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_ACTIVITY) << BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY)
#define BIT_IC_INTR_STAT_R_RX_DONE BIT(7)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_DONE 7
#define BIT_MASK_IC_INTR_STAT_R_RX_DONE 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_DONE) << BIT_SHIFT_IC_INTR_STAT_R_RX_DONE)
#define BIT_IC_INTR_STAT_R_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT 6
#define BIT_MASK_IC_INTR_STAT_R_TX_ABRT 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_ABRT) << BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT)
#define BIT_IC_INTR_STAT_R_RD_REQ BIT(5)
#define BIT_SHIFT_IC_INTR_STAT_R_RD_REQ 5
#define BIT_MASK_IC_INTR_STAT_R_RD_REQ 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RD_REQ) << BIT_SHIFT_IC_INTR_STAT_R_RD_REQ)
#define BIT_IC_INTR_STAT_R_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY 4
#define BIT_MASK_IC_INTR_STAT_R_TX_EMPTY 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_EMPTY) << BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY)
#define BIT_IC_INTR_STAT_R_TX_OVER BIT(3)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_OVER 3
#define BIT_MASK_IC_INTR_STAT_R_TX_OVER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_TX_OVER)
#define BIT_IC_INTR_STAT_R_RX_FULL BIT(2)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_FULL 2
#define BIT_MASK_IC_INTR_STAT_R_RX_FULL 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_FULL) << BIT_SHIFT_IC_INTR_STAT_R_RX_FULL)
#define BIT_IC_INTR_STAT_R_RX_OVER BIT(1)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_OVER 1
#define BIT_MASK_IC_INTR_STAT_R_RX_OVER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_RX_OVER)
#define BIT_IC_INTR_STAT_R_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER 0
#define BIT_MASK_IC_INTR_STAT_R_RX_UNDER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_UNDER) << BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER)
//2 REG_DW_I2C_IC_INTR_MASK
#define BIT_IC_INTR_MASK_M_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL 11
#define BIT_MASK_IC_INTR_MASK_M_GEN_CALL 0x1
#define BIT_CTRL_IC_INTR_MASK_M_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_GEN_CALL) << BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL)
#define BIT_IC_INTR_MASK_M_START_DET BIT(10)
#define BIT_SHIFT_IC_INTR_MASK_M_START_DET 10
#define BIT_MASK_IC_INTR_MASK_M_START_DET 0x1
#define BIT_CTRL_IC_INTR_MASK_M_START_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_START_DET) << BIT_SHIFT_IC_INTR_MASK_M_START_DET)
#define BIT_IC_INTR_MASK_M_STOP_DET BIT(9)
#define BIT_SHIFT_IC_INTR_MASK_M_STOP_DET 9
#define BIT_MASK_IC_INTR_MASK_M_STOP_DET 0x1
#define BIT_CTRL_IC_INTR_MASK_M_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_STOP_DET) << BIT_SHIFT_IC_INTR_MASK_M_STOP_DET)
#define BIT_IC_INTR_MASK_M_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY 8
#define BIT_MASK_IC_INTR_MASK_M_ACTIVITY 0x1
#define BIT_CTRL_IC_INTR_MASK_M_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_ACTIVITY) << BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY)
#define BIT_IC_INTR_MASK_M_RX_DONE BIT(7)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_DONE 7
#define BIT_MASK_IC_INTR_MASK_M_RX_DONE 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_DONE) << BIT_SHIFT_IC_INTR_MASK_M_RX_DONE)
#define BIT_IC_INTR_MASK_M_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT 6
#define BIT_MASK_IC_INTR_MASK_M_TX_ABRT 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_ABRT) << BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT)
#define BIT_IC_INTR_MASK_M_RD_REQ BIT(5)
#define BIT_SHIFT_IC_INTR_MASK_M_RD_REQ 5
#define BIT_MASK_IC_INTR_MASK_M_RD_REQ 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RD_REQ) << BIT_SHIFT_IC_INTR_MASK_M_RD_REQ)
#define BIT_IC_INTR_MASK_M_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY 4
#define BIT_MASK_IC_INTR_MASK_M_TX_EMPTY 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_EMPTY) << BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY)
#define BIT_IC_INTR_MASK_M_TX_OVER BIT(3)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_OVER 3
#define BIT_MASK_IC_INTR_MASK_M_TX_OVER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_TX_OVER)
#define BIT_IC_INTR_MASK_M_RX_FULL BIT(2)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_FULL 2
#define BIT_MASK_IC_INTR_MASK_M_RX_FULL 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_FULL) << BIT_SHIFT_IC_INTR_MASK_M_RX_FULL)
#define BIT_IC_INTR_MASK_M_RX_OVER BIT(1)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_OVER 1
#define BIT_MASK_IC_INTR_MASK_M_RX_OVER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_RX_OVER)
#define BIT_IC_INTR_MASK_M_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER 0
#define BIT_MASK_IC_INTR_MASK_M_RX_UNDER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_UNDER) << BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER)
//2 REG_DW_I2C_IC_RAW_INTR_STAT
#define BIT_IC_RAW_INTR_STAT_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL 11
#define BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_GEN_CALL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL) << BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL)
#define BIT_IC_RAW_INTR_STAT_START_DET BIT(10)
#define BIT_SHIFT_IC_RAW_INTR_STAT_START_DET 10
#define BIT_MASK_IC_RAW_INTR_STAT_START_DET 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_START_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_START_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_START_DET)
#define BIT_IC_RAW_INTR_STAT_STOP_DET BIT(9)
#define BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET 9
#define BIT_MASK_IC_RAW_INTR_STAT_STOP_DET 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_STOP_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_STOP_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET)
#define BIT_IC_RAW_INTR_STAT_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY 8
#define BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_ACTIVITY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY) << BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY)
#define BIT_IC_RAW_INTR_STAT_RX_DONE BIT(7)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE 7
#define BIT_MASK_IC_RAW_INTR_STAT_RX_DONE 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_DONE(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_DONE) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE)
#define BIT_IC_RAW_INTR_STAT_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT 6
#define BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_ABRT(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT)
#define BIT_IC_RAW_INTR_STAT_RD_REQ BIT(5)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ 5
#define BIT_MASK_IC_RAW_INTR_STAT_RD_REQ 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RD_REQ(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RD_REQ) << BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ)
#define BIT_IC_RAW_INTR_STAT_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY 4
#define BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_EMPTY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY)
#define BIT_IC_RAW_INTR_STAT_TX_OVER BIT(3)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER 3
#define BIT_MASK_IC_RAW_INTR_STAT_TX_OVER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER)
#define BIT_IC_RAW_INTR_STAT_RX_FULL BIT(2)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL 2
#define BIT_MASK_IC_RAW_INTR_STAT_RX_FULL 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_FULL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_FULL) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL)
#define BIT_IC_RAW_INTR_STAT_RX_OVER BIT(1)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER 1
#define BIT_MASK_IC_RAW_INTR_STAT_RX_OVER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER)
#define BIT_IC_RAW_INTR_STAT_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER 0
#define BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_UNDER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER)
//2 REG_DW_I2C_IC_RX_TL
#define BIT_SHIFT_IC_RX_TL 0
#define BIT_MASK_IC_RX_TL 0xff
#define BIT_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
#define BIT_CTRL_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
#define BIT_GET_IC_RX_TL(x) (((x) >> BIT_SHIFT_IC_RX_TL) & BIT_MASK_IC_RX_TL)
//2 REG_DW_I2C_IC_TX_TL
#define BIT_SHIFT_IC_TX_TL 0
#define BIT_MASK_IC_TX_TL 0xff
#define BIT_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
#define BIT_CTRL_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
#define BIT_GET_IC_TX_TL(x) (((x) >> BIT_SHIFT_IC_TX_TL) & BIT_MASK_IC_TX_TL)
//2 REG_DW_I2C_IC_CLR_INTR
#define BIT_IC_CLR_INTR BIT(0)
#define BIT_SHIFT_IC_CLR_INTR 0
#define BIT_MASK_IC_CLR_INTR 0x1
#define BIT_CTRL_IC_CLR_INTR(x) (((x) & BIT_MASK_IC_CLR_INTR) << BIT_SHIFT_IC_CLR_INTR)
//2 REG_DW_I2C_IC_CLR_RX_UNDER
#define BIT_IC_CLR_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_CLR_RX_UNDER 0
#define BIT_MASK_IC_CLR_RX_UNDER 0x1
#define BIT_CTRL_IC_CLR_RX_UNDER(x) (((x) & BIT_MASK_IC_CLR_RX_UNDER) << BIT_SHIFT_IC_CLR_RX_UNDER)
//2 REG_DW_I2C_IC_CLR_RX_OVER
#define BIT_IC_CLR_RX_OVER BIT(0)
#define BIT_SHIFT_IC_CLR_RX_OVER 0
#define BIT_MASK_IC_CLR_RX_OVER 0x1
#define BIT_CTRL_IC_CLR_RX_OVER(x) (((x) & BIT_MASK_IC_CLR_RX_OVER) << BIT_SHIFT_IC_CLR_RX_OVER)
//2 REG_DW_I2C_IC_CLR_TX_OVER
#define BIT_IC_CLR_TX_OVER BIT(0)
#define BIT_SHIFT_IC_CLR_TX_OVER 0
#define BIT_MASK_IC_CLR_TX_OVER 0x1
#define BIT_CTRL_IC_CLR_TX_OVER(x) (((x) & BIT_MASK_IC_CLR_TX_OVER) << BIT_SHIFT_IC_CLR_TX_OVER)
//2 REG_DW_I2C_IC_CLR_RD_REQ
#define BIT_IC_CLR_RD_REQ BIT(0)
#define BIT_SHIFT_IC_CLR_RD_REQ 0
#define BIT_MASK_IC_CLR_RD_REQ 0x1
#define BIT_CTRL_IC_CLR_RD_REQ(x) (((x) & BIT_MASK_IC_CLR_RD_REQ) << BIT_SHIFT_IC_CLR_RD_REQ)
//2 REG_DW_I2C_IC_CLR_TX_ABRT
#define BIT_CLR_RD_REQ BIT(0)
#define BIT_SHIFT_CLR_RD_REQ 0
#define BIT_MASK_CLR_RD_REQ 0x1
#define BIT_CTRL_CLR_RD_REQ(x) (((x) & BIT_MASK_CLR_RD_REQ) << BIT_SHIFT_CLR_RD_REQ)
//2 REG_DW_I2C_IC_CLR_RX_DONE
#define BIT_IC_CLR_RX_DONE BIT(0)
#define BIT_SHIFT_IC_CLR_RX_DONE 0
#define BIT_MASK_IC_CLR_RX_DONE 0x1
#define BIT_CTRL_IC_CLR_RX_DONE(x) (((x) & BIT_MASK_IC_CLR_RX_DONE) << BIT_SHIFT_IC_CLR_RX_DONE)
//2 REG_DW_I2C_IC_CLR_ACTIVITY
#define BIT_IC_CLR_ACTIVITY BIT(0)
#define BIT_SHIFT_IC_CLR_ACTIVITY 0
#define BIT_MASK_IC_CLR_ACTIVITY 0x1
#define BIT_CTRL_IC_CLR_ACTIVITY(x) (((x) & BIT_MASK_IC_CLR_ACTIVITY) << BIT_SHIFT_IC_CLR_ACTIVITY)
//2 REG_DW_I2C_IC_CLR_STOP_DET
#define BIT_IC_CLR_STOP_DET BIT(0)
#define BIT_SHIFT_IC_CLR_STOP_DET 0
#define BIT_MASK_IC_CLR_STOP_DET 0x1
#define BIT_CTRL_IC_CLR_STOP_DET(x) (((x) & BIT_MASK_IC_CLR_STOP_DET) << BIT_SHIFT_IC_CLR_STOP_DET)
//2 REG_DW_I2C_IC_CLR_START_DET
#define BIT_IC_CLR_START_DET BIT(0)
#define BIT_SHIFT_IC_CLR_START_DET 0
#define BIT_MASK_IC_CLR_START_DET 0x1
#define BIT_CTRL_IC_CLR_START_DET(x) (((x) & BIT_MASK_IC_CLR_START_DET) << BIT_SHIFT_IC_CLR_START_DET)
//2 REG_DW_I2C_IC_CLR_GEN_CALL
#define BIT_IC_CLR_GEN_CALL BIT(0)
#define BIT_SHIFT_IC_CLR_GEN_CALL 0
#define BIT_MASK_IC_CLR_GEN_CALL 0x1
#define BIT_CTRL_IC_CLR_GEN_CALL(x) (((x) & BIT_MASK_IC_CLR_GEN_CALL) << BIT_SHIFT_IC_CLR_GEN_CALL)
//2 REG_DW_I2C_IC_ENABLE
#define BIT_IC_ENABLE BIT(0)
#define BIT_SHIFT_IC_ENABLE 0
#define BIT_MASK_IC_ENABLE 0x1
#define BIT_CTRL_IC_ENABLE(x) (((x) & BIT_MASK_IC_ENABLE) << BIT_SHIFT_IC_ENABLE)
//2 REG_DW_I2C_IC_STATUS
#define BIT_IC_STATUS_SLV_ACTIVITY BIT(6)
#define BIT_SHIFT_IC_STATUS_SLV_ACTIVITY 6
#define BIT_MASK_IC_STATUS_SLV_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_SLV_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_SLV_ACTIVITY) << BIT_SHIFT_IC_STATUS_SLV_ACTIVITY)
#define BIT_IC_STATUS_MST_ACTIVITY BIT(5)
#define BIT_SHIFT_IC_STATUS_MST_ACTIVITY 5
#define BIT_MASK_IC_STATUS_MST_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_MST_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_MST_ACTIVITY) << BIT_SHIFT_IC_STATUS_MST_ACTIVITY)
#define BIT_IC_STATUS_RFF BIT(4)
#define BIT_SHIFT_IC_STATUS_RFF 4
#define BIT_MASK_IC_STATUS_RFF 0x1
#define BIT_CTRL_IC_STATUS_RFF(x) (((x) & BIT_MASK_IC_STATUS_RFF) << BIT_SHIFT_IC_STATUS_RFF)
#define BIT_IC_STATUS_RFNE BIT(3)
#define BIT_SHIFT_IC_STATUS_RFNE 3
#define BIT_MASK_IC_STATUS_RFNE 0x1
#define BIT_CTRL_IC_STATUS_RFNE(x) (((x) & BIT_MASK_IC_STATUS_RFNE) << BIT_SHIFT_IC_STATUS_RFNE)
#define BIT_IC_STATUS_TFE BIT(2)
#define BIT_SHIFT_IC_STATUS_TFE 2
#define BIT_MASK_IC_STATUS_TFE 0x1
#define BIT_CTRL_IC_STATUS_TFE(x) (((x) & BIT_MASK_IC_STATUS_TFE) << BIT_SHIFT_IC_STATUS_TFE)
#define BIT_IC_STATUS_TFNF BIT(1)
#define BIT_SHIFT_IC_STATUS_TFNF 1
#define BIT_MASK_IC_STATUS_TFNF 0x1
#define BIT_CTRL_IC_STATUS_TFNF(x) (((x) & BIT_MASK_IC_STATUS_TFNF) << BIT_SHIFT_IC_STATUS_TFNF)
#define BIT_IC_STATUS_ACTIVITY BIT(0)
#define BIT_SHIFT_IC_STATUS_ACTIVITY 0
#define BIT_MASK_IC_STATUS_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_ACTIVITY) << BIT_SHIFT_IC_STATUS_ACTIVITY)
//2 REG_DW_I2C_IC_TXFLR
#define BIT_SHIFT_IC_TXFLR 0
#define BIT_MASK_IC_TXFLR 0x3f
#define BIT_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
#define BIT_CTRL_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
#define BIT_GET_IC_TXFLR(x) (((x) >> BIT_SHIFT_IC_TXFLR) & BIT_MASK_IC_TXFLR)
//2 REG_DW_I2C_IC_RXFLR
#define BIT_SHIFT_IC_RXFLR 0
#define BIT_MASK_IC_RXFLR 0x1f
#define BIT_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
#define BIT_CTRL_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
#define BIT_GET_IC_RXFLR(x) (((x) >> BIT_SHIFT_IC_RXFLR) & BIT_MASK_IC_RXFLR)
//2 REG_DW_I2C_IC_SDA_HOLD
#define BIT_SHIFT_IC_SDA_HOLD 0
#define BIT_MASK_IC_SDA_HOLD 0xffff
#define BIT_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
#define BIT_CTRL_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
#define BIT_GET_IC_SDA_HOLD(x) (((x) >> BIT_SHIFT_IC_SDA_HOLD) & BIT_MASK_IC_SDA_HOLD)
//2 REG_DW_I2C_IC_TX_ABRT_SOURCE
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX BIT(15)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 15
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST BIT(14)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 14
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO BIT(13)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 13
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO)
#define BIT_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST 12
#define BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ARB_LOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS BIT(11)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 11
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT BIT(10)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 10
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 9
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT BIT(8)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 8
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET BIT(7)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 7
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET BIT(6)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 6
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ BIT(5)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 5
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK BIT(4)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 4
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK BIT(3)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 3
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK BIT(2)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 2
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK BIT(1)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 1
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK BIT(0)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK)
//2 REG_DW_I2C_IC_SLV_DATA_NACK_ONLY
#define BIT_IC_SLV_DATA_NACK_ONLY BIT(0)
#define BIT_SHIFT_IC_SLV_DATA_NACK_ONLY 0
#define BIT_MASK_IC_SLV_DATA_NACK_ONLY 0x1
#define BIT_CTRL_IC_SLV_DATA_NACK_ONLY(x) (((x) & BIT_MASK_IC_SLV_DATA_NACK_ONLY) << BIT_SHIFT_IC_SLV_DATA_NACK_ONLY)
//2 REG_DW_I2C_IC_DMA_CR
#define BIT_IC_DMA_CR_TDMAE BIT(1)
#define BIT_SHIFT_IC_DMA_CR_TDMAE 1
#define BIT_MASK_IC_DMA_CR_TDMAE 0x1
#define BIT_CTRL_IC_DMA_CR_TDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_TDMAE) << BIT_SHIFT_IC_DMA_CR_TDMAE)
#define BIT_IC_DMA_CR_RDMAE BIT(0)
#define BIT_SHIFT_IC_DMA_CR_RDMAE 0
#define BIT_MASK_IC_DMA_CR_RDMAE 0x1
#define BIT_CTRL_IC_DMA_CR_RDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_RDMAE) << BIT_SHIFT_IC_DMA_CR_RDMAE)
//2 REG_DW_I2C_IC_DMA_TDLR
#define BIT_SHIFT_IC_DMA_TDLR_DMATDL 0
#define BIT_MASK_IC_DMA_TDLR_DMATDL 0x1f
#define BIT_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
#define BIT_CTRL_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
#define BIT_GET_IC_DMA_TDLR_DMATDL(x) (((x) >> BIT_SHIFT_IC_DMA_TDLR_DMATDL) & BIT_MASK_IC_DMA_TDLR_DMATDL)
//2 REG_DW_I2C_IC_DMA_RDLR
#define BIT_SHIFT_IC_DMA_RDLR_DMARDL 0
#define BIT_MASK_IC_DMA_RDLR_DMARDL 0xf
#define BIT_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
#define BIT_CTRL_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
#define BIT_GET_IC_DMA_RDLR_DMARDL(x) (((x) >> BIT_SHIFT_IC_DMA_RDLR_DMARDL) & BIT_MASK_IC_DMA_RDLR_DMARDL)
//2 REG_DW_I2C_IC_SDA_SETUP
#define BIT_SHIFT_IC_SDA_SETUP 0
#define BIT_MASK_IC_SDA_SETUP 0xff
#define BIT_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
#define BIT_CTRL_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
#define BIT_GET_IC_SDA_SETUP(x) (((x) >> BIT_SHIFT_IC_SDA_SETUP) & BIT_MASK_IC_SDA_SETUP)
//2 REG_DW_I2C_IC_ACK_GENERAL_CALL
#define BIT_IC_ACK_GENERAL_CALL BIT(0)
#define BIT_SHIFT_IC_ACK_GENERAL_CALL 0
#define BIT_MASK_IC_ACK_GENERAL_CALL 0x1
#define BIT_CTRL_IC_ACK_GENERAL_CALL(x) (((x) & BIT_MASK_IC_ACK_GENERAL_CALL) << BIT_SHIFT_IC_ACK_GENERAL_CALL)
//2 REG_DW_I2C_IC_ENABLE_STATUS
#define BIT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST BIT(2)
#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 2
#define BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_SLV_RX_DATA_LOST(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST)
#define BIT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY BIT(1)
#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 1
#define BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY)
#define BIT_IC_ENABLE_STATUS_IC_EN BIT(0)
#define BIT_SHIFT_IC_ENABLE_STATUS_IC_EN 0
#define BIT_MASK_IC_ENABLE_STATUS_IC_EN 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_IC_EN(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_IC_EN) << BIT_SHIFT_IC_ENABLE_STATUS_IC_EN)
//2 REG_DW_I2C_IC_COMP_PARAM_1
#define BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 16
#define BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 0xff
#define BIT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_CTRL_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_GET_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 8
#define BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 0xff
#define BIT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_CTRL_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_GET_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS BIT(7)
#define BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 7
#define BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) << BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS)
#define BIT_IC_COMP_PARAM_1_HAS_DMA BIT(6)
#define BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA 6
#define BIT_MASK_IC_COMP_PARAM_1_HAS_DMA 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_HAS_DMA(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HAS_DMA) << BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA)
#define BIT_IC_COMP_PARAM_1_INTR_IO BIT(5)
#define BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO 5
#define BIT_MASK_IC_COMP_PARAM_1_INTR_IO 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_INTR_IO(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_INTR_IO) << BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO)
#define BIT_IC_COMP_PARAM_1_HC_COUNT_VALUES BIT(4)
#define BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES 4
#define BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_HC_COUNT_VALUES(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES) << BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES)
#define BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE 2
#define BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE 0x3
#define BIT_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_CTRL_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_GET_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH 0
#define BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH 0x3
#define BIT_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
#define BIT_CTRL_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
#define BIT_GET_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH)
//2 REG_DW_I2C_IC_COMP_VERSION
#define BIT_SHIFT_IC_COMP_VERSION 0
#define BIT_MASK_IC_COMP_VERSION 0xffffffffL
#define BIT_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
#define BIT_CTRL_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
#define BIT_GET_IC_COMP_VERSION(x) (((x) >> BIT_SHIFT_IC_COMP_VERSION) & BIT_MASK_IC_COMP_VERSION)
//2 REG_DW_I2C_IC_COMP_TYPE
#define BIT_SHIFT_IC_COMP_TYPE 0
#define BIT_MASK_IC_COMP_TYPE 0xffffffffL
#define BIT_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
#define BIT_CTRL_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
#define BIT_GET_IC_COMP_TYPE(x) (((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE)
//======================== Register Address Definition ========================
#define REG_DW_I2C_IC_CON 0x0000
#define REG_DW_I2C_IC_TAR 0x0004
#define REG_DW_I2C_IC_SAR 0x0008
#define REG_DW_I2C_IC_HS_MADDR 0x000C
#define REG_DW_I2C_IC_DATA_CMD 0x0010
#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014
#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018
#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C
#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020
#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024
#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028
#define REG_DW_I2C_IC_INTR_STAT 0x002C
#define REG_DW_I2C_IC_INTR_MASK 0x0030
#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034
#define REG_DW_I2C_IC_RX_TL 0x0038
#define REG_DW_I2C_IC_TX_TL 0x003C
#define REG_DW_I2C_IC_CLR_INTR 0x0040
#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044
#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048
#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C
#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050
#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054
#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058
#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C
#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060
#define REG_DW_I2C_IC_CLR_START_DET 0x0064
#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068
#define REG_DW_I2C_IC_ENABLE 0x006C
#define REG_DW_I2C_IC_STATUS 0x0070
#define REG_DW_I2C_IC_TXFLR 0x0074
#define REG_DW_I2C_IC_RXFLR 0x0078
#define REG_DW_I2C_IC_SDA_HOLD 0x007C
#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080
#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084
#define REG_DW_I2C_IC_DMA_CR 0x0088
#define REG_DW_I2C_IC_DMA_TDLR 0x008C
#define REG_DW_I2C_IC_DMA_RDLR 0x0090
#define REG_DW_I2C_IC_SDA_SETUP 0x0094
#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098
#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C
#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4
#define REG_DW_I2C_IC_COMP_VERSION 0x00F8
#define REG_DW_I2C_IC_COMP_TYPE 0x00FC
//======================================================
// I2C related enumeration
// I2C Address Mode
typedef enum _I2C_ADDR_MODE_ {
I2C_ADDR_7BIT = 0,
I2C_ADDR_10BIT = 1,
}I2C_ADDR_MODE,*PI2C_ADDR_MODE;
// I2C Speed Mode
typedef enum _I2C_SPD_MODE_ {
I2C_SS_MODE = 1,
I2C_FS_MODE = 2,
I2C_HS_MODE = 3,
}I2C_SPD_MODE,*PI2C_SPD_MODE;
//I2C Timing Parameters
#define I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns.
#define I2C_SS_MIN_SCL_LTIME 4700 //the unit is ns.
#define I2C_FS_MIN_SCL_HTIME 600 //the unit is ns.
#define I2C_FS_MIN_SCL_LTIME 1300 //the unit is ns.
#define I2C_HS_MIN_SCL_HTIME_100 60 //the unit is ns, with bus loading = 100pf
#define I2C_HS_MIN_SCL_LTIME_100 120 //the unit is ns., with bus loading = 100pf
#define I2C_HS_MIN_SCL_HTIME_400 160 //the unit is ns, with bus loading = 400pf
#define I2C_HS_MIN_SCL_LTIME_400 320 //the unit is ns., with bus loading = 400pf
//======================================================
//I2C Essential functions and macros
_LONG_CALL_ VOID HalI2CWrite32(IN u8 I2CIdx, IN u8 I2CReg, IN u32 I2CVal);
_LONG_CALL_ u32 HalI2CRead32(IN u8 I2CIdx, IN u8 I2CReg);
#define HAL_I2C_WRITE32(I2CIdx, addr, value) HalI2CWrite32(I2CIdx,addr,value)
#define HAL_I2C_READ32(I2CIdx, addr) HalI2CRead32(I2CIdx,addr)
// Rtl8195a I2C function prototypes
_LONG_CALL_ HAL_Status HalI2CEnableRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CInit8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CDeInit8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CSendRtl8195a(IN VOID *Data);
_LONG_CALL_ u8 HalI2CReceiveRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CIntrCtrl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CClrIntrRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CClrAllIntrRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data);
_LONG_CALL_ u32 HalI2CReadRegRtl8195a(IN VOID *Data, IN u8 I2CReg);
_LONG_CALL_ HAL_Status HalI2CWriteRegRtl8195a(IN VOID *Data, IN u8 I2CReg, IN u32 RegVal);
_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data);
//Rtl8195a I2C V02 function prototype
_LONG_CALL_ HAL_Status HalI2CSendRtl8195aV02(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data);
//Rtl8195a I2C V02 function prototype END
#endif

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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2s.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_I2S_H_
#define _RTL8195A_I2S_H_
//=============== Register Bit Field Definition ====================
// REG_I2S_CONTROL
#define BIT_CTLX_I2S_EN BIT(0)
#define BIT_SHIFT_CTLX_I2S_EN 0
#define BIT_MASK_CTLX_I2S_EN 0x1
#define BIT_CTRL_CTLX_I2S_EN(x) (((x) & BIT_MASK_CTLX_I2S_EN) << BIT_SHIFT_CTLX_I2S_EN)
#define BIT_SHIFT_CTLX_I2S_TRX_ACT 1
#define BIT_MASK_CTLX_I2S_TRX_ACT 0x3
#define BIT_CTRL_CTLX_I2S_TRX_ACT(x) (((x) & BIT_MASK_CTLX_I2S_TRX_ACT) << BIT_SHIFT_CTLX_I2S_TRX_ACT)
#define BIT_GET_CTLX_I2S_TRX_ACT(x) (((x) >> BIT_SHIFT_CTLX_I2S_TRX_ACT) & BIT_MASK_CTLX_I2S_TRX_ACT)
#define BIT_SHIFT_CTLX_I2S_CH_NUM 3
#define BIT_MASK_CTLX_I2S_CH_NUM 0x3
#define BIT_CTRL_CTLX_I2S_CH_NUM(x) (((x) & BIT_MASK_CTLX_I2S_CH_NUM) << BIT_SHIFT_CTLX_I2S_CH_NUM)
#define BIT_GET_CTLX_I2S_CH_NUM(x) (((x) >> BIT_SHIFT_CTLX_I2S_CH_NUM) & BIT_MASK_CTLX_I2S_CH_NUM)
#define BIT_CTLX_I2S_WL BIT(6)
#define BIT_SHIFT_CTLX_I2S_WL 6
#define BIT_MASK_CTLX_I2S_WL 0x1
#define BIT_CTRL_CTLX_I2S_WL(x) (((x) & BIT_MASK_CTLX_I2S_WL) << BIT_SHIFT_CTLX_I2S_WL)
#define BIT_CTLX_I2S_LRSWAP BIT(10)
#define BIT_SHIFT_CTLX_I2S_LRSWAP 10
#define BIT_MASK_CTLX_I2S_LRSWAP 0x1
#define BIT_CTRL_CTLX_I2S_LRSWAP(x) (((x) & BIT_MASK_CTLX_I2S_LRSWAP) << BIT_SHIFT_CTLX_I2S_LRSWAP)
#define BIT_CTLX_I2S_SCK_INV BIT(11)
#define BIT_SHIFT_CTLX_I2S_SCK_INV 11
#define BIT_MASK_CTLX_I2S_SCK_INV 0x1
#define BIT_CTRL_CTLX_I2S_SCK_INV(x) (((x) & BIT_MASK_CTLX_I2S_SCK_INV) << BIT_SHIFT_CTLX_I2S_SCK_INV)
#define BIT_CTLX_I2S_ENDIAN_SWAP BIT(12)
#define BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP 12
#define BIT_MASK_CTLX_I2S_ENDIAN_SWAP 0x1
#define BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_I2S_ENDIAN_SWAP) << BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP)
#define BIT_CTLX_I2S_SLAVE_MODE BIT(29)
#define BIT_SHIFT_CTLX_I2S_SLAVE_MODE 29
#define BIT_MASK_CTLX_I2S_SLAVE_MODE 0x1
#define BIT_CTRL_CTLX_I2S_SLAVE_MODE(x) (((x) & BIT_MASK_CTLX_I2S_SLAVE_MODE) << BIT_SHIFT_CTLX_I2S_SLAVE_MODE)
#define BIT_CTLX_I2S_CLK_SRC BIT(30)
#define BIT_SHIFT_CTLX_I2S_CLK_SRC 30
#define BIT_MASK_CTLX_I2S_CLK_SRC 0x1
#define BIT_CTRL_CTLX_I2S_CLK_SRC(x) (((x) & BIT_MASK_CTLX_I2S_CLK_SRC) << BIT_SHIFT_CTLX_I2S_CLK_SRC)
#define BIT_CTLX_I2S_SW_RSTN BIT(31)
#define BIT_SHIFT_CTLX_I2S_SW_RSTN 31
#define BIT_MASK_CTLX_I2S_SW_RSTN 0x1
#define BIT_CTRL_CTLX_I2S_SW_RSTN(x) (((x) & BIT_MASK_CTLX_I2S_SW_RSTN) << BIT_SHIFT_CTLX_I2S_SW_RSTN)
// REG_I2S_SETTING
#define BIT_SHIFT_SETTING_I2S_PAGE_SZ 0
#define BIT_MASK_SETTING_I2S_PAGE_SZ 0xFFF
#define BIT_CTRL_SETTING_I2S_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_SZ) << BIT_SHIFT_SETTING_I2S_PAGE_SZ)
#define BIT_GET_SETTING_I2S_PAGE_SZ(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_SZ) & BIT_MASK_SETTING_I2S_PAGE_SZ)
#define BIT_SHIFT_SETTING_I2S_PAGE_NUM 12
#define BIT_MASK_SETTING_I2S_PAGE_NUM 0x3
#define BIT_CTRL_SETTING_I2S_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_NUM) << BIT_SHIFT_SETTING_I2S_PAGE_NUM)
#define BIT_GET_SETTING_I2S_PAGE_NUM(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_NUM) & BIT_MASK_SETTING_I2S_PAGE_NUM)
#define BIT_SHIFT_SETTING_I2S_SAMPLE_RATE 14
#define BIT_MASK_SETTING_I2S_SAMPLE_RATE 0x7
#define BIT_CTRL_SETTING_I2S_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_I2S_SAMPLE_RATE) << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE)
#define BIT_GET_SETTING_I2S_SAMPLE_RATE(x) (((x) >> BIT_SHIFT_SETTING_I2S_SAMPLE_RATE) & BIT_MASK_SETTING_I2S_SAMPLE_RATE)
// i2s trx page own bit
#define BIT_PAGE_I2S_OWN_BIT BIT(31)
#define BIT_SHIFT_PAGE_I2S_OWN_BIT 31
#define BIT_MASK_PAGE_I2S_OWN_BIT 0x1
#define BIT_CTRL_PAGE_I2S_OWN_BIT(x) (((x) & BIT_MASK_PAGE_I2S_OWN_BIT) << BIT_SHIFT_PAGE_I2S_OWN_BIT)
//=============== Register Address Definition ====================
#define REG_I2S_PAGE_OWN_OFF 0x004
#define REG_I2S_CTL 0x000
#define REG_I2S_TX_PAGE_PTR 0x004
#define REG_I2S_RX_PAGE_PTR 0x008
#define REG_I2S_SETTING 0x00C
#define REG_I2S_TX_MASK_INT 0x010
#define REG_I2S_TX_STATUS_INT 0x014
#define REG_I2S_RX_MASK_INT 0x018
#define REG_I2S_RX_STATUS_INT 0x01c
#define REG_I2S_TX_PAGE0_OWN 0x020
#define REG_I2S_TX_PAGE1_OWN 0x024
#define REG_I2S_TX_PAGE2_OWN 0x028
#define REG_I2S_TX_PAGE3_OWN 0x02C
#define REG_I2S_RX_PAGE0_OWN 0x030
#define REG_I2S_RX_PAGE1_OWN 0x034
#define REG_I2S_RX_PAGE2_OWN 0x038
#define REG_I2S_RX_PAGE3_OWN 0x03C
/*I2S Essential Functions and Macros*/
VOID
HalI2SWrite32(
IN u8 I2SIdx,
IN u8 I2SReg,
IN u32 I2SVal
);
u32
HalI2SRead32(
IN u8 I2SIdx,
IN u8 I2SReg
);
/*
#define HAL_I2SX_READ32(I2sIndex, addr) \
HAL_READ32(I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF), addr)
#define HAL_I2SX_WRITE32(I2sIndex, addr, value) \
HAL_WRITE32((I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF)), addr, value)
*/
#define HAL_I2S_WRITE32(I2SIdx, addr, value) HalI2SWrite32(I2SIdx,addr,value)
#define HAL_I2S_READ32(I2SIdx, addr) HalI2SRead32(I2SIdx,addr)
/* I2S debug output*/
#define I2S_PREFIX "RTL8195A[i2s]: "
#define I2S_PREFIX_LVL " [i2s_DBG]: "
typedef enum _I2S_DBG_LVL_ {
HAL_I2S_LVL = 0x01,
SAL_I2S_LVL = 0x02,
VERI_I2S_LVL = 0x03,
}I2S_DBG_LVL,*PI2S_DBG_LVL;
#ifdef CONFIG_DEBUG_LOG
#ifdef CONFIG_DEBUG_LOG_I2S_HAL
#define DBG_8195A_I2S(...) do{ \
_DbgDump("\r"I2S_PREFIX __VA_ARGS__);\
}while(0)
#define I2SDBGLVL 0xFF
#define DBG_8195A_I2S_LVL(LVL,...) do{\
if (LVL&I2SDBGLVL){\
_DbgDump("\r"I2S_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_I2S_LOG_PERD 100
#define DBG_8195A_I2S(...)
#define DBG_8195A_I2S_LVL(...)
#endif
#else
#define DBG_I2S_LOG_PERD 100
#define DBG_8195A_I2S(...)
#define DBG_8195A_I2S_LVL(...)
#endif
/*
#define REG_I2S_PAGE_OWN_OFF 0x004
#define REG_I2S_CTL 0x000
#define REG_I2S_TX_PAGE_PTR 0x004
#define REG_I2S_RX_PAGE_PTR 0x008
#define REG_I2S_SETTING 0x00C
#define REG_I2S_TX_MASK_INT 0x010
#define REG_I2S_TX_STATUS_INT 0x014
#define REG_I2S_RX_MASK_INT 0x018
#define REG_I2S_RX_STATUS_INT 0x01c
#define REG_I2S_TX_PAGE0_OWN 0x020
#define REG_I2S_TX_PAGE1_OWN 0x024
#define REG_I2S_TX_PAGE2_OWN 0x028
#define REG_I2S_TX_PAGE3_OWN 0x02C
#define REG_I2S_RX_PAGE0_OWN 0x030
#define REG_I2S_RX_PAGE1_OWN 0x034
#define REG_I2S_RX_PAGE2_OWN 0x038
#define REG_I2S_RX_PAGE3_OWN 0x03C
*/
/* template
#define BIT_SHIFT_CTLX_ 7
#define BIT_MASK_CTLX_ 0x1
#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
*//*
#define BIT_SHIFT_CTLX_IIS_EN 0
#define BIT_MASK_CTLX_IIS_EN 0x1
#define BIT_CTLX_IIS_EN(x) (((x) & BIT_MASK_CTLX_IIS_EN) << BIT_SHIFT_CTLX_IIS_EN)
#define BIT_INV_CTLX_IIS_EN (~(BIT_MASK_CTLX_IIS_EN << BIT_SHIFT_CTLX_IIS_EN))
#define BIT_SHIFT_CTLX_TRX 1
#define BIT_MASK_CTLX_TRX 0x3
#define BIT_CTLX_TRX(x) (((x) & BIT_MASK_CTLX_TRX) << BIT_SHIFT_CTLX_TRX)
#define BIT_INV_CTLX_TRX (~(BIT_MASK_CTLX_TRX << BIT_SHIFT_CTLX_TRX))
#define BIT_SHIFT_CTLX_CH_NUM 3
#define BIT_MASK_CTLX_CH_NUM 0x3
#define BIT_CTLX_CH_NUM(x) (((x) & BIT_MASK_CTLX_CH_NUM) << BIT_SHIFT_CTLX_CH_NUM)
#define BIT_INV_CTLX_CH_NUM (~(BIT_MASK_CTLX_CH_NUM << BIT_SHIFT_CTLX_CH_NUM))
#define BIT_SHIFT_CTLX_EDGE_SW 5
#define BIT_MASK_CTLX_EDGE_SW 0x1
#define BIT_CTLX_EDGE_SW(x) (((x) & BIT_MASK_CTLX_EDGE_SW) << BIT_SHIFT_CTLX_EDGE_SW)
#define BIT_INV_CTLX_EDGE_SW (~(BIT_MASK_CTLX_EDGE_SW << BIT_SHIFT_CTLX_EDGE_SW))
#define BIT_SHIFT_CTLX_WL 6
#define BIT_MASK_CTLX_WL 0x1
#define BIT_CTLX_WL(x) (((x) & BIT_MASK_CTLX_WL) << BIT_SHIFT_CTLX_WL)
#define BIT_INV_CTLX_WL (~(BIT_MASK_CTLX_WL << BIT_SHIFT_CTLX_WL))
#define BIT_SHIFT_CTLX_LOOP_BACK 7
#define BIT_MASK_CTLX_LOOP_BACK 0x1
#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
#define BIT_SHIFT_CTLX_FORMAT 8
#define BIT_MASK_CTLX_FORMAT 0x3
#define BIT_CTLX_FORMAT(x) (((x) & BIT_MASK_CTLX_FORMAT) << BIT_SHIFT_CTLX_FORMAT)
#define BIT_INV_CTLX_FORMAT (~(BIT_MASK_CTLX_FORMAT << BIT_SHIFT_CTLX_FORMAT))
#define BIT_SHIFT_CTLX_LRSWAP 10
#define BIT_MASK_CTLX_LRSWAP 0x1
#define BIT_CTLX_LRSWAP(x) (((x) & BIT_MASK_CTLX_LRSWAP) << BIT_SHIFT_CTLX_LRSWAP)
#define BIT_INV_CTLX_LRSWAP (~(BIT_MASK_CTLX_LRSWAP << BIT_SHIFT_CTLX_LRSWAP))
#define BIT_SHIFT_CTLX_SCK_INV 11
#define BIT_MASK_CTLX_SCK_INV 0x1
#define BIT_CTLX_SCK_INV(x) (((x) & BIT_MASK_CTLX_SCK_INV) << BIT_SHIFT_CTLX_SCK_INV)
#define BIT_INV_CTLX_SCK_INV (~(BIT_MASK_CTLX_SCK_INV << BIT_SHIFT_CTLX_SCK_INV))
#define BIT_SHIFT_CTLX_ENDIAN_SWAP 12
#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1
#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
#define BIT_SHIFT_CTLX_DEBUG_SWITCH 15
#define BIT_MASK_CTLX_DEBUG_SWITCH 0x3
#define BIT_CTLX_DEBUG_SWITCH(x) (((x) & BIT_MASK_CTLX_DEBUG_SWITCH) << BIT_SHIFT_CTLX_DEBUG_SWITCH)
#define BIT_INV_CTLX_DEBUG_SWITCH (~(BIT_MASK_CTLX_DEBUG_SWITCH << BIT_SHIFT_CTLX_DEBUG_SWITCH))
#define BIT_SHIFT_CTLX_SLAVE_SEL 29
#define BIT_MASK_CTLX_SLAVE_SEL 0x1
#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
#define BIT_SHIFT_CTLX_CLK_SRC 30
#define BIT_MASK_CTLX_CLK_SRC 0x1
#define BIT_CTLX_CLK_SRC(x) (((x) & BIT_MASK_CTLX_CLK_SRC) << BIT_SHIFT_CTLX_CLK_SRC)
#define BIT_INV_CTLX_CLK_SRC (~(BIT_MASK_CTLX_CLK_SRC << BIT_SHIFT_CTLX_CLK_SRC))
#define BIT_SHIFT_CTLX_SW_RSTN 31
#define BIT_MASK_CTLX_SW_RSTN 0x1
#define BIT_CTLX_SW_RSTN(x) (((x) & BIT_MASK_CTLX_SW_RSTN) << BIT_SHIFT_CTLX_SW_RSTN)
#define BIT_INV_CTLX_SW_RSTN (~(BIT_MASK_CTLX_SW_RSTN << BIT_SHIFT_CTLX_SW_RSTN))
#define BIT_SHIFT_SETTING_PAGE_SZ 0
#define BIT_MASK_SETTING_PAGE_SZ 0xFFF
#define BIT_SETTING_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_PAGE_SZ) << BIT_SHIFT_SETTING_PAGE_SZ)
#define BIT_INV_SETTING_PAGE_SZ (~(BIT_MASK_SETTING_PAGE_SZ << BIT_SHIFT_SETTING_PAGE_SZ))
#define BIT_SHIFT_SETTING_PAGE_NUM 12
#define BIT_MASK_SETTING_PAGE_NUM 0x3
#define BIT_SETTING_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_PAGE_NUM) << BIT_SHIFT_SETTING_PAGE_NUM)
#define BIT_INV_SETTING_PAGE_NUM (~(BIT_MASK_SETTING_PAGE_NUM << BIT_SHIFT_SETTING_PAGE_NUM))
#define BIT_SHIFT_SETTING_SAMPLE_RATE 14
#define BIT_MASK_SETTING_SAMPLE_RATE 0x7
#define BIT_SETTING_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_SAMPLE_RATE) << BIT_SHIFT_SETTING_SAMPLE_RATE)
#define BIT_INV_SETTING_SAMPLE_RATE (~(BIT_MASK_SETTING_SAMPLE_RATE << BIT_SHIFT_SETTING_SAMPLE_RATE))
*/
typedef enum _I2S_CTL_FORMAT {
FormatI2s = 0x00,
FormatLeftJustified = 0x01,
FormatRightJustified = 0x02
}I2S_CTL_FORMAT, *PI2S_CTL_FORMAT;
typedef enum _I2S_CTL_CHNUM {
ChannelStereo = 0x00,
Channel5p1 = 0x01,
ChannelMono = 0x02
}I2S_CTL_CHNUM, *PI2S_CTL_CHNUM;
typedef enum _I2S_CTL_TRX_ACT {
RxOnly = 0x00,
TxOnly = 0x01,
TXRX = 0x02
}I2S_CTL_TRX_ACT, *PI2S_CTL_TRX_ACT;
/*
typedef struct _I2S_CTL_REG_ {
I2S_CTL_FORMAT Format;
I2S_CTL_CHNUM ChNum;
I2S_CTL_TRX_ACT TrxAct;
u32 I2s_En :1; // Bit 0
u32 Rsvd1to4 :4; // Bit 1-4 is TrxAct, ChNum
u32 EdgeSw :1; // Bit 5 Edge switch
u32 WordLength :1; // Bit 6
u32 LoopBack :1; // Bit 7
u32 Rsvd8to9 :2; // Bit 8-9 is Format
u32 DacLrSwap :1; // Bit 10
u32 SckInv :1; // Bit 11
u32 EndianSwap :1; // Bit 12
u32 Rsvd13to14 :2; // Bit 11-14
u32 DebugSwitch :2; // Bit 15-16
u32 Rsvd17to28 :12; // Bit 17-28
u32 SlaveMode :1; // Bit 29
u32 SR44p1KHz :1; // Bit 30
u32 SwRstn :1; // Bit 31
} I2S_CTL_REG, *PI2S_CTL_REG;
*/
typedef enum _I2S_SETTING_PAGE_NUM {
I2s1Page = 0x00,
I2s2Page = 0x01,
I2s3Page = 0x02,
I2s4Page = 0x03
}I2S_SETTING_PAGE_NUM, *PI2S_SETTING_PAGE_NUM;
//sampling rate
typedef enum _I2S_SETTING_SR {
I2sSR8K = 0x00,
I2sSR16K = 0x01,
I2sSR24K = 0x02,
I2sSR32K = 0x03,
I2sSR48K = 0x05,
I2sSR44p1K = 0x15,
I2sSR96K = 0x06,
I2sSR88p2K = 0x16
}I2S_SETTING_SR, *PI2S_SETTING_SR;
/*
typedef struct _I2S_SETTING_REG_ {
I2S_SETTING_PAGE_NUM PageNum;
I2S_SETTING_SR SampleRate;
u32 PageSize:12; // Bit 0-11
}I2S_SETTING_REG, *PI2S_SETTING_REG;
typedef enum _I2S_TX_ISR {
I2sTxP0OK = 0x01,
I2sTxP1OK = 0x02,
I2sTxP2OK = 0x04,
I2sTxP3OK = 0x08,
I2sTxPageUn = 0x10,
I2sTxFifoEmpty = 0x20
}I2S_TX_ISR, *PI2S_TX_ISR;
typedef enum _I2S_RX_ISR {
I2sRxP0OK = 0x01,
I2sRxP1OK = 0x02,
I2sRxP2OK = 0x04,
I2sRxP3OK = 0x08,
I2sRxPageUn = 0x10,
I2sRxFifoFull = 0x20
}I2S_RX_ISR, *PI2S_RX_ISR;
*/
/* Hal I2S function prototype*/
RTK_STATUS
HalI2SInitRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SInitRtl8195a_Patch(
IN VOID *Data
);
RTK_STATUS
HalI2SDeInitRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2STxRtl8195a(
IN VOID *Data,
IN u8 *pBuff
);
RTK_STATUS
HalI2SRxRtl8195a(
IN VOID *Data,
OUT u8 *pBuff
);
RTK_STATUS
HalI2SEnableRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SIntrCtrlRtl8195a(
IN VOID *Data
);
u32
HalI2SReadRegRtl8195a(
IN VOID *Data,
IN u8 I2SReg
);
RTK_STATUS
HalI2SSetRateRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetWordLenRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetChNumRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetPageNumRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetPageSizeRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetDirectionRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetDMABufRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SClrIntrRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SClrAllIntrRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SDMACtrlRtl8195a(
IN VOID *Data
);
u8
HalI2SGetTxPageRtl8195a(
IN VOID *Data
);
u8
HalI2SGetRxPageRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SPageSendRtl8195a(
IN VOID *Data,
IN u8 PageIdx
);
#if 0
RTK_STATUS
HalI2SPageRecvRtl8195a(
IN VOID *Data,
IN u8 PageIdx
);
#else
RTK_STATUS
HalI2SPageRecvRtl8195a(
IN VOID *Data
);
#endif
RTK_STATUS
HalI2SClearAllOwnBitRtl8195a(
IN VOID *Data
);
// HAL functions Wrapper
static __inline VOID
HalI2SSetRate(
IN VOID *Data
)
{
HalI2SSetRateRtl8195a(Data);
}
static __inline VOID
HalI2SSetWordLen(
IN VOID *Data
)
{
HalI2SSetWordLenRtl8195a(Data);
}
static __inline VOID
HalI2SSetChNum(
IN VOID *Data
)
{
HalI2SSetChNumRtl8195a(Data);
}
static __inline VOID
HalI2SSetPageNum(
IN VOID *Data
)
{
HalI2SSetPageNumRtl8195a(Data);
}
static __inline VOID
HalI2SSetPageSize(
IN VOID *Data
)
{
HalI2SSetPageSizeRtl8195a(Data);
}
static __inline VOID
HalI2SSetDirection(
IN VOID *Data
)
{
HalI2SSetDirectionRtl8195a(Data);
}
static __inline VOID
HalI2SSetDMABuf(
IN VOID *Data
)
{
HalI2SSetDMABufRtl8195a(Data);
}
static __inline u8
HalI2SGetTxPage(
IN VOID *Data
)
{
return HalI2SGetTxPageRtl8195a(Data);
}
static __inline u8
HalI2SGetRxPage(
IN VOID *Data
)
{
return HalI2SGetRxPageRtl8195a(Data);
}
static __inline VOID
HalI2SPageSend(
IN VOID *Data,
IN u8 PageIdx
)
{
HalI2SPageSendRtl8195a(Data, PageIdx);
}
#if 0
static __inline VOID
HalI2SPageRecv(
IN VOID *Data,
IN u8 PageIdx
)
{
HalI2SPageRecvRtl8195a(Data, PageIdx);
}
#else
static __inline VOID
HalI2SPageRecv(
IN VOID *Data
)
{
HalI2SPageRecvRtl8195a(Data);
}
#endif
static __inline VOID
HalI2SClearAllOwnBit(
IN VOID *Data
)
{
HalI2SClearAllOwnBitRtl8195a(Data);
}
#endif /* _RTL8195A_I2S_H_ */

674
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_mii.h Normal file
View file

@ -0,0 +1,674 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_MII_H_
#define _RTL8195A_MII_H_
#include "basic_types.h"
#include "hal_api.h"
#define ETHERNET_REG_BASE 0x40050000
#define ETHERNET_MODULE_BASE ETHERNET_REG_BASE + 0x0000
#define CPU_INTERFACE_BASE ETHERNET_REG_BASE + 0x1300
/* Ethernet Module registers */
#define REG_RTL_MII_IDR0 0x0000 // Table 2 IDR0 (Offset 0000h-0003h, R/W)
#define REG_RTL_MII_IDR4 0x0004 // Table 3 IDR4 (Offset 0004h-0007h, R/W)
#define REG_RTL_MII_MAR0 0x0008 // Table 4 MAR0 (Offset 0008h-000bh, R/W)
#define REG_RTL_MII_MAR4 0x000C // Table 5 MAR4 (Offset 000ch-000fh, R/W)
#define REG_RTL_MII_CR 0x0038 // Table 21 Command Register (COM_REG, Offset 0038-003Bh, R/W)
#define REG_RTL_MII_IMRISR 0x003C // Table 22 + Table 23
#define REG_RTL_MII_TCR 0x0040 // Table 24 Transmit Configuration Register (TC_REG, Offset 0040h-0043h, R/W)
#define REG_RTL_MII_RCR 0x0044 // Table 25 Receive Configuration Register (RC_REG, Offset 0044h-0047h, R/W)
#define REG_RTL_MII_CTCR 0x0048 // Table 26 CPU Tag Control Register (CPUTAG_REG, Offset 0048h-004bh, R/W)
#define REG_RTL_MII_CONFIG 0x004C // Table 27 Configuration Register (CONFIG_REG, Offset 004ch-004fh, R/W)
#define REG_RTL_MII_CTCR1 0x0050 // Table 28 CPUTAG1 Register (CPUTAG1_REG, Offset 0050h-0053h, R/W)
#define REG_RTL_MII_MSR 0x0058 // Table 29 Media Status Register (MS_reg: Offset 0058h – 005bh, R/W)
#define REG_RTL_MII_MIIAR 0x005C // Table 30 MII Access Register (MIIA_REG, Offset 005c-005fh, R/W)
#define REG_RTL_MII_VR 0x0064 // Table 32 VLAN Register (VLAN_REG, Offset 0064-0067h, R/W)
#define REG_RTL_MII_IMR0 0x00D0 // Table 50 IMR0_REG (IMR0_REG, Offset D0h-D3h)
#define REG_RTL_MII_IMR1 0x00D4 // Table 51 IMR1_REG (IMR1_REG, Offset d4h-d7h)
#define REG_RTL_MII_ISR1 0x00D8 // Table 52 ISR1 Register (ISR1_REG, Offset D8h-DBh)
#define REG_RTL_MII_INTR 0x00DC // Table 53 Interrupt routing register (INTR_REG, Offset DCh-DFh)
#define REG_RTL_MII_CCR 0x00E4 // Table xx Clock Control Register (CLKCTL_REG, Offset E4h-E7h)
/* CPU Interface registers */
#define REG_RTL_MII_TXFDP1 0x1300 // Table 55 TxFDP1 register (TXFDP1_REG, offset 1300h-1303h)
#define REG_RTL_MII_TXCDO1 0x1304 // Table 56 TxCDO1 register (TXCDO1_REG, offset 1304h-1305h)
#define REG_RTL_MII_TXFDP2 0x1310 // Table 57 TxFDP2 register (TXFDP2_REG, offset 1310h-1313h)
#define REG_RTL_MII_TXCDO2 0x1314 // Table 58 TxCDO2 register (TXCDO2_REG, offset 1314h-1315h)
#define REG_RTL_MII_TXFDP3 0x1320 // Table 59 TxFDP3 register (TXFDP3_REG, offset 1320h-1323h)
#define REG_RTL_MII_TXCDO3 0x1324 // Table 60 TxCDO3 register (TXCDO3_REG, offset 1324h-1325h)
#define REG_RTL_MII_TXFDP4 0x1330 // Table 61 TxFDP4 register (TXFDP4_REG, offset 1330h-1333h)
#define REG_RTL_MII_TXCDO4 0x1334 // Table 62 TxCDO4 register (TXCDO4_REG, offset 1334h-1335h)
#define REG_RTL_MII_TXFDP5 0x1340 // Table 63 TxFDP5 register (TXFDP5_REG, offset 1340h-1343h)
#define REG_RTL_MII_TXCDO5 0x1344 // Table 64 TxCDO5 register (TXCDO5_REG, offset 1344h-1345h)
#define REG_RTL_MII_RXFDP2 0x1390 // Table 66 RxFDP2 register (RXFDP#_REG, offset 1390h-1393h)
#define REG_RTL_MII_RXFDP1 0x13F0 // Table 71 RxFDP1 register (RXFDP1_REG, offset 13F0h-13F3h)
#define REG_RTL_MII_RXRS1 0x13F6 // Table 73 Rx Ring Size1 register (RX_RS1_REG, offset 13F6h-13F7h)
#define REG_RTL_MII_RX_PSE1 0x142C // Table 77 Rx_Pse_Des_Thres_1_h (RX_PSE1_REG, Offset 142ch)
#define REG_RTL_MII_ETNRXCPU1 0x1430 // Table 79 EhtrntRxCPU_Des_Num1 (ETNRXCPU1_REG, Offset 1430h-1433h)
#define REG_RTL_MII_IOCMD 0x1434 // Table 80 Ethernet_IO_CMD (ETN_IO_CMD_REG, Offset 1434h-1437h)
#define REG_RTL_MII_IOCMD1 0x1438 // Table 81 Ethernet_IO_CMD1 (IO_CMD1_REG: Offset 1438h-143bh)
#define HAL_MII_READ32(addr) \
HAL_READ32(ETHERNET_REG_BASE, addr)
#define HAL_MII_WRITE32(addr, value) \
HAL_WRITE32(ETHERNET_REG_BASE, addr, value)
#define HAL_MII_READ16(addr) \
HAL_READ16(ETHERNET_REG_BASE, addr)
#define HAL_MII_WRITE16(addr, value) \
HAL_WRITE16(ETHERNET_REG_BASE, addr, value)
#define HAL_MII_READ8(addr) \
HAL_READ8(ETHERNET_REG_BASE, addr)
#define HAL_MII_WRITE8(addr, value) \
HAL_WRITE8(ETHERNET_REG_BASE, addr, value)
#define CMD_CONFIG 0x00081000
//2014-04-29 yclin (disable [27] r_en_precise_dma)
// #define CMD1_CONFIG 0x39000000
#define CMD1_CONFIG 0x31000000
// #define MAX_RX_DESC_SIZE 6
#define MAX_RX_DESC_SIZE 1
#define MAX_TX_DESC_SIZE 5
// 0058h
#define BIT_SHIFT_MSR_FORCE_SPEED_SELECT 16
#define BIT_MASK_MSR_FORCE_SPEED_SELECT 0x3
#define BIT_MSR_FORCE_SPEED_SELECT(x)(((x) & BIT_MASK_MSR_FORCE_SPEED_SELECT) << BIT_SHIFT_MSR_FORCE_SPEED_SELECT)
#define BIT_INVC_MSR_FORCE_SPEED_SELECT (~(BIT_MASK_MSR_FORCE_SPEED_SELECT << BIT_SHIFT_MSR_FORCE_SPEED_SELECT))
#define BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE 10
#define BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE 0x1
#define BIT_MSR_FORCE_SPEED_MODE_ENABLE(x)(((x) & BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE) << BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE)
#define BIT_INVC_MSR_FORCE_SPEED_MODE_ENABLE (~(BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE << BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE))
// 1434h
#define BIT_SHIFT_IOCMD_RXENABLE 5
#define BIT_MASK_IOCMD_RXENABLE 0x1
#define BIT_IOCMD_RXENABLE(x)(((x) & BIT_MASK_IOCMD_RXENABLE) << BIT_SHIFT_IOCMD_RXENABLE)
#define BIT_INVC_IOCMD_RXENABLE (~(BIT_MASK_IOCMD_RXENABLE << BIT_SHIFT_IOCMD_RXENABLE))
#define BIT_SHIFT_IOCMD_TXENABLE 4
#define BIT_MASK_IOCMD_TXENABLE 0x1
#define BIT_IOCMD_TXENABLE(x)(((x) & BIT_MASK_IOCMD_TXENABLE) << BIT_SHIFT_IOCMD_TXENABLE)
#define BIT_INVC_IOCMD_TXENABLE (~(BIT_MASK_IOCMD_TXENABLE << BIT_SHIFT_IOCMD_TXENABLE))
#define BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE 0
#define BIT_MASK_IOCMD_FIRST_DMATX_ENABLE 0x1
#define BIT_IOCMD_FIRST_DMATX_ENABLE(x)(((x) & BIT_MASK_IOCMD_FIRST_DMATX_ENABLE) << BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE)
#define BIT_INVC_IOCMD_FIRST_DMATX_ENABLE (~(BIT_MASK_IOCMD_FIRST_DMATX_ENABLE << BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE))
// 1438h
#define BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE 16
#define BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE 0x1
#define BIT_IOCMD1_FIRST_DMARX_ENABLE(x)(((x) & BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE) << BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE)
#define BIT_INVC_IOCMD1_FIRST_DMARX_ENABLE (~(BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE << BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE))
/**
* 1.4.1.7 Tx command descriptor used in RL6266
* 5 dobule words
*/
typedef struct _TX_INFO_ {
union {
struct {
u32 own:1; //31
u32 eor:1; //30
u32 fs:1; //29
u32 ls:1; //28
u32 ipcs:1; //27
u32 l4cs:1; //26
u32 keep:1; //25
u32 blu:1; //24
u32 crc:1; //23
u32 vsel:1; //22
u32 dislrn:1; //21
u32 cputag_ipcs:1; //20
u32 cputag_l4cs:1; //19
u32 cputag_psel:1; //18
u32 rsvd:1; //17
u32 data_length:17; //0~16
} bit;
u32 dw; //double word
} opts1;
u32 addr;
union {
struct {
u32 cputag:1; //31
u32 aspri:1; //30
u32 cputag_pri:3; //27~29
u32 tx_vlan_action:2; //25~26
u32 tx_pppoe_action:2; //23~24
u32 tx_pppoe_idx:3; //20~22
u32 efid:1; //19
u32 enhance_fid:3; //16~18
u32 vidl:8; // 8~15
u32 prio:3; // 5~7
u32 cfi:1; // 4
u32 vidh:4; // 0~3
} bit;
u32 dw; //double word
} opts2;
union {
struct {
u32 extspa:3; //29~31
u32 tx_portmask:6; //23~28
u32 tx_dst_stream_id:7; //16~22
u32 rsvd:14; // 2~15
u32 l34keep:1; // 1
u32 ptp:1; // 0
} bit;
u32 dw; //double word
} opts3;
union {
struct {
u32 lgsen:1; //31
u32 lgmss:11; //20~30
u32 rsvd:20; // 0~19
} bit;
u32 dw; //double word
} opts4;
} TX_INFO, *PTX_INFO;
typedef struct _RX_INFO_ {
union{
struct{
u32 own:1; //31
u32 eor:1; //30
u32 fs:1; //29
u32 ls:1; //28
u32 crcerr:1; //27
u32 ipv4csf:1; //26
u32 l4csf:1; //25
u32 rcdf:1; //24
u32 ipfrag:1; //23
u32 pppoetag:1; //22
u32 rwt:1; //21
u32 pkttype:4; //20-17
u32 l3routing:1; //16
u32 origformat:1; //15
u32 pctrl:1; //14
#ifdef CONFIG_RG_JUMBO_FRAME
u32 data_length:14; //13~0
#else
u32 rsvd:2; //13~12
u32 data_length:12; //11~0
#endif
}bit;
u32 dw; //double word
}opts1;
u32 addr;
union{
struct{
u32 cputag:1; //31
u32 ptp_in_cpu_tag_exist:1; //30
u32 svlan_tag_exist:1; //29
u32 rsvd_2:2; //27~28
u32 pon_stream_id:7; //20~26
u32 rsvd_1:3; //17~19
u32 ctagva:1; //16
u32 cvlan_tag:16; //15~0
}bit;
u32 dw; //double word
}opts2;
union{
struct{
u32 src_port_num:5; //27~31
u32 dst_port_mask:6; //21~26
u32 reason:8; //13~20
u32 internal_priority:3; //10~12
u32 ext_port_ttl_1:5; //5~9
u32 rsvd:5; //4~0
}bit;
u32 dw; //double word
}opts3;
} RX_INFO, *PRX_INFO;
/**
* GMAC_STATUS_REGS
*/
// TX/RX Descriptor Common
#define BIT_SHIFT_GMAC_DESCOWN 31
#define BIT_MASK_GMAC_DESCOWN 0x1
#define BIT_GMAC_DESCOWN(x)(((x) & BIT_MASK_GMAC_DESCOWN) << BIT_SHIFT_GMAC_DESCOWN)
#define BIT_INVC_GMAC_DESCOWN (~(BIT_MASK_GMAC_DESCOWN << BIT_SHIFT_GMAC_DESCOWN))
#define BIT_SHIFT_GMAC_RINGEND 30
#define BIT_MASK_GMAC_RINGEND 0x1
#define BIT_GMAC_RINGEND(x)(((x) & BIT_MASK_GMAC_RINGEND) << BIT_SHIFT_GMAC_RINGEND)
#define BIT_INVC_GMAC_RINGEND (~(BIT_MASK_GMAC_RINGEND << BIT_SHIFT_GMAC_RINGEND))
#define BIT_SHIFT_GMAC_FIRSTFRAG 29
#define BIT_MASK_GMAC_FIRSTFRAG 0x1
#define BIT_GMAC_FIRSTFRAG(x)(((x) & BIT_MASK_GMAC_FIRSTFRAG) << BIT_SHIFT_GMAC_FIRSTFRAG)
#define BIT_INVC_GMAC_FIRSTFRAG (~(BIT_MASK_GMAC_FIRSTFRAG << BIT_SHIFT_GMAC_FIRSTFRAG))
#define BIT_SHIFT_GMAC_LASTFRAG 28
#define BIT_MASK_GMAC_LASTFRAG 0x1
#define BIT_GMAC_LASTFRAG(x)(((x) & BIT_MASK_GMAC_LASTFRAG) << BIT_SHIFT_GMAC_LASTFRAG)
#define BIT_INVC_GMAC_LASTFRAG (~(BIT_MASK_GMAC_LASTFRAG << BIT_SHIFT_GMAC_LASTFRAG))
// TX Descriptor opts1
#define BIT_SHIFT_GMAC_IPCS 27
#define BIT_MASK_GMAC_IPCS 0x1
#define BIT_GMAC_IPCS(x)(((x) & BIT_MASK_GMAC_IPCS) << BIT_SHIFT_GMAC_IPCS)
#define BIT_INVC_GMAC_IPCS (~(BIT_MASK_GMAC_IPCS << BIT_SHIFT_GMAC_IPCS))
#define BIT_SHIFT_GMAC_L4CS 26
#define BIT_MASK_GMAC_L4CS 0x1
#define BIT_GMAC_L4CS(x)(((x) & BIT_MASK_GMAC_L4CS) << BIT_SHIFT_GMAC_L4CS)
#define BIT_INVC_GMAC_L4CS (~(BIT_MASK_GMAC_L4CS << BIT_SHIFT_GMAC_L4CS))
#define BIT_SHIFT_GMAC_KEEP 25
#define BIT_MASK_GMAC_KEEP 0x1
#define BIT_GMAC_KEEP(x)(((x) & BIT_MASK_GMAC_KEEP) << BIT_SHIFT_GMAC_KEEP)
#define BIT_INVC_GMAC_KEEP (~(BIT_MASK_GMAC_KEEP << BIT_SHIFT_GMAC_KEEP))
#define BIT_SHIFT_GMAC_BLU 24
#define BIT_MASK_GMAC_BLU 0x1
#define BIT_GMAC_BLU(x)(((x) & BIT_MASK_GMAC_BLU) << BIT_SHIFT_GMAC_BLU)
#define BIT_INVC_GMAC_BLU (~(BIT_MASK_GMAC_BLU << BIT_SHIFT_GMAC_BLU))
#define BIT_SHIFT_GMAC_TXCRC 23
#define BIT_MASK_GMAC_TXCRC 0x1
#define BIT_GMAC_TXCRC(x)(((x) & BIT_MASK_GMAC_TXCRC) << BIT_SHIFT_GMAC_TXCRC)
#define BIT_INVC_GMAC_TXCRC (~(BIT_MASK_GMAC_TXCRC << BIT_SHIFT_GMAC_TXCRC))
#define BIT_SHIFT_GMAC_VSEL 22
#define BIT_MASK_GMAC_VSEL 0x1
#define BIT_GMAC_VSEL(x)(((x) & BIT_MASK_GMAC_VSEL) << BIT_SHIFT_GMAC_VSEL)
#define BIT_INVC_GMAC_VSEL (~(BIT_MASK_GMAC_VSEL << BIT_SHIFT_GMAC_VSEL))
#define BIT_SHIFT_GMAC_DISLRN 21
#define BIT_MASK_GMAC_DISLRN 0x1
#define BIT_GMAC_DISLRN(x)(((x) & BIT_MASK_GMAC_DISLRN) << BIT_SHIFT_GMAC_DISLRN)
#define BIT_INVC_GMAC_DISLRN (~(BIT_MASK_GMAC_DISLRN << BIT_SHIFT_GMAC_DISLRN))
#define BIT_SHIFT_GMAC_CPUTAG_IPCS 20
#define BIT_MASK_GMAC_CPUTAG_IPCS 0x1
#define BIT_GMAC_CPUTAG_IPCS(x)(((x) & BIT_MASK_GMAC_CPUTAG_IPCS) << BIT_SHIFT_GMAC_CPUTAG_IPCS)
#define BIT_INVC_GMAC_CPUTAG_IPCS (~(BIT_MASK_GMAC_CPUTAG_IPCS << BIT_SHIFT_GMAC_CPUTAG_IPCS))
#define BIT_SHIFT_GMAC_CPUTAG_L4CS 19
#define BIT_MASK_GMAC_CPUTAG_L4CS 0x1
#define BIT_GMAC_CPUTAG_L4CS(x)(((x) & BIT_MASK_GMAC_CPUTAG_L4CS) << BIT_SHIFT_GMAC_CPUTAG_L4CS)
#define BIT_INVC_GMAC_CPUTAG_L4CS (~(BIT_MASK_GMAC_CPUTAG_L4CS << BIT_SHIFT_GMAC_CPUTAG_L4CS))
#define BIT_SHIFT_GMAC_CPUTAG_PSEL 18
#define BIT_MASK_GMAC_CPUTAG_PSEL 0x1
#define BIT_GMAC_CPUTAG_PSEL(x)(((x) & BIT_MASK_GMAC_CPUTAG_PSEL) << BIT_SHIFT_GMAC_CPUTAG_PSEL)
#define BIT_INVC_GMAC_CPUTAG_PSEL (~(BIT_MASK_GMAC_CPUTAG_PSEL << BIT_SHIFT_GMAC_CPUTAG_PSEL))
#if 0
enum RE8670_STATUS_REGS
{
/*TX/RX share */
DescOwn = (1 << 31), /* Descriptor is owned by NIC */
RingEnd = (1 << 30), /* End of descriptor ring */
FirstFrag = (1 << 29), /* First segment of a packet */
LastFrag = (1 << 28), /* Final segment of a packet */
/*Tx descriptor opt1*/
IPCS = (1 << 27),
L4CS = (1 << 26),
KEEP = (1 << 25),
BLU = (1 << 24),
TxCRC = (1 << 23),
VSEL = (1 << 22),
DisLrn = (1 << 21),
CPUTag_ipcs = (1 << 20),
CPUTag_l4cs = (1 << 19),
/*Tx descriptor opt2*/
CPUTag = (1 << 31),
aspri = (1 << 30),
CPRI = (1 << 27),
TxVLAN_int = (0 << 25), //intact
TxVLAN_ins = (1 << 25), //insert
TxVLAN_rm = (2 << 25), //remove
TxVLAN_re = (3 << 25), //remark
//TxPPPoEAct = (1 << 23),
TxPPPoEAct = 23,
//TxPPPoEIdx = (1 << 20),
TxPPPoEIdx = 20,
Efid = (1 << 19),
//Enhan_Fid = (1 << 16),
Enhan_Fid = 16,
/*Tx descriptor opt3*/
SrcExtPort = 29,
TxDesPortM = 23,
TxDesStrID = 16,
TxDesVCM = 0,
/*Tx descriptor opt4*/
/*Rx descriptor opt1*/
CRCErr = (1 << 27),
IPV4CSF = (1 << 26),
L4CSF = (1 << 25),
RCDF = (1 << 24),
IP_FRAG = (1 << 23),
PPPoE_tag = (1 << 22),
RWT = (1 << 21),
PktType = (1 << 17),
RxProtoIP = 1,
RxProtoPPTP = 2,
RxProtoICMP = 3,
RxProtoIGMP = 4,
RxProtoTCP = 5,
RxProtoUDP = 6,
RxProtoIPv6 = 7,
RxProtoICMPv6 = 8,
RxProtoTCPv6 = 9,
RxProtoUDPv6 = 10,
L3route = (1 << 16),
OrigFormat = (1 << 15),
PCTRL = (1 << 14),
/*Rx descriptor opt2*/
PTPinCPU = (1 << 30),
SVlanTag = (1 << 29),
/*Rx descriptor opt3*/
SrcPort = (1 << 27),
DesPortM = (1 << 21),
Reason = (1 << 13),
IntPriority = (1 << 10),
ExtPortTTL = (1 << 5),
};
enum _DescStatusBit {
DescOwn = (1 << 31), /* Descriptor is owned by NIC */
RingEnd = (1 << 30), /* End of descriptor ring */
FirstFrag = (1 << 29), /* First segment of a packet */
LastFrag = (1 << 28), /* Final segment of a packet */
/* Tx private */
LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
MSSShift = 16, /* MSS value position */
MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
IPCS = (1 << 18), /* Calculate IP checksum */
UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
TxVlanTag = (1 << 17), /* Add VLAN tag */
/* Rx private */
PID1 = (1 << 18), /* Protocol ID bit 1/2 */
PID0 = (1 << 17), /* Protocol ID bit 2/2 */
#define RxProtoUDP (PID1)
#define RxProtoTCP (PID0)
#define RxProtoIP (PID1 | PID0)
#define RxProtoMask RxProtoIP
IPFail = (1 << 16), /* IP checksum failed */
UDPFail = (1 << 15), /* UDP/IP checksum failed */
TCPFail = (1 << 14), /* TCP/IP checksum failed */
RxVlanTag = (1 << 16), /* VLAN tag available */
};
#endif
typedef struct _PHY_MODE_INFO_ {
u8 PhyAddress;
u8 PhyMode;
u8 PhyInterface;
} PHY_MODE_INFO, *PPHY_MODE_INFO;
typedef enum _PHY_MODE_SWITCH_ {
PHY_MODE_DISABLE = 0,
PHY_MODE_ENABLE = 1
} PHY_MODE_SWITCH, *PPHY_MODE_SWITCH;
typedef enum _PHY_INTERFACE_SELECT_ {
PHY_INTERFACE_ONE_WORKS = 0,
PHY_INTERFACE_ZERO_WORKS = 1
} PHY_INTERFACE_SELECT, *PPHY_INTERFACE_SELECT;
typedef enum _GMAC_MSR_FORCE_SPEED_ {
FORCE_SPD_100M = 0,
FORCE_SPD_10M = 1,
FORCE_SPD_GIGA = 2,
NO_FORCE_SPD = 3
}GMAC_MSR_FORCE_SPEED, *PGMAC_MSR_FORCE_SPEED;
// typedef enum _GMAC_INTERRUPT_MASK_ {
// GMAC_IMR_ROK = BIT0,
// GMAC_IMR_CNT_WRAP = BIT1,
// GMAC_IMR_RER_RUNT = BIT2,
// // BIT3 Reserved
// GMAC_IMR_RER_OVF = BIT4,
// GMAC_IMR_RDU = BIT5,
// GMAC_IMR_TOK_TI = BIT6,
// GMAC_IMR_TER = BIT7,
// GMAC_IMR_LINKCHG = BIT8,
// GMAC_IMR_TDU = BIT9,
// GMAC_IMR_SWINT = BIT10,
// GMAC_IMR_RDU2 = BIT11,
// GMAC_IMR_RDU3 = BIT12,
// GMAC_IMR_RDU4 = BIT13,
// GMAC_IMR_RDU5 = BIT14,
// GMAC_IMR_RDU6 = BIT15,
// } GMAC_INTERRUPT_MASK, *PGMAC_INTERRUPT_MASK;
typedef enum _GMAC_INTERRUPT_MASK_ {
GMAC_IMR_ROK = BIT16,
GMAC_IMR_CNT_WRAP = BIT17,
GMAC_IMR_RER_RUNT = BIT18,
// BIT19 Reserved
GMAC_IMR_RER_OVF = BIT20,
GMAC_IMR_RDU = BIT21,
GMAC_IMR_TOK_TI = BIT22,
GMAC_IMR_TER = BIT23,
GMAC_IMR_LINKCHG = BIT24,
GMAC_IMR_TDU = BIT25,
GMAC_IMR_SWINT = BIT26,
GMAC_IMR_RDU2 = BIT27,
GMAC_IMR_RDU3 = BIT28,
GMAC_IMR_RDU4 = BIT29,
GMAC_IMR_RDU5 = BIT30,
GMAC_IMR_RDU6 = BIT31,
} GMAC_INTERRUPT_MASK, *PGMAC_INTERRUPT_MASK;
typedef enum _GMAC_INTERRUPT_STATUS_ {
GMAC_ISR_ROK = BIT0,
GMAC_ISR_CNT_WRAP = BIT1,
GMAC_ISR_RER_RUNT = BIT2,
// BIT3 Reserved
GMAC_ISR_RER_OVF = BIT4,
GMAC_ISR_RDU = BIT5,
GMAC_ISR_TOK_TI = BIT6,
GMAC_ISR_TER = BIT7,
GMAC_ISR_LINKCHG = BIT8,
GMAC_ISR_TDU = BIT9,
GMAC_ISR_SWINT = BIT10,
GMAC_ISR_RDU2 = BIT11,
GMAC_ISR_RDU3 = BIT12,
GMAC_ISR_RDU4 = BIT13,
GMAC_ISR_RDU5 = BIT14,
GMAC_ISR_RDU6 = BIT15,
} GMAC_INTERRUPT_STATUS, *PGMAC_INTERRUPT_STATUS;
typedef enum _GMAC_TX_VLAN_ACTION_ {
INTACT = 0,
INSERT_VLAN_HDR = 1,
REMOVE_VLAN_HDR = 2,
REMARKING_VID = 3
}GMAC_TX_VLAN_ACTION, *PGMAC_TX_VLAN_ACTION;
typedef enum _GMAC_RX_PACKET_TYPE_ {
TYPE_ETHERNET = 0,
TYPE_IPV4 = 1,
TYPE_IPV4_PPTP = 2,
TYPE_IPV4_ICMP = 3,
TYPE_IPV4_IGMP = 4,
TYPE_IPV4_TCP = 5,
TYPE_IPV4_UDP = 6,
TYPE_IPV6 = 7,
TYPE_ICMPV6 = 8,
TYPE_IPV6_TCP = 9,
TYPE_IPV6_UDP = 10
}GMAC_RX_PACKET_TYPE, *PGMAC_RX_PACKET_TYPE;
/*
// Memory Map of DW_apb_ssi
#define REG_DW_SSI_CTRLR0 0x00 // 16 bits
#define REG_DW_SSI_CTRLR1 0x04 // 16 bits
#define REG_DW_SSI_SSIENR 0x08 // 1 bit
#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits
#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits
#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits
#define REG_DW_SSI_RSVD_2 0xFC // 32 bits
// CTRLR0 0x00 // 16 bits, 6.2.1
// DFS Reset Value: 0x7
#define BIT_SHIFT_CTRLR0_DFS 0
#define BIT_MASK_CTRLR0_DFS 0xF
#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS)
#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS))
#define BIT_SHIFT_CTRLR0_FRF 4
#define BIT_MASK_CTRLR0_FRF 0x3
#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF)
#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF))
#define BIT_SHIFT_CTRLR0_SCPH 6
#define BIT_MASK_CTRLR0_SCPH 0x1
#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH)
#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH))
// CTRLR1 0x04 // 16 bits
#define BIT_SHIFT_CTRLR1_NDF 0
#define BIT_MASK_CTRLR1_NDF 0xFFFF
#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF)
#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF))
// TXFLTR 0x18 // Variable Length
#define BIT_SHIFT_TXFTLR_TFT 0
#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0
#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT)
#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT))
// TXFLR 0x20 // see [READ ONLY]
#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0
// RXFLR 0x24 // see [READ ONLY]
#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0
// SR 0x28 // 7 bits [READ ONLY]
#define BIT_SR_BUSY BIT0
#define BIT_SR_TFNF BIT1
#define BIT_SR_TFE BIT2
#define BIT_SR_RFNE BIT3
#define BIT_SR_RFF BIT4
#define BIT_SR_TXE BIT5
#define BIT_SR_DCOL BIT6
#define BIT_IMR_TXEIM BIT0
#define BIT_IMR_TXOIM BIT1
#define BIT_IMR_RXUIM BIT2
#define BIT_IMR_RXOIM BIT3
#define BIT_IMR_RXFIM BIT4
#define BIT_IMR_MSTIM BIT5
// ISR 0x30 // 6 bits [READ ONLY]
#define BIT_ISR_TXEIS BIT0
#define BIT_ISR_TXOIS BIT1
#define BIT_ISR_RXUIS BIT2
#define BIT_ISR_RXOIS BIT3
#define BIT_ISR_RXFIS BIT4
#define BIT_ISR_MSTIS BIT5
*/
BOOL
HalMiiGmacInitRtl8195a(
IN VOID *Data
);
BOOL
HalMiiInitRtl8195a(
IN VOID *Data
);
BOOL
HalMiiGmacResetRtl8195a(
IN VOID *Data
);
BOOL
HalMiiGmacEnablePhyModeRtl8195a(
IN VOID *Data
);
u32
HalMiiGmacXmitRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacCleanTxRingRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacFillTxInfoRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacFillRxInfoRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacTxRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacRxRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacSetDefaultEthIoCmdRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacInitIrqRtl8195a(
IN VOID *Data
);
u32
HalMiiGmacGetInterruptStatusRtl8195a(
VOID
);
VOID
HalMiiGmacClearInterruptStatusRtl8195a(
u32 IsrStatus
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_NFC_H_
#define _RTL8195A_NFC_H_
#include "hal_api.h"
#include "osdep_api.h"
#ifdef CONFIG_NFC_VERIFY
#include "../test/nfc/rtl8195a_nfc_test.h"
#endif
#if CONFIG_NFC_NORMAL
//===================== Register Bit Field Definition =====================
// TODO:
//===================== Register Address Definition =====================
//TODO:
#include "osdep_api.h"
#define N2A_Q_LENGTH 10
#define N2ARLENGTH 4
//#define NFCTAGLENGTH 36 // maximum 36*4=144 bytes
#define NFCTAG_BASE 0x7F000
#define NFCTAG_PAGESIZE 256
#define NFCTAG_MAXPAGEIDX 16//(4*(1024/NFCTAG_PAGESIZE))
#define A2NWCLENGTH 4
#define FLASHAPPLENGTH 31
#define FLASHAPP_BASE 0x7E000
#define FLASH_PAGESIZE 128
#define FLASH_MAXPAGEIDX 32//(4*(1024/FLASH_PAGESIZE))
typedef struct _A2N_CATCH_W_ {
//u8 Vaild;
u8 A2NCatchRPage;
u32 A2NCatchWData[A2NWCLENGTH];
}A2N_CATCH_W_QUEUE, *PA2N_CATCH_W_QUEUE;
typedef struct _A2N_MAILBOX_Q_ {
u8 Length;
u8 Response;
u32 Content[A2NWCLENGTH+1];
}A2N_MAILBOX_Q,*PA2N_MAILBOX_Q;
typedef struct _N2A_CATCH_R_ {
u8 Vaild;
u8 N2ACatchRPage;
u32 N2ACatchRData[N2ARLENGTH];
}N2A_CATCH_R_QUEUE, *PN2A_CATCH_R_QUEUE;
typedef struct _N2A_R_ {
u8 Vaild;
u8 N2ARPage;
}N2A_R_QUEUE, *PN2A_R_QUEUE;
typedef struct _N2A_W_ {
u8 Vaild;
u8 N2AWPage;
u32 N2AWData;
}N2A_W_QUEUE, *PN2A_W_QUEUE;
typedef struct _NFC_ADAPTER_ {
u8 Function;
u32 NFCIsr;
u8 N2ABoxOpen;
u8 A2NSeq;
//u8 NFCTagFlashWIdx;
//u8 NFCTagFlashRIdx;
// u32 NFCTag[NFCTAGLENGTH];
#if !TASK_SCHEDULER_DISABLED
_Sema VeriSema;
#else
u32 VeriSema;
#endif
#ifdef PLATFORM_FREERTOS
xTaskHandle NFCTask;
#else
u32 NFCTask;
#endif
#ifdef CONFIG_NFC_VERIFY
//N2A Write Tag
u8 N2AWQRIdx;
u8 N2AWQWIdx;
N2A_W_QUEUE N2AWQ[N2A_Q_LENGTH];
//N2A Read Tag
u8 N2ARQRIdx;
u8 N2ARQWIdx;
N2A_R_QUEUE N2ARQ[N2A_Q_LENGTH];
//N2A Read Catch
u8 N2ARCRIdx;
u8 N2ARCWIdx;
N2A_CATCH_R_QUEUE N2ACatchR[N2A_Q_LENGTH];
#endif
//A2N Write Catch
//u8 A2NWCRIdx;
//u8 A2NWCWIdx;
//A2N_CATCH_W_QUEUE A2NCatchW[N2A_Q_LENGTH];
//A2N Write mailbox queue
u8 A2NWMailBox;
u8 A2NWQRIdx;
u8 A2NWQWIdx;
A2N_MAILBOX_Q A2NMAILQ[N2A_Q_LENGTH];
u8 TaskStop;
void *nfc_obj;
}NFC_ADAPTER, *PNFC_ADAPTER;
typedef enum _N2A_CMD_ {
TAG_READ = 0,
TAG_WRITE = 1,
CATCH_READ_DATA = 2,
NFC_R_PRESENT = 4,
N2A_MAILBOX_STATE = 5,
EXT_CLK_REQ = 6,
MAX_N2ACMD
};
typedef enum _A2N_CMD_ {
TAG_READ_DATA = 0,
CATCH_READ = 2,
CATCH_WRITE = 3,
A2N_MAILBOX_STATE = 4,
CONFIRM_N2A_BOX_STATE = 5,
EXT_CLK_RSP = 6,
MAX_A2NCMD
};
// Callback event defination
typedef enum _NFC_HAL_EVENT_ {
NFC_HAL_READER_PRESENT = (1<<0),
NFC_HAL_READ = (1<<1),
NFC_HAL_WRITE = (1<<2),
NFC_HAL_ERR = (1<<3),
NFC_HAL_CACHE_RD = (1<<4)
}NFC_CB_EVENT, *PNFC_CB_EVENT;
VOID A2NWriteCatch(IN VOID *pNFCAdapte, IN u8 N2AWPage,
IN u8 Length, IN u32 *WData);
VOID A2NReadCatch(IN VOID *pNFCAdapte, IN u8 A2NRPage);
VOID HalNFCDmemInit(IN u32 *pTagData, IN u32 TagLen);
VOID HalNFCInit(PNFC_ADAPTER pNFCAdp);
VOID HalNFCDeinit(PNFC_ADAPTER pNFCAdp);
VOID HalNFCFwDownload(VOID);
#endif //CONFIG_NFC_NORMAL
#endif

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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pcm.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_PCM_H_
#define _RTL8195A_PCM_H_
#include "basic_types.h"
#include "hal_api.h"
#define HAL_PCMX_READ32(PcmIndex, addr) \
HAL_READ32(PCM0_REG_BASE+ (PcmIndex*PCM1_REG_OFF), addr)
#define HAL_PCMX_WRITE32(PcmIndex, addr, value) \
HAL_WRITE32((PCM0_REG_BASE+ (PcmIndex*PCM1_REG_OFF)), addr, value)
#define REG_PCM_TRXBSA_OFF 0x004
#define REG_PCM_CTL 0x000
#define REG_PCM_CHCNR03 0x004
#define REG_PCM_TSR03 0x008
#define REG_PCM_BSIZE03 0x00C
#define REG_PCM_CH0TXBSA 0x010
#define REG_PCM_CH1TXBSA 0x014
#define REG_PCM_CH2TXBSA 0x018
#define REG_PCM_CH3TXBSA 0x01c
#define REG_PCM_CH0RXBSA 0x020
#define REG_PCM_CH1RXBSA 0x024
#define REG_PCM_CH2RXBSA 0x028
#define REG_PCM_CH3RXBSA 0x02c
#define REG_PCM_IMR03 0x030
#define REG_PCM_ISR03 0x034
#define REG_PCM_CHCNR47 0x038
#define REG_PCM_TSR47 0x03c
#define REG_PCM_BSIZE47 0x040
#define REG_PCM_CH4TXBSA 0x044
#define REG_PCM_CH5TXBSA 0x048
#define REG_PCM_CH6TXBSA 0x04c
#define REG_PCM_CH7TXBSA 0x050
#define REG_PCM_CH4RXBSA 0x054
#define REG_PCM_CH5RXBSA 0x058
#define REG_PCM_CH6RXBSA 0x05c
#define REG_PCM_CH7RXBSA 0x060
#define REG_PCM_IMR47 0x064
#define REG_PCM_ISR47 0x068
#define REG_PCM_CHCNR811 0x06c
#define REG_PCM_TSR811 0x070
#define REG_PCM_BSIZE811 0x074
#define REG_PCM_CH8TXBSA 0x078
#define REG_PCM_CH9TXBSA 0x07c
#define REG_PCM_CH10TXBSA 0x080
#define REG_PCM_CH11TXBSA 0x084
#define REG_PCM_CH8RXBSA 0x088
#define REG_PCM_CH9RXBSA 0x08c
#define REG_PCM_CH10RXBSA 0x090
#define REG_PCM_CH11RXBSA 0x094
#define REG_PCM_IMR811 0x098
#define REG_PCM_ISR811 0x09c
#define REG_PCM_CHCNR1215 0x0a0
#define REG_PCM_TSR1215 0x0a4
#define REG_PCM_BSIZE1215 0x0a8
#define REG_PCM_CH12TXBSA 0x0ac
#define REG_PCM_CH13TXBSA 0x0b0
#define REG_PCM_CH14TXBSA 0x0b4
#define REG_PCM_CH15TXBSA 0x0b8
#define REG_PCM_CH12RXBSA 0x0bc
#define REG_PCM_CH13RXBSA 0x0c0
#define REG_PCM_CH14RXBSA 0x0c4
#define REG_PCM_CH15RXBSA 0x0c8
#define REG_PCM_IMR1215 0x0cc
#define REG_PCM_ISR1215 0x0d0
#define REG_PCM_INTMAP 0x0d4
#define REG_PCM_WTSR03 0x0d8
#define REG_PCM_WTSR47 0x0dc
#define REG_PCM_RX_BUFOW 0x0e0
/* template
#define BIT_SHIFT_CTLX_ 7
#define BIT_MASK_CTLX_ 0x1
#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
*/
#define BIT_SHIFT_CTLX_SLAVE_SEL 8
#define BIT_MASK_CTLX_SLAVE_SEL 0x1
#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
#define BIT_SHIFT_CTLX_FSINV 9
#define BIT_MASK_CTLX_FSINV 0x1
#define BIT_CTLX_FSINV(x) (((x) & BIT_MASK_CTLX_FSINV) << BIT_SHIFT_CTLX_FSINV)
#define BIT_INV_CTLX_FSINV (~(BIT_MASK_CTLX_FSINV << BIT_SHIFT_CTLX_FSINV))
#define BIT_SHIFT_CTLX_PCM_EN 12
#define BIT_MASK_CTLX_PCM_EN 0x1
#define BIT_CTLX_PCM_EN(x) (((x) & BIT_MASK_CTLX_PCM_EN) << BIT_SHIFT_CTLX_PCM_EN)
#define BIT_INV_CTLX_PCM_EN (~(BIT_MASK_CTLX_PCM_EN << BIT_SHIFT_CTLX_PCM_EN))
#define BIT_SHIFT_CTLX_LINEARMODE 13
#define BIT_MASK_CTLX_LINEARMODE 0x1
#define BIT_CTLX_LINEARMODE(x) (((x) & BIT_MASK_CTLX_LINEARMODE) << BIT_SHIFT_CTLX_LINEARMODE)
#define BIT_INV_CTLX_LINEARMODE (~(BIT_MASK_CTLX_LINEARMODE << BIT_SHIFT_CTLX_LINEARMODE))
#define BIT_SHIFT_CTLX_LOOP_BACK 14
#define BIT_MASK_CTLX_LOOP_BACK 0x1
#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
#define BIT_SHIFT_CTLX_ENDIAN_SWAP 17
#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1
#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
#define BIT_SHIFT_CHCNR03_CH0RE 24
#define BIT_MASK_CHCNR03_CH0RE 0x1
#define BIT_CHCNR03_CH0RE(x) (((x) & BIT_MASK_CHCNR03_CH0RE) << BIT_SHIFT_CHCNR03_CH0RE)
#define BIT_INV_CHCNR03_CH0RE (~(BIT_MASK_CHCNR03_CH0RE << BIT_SHIFT_CHCNR03_CH0RE))
#define BIT_SHIFT_CHCNR03_CH0TE 25
#define BIT_MASK_CHCNR03_CH0TE 0x1
#define BIT_CHCNR03_CH0TE(x) (((x) & BIT_MASK_CHCNR03_CH0TE) << BIT_SHIFT_CHCNR03_CH0TE)
#define BIT_INV_CHCNR03_CH0TE (~(BIT_MASK_CHCNR03_CH0TE << BIT_SHIFT_CHCNR03_CH0TE))
#define BIT_SHIFT_CHCNR03_CH1RE 16
#define BIT_MASK_CHCNR03_CH1RE 0x1
#define BIT_CHCNR03_CH1RE(x) (((x) & BIT_MASK_CHCNR03_CH1RE) << BIT_SHIFT_CHCNR03_CH1RE)
#define BIT_INV_CHCNR03_CH1RE (~(BIT_MASK_CHCNR03_CH1RE << BIT_SHIFT_CHCNR03_CH1RE))
#define BIT_SHIFT_CHCNR03_CH1TE 17
#define BIT_MASK_CHCNR03_CH1TE 0x1
#define BIT_CHCNR03_CH1TE(x) (((x) & BIT_MASK_CHCNR03_CH1TE) << BIT_SHIFT_CHCNR03_CH1TE)
#define BIT_INV_CHCNR03_CH1TE (~(BIT_MASK_CHCNR03_CH1TE << BIT_SHIFT_CHCNR03_CH1TE))
#define BIT_SHIFT_CHCNR03_CH2RE 8
#define BIT_MASK_CHCNR03_CH2RE 0x1
#define BIT_CHCNR03_CH2RE(x) (((x) & BIT_MASK_CHCNR03_CH2RE) << BIT_SHIFT_CHCNR03_CH2RE)
#define BIT_INV_CHCNR03_CH2RE (~(BIT_MASK_CHCNR03_CH2RE << BIT_SHIFT_CHCNR03_CH2RE))
#define BIT_SHIFT_CHCNR03_CH2TE 9
#define BIT_MASK_CHCNR03_CH2TE 0x1
#define BIT_CHCNR03_CH2TE(x) (((x) & BIT_MASK_CHCNR03_CH2TE) << BIT_SHIFT_CHCNR03_CH2TE)
#define BIT_INV_CHCNR03_CH2TE (~(BIT_MASK_CHCNR03_CH2TE << BIT_SHIFT_CHCNR03_CH2TE))
#define BIT_SHIFT_CHCNR03_CH3RE 0
#define BIT_MASK_CHCNR03_CH3RE 0x1
#define BIT_CHCNR03_CH3RE(x) (((x) & BIT_MASK_CHCNR03_CH3RE) << BIT_SHIFT_CHCNR03_CH3RE)
#define BIT_INV_CHCNR03_CH3RE (~(BIT_MASK_CHCNR03_CH3RE << BIT_SHIFT_CHCNR03_CH3RE))
#define BIT_SHIFT_CHCNR03_CH3TE 1
#define BIT_MASK_CHCNR03_CH3TE 0x1
#define BIT_CHCNR03_CH3TE(x) (((x) & BIT_MASK_CHCNR03_CH3TE) << BIT_SHIFT_CHCNR03_CH3TE)
#define BIT_INV_CHCNR03_CH3TE (~(BIT_MASK_CHCNR03_CH3TE << BIT_SHIFT_CHCNR03_CH3TE))
#define BIT_SHIFT_CHCNR03_CH0MUA 26
#define BIT_MASK_CHCNR03_CH0MUA 0x1
#define BIT_CHCNR03_CH0MUA(x) (((x) & BIT_MASK_CHCNR03_CH0MUA) << BIT_SHIFT_CHCNR03_CH0MUA)
#define BIT_INV_CHCNR03_CH0MUA (~(BIT_MASK_CHCNR03_CH0MUA << BIT_SHIFT_CHCNR03_CH0MUA))
#define BIT_SHIFT_CHCNR03_CH0BAND 27
#define BIT_MASK_CHCNR03_CH0BAND 0x1
#define BIT_CHCNR03_CH0BAND(x) (((x) & BIT_MASK_CHCNR03_CH0BAND) << BIT_SHIFT_CHCNR03_CH0BAND)
#define BIT_INV_CHCNR03_CH0BAND (~(BIT_MASK_CHCNR03_CH0BAND << BIT_SHIFT_CHCNR03_CH0BAND))
#define BIT_SHIFT_TSR03_CH0TSA 24
#define BIT_MASK_TSR03_CH0TSA 0x1F
#define BIT_TSR03_CH0TSA(x) (((x) & BIT_MASK_TSR03_CH0TSA) << BIT_SHIFT_TSR03_CH0TSA)
#define BIT_INV_TSR03_CH0TSA (~(BIT_MASK_TSR03_CH0TSA << BIT_SHIFT_TSR03_CH0TSA))
#define BIT_SHIFT_BSIZE03_CH0BSIZE 24
#define BIT_MASK_BSIZE03_CH0BSIZE 0xFF
#define BIT_BSIZE03_CH0BSIZE(x) (((x) & BIT_MASK_BSIZE03_CH0BSIZE) << BIT_SHIFT_BSIZE03_CH0BSIZE)
#define BIT_INV_BSIZE03_CH0BSIZE (~(BIT_MASK_BSIZE03_CH0BSIZE << BIT_SHIFT_BSIZE03_CH0BSIZE))
typedef struct _PCM_CTL_REG_ {
u32 FCNT :8; // Bit 0-7
u32 SlaveMode :1; // Bit 8
u32 FsInv :1; // Bit 9
u32 Rsvd10to11 :1; // Bit 10-11
u32 Pcm_En :1; // Bit 12
u32 LinearMode :1; // Bit 13
u32 LoopBack :1; // Bit 14
u32 Rsvd15to16 :2; // Bit 15-16
u32 EndianSwap :1; // Bit 17
u32 Rsvd18to31 :14; // Bit 18-31
} PCM_CTL_REG, *PPCM_CTL_REG;
typedef struct _PCM_CHCNR03_REG_ {
u32 CH3RE :1; // Bit 0
u32 CH3TE :1; // Bit 1
u32 CH3MuA :1; // Bit 2
u32 CH3Band :1; // Bit 3
u32 CH3SlicSel:4; // Bit 4-7
u32 CH2RE :1; // Bit 8
u32 CH2TE :1; // Bit 9
u32 CH2MuA :1; // Bit 10
u32 CH2Band :1; // Bit 11
u32 CH2SlicSel:4; // Bit 12-15
u32 CH1RE :1; // Bit 16
u32 CH1TE :1; // Bit 17
u32 CH1MuA :1; // Bit 18
u32 CH1Band :1; // Bit 19
u32 CH1SlicSel:4; // Bit 20-23
u32 CH0RE :1; // Bit 24
u32 CH0TE :1; // Bit 25
u32 CH0MuA :1; // Bit 26
u32 CH0Band :1; // Bit 27
u32 CH0SlicSel:4; // Bit 28-31
}PCM_CHCNR03_REG, *PPCM_CHCNR03_REG;
typedef struct _PCM_TSR03_REG_ {
u32 CH3TSA :5; // Bit 0-4
u32 Rsvd5to7 :3; // Bit 5-7
u32 CH2TSA :5; // Bit 8-12
u32 Rsvd13to15:3; // Bit 13-15
u32 CH1TSA :5; // Bit 16-20
u32 Rsvd21to23:3; // Bit 21-23
u32 CH0TSA :5; // Bit 24-28
u32 Rsvd29to31:3; // Bit 29-31
}PCM_TSR03_REG, *PPCM_TSR03_REG;
typedef struct _PCM_BSIZE03_REG_ {
u32 CH3BSize :8; // Bit 0-7
u32 CH2BSize :8; // Bit 8-15
u32 CH1BSize :8; // Bit 16-23
u32 CH0BSize :8; // Bit 24-31
}PCM_BSIZE03_REG, *PPCM_BSIZE03_REG;
typedef struct _PCM_ISR03_REG_ {
u32 CH3RXP1UA :1; // Bit 0
u32 CH3RXP0UA :1; // Bit 1
u32 CH3TXP1UA :1; // Bit 2
u32 CH3TXP0UA :1; // Bit 3
u32 CH3RXP1IP :1; // Bit 4
u32 CH3RXP0IP :1; // Bit 5
u32 CH3TXP1IP :1; // Bit 6
u32 CH3TXP0IP :1; // Bit 7
u32 CH2RXP1UA :1; // Bit 8
u32 CH2RXP0UA :1; // Bit 9
u32 CH2TXP1UA :1; // Bit 10
u32 CH2TXP0UA :1; // Bit 11
u32 CH2RXP1IP :1; // Bit 12
u32 CH2RXP0IP :1; // Bit 13
u32 CH2TXP1IP :1; // Bit 14
u32 CH2TXP0IP :1; // Bit 15
u32 CH1RXP1UA :1; // Bit 16
u32 CH1RXP0UA :1; // Bit 17
u32 CH1TXP1UA :1; // Bit 18
u32 CH1TXP0UA :1; // Bit 19
u32 CH1RXP1IP :1; // Bit 20
u32 CH1RXP0IP :1; // Bit 21
u32 CH1TXP1IP :1; // Bit 22
u32 CH1TXP0IP :1; // Bit 23
u32 CH0RXP1UA :1; // Bit 24
u32 CH0RXP0UA :1; // Bit 25
u32 CH0TXP1UA :1; // Bit 26
u32 CH0TXP0UA :1; // Bit 27
u32 CH0RXP1IP :1; // Bit 28
u32 CH0RXP0IP :1; // Bit 29
u32 CH0TXP1IP :1; // Bit 30
u32 CH0TXP0IP :1; // Bit 31
}PCM_ISR03_REG, *PPCM_ISR03_REG;
typedef enum _PCM_ISR015 {
PcmCh3P1RBU = 0x00000001, //ch0-3
PcmCh3P0RBU = 0x00000002,
PcmCh3P1TBU = 0x00000004,
PcmCh3P0TBU = 0x00000008,
PcmCh3P1ROK = 0x00000010,
PcmCh3P0ROK = 0x00000020,
PcmCh3P1TOK = 0x00000040,
PcmCh3P0TOK = 0x00000080,
PcmCh2P1RBU = 0x00000100,
PcmCh2P0RBU = 0x00000200,
PcmCh2P1TBU = 0x00000400,
PcmCh2P0TBU = 0x00000800,
PcmCh2P1ROK = 0x00001000,
PcmCh2P0ROK = 0x00002000,
PcmCh2P1TOK = 0x00004000,
PcmCh2P0TOK = 0x00008000,
PcmCh1P1RBU = 0x00010000,
PcmCh1P0RBU = 0x00020000,
PcmCh1P1TBU = 0x00040000,
PcmCh1P0TBU = 0x00080000,
PcmCh1P1ROK = 0x00100000,
PcmCh1P0ROK = 0x00200000,
PcmCh1P1TOK = 0x00400000,
PcmCh1P0TOK = 0x00800000,
PcmCh0P1RBU = 0x01000000,
PcmCh0P0RBU = 0x02000000,
PcmCh0P1TBU = 0x04000000,
PcmCh0P0TBU = 0x08000000,
PcmCh0P1ROK = 0x10000000,
PcmCh0P0ROK = 0x20000000,
PcmCh0P1TOK = 0x40000000,
PcmCh0P0TOK = 0x80000000,
PcmCh7P1RBU = 0x00000001, //ch4-7
PcmCh7P0RBU = 0x00000002,
PcmCh7P1TBU = 0x00000004,
PcmCh7P0TBU = 0x00000008,
PcmCh7P1ROK = 0x00000010,
PcmCh7P0ROK = 0x00000020,
PcmCh7P1TOK = 0x00000040,
PcmCh7P0TOK = 0x00000080,
PcmCh6P1RBU = 0x00000100,
PcmCh6P0RBU = 0x00000200,
PcmCh6P1TBU = 0x00000400,
PcmCh6P0TBU = 0x00000800,
PcmCh6P1ROK = 0x00001000,
PcmCh6P0ROK = 0x00002000,
PcmCh6P1TOK = 0x00004000,
PcmCh6P0TOK = 0x00008000,
PcmCh5P1RBU = 0x00010000,
PcmCh5P0RBU = 0x00020000,
PcmCh5P1TBU = 0x00040000,
PcmCh5P0TBU = 0x00080000,
PcmCh5P1ROK = 0x00100000,
PcmCh5P0ROK = 0x00200000,
PcmCh5P1TOK = 0x00400000,
PcmCh5P0TOK = 0x00800000,
PcmCh4P1RBU = 0x01000000,
PcmCh4P0RBU = 0x02000000,
PcmCh4P1TBU = 0x04000000,
PcmCh4P0TBU = 0x08000000,
PcmCh4P1ROK = 0x10000000,
PcmCh4P0ROK = 0x20000000,
PcmCh4P1TOK = 0x40000000,
PcmCh4P0TOK = 0x80000000,
PcmCh11P1RBU = 0x00000001, //ch8-11
PcmCh11P0RBU = 0x00000002,
PcmCh11P1TBU = 0x00000004,
PcmCh11P0TBU = 0x00000008,
PcmCh11P1ROK = 0x00000010,
PcmCh11P0ROK = 0x00000020,
PcmCh11P1TOK = 0x00000040,
PcmCh11P0TOK = 0x00000080,
PcmCh10P1RBU = 0x00000100,
PcmCh10P0RBU = 0x00000200,
PcmCh10P1TBU = 0x00000400,
PcmCh10P0TBU = 0x00000800,
PcmCh10P1ROK = 0x00001000,
PcmCh10P0ROK = 0x00002000,
PcmCh10P1TOK = 0x00004000,
PcmCh10P0TOK = 0x00008000,
PcmCh9P1RBU = 0x00010000,
PcmCh9P0RBU = 0x00020000,
PcmCh9P1TBU = 0x00040000,
PcmCh9P0TBU = 0x00080000,
PcmCh9P1ROK = 0x00100000,
PcmCh9P0ROK = 0x00200000,
PcmCh9P1TOK = 0x00400000,
PcmCh9P0TOK = 0x00800000,
PcmCh8P1RBU = 0x01000000,
PcmCh8P0RBU = 0x02000000,
PcmCh8P1TBU = 0x04000000,
PcmCh8P0TBU = 0x08000000,
PcmCh8P1ROK = 0x10000000,
PcmCh8P0ROK = 0x20000000,
PcmCh8P1TOK = 0x40000000,
PcmCh8P0TOK = 0x80000000,
PcmCh15P1RBU = 0x00000001, //ch12-15
PcmCh15P0RBU = 0x00000002,
PcmCh15P1TBU = 0x00000004,
PcmCh15P0TBU = 0x00000008,
PcmCh15P1ROK = 0x00000010,
PcmCh15P0ROK = 0x00000020,
PcmCh15P1TOK = 0x00000040,
PcmCh15P0TOK = 0x00000080,
PcmCh14P1RBU = 0x00000100,
PcmCh14P0RBU = 0x00000200,
PcmCh14P1TBU = 0x00000400,
PcmCh14P0TBU = 0x00000800,
PcmCh14P1ROK = 0x00001000,
PcmCh14P0ROK = 0x00002000,
PcmCh14P1TOK = 0x00004000,
PcmCh14P0TOK = 0x00008000,
PcmCh13P1RBU = 0x00010000,
PcmCh13P0RBU = 0x00020000,
PcmCh13P1TBU = 0x00040000,
PcmCh13P0TBU = 0x00080000,
PcmCh13P1ROK = 0x00100000,
PcmCh13P0ROK = 0x00200000,
PcmCh13P1TOK = 0x00400000,
PcmCh13P0TOK = 0x00800000,
PcmCh12P1RBU = 0x01000000,
PcmCh12P0RBU = 0x02000000,
PcmCh12P1TBU = 0x04000000,
PcmCh12P0TBU = 0x08000000,
PcmCh12P1ROK = 0x10000000,
PcmCh12P0ROK = 0x20000000,
PcmCh12P1TOK = 0x40000000,
PcmCh12P0TOK = 0x80000000
}PCM_ISR015, *PPCM_ISR015;
VOID
HalPcmOnOffRtl8195a(
IN VOID *Data
);
BOOL
HalPcmInitRtl8195a(
IN VOID *Data
);
BOOL
HalPcmSettingRtl8195a(
IN VOID *Data
);
BOOL
HalPcmEnRtl8195a(
IN VOID *Data
);
BOOL
HalPcmIsrEnAndDisRtl8195a(
IN VOID *Data
);
BOOL
HalPcmDumpRegRtl8195a(
IN VOID *Data
);
BOOL
HalPcmRtl8195a(
IN VOID *Data
);
#endif /* _RTL8195A_PCM_H_ */

1251
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h Normal file
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37
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_PWM_H_
#define _RTL8195A_PWM_H_
extern void
HAL_Pwm_SetDuty_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern HAL_Status
HAL_Pwm_Init_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Enable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Disable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
#endif

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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_SDIO_H_
#define _RTL8195A_SDIO_H_
#include "hal_api.h"
#include "hal_util.h"
#if defined(CONFIG_SDIO_BOOT_SIM) || defined(CONFIG_SDIO_BOOT_ROM)
#define SDIO_BOOT_DRIVER 1 // is this SDIO driver works for booting
#else
#include "osdep_api.h"
#define SDIO_BOOT_DRIVER 0 // is this SDIO driver works for booting
#endif
#define SDIO_DEBUG 1
#define SDIO_MP_MODE 1 // if includes MP mode function
#define SDIO_MAX_WAIT_RX_DMA 100 // Wait RX DMA done
#define SDIO_RX_PKT_SIZE_OVER_16K 0 /* is support SDIO RX packet size > 16K. if true,
a big packet will be transmited via multiple RX_BD */
#define SDIO_MAILBOX_SIZE 10 // the maximum number of message block can be stored in this mailbox
#define SDIO_PERIODICAL_TIMER_INTERVAL 2000 // in ms, the interval of SDIO periodical timer
#define SDIO_AVG_TP_WIN_SIZE 20 // the number of entry to log the byte count for every periodical timer statistic, to calculate throughput
#define HAL_SDIO_READ32(addr) HAL_READ32(SDIO_DEVICE_REG_BASE, addr)
#define HAL_SDIO_WRITE32(addr, value) HAL_WRITE32(SDIO_DEVICE_REG_BASE, addr, value)
#define HAL_SDIO_READ16(addr) HAL_READ16(SDIO_DEVICE_REG_BASE, addr)
#define HAL_SDIO_WRITE16(addr, value) HAL_WRITE16(SDIO_DEVICE_REG_BASE, addr, value)
#define HAL_SDIO_READ8(addr) HAL_READ8(SDIO_DEVICE_REG_BASE, addr)
#define HAL_SDIO_WRITE8(addr, value) HAL_WRITE8(SDIO_DEVICE_REG_BASE, addr, value)
/***** Register Address *****/
#define REG_SPDIO_TXBD_ADDR 0xA0 // 4 Bytes
#define REG_SPDIO_TXBD_SIZE 0xA4 // 4 Bytes
#define REG_SPDIO_TXBD_WPTR 0xA8 // 2 Bytes
#define REG_SPDIO_TXBD_RPTR 0xAC // 2 Bytes
#define REG_SPDIO_RXBD_ADDR 0xB0 // 4 Bytes
#define REG_SPDIO_RXBD_SIZE 0xB4 // 2 Bytes
#define REG_SPDIO_RXBD_C2H_WPTR 0xB6 // 2 Bytes
#define REG_SPDIO_RXBD_C2H_RPTR 0xB8 // 2 Bytes
#define REG_SPDIO_HCI_RX_REQ 0xBA // 1 Byte
#define REG_SPDIO_CPU_RST_DMA 0xBB // 1 Byte
#define REG_SPDIO_RX_REQ_ADDR 0xBC // 2 Bytes
#define REG_SPDIO_CPU_INT_MASK 0xC0 // 2 Bytes
#define REG_SPDIO_CPU_INT_STAS 0xC2 // 2 Bytes
#define REG_SPDIO_CCPWM 0xC4 // 1 Byts
#define REG_SPDIO_CPU_IND 0xC5 // 1 Byte
#define REG_SPDIO_CCPWM2 0xC6 // 2 Bytes
#define REG_SPDIO_CPU_H2C_MSG 0xC8 // 4 Bytes
#define REG_SPDIO_CPU_C2H_MSG 0xCC // 4 Bytes
#define REG_SPDIO_CRPWM 0xD0 // 1 Bytes
#define REG_SPDIO_CRPWM2 0xD2 // 2 Bytes
#define REG_SPDIO_AHB_DMA_CTRL 0xD4 // 4 Bytes
#define REG_SPDIO_RXBD_CNT 0xD8 // 4 Bytes
#define REG_SPDIO_TX_BUF_UNIT_SZ 0xD9 // 1 Bytes
#define REG_SPDIO_RX_BD_FREE_CNT 0xDA // 2 Bytes
#define REG_SPDIO_CPU_H2C_MSG_EXT 0xDC // 4 Bytes
#define REG_SPDIO_CPU_C2H_MSG_EXT 0xE0 // 4 Bytes
// Register REG_SPDIO_CPU_RST_DMA
#define BIT_CPU_RST_SDIO_DMA BIT(7)
// Register REG_SPDIO_CPU_INT_MASK, REG_SPDIO_CPU_INT_STAS
#define BIT_TXFIFO_H2C_OVF BIT(0)
#define BIT_H2C_BUS_RES_FAIL BIT(1)
#define BIT_H2C_DMA_OK BIT(2)
#define BIT_C2H_DMA_OK BIT(3)
#define BIT_H2C_MSG_INT BIT(4)
#define BIT_RPWM1_INT BIT(5)
#define BIT_RPWM2_INT BIT(6)
#define BIT_SDIO_RST_CMD_INT BIT(7)
#define BIT_RXBD_FLAG_ERR_INT BIT(8)
#define BIT_RX_BD_AVAI_INT BIT(9)
#define BIT_HOST_WAKE_CPU_INT BIT(10)
// Register REG_SPDIO_CPU_IND
#define BIT_SYSTEM_TRX_RDY_IND BIT(0)
// Register REG_SPDIO_HCI_RX_REQ
#define BIT_HCI_RX_REQ BIT(0)
/* Register for SOC_HCI_COM_FUN_EN */
#define BIT_SOC_HCI_SDIOD_OFF_EN BIT(1) // SDIO Function Block on Power_Off domain
#define BIT_SOC_HCI_SDIOD_ON_EN BIT(0) // SDIO Function Block on Power_On domain
/* Register REG_PESOC_HCI_CLK_CTRL0 */
#define BIT_SOC_SLPCK_SDIO_HST_EN BIT(3) // SDIO_HST clock enable when CPU sleep command
#define BIT_SOC_ACTCK_SDIO_HST_EN BIT(2) // SDIO_HST clock enable in CPU run mode
#define BIT_SOC_SLPCK_SDIO_DEV_EN BIT(1) // SDIO_DEV clock enable when CPU sleep command
#define BIT_SOC_ACTCK_SDIO_DEV_EN BIT(0) // SDIO_DEV clock enable in CPU run mode
/***** Structer for each Register *****/
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
// Little Endian
// Register REG_SPDIO_HCI_RX_REQ @ 0xBA
typedef struct _SPDIO_HCI_RX_REQ {
u8 HCI_RX_REQ:1; /* bit[0], CPU trigger this bit to enable SDIO IP RX transfer by fetch BD info */
u8 Reserved:7; /* bit[7:1], Reserved */
} SPDIO_HCI_RX_REQ, *PSPDIO_HCI_RX_REQ;
// Register REG_SPDIO_CPU_RST_DMA @ 0xBB
typedef struct _SPDIO_CPU_RST_DMA {
u8 Reserved:7; /* bit[6:0], Reserved */
u8 CPU_RST_SDIO:1; /* bit[7], CPU set this bit to reset SDIO DMA */
} SPDIO_CPU_RST_DMA, *PSPDIO_CPU_RST_DMA;
// Register REG_SPDIO_CPU_INT_MASK @ 0xC0
typedef struct _SPDIO_CPU_INT_MASK {
u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */
u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */
u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */
u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */
u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */
u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */
u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */
u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */
u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */
u16 Reserved:7; /* bit[15:9], Reserved */
} SPDIO_CPU_INT_MASK, *PSPDIO_CPU_INT_MASK;
// Register REG_SPDIO_CPU_INT_STATUS @ 0xC2
typedef struct _SPDIO_CPU_INT_STAS {
u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */
u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */
u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */
u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */
u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */
u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */
u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */
u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */
u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */
u16 Reserved:7; /* bit[15:9], Reserved */
} SPDIO_CPU_INT_STAS, *PSPDIO_CPU_INT_STAS;
// Register REG_SPDIO_CCPWM @ 0xC4
typedef struct _SPDIO_CCPWM {
u8 :1; /* bit[0] */
u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */
u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */
u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */
u8 Reserved:3; /* bit[6:4], Reserved */
u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */
} SPDIO_CCPWM, *PSPDIO_CCPWM;
// Register REG_SPDIO_CPU_IND @ 0xC5
typedef struct _SPDIO_CPU_IND {
u8 SYS_TRX_RDY:1; /* bit[0], To indicate the Host system that CPU is ready for TRX
, to be sync to 0x87[0] */
u8 Reserved:7; /* bit[7:1], Reserved */
} SPDIO_CPU_IND, *PSPDIO_CPU_IND;
// Register REG_SPDIO_CPU_H2C_MSG @ 0xC8
typedef struct _SPDIO_CPU_H2C_MSG {
u32 CPU_H2C_MSG:30; /* bit[30:0], Host CPU to FW message, sync from REG_SDIO_H2C_MSG */
u32 Reserved:1; /* bit[31], Reserved */
} SPDIO_CPU_H2C_MSG, *PSPDIO_CPU_H2C_MSG;
// Register REG_SPDIO_CPU_C2H_MSG @ 0xCC
typedef struct _SPDIO_CPU_C2H_MSG {
u32 CPU_C2H_MSG:30; /* bit[30:0], FW to Host CPU message, sync to REG_SDIO_C2H_MSG */
u32 Reserved:1; /* bit[31], Reserved */
} SPDIO_CPU_C2H_MSG, *PSPDIO_CPU_C2H_MSG;
// Register REG_SPDIO_CRPWM @ 0xD0
typedef struct _SPDIO_CRPWM {
u8 :1; /* bit[0] */
u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */
u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */
u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */
u8 Reserved:3; /* bit[6:4], Reserved */
u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */
} SPDIO_CRPWM, *PSPDIO_CRPWM;
// Register REG_SPDIO_AHB_DMA_CTRL @ 0xD4
typedef struct _SPDIO_AHB_DMA_CTRL {
u32 TXFF_WLEVEL:7; /* bit[6:0], SPDIO TX FIFO water level */
u32 :1; /* bit[7] */
u32 RXFF_WLEVEL:7; /* bit[14:8], SPDIO RX FIFO water level */
u32 :1; /* bit[15] */
u32 AHB_DMA_CS:4; /* bit[19:16], AHB DMA state */
u32 :1; /* bit[20] */
u32 AHB_MASTER_RDY:1; /* bit[21], AHB Master Hready signal */
u32 AHB_DMA_TRANS:2; /* bit[23:22], AHB DMA Trans value, for debugging */
u32 AHB_BUSY_WAIT_CNT:4; /* bit[27:24], timeout for AHB controller to wait busy */
u32 AHB_BURST_TYPE:3; /* bit[30:28], AHB burst type */
u32 DISPATCH_TXAGG:1; /* bit[31], Enable to dispatch aggregated TX packet */
} SPDIO_AHB_DMA_CTRL, *PSPDIO_AHB_DMA_CTRL;
#else /* else of '#if LITTLE_ENDIAN' */
// Big Endian
typedef struct _SPDIO_HCI_RX_REQ {
u8 Reserved:7; /* bit[7:1], Reserved */
u8 HCI_RX_REQ:1; /* bit[0], CPU trigger this bit to enable SDIO IP RX transfer by fetch BD info */
} SPDIO_HCI_RX_REQ, *PSPDIO_HCI_RX_REQ;
// Register REG_SPDIO_CPU_RST_DMA @ 0xBB
typedef struct _SPDIO_CPU_RST_DMA {
u8 CPU_RST_SDIO:1; /* bit[7], CPU set this bit to reset SDIO DMA */
u8 Reserved:7; /* bit[6:0], Reserved */
} SPDIO_CPU_RST_DMA, *PSPDIO_CPU_RST_DMA;
// Register REG_SPDIO_CPU_INT_MASK @ 0xC0
typedef struct _SPDIO_CPU_INT_MASK {
u16 Reserved:7; /* bit[15:9], Reserved */
u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */
u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */
u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */
u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */
u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */
u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */
u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */
u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */
u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */
} SPDIO_CPU_INT_MASK, *PSPDIO_CPU_INT_MASK;
// Register REG_SPDIO_CPU_INT_STAS @ 0xC2
typedef struct _SPDIO_CPU_INT_STAS {
u16 Reserved:7; /* bit[15:9], Reserved */
u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */
u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */
u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */
u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */
u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */
u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */
u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */
u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */
u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */
} SPDIO_CPU_INT_STAS, *PSPDIO_CPU_INT_STAS;
// Register REG_SPDIO_CCPWM @ 0xC4
typedef struct _SPDIO_CCPWM {
u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */
u8 Reserved:3; /* bit[6:4], Reserved */
u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */
u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */
u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */
u8 :1; /* bit[0] */
} SPDIO_CCPWM, *PSPDIO_CCPWM;
// Register REG_SPDIO_CPU_IND @ 0xC5
typedef struct _SPDIO_CPU_IND {
u8 Reserved:7; /* bit[7:1], Reserved */
u8 SYS_TRX_RDY:1; /* bit[0], To indicate the Host system that CPU is ready for TRX
, to be sync to 0x87[0] */
} SPDIO_CPU_IND, *PSPDIO_CPU_IND;
// Register REG_SPDIO_CPU_H2C_MSG @ 0xC8
typedef struct _SPDIO_CPU_H2C_MSG {
u32 Reserved:1; /* bit[31], Reserved */
u32 CPU_H2C_MSG:30; /* bit[30:0], Host CPU to FW message */
} SPDIO_CPU_H2C_MSG, *PSPDIO_CPU_H2C_MSG;
// Register REG_SPDIO_CPU_C2H_MSG @ 0xCC
typedef struct _SPDIO_CPU_C2H_MSG {
u32 Reserved:1; /* bit[31], Reserved */
u32 CPU_C2H_MSG:30; /* bit[30:0], FW to Host CPU message, sync to REG_SDIO_C2H_MSG */
} SPDIO_CPU_C2H_MSG, *PSPDIO_CPU_C2H_MSG;
// Register REG_SPDIO_CRPWM @ 0xD0
typedef struct _SPDIO_CRPWM {
u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */
u8 Reserved:3; /* bit[6:4], Reserved */
u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */
u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */
u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */
u8 :1; /* bit[0] */
} SPDIO_CRPWM, *PSPDIO_CRPWM;
// Register REG_SPDIO_AHB_DMA_CTRL @ 0xD4
typedef struct _SPDIO_AHB_DMA_CTRL {
u32 DISPATCH_TXAGG:1; /* bit[31], Enable to dispatch aggregated TX packet */
u32 AHB_BURST_TYPE:3; /* bit[30:28], AHB burst type */
u32 AHB_BUSY_WAIT_CNT:4; /* bit[27:24], timeout for AHB controller to wait busy */
u32 AHB_DMA_TRANS:2; /* bit[23:22], AHB DMA Trans value, for debugging */
u32 AHB_MASTER_RDY:1; /* bit[21], AHB Master Hready signal */
u32 :1; /* bit[20] */
u32 AHB_DMA_CS:4; /* bit[19:16], AHB DMA state */
u32 :1; /* bit[15] */
u32 RXFF_WLEVEL:7; /* bit[14:8], SPDIO RX FIFO water level */
u32 :1; /* bit[7] */
u32 TXFF_WLEVEL:7; /* bit[6:0], SPDIO TX FIFO water level */
} SPDIO_AHB_DMA_CTRL, *PSPDIO_AHB_DMA_CTRL;
#endif /* end of '#if LITTLE_ENDIAN' */
//#define TX_FIFO_ADDR 0x0000
//#define TX_FIFO_SIZE 0x8000
//TX BD setting
#if SDIO_BOOT_DRIVER
// for build ROM library
#define SDIO_TX_BD_NUM 2 // Number of TX BD
#define SDIO_TX_BD_BUF_SIZE (2048+32) // the size of a TX BD pointed buffer, WLan header = 26 bytes
#define SDIO_TX_PKT_NUM 10 // Number of TX packet handler
//RX BD setting
#define RX_BD_FREE_TH 4 // trigger the interrupt when free RX BD over this threshold
#define MAX_RX_BD_BUF_SIZE 16380 // the Maximum size for a RX_BD point to, make it 4-bytes aligned
#define SDIO_RX_PKT_NUM 3 // Number of RX packet handler
//#define SDIO_RX_BD_NUM 10 // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least
#define SDIO_RX_BD_NUM (SDIO_RX_PKT_NUM*2) // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least
#define SDIO_RX_BD_BUF_SIZE (2048+24) // the size of a RX BD pointed buffer, sizeof(RX Desc) = 26 bytes
#define MIN_RX_BD_SEND_PKT 2 /* the minum needed RX_BD to send a Packet to Host, we need 2:
one for RX_Desc, the other for payload */
// CCPWM2 bit map definition for Firmware download
#define SDIO_INIT_DONE (BIT0)
#define SDIO_MEM_WR_DONE (BIT1)
#define SDIO_MEM_RD_DONE (BIT2)
#define SDIO_MEM_ST_DONE (BIT3)
#define SDIO_CPWM2_TOGGLE (BIT15)
#else
#define SDIO_TX_BD_NUM 24 // Number of TX BD
#define SDIO_TX_BD_BUF_SIZE (2048+32) // the size of a TX BD pointed buffer, WLan header = 26 bytes
#define SDIO_TX_PKT_NUM 128 // Number of TX packet handler
//RX BD setting
#define RX_BD_FREE_TH 5 // trigger the interrupt when free RX BD over this threshold
#define SDIO_RX_BD_BUF_SIZE 2048
#define MAX_RX_BD_BUF_SIZE 16380 // the Maximum size for a RX_BD point to, make it 4-bytes aligned
//#define SDIO_TX_FIFO_SIZE (1024*64) // 64K
#define SDIO_RX_BD_NUM 24 // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least
#define SDIO_RX_PKT_NUM 128 // Number of RX packet handler
#define MIN_RX_BD_SEND_PKT 2 /* the minum needed RX_BD to send a Packet to Host, we need 2:
one for RX_Desc, the other for payload */
#endif
#define SDIO_IRQ_PRIORITY 10
/* SDIO Events */
#define SDIO_EVENT_IRQ BIT(0) // Interrupt triggered
#define SDIO_EVENT_RX_PKT_RDY BIT(1) // A new SDIO packet ready
#define SDIO_EVENT_C2H_DMA_DONE BIT(2) // Interrupt of C2H DMA done triggered
#define SDIO_EVENT_DUMP BIT(3) // SDIO status dump periodically Enable
#define SDIO_EVENT_TXBD_REFILL BIT(4) // To refill TX BD buffer
#define SDIO_EVENT_EXIT BIT(28) // Request to exit the SDIO task
#define SDIO_EVENT_MP_STOPPED BIT(29) // The SDIO task is stopped
#define SDIO_EVENT_TX_STOPPED BIT(30) // The SDIO task is stopped
#define SDIO_EVENT_RX_STOPPED BIT(31) // The SDIO task is stopped
#define SDIO_TASK_PRIORITY 1 // it can be 0(lowest) ~ configMAX_PRIORITIES-1(highest)
#define SDIO_MP_TASK_PRIORITY 2 // it can be 0(lowest) ~ configMAX_PRIORITIES-1(highest)
//#if SDIO_TASK_PRIORITY > (configMAX_PRIORITIES - 1)
#if SDIO_TASK_PRIORITY > (4 - 1)
#error "SDIO Task Priority Should be 0~(configMAX_PRIORITIES-1)"
#endif
//#define TX_RX_PACKET_SIZE 0x144
typedef struct _SDIO_TX_BD_ {
u32 Address; /* The TX buffer physical address, it must be 4-bytes aligned */
}SDIO_TX_BD, *PSDIO_TX_BD;
#define TX_BD_STRUCTURE_SIZE (sizeof(SDIO_TX_BD))
/* The RX Buffer Descriptor format */
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
typedef struct _SDIO_RX_BD_ {
u32 BuffSize:14; /* bit[13:0], RX Buffer Size, Maximum 16384-1 */
u32 LS:1; /* bit[14], is the Last Segment ? */
u32 FS:1; /* bit[15], is the First Segment ? */
u32 Seq:16; /* bit[31:16], The sequence number, it's no use for now */
u32 PhyAddr; /* The RX buffer physical address, it must be 4-bytes aligned */
} SDIO_RX_BD, *PSDIO_RX_BD;
#else
typedef struct _SDIO_RX_BD_ {
u32 Seq:16; /* bit[31:16], The sequence number, be used for ?? */
u32 FS:1; /* bit[15], is the First Segment ? */
u32 LS:1; /* bit[14], is the Last Segment ? */
u32 BuffSize:14; /* bit[13:0], RX Buffer Size, Maximum 16384 */
u32 PhyAddr; /* The RX buffer physical address, it must be 4-bytes aligned */
} SDIO_RX_BD, *PSDIO_RX_BD;
#endif
#define RX_BD_STRUCTURE_SIZE (sizeof(SDIO_RX_BD))
// TODO: This data structer just for test, we should modify it for the normal driver
typedef struct _SDIO_TX_DESC{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 rsvd0:24;
#else
u32 rsvd0:24;
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 rsvd1;
// u4Byte 3
u32 rsvd2;
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} SDIO_TX_DESC, *PSDIO_TX_DESC;
// TX Desc for Memory Write command
typedef struct _SDIO_TX_DESC_MW{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 reply:1; // bit[8], request to send a reply message
u32 rsvd0:23;
#else
u32 rsvd0:23;
u32 reply:1; // bit[8], request to send a reply message
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 start_addr; // memory write start address
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 write_len:16; // bit[15:0], the length to write
u32 rsvd2:16; // bit[31:16]
#else
u32 rsvd2:16; // bit[31:16]
u32 write_len:16; // bit[15:0], the length to write
#endif
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} SDIO_TX_DESC_MW, *PSDIO_TX_DESC_MW;
// TX Desc for Memory Read command
typedef struct _SDIO_TX_DESC_MR{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 rsvd0:24;
#else
u32 rsvd0:24;
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 start_addr; // memory write start address
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 read_len:16; // bit[15:0], the length to read
u32 rsvd2:16; // bit[31:16]
#else
u32 rsvd2:16; // bit[31:16]
u32 read_len:16; // bit[15:0], the length to read
#endif
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} SDIO_TX_DESC_MR, *PSDIO_TX_DESC_MR;
// TX Desc for Memory Set command
typedef struct _SDIO_TX_DESC_MS{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 data:8; // bit[8:15], the value to be written to the memory
u32 reply:1; // bit[16], request to send a reply message
u32 rsvd0:15;
#else
u32 rsvd0:15;
u32 reply:1; // bit[16], request to send a reply message
u32 data:8; // bit[8:15], the value to be written to the memory
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 start_addr; // memory write start address
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 write_len:16; // bit[15:0], the length to write
u32 rsvd2:16; // bit[31:16]
#else
u32 rsvd2:16; // bit[31:16]
u32 write_len:16; // bit[15:0], the length to write
#endif
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} SDIO_TX_DESC_MS, *PSDIO_TX_DESC_MS;
// TX Desc for Jump to Start command
typedef struct _SDIO_TX_DESC_JS{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 rsvd0:24;
#else
u32 rsvd0:24;
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 start_fun; // the pointer of the startup function
// u4Byte 3
u32 rsvd2;
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} SDIO_TX_DESC_JS, *PSDIO_TX_DESC_JS;
#define SIZE_TX_DESC (sizeof(SDIO_TX_DESC))
// define the TX BD buffer size with unite of 64 byets
/* Be carefull!! the setting of hardware's TX BD buffer size may exceed the real size of
the TX BD buffer size, and then it may cause the hardware DMA write the buffer overflow */
#define SDIO_TX_BUF_SZ_UNIT 64
#define SDIO_TX_BD_BUF_USIZE ((((SDIO_TX_BD_BUF_SIZE+sizeof(SDIO_TX_DESC)-1)/SDIO_TX_BUF_SZ_UNIT)+1)&0xff)
typedef struct _SDIO_TX_BD_BUFFER_ {
SDIO_TX_DESC TX_Desc;
u8 TX_Buffer[SDIO_TX_BD_BUF_SIZE];
}SDIO_TX_BD_BUFFER, *PSDIO_TX_BD_BUFFER;
// TODO: This data structer just for test, we should modify it for the normal driver
typedef struct _SDIO_RX_DESC{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:6; // bit[29:24]
u32 icv:1; // bit[30], ICV error
u32 crc:1; // bit[31], CRC error
#else
u32 crc:1; // bit[31], CRC error
u32 icv:1; // bit[30], ICV error
u32 rsvd0:6; // bit[29:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 rsvd2;
// u4Byte 3
u32 rsvd3;
// u4Byte 4
u32 rsvd4;
// u4Byte 5
u32 rsvd5;
} SDIO_RX_DESC, *PSDIO_RX_DESC;
// For memory read command
typedef struct _SDIO_RX_DESC_MR{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:8; // bit[31:24]
#else
u32 rsvd0:8; // bit[31:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 start_addr;
// u4Byte 3
u32 rsvd2;
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} SDIO_RX_DESC_MR, *PSDIO_RX_DESC_MR;
// For memory write reply command
typedef struct _SDIO_RX_DESC_MW{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:8; // bit[31:24]
#else
u32 rsvd0:8; // bit[31:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 start_addr;
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 write_len:16; // bit[15:0], the type of this packet
u32 result:8; // bit[23:16], the result of memory write command
u32 rsvd2:8; // bit[31:24]
#else
u32 rsvd2:8; // bit[31:24]
u32 result:8; // bit[23:16], the result of memory write command
u32 write_len:16; // bit[15:0], the type of this packet
#endif
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} SDIO_RX_DESC_MW, *PSDIO_RX_DESC_MW;
// For memory set reply command
typedef struct _SDIO_RX_DESC_MS{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:8; // bit[31:24]
#else
u32 rsvd0:8; // bit[31:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 start_addr;
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 write_len:16; // bit[15:0], the type of this packet
u32 result:8; // bit[23:16], the result of memory write command
u32 rsvd2:8; // bit[31:24]
#else
u32 rsvd2:8; // bit[31:24]
u32 result:8; // bit[23:16], the result of memory write command
u32 write_len:16; // bit[15:0], the type of this packet
#endif
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} SDIO_RX_DESC_MS, *PSDIO_RX_DESC_MS;
#define SIZE_RX_DESC (sizeof(SDIO_RX_DESC))
typedef struct _SDIO_RX_BD_BUFFER_ {
SDIO_RX_DESC RX_Desc;
u8 RX_Buffer[SDIO_RX_BD_BUF_SIZE];
}SDIO_RX_BD_BUFFER, *PSDIO_RX_BD_BUFFER;
/* The data structer for a packet fordwarding to the WLan driver to transmit it */
// TODO: This data structer just for test, we may need modify it for the normal driver
typedef struct _SDIO_TX_PACKET_ {
u8 *pHeader; // Point to the 1st byte of the packets
u16 PktSize; // the size (bytes) of this packet
_LIST list; // the link list to chain packets
u8 isDyna; // is Dynamic allocated
} SDIO_TX_PACKET, *PSDIO_TX_PACKET;
/* the data structer to bind a TX_BD with a TX Packet */
typedef struct _SDIO_TX_BD_HANDLE_ {
SDIO_TX_BD *pTXBD; // Point to the TX_BD buffer
SDIO_TX_PACKET *pPkt; // point to the Tx Packet
u8 isPktEnd; // For a packet over 1 BD , this flag to indicate is this BD contains a packet end
u8 isFree; // is this TX BD free
} SDIO_TX_BD_HANDLE, *PSDIO_TX_BD_HANDLE;
/* The data structer for a packet which from the WLan driver to send to the Host */
// TODO: This data structer just for test, we may need modify it for the normal driver
#if SDIO_BOOT_DRIVER
typedef struct _SDIO_RX_PACKET_ {
// SDIO_RX_DESC RxDesc; // The RX Descriptor for this packet, to be send to Host ahead this packet
u8 *pData; // point to the head of payload of this packet
u16 Offset; // the offset from the pData to the payload buffer
_LIST list; // the link list to chain packets
u8 PktBuf[SDIO_RX_BD_BUF_SIZE]; // the Rx_Desc + payload data buffer, the first 24 bytes is reserved for RX_DESC
} SDIO_RX_PACKET, *PSDIO_RX_PACKET;
#else
typedef struct _SDIO_RX_PACKET_ {
SDIO_RX_DESC RxDesc; // The RX Descriptor for this packet, to be send to Host ahead this packet
u8 *pData; // point to the head of payload of this packet
u16 Offset; // the offset from the pData to the payload buffer
_LIST list; // the link list to chain packets
u8 isDyna; // is Dynamic allocated
} SDIO_RX_PACKET, *PSDIO_RX_PACKET;
#endif
/* the data structer to bind a RX_BD with a RX Packet */
typedef struct _SDIO_RX_BD_HANDLE_ {
SDIO_RX_BD *pRXBD; // Point to the RX_BD buffer
SDIO_RX_PACKET *pPkt; // point to the Rx Packet
u8 isPktEnd; // For a packet over 1 BD , this flag to indicate is this BD contains a packet end
u8 isFree; // is this RX BD free (DMA done and its RX packet has been freed)
} SDIO_RX_BD_HANDLE, *PSDIO_RX_BD_HANDLE;
#if SDIO_MP_MODE
typedef struct _SDIO_MP_CMD_ {
u8 cmd_name[16];
u32 cmd_type;
} SDIO_MP_CMD, *PSDIO_MP_CMD;
typedef enum _SDIO_MP_CMD_TYPE_{
SDIO_MP_START=1,
SDIO_MP_STOP=2,
SDIO_MP_LOOPBACK=3,
SDIO_MP_STATUS=4,
SDIO_MP_READ_REG8=5,
SDIO_MP_READ_REG16=6,
SDIO_MP_READ_REG32=7,
SDIO_MP_WRITE_REG8=8,
SDIO_MP_WRITE_REG16=9,
SDIO_MP_WRITE_REG32=10,
SDIO_MP_WAKEUP=11, // wakeup the SDIO task manually, for debugging
SDIO_MP_DUMP=12, // start/stop to dump the SDIO status periodically
SDIO_MP_CTX=13, // setup continue TX test
SDIO_MP_CRX=14, // setup continue RX test
SDIO_MP_CRX_DA=15, // setup continue RX with dynamic allocate RX Buf test
SDIO_MP_CRX_STOP=16, // setup continue RX test
SDIO_MP_DBG_MSG=17, // Debug message On/Off
}SDIO_MP_CMD_TYPE;
typedef enum _SDIO_CRX_MODE_{
SDIO_CRX_STATIC_BUF = 1,
SDIO_CRX_DYNA_BUF = 2,
} SDIO_CRX_MODE;
typedef struct _SDIO_MP_RX_PACKET_ {
_LIST list; // this member MUST be the 1st one, the link list to chain packets
u8 *pData; // point to the head of payload of this packet
u16 Offset; // the offset from the pData to the payload
u16 DataLen; // the data length of this packet
} SDIO_MP_RX_PACKET, *PSDIO_MP_RX_PACKET;
#endif // end of '#if SDIO_MP_MODE'
#define SDIO_CMD_TX_ETH 0x83 // request to TX a 802.3 packet
#define SDIO_CMD_TX_WLN 0x81 // request to TX a 802.11 packet
#define SDIO_CMD_H2C 0x11 // H2C(host to device) command packet
#define SDIO_CMD_MEMRD 0x51 // request to read a block of memory data
#define SDIO_CMD_MEMWR 0x53 // request to write a block of memory
#define SDIO_CMD_MEMST 0x55 // request to set a block of memory with a value
#define SDIO_CMD_STARTUP 0x61 // request to jump to the start up function
#define SDIO_CMD_RX_ETH 0x82 // indicate a RX 802.3 packet
#define SDIO_CMD_RX_WLN 0x80 // indicate a RX 802.11 packet
#define SDIO_CMD_C2H 0x10 // C2H(device to host) command packet
#define SDIO_CMD_MEMRD_RSP 0x50 // response to memory block read command
#define SDIO_CMD_MEMWR_RSP 0x52 // response to memory write command
#define SDIO_CMD_MEMST_RSP 0x54 // response to memory set command
#define SDIO_CMD_STARTED 0x60 // indicate the program has jumped to the given function
#ifdef CONFIG_SDIO_DEVICE_VERIFY
#define TX_BD_STRUCTURE_NUM 10
#define RX_BD_STRUCTURE_NUM 10
#define TX_BD_BUFFER_SIZE 0x1000//0x2000//0x800
#define RX_BD_BUFFER_SIZE 0x400//0x800
#define SDIO_RAM_ADDR_BASE 0x20080000
#define SDIO_BUFFER_HEAD(addr) SDIO_RAM_ADDR_BASE + addr
#define HAL_SDIO_BUFFER_READ8(addr) HAL_READ8(SDIO_RAM_ADDR_BASE, addr)
#define HAL_SDIO_BUFFER_READ32(addr) HAL_READ32(SDIO_RAM_ADDR_BASE, addr)
#define HAL_SDIO_BUFFER_WRITE32(addr, value) HAL_WRITE32(SDIO_RAM_ADDR_BASE, addr, value)
//#define RX_BD_ADDR 0x8000
//#define RX_BUFFER_ADDR 0x8050
typedef enum _SDIO_TEST_FUNC_ {
SDIO_TEST_INIT, // 0
SDIO_TEST_INT_ON, // 1
SDIO_TEST_INT_OFF, // 2
SDIO_HCI_RX_REQ, // 3
SDIO_RESET_TXFIFIO, // 4
SDIO_CPU_RST_DMA, // 5
SDIO_CPU_CLR_INT_REG, // 6
SDIO_TIMER_TEST, // 7
SDIO_TEST_DEBUG, // 8
SDIO_TEST, // 9
SDIO_HELP = 0xff
}SDIO_TEST_FUNC, *PSDIO_TEST_FUNC;
typedef struct _SDIO_TEST_ADAPTER_ {
u32 TXWritePtr;
u32 TXReadPtr;
u16 RXWritePtr;
u16 RXReadPtr;
u16 IntMask;
u16 IntStatus;
} SDIO_TEST_ADAPTER, *PSDIO_TEST_ADAPTER;
VOID
MovePKTToRX(
IN u32 Source, IN u32 Destination, IN u32 PKTSize
);
BOOL
PacketProcess(
IN SDIO_TEST_ADAPTER *pDevStatus
);
VOID
SdioDeviceIrqHandleFunc(
IN VOID *DATA
);
VOID
SdioDeviceTestApp(
IN u32 Data
);
VOID
InitRXBD(VOID);
VOID
InitTXFIFO(VOID);
VOID
IrqRegister(VOID);
#endif // end of "#ifdef CONFIG_SDIO_DEVICE_VERIFY"
#endif /* #ifndef _RTL8195A_SDIO_H_ */

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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio_host.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_SDIO_HOST_H_
#define _RTL8195A_SDIO_HOST_H_
#include "hal_api.h"
#include "osdep_api.h"
#ifdef CONFIG_SDIO_HOST_VERIFY
#define HAL_MMC_HOST_READ32(addr) HAL_READ32(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE32(addr, value) HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value)
#define HAL_MMC_HOST_READ16(addr) HAL_READ16(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE16(addr, value) HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value)
#define HAL_MMC_HOST_READ8(addr) HAL_READ8(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE8(addr, value) HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value)
/* RTL8195A Register */
// REG_SOC_HCI_COM_FUNC_EN (0x214)
#define SD_DEVICE_IP_ON_BLK BIT0
#define SD_DEVICE_IP_OFF_BLK BIT1
#define SD_HOST_IP_BLK BIT2
// REG_PESOC_HCI_CLK_CTRL0 (0x240)
#define SD_HOST_CLKEN_IN_CPU_RUN_MODE BIT2
// REG_HCI_PINMUX_CTRL (0x2A0)
#define SD_DEVICE_MODE_PINMUX_EN BIT0
#define SD_HOST_MODE_PINMUX_EN BIT1
// 0x40059000
#define SD_HOST_CARD_DETECT_CIRCUIT BIT10
/* SD Host Register */
#define REG_SDMA_SYS_ADDR_ARG 0x00 // 4byte
#define REG_BLOCK_SIZE 0x04 // 2byte
#define REG_BLOCK_COUNT 0x06 // 2byte
#define REG_ARGUMENT1 0x08 // 4byte
#define REG_TRANSFER_MODE 0x0C // 2byte
#define REG_COMMAND 0x0E // 2byte
#define REG_RESPONSE0 0x10 // 4byte
#define REG_RESPONSE2 0x14 // 4byte
#define REG_RESPONSE4 0x18 // 4byte
#define REG_RESPONSE6 0x1C // 4byte
#define REG_BUFFER_DATA_PORT 0x20 // 4byte
#define REG_PRESENT_STATE 0x24 // 4byte
#define REG_HOST_CONTROL1 0x28 // 1byte
#define REG_POWER_CONTROL 0x29 // 1byte
#define REG_BLOCK_GAP_CONTROL 0x2A // 1byte
#define REG_WAKEUP_CONTROL 0x2B // 1byte
#define REG_CLOCK_CONTROL 0x2C // 2byte
#define REG_TIMEOUT_CONTROL 0x2E // 1byte
#define REG_SW_RESET 0x2F // 1byte
#define REG_NORMAL_INT_STATUS 0x30 // 2byte
#define REG_ERROR_INT_STATUS 0x32 // 2byte
#define REG_NORMAL_INT_STATUS_ENABLE 0x34 // 2byte
#define REG_ERROR_INT_STATUS_ENABLE 0x36 // 2byte
#define REG_NORMAL_INT_SIGNAL_ENABLE 0x38 // 2byte
#define REG_ERROR_INT_SIGNAL_ENABLE 0x3A // 2byte
#define REG_CAPABILITIES 0x40 // 8byte
#define REG_ADMA_ADDRESS 0x58 // 8byte
// Transfer Mode (0x0C)
#define BIT_DMA_EN BIT0
#define BIT_BLK_CNT_EN BIT1
#define BIT_AUTO_CMD12_EN BIT2
#define BIT_AUTO_CMD23_EN BIT3
#define BIT_READ_TRANS BIT4
#define BIT_MULTI_BLK BIT5
// Present State (0x24)
#define BIT_CMD_INHIBIT_CMD BIT0
#define BIT_CMD_INHIBIT_DAT BIT1
#define BIT_CARD_INSERTED BIT16
#define BIT_WRITE_PROTECT_SWITCH_PIN BIT19
// Power Control (0x29)
#define BIT_POWER_33 0xE
#define BIT_POWER_30 0xC
#define BIT_POWER_18 0xA
// Clock Control (0x2C)
#define BIT_INTERNAL_CLK_EN BIT0
#define BIT_INTERNAL_CLK_STABLE BIT1
#define BIT_SD_CLK_EN BIT2
// Software Reset (0x2F)
#define BIT_SW_RESET_ALL BIT0
#define BIT_SW_RESET_CMD_LINE BIT1
#define BIT_SW_RESET_DAT_LINE BIT2
// Norma Interrupt Status (0x30)
#define BIT_COMMAND_COMPLETE BIT0
#define BIT_TRANSFER_COMPLETE BIT1
#define BIT_BLOCK_GAP_EVENT BIT2
#define BIT_DMA_INT BIT3
#define BIT_BUFFER_WRITE_RDY BIT4
#define BIT_BUFFER_READ_RDY BIT5
#define BIT_CARD_INSERTION BIT6
#define BIT_CARD_REMOVAL BIT7
#define BIT_CARD_INT BIT8
#define BIT_ERROR_INT BIT15
// Error Interrupt Status (0x32)
#define BIT_DATA_TIME_OUT_ERROR BIT4
#define BIT_DATA_CRC_ERROR BIT5
#define BIT_ADMA_ERROR BIT9
// Capabilities (0x40)
#define BIT_VDD_33 BIT24
#define BIT_VDD_30 BIT25
#define BIT_VDD_18 BIT26
#define ENABLE 1
#define DISABLE 0
#define ADMA_DESC_NUM 50
#define BUFFER_UNIT_SIZE 512
typedef enum _MMC_HOST_TEST_FUNC_ {
MMC_HOST_TEST_HW_INIT, // 0
MMC_HOST_TEST_CARD_INIT, // 1
MMC_HOST_TEST_SEND_CMD, // 2
MMC_HOST_TEST_DEBUG, // 3
MMC_HOST_TEST_SW_RESET, // 4
MMC_HOST_TEST_READ_SINGLE, // 5
MMC_HOST_TEST_WRITE_SINGLE, // 6
MMC_HOST_TEST_READ_MULTI, // 7
MMC_HOST_TEST_WRITE_MULTI, // 8
MMC_HOST_TEST_SINGLE_LONGRUN, // 9
MMC_HOST_TEST_MULTI_LONGRUN, // 10
MMC_HOST_TEST_CARD_DETECTION, // 11
MMC_HOST_TEST_WRITE_PROTECT, // 12
MMC_HOST_TEST_REGISTER_RW // 13
}MMC_HOST_TEST_FUNC;
typedef enum _RESPONSE_TYPE_ {
No_Response, // 00b
Response_136, // 01b
Response_48, // 10b
Response_48_Busy // 11b
}RESPONSE_TYPE;
typedef enum _COMMAND_TYPE_ {
Normal, // 00b
Suspend, // 01b
Resume, // 10b
Abort // 11b
}COMMAND_TYPE;
typedef enum _DATA_PRESENT_ {
No_Data_Present, // 00b
Data_Present, // 01b
}DATA_PRESENT;
typedef enum _SUPPLY_VOLTAGE_ {
MMC_VDD_27_28 = BIT15,
MMC_VDD_28_29 = BIT16,
MMC_VDD_29_30 = BIT17,
MMC_VDD_30_31 = BIT18,
MMC_VDD_31_32 = BIT19,
MMC_VDD_32_33 = BIT20,
MMC_VDD_33_34 = BIT21,
MMC_VDD_34_35 = BIT22,
MMC_VDD_35_36 = BIT23,
}SUPPLY_VOLTAGE;
typedef enum _COMMAND_INDEX_ {
GO_IDLE_STATE = 0,
ALL_SEND_CID = 2,
SEND_RELATIVE_ADDR = 3,
SET_BUS_WIDTH = 6,
SELECT_CARD = 7,
SEND_IF_COND = 8,
SEND_CSD = 9,
STOP_TRANSMISSION = 12,
SEND_STATUS = 13,
READ_SINGLE_BLOCK = 17,
READ_MULTIPLE_BLOCK = 18,
WRITE_BLOCK = 24,
WRITE_MULTIPLE_BLOCK = 25,
SD_SEND_OP_COND = 41,
APP_CMD = 55,
}COMMAND_INDEX;
typedef enum _TRANSFER_CONFIG_ {
Read_Data = 0,
Write_Data = 1,
Single_Block = 0,
Multiple_Block = 1,
}TRANSFER_CONFIG;
typedef enum _ERROR_STATUS_ {
General_Error, // 0
CRC_Error, // 1
TIME_OUT_ERROR, // 2
CRC_Error_NeedCMD12, // 3
Transfer_OK // 4
}ERROR_STATUS;
typedef enum _CARD_CURRENT_STATE_ {
IDLE_STATE,
READY_STATE,
IDENT_STATE,
STBY_STATE,
TRAN_STATE,
DATA_STATE,
RCV_STATE,
PRG_STATE,
DIS_STATE,
UNKNOWN_STATE
}CARD_CURRENT_STATE;
typedef struct _COMMAND_FORMAT_
{
u16 Resp_Type:2;
u16 Rsvd0:1;
u16 CMD_CRC_Chk:1;
u16 CMD_Idx_Chk:1;
u16 Data_Present:1;
u16 CMD_Type:2;
u16 CMD_Idx:6;
u16 Rsvd1:2;
}COMMAND_FORMAT, *PCOMMAND_FPRMAT;
typedef struct _MMC_COMMAND
{
COMMAND_FORMAT Cmd_Format;
u32 Arg;
}MMC_COMMAND;
typedef struct _MMC_HOST_
{
u32 OCR_Avail;
u32 Resp[4];
u32 CID[4];
u32 RCA;
}MMC_HOST, *PMMC_HOST;
typedef struct _ADMA_ATTR_
{
u16 Valid:1;
u16 End:1;
u16 Int:1;
u16 Rsvd1:1;
u16 Act1:1;
u16 Act2:1;
u16 Rsvd2:10;
}ADMA_ATTR, *PADMA_ATTR;
// 24 bytes
typedef struct _ADMA_DESC_TABLE_
{
// 1st buffer desc
ADMA_ATTR Attribute1;
u16 Length1;
u32 Address1;
// 2nd buffer desc
ADMA_ATTR Attribute2;
u16 Length2;
u32 Address2;
// 3rd buffer desc
ADMA_ATTR Attribute3;
u16 Length3;
u32 Address3;
}ADMA_DESC_TABLE, *PADMA_DESC_TABLE;
// 1024 bytes
typedef struct _ADMA_BUFFER_
{
u8 Data1[512]; /* 1st buffer */
u8 Data2[512]; /* 2nd buffer */
}ADMA_BUFFER, *PADMA_BUFFER;
VOID
SdHostTestApp(
IN u8 *argv[]
);
#endif // end of "#ifdef CONFIG_SDIO_HOST_VERIFY"
#endif /* #ifndef _RTL8195A_SDIO_HOST_H_ */

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#ifndef _RTL8195A_SDR_H
#define _RTL8195A_SDR_H
#define MS_0_CTRL_BASE BSP_MS_I_DRAMC_0_BASE
#define MS_0_CTRL_PHY_BASE (BSP_MS_I_DRAMC_0_BASE)
#define MS_0_WRAP_BASE (MS_0_CTRL_BASE + 0x200)
#define MS_1_CTRL_BASE BSP_MS_I_DRAMC_1_BASE
#define MS_1_CTRL_PHY_BASE (BSP_MS_I_DRAMC_1_BASE)
#define MS_1_WRAP_BASE (MS_1_CTRL_BASE + 0x200)
#define MS_PCTL_CCR_OFFSET 0x000
#define MS_PCTL_DCR_OFFSET 0x004
#define MS_PCTL_IOCR_OFFSET 0x008
#define MS_PCTL_CSR_OFFSET 0x00c
#define MS_PCTL_DRR_OFFSET 0x010
#define MS_PCTL_TPR0_OFFSET 0x014
#define MS_PCTL_TPR1_OFFSET 0x018
#define MS_PCTL_TPR2_OFFSET 0x01c
#define MS_PCTL_MR_OFFSET 0x020
#define MS_PCTL_EMR1_OFFSET 0x024
#define MS_PCTL_EMR2_OFFSET 0x028
#define MS_PCTL_EMR3_OFFSET 0x02c
#define MS_PCTL_CSR2_OFFSET 0x030
#define MS_PCTL_SRST_OFFSET 0x034
#define MS_PCTL_DTR2_OFFSET 0x038
#define MS_PCTL_DTR3_OFFSET 0x03c
#define MS_PCTL_GDLLCR_OFFSET 0x040
#define MS_PCTL_DLLCR0_OFFSET 0x044
#define MS_PCTL_DLLCR1_OFFSET 0x048
#define MS_PCTL_DLLCR2_OFFSET 0x04c
#define MS_PCTL_DLLCR3_OFFSET 0x050
#define MS_PCTL_DLLCR4_OFFSET 0x054
#define MS_PCTL_DLLCR5_OFFSET 0x058
#define MS_PCTL_DLLCR6_OFFSET 0x05c
#define MS_PCTL_DLLCR7_OFFSET 0x060
#define MS_PCTL_DLLCR8_OFFSET 0x064
#define MS_PCTL_DQTR0_OFFSET 0x068
#define MS_PCTL_DQTR1_OFFSET 0x06c
#define MS_PCTL_DQTR2_OFFSET 0x070
#define MS_PCTL_DQTR3_OFFSET 0x074
#define MS_PCTL_DQTR4_OFFSET 0x078
#define MS_PCTL_DQTR5_OFFSET 0x07c
#define MS_PCTL_DQTR6_OFFSET 0x080
#define MS_PCTL_DQTR7_OFFSET 0x084
#define MS_PCTL_DQSTR_OFFSET 0x088
#define MS_PCTL_DQSBTR_OFFSET 0x08c
#define MS_PCTL_ODTCR_OFFSET 0x090
#define MS_PCTL_DTR0_OFFSET 0x094
#define MS_PCTL_DTR1_OFFSET 0x098
#define MS_PCTL_DTAR_OFFSET 0x09c
#define MS_PCTL_ZQCR0_OFFSET 0x0a0
#define MS_PCTL_ZQCR1_OFFSET 0x0a4
#define MS_PCTL_ZQSR_OFFSET 0x0a8
#define MS_PCTL_RSLR0_OFFSET 0x0ac
#define MS_PCTL_RSLR1_OFFSET 0x0b0
#define MS_PCTL_RSLR2_OFFSET 0x0b4
#define MS_PCTL_RSLR3_OFFSET 0x0b8
#define MS_PCTL_RDGR0_OFFSET 0x0bc
#define MS_PCTL_RDGR1_OFFSET 0x0c0
#define MS_PCTL_RDGR2_OFFSET 0x0c4
#define MS_PCTL_RDGR3_OFFSET 0x0c8
#define MS_PCTL_MXSL_OFFSET 0x0cc
#define MS_PCTL_BCR_OFFSET 0x0d0
#define MS_PCTL_BALR0_OFFSET 0x0d4
#define MS_PCTL_BALR1_OFFSET 0x0d8
#define MS_PCTL_BDR0_OFFSET 0x0dc
#define MS_PCTL_BDR1_OFFSET 0x0e0
#define MS_PCTL_BBR_OFFSET 0x0e4
#define MS_PCTL_BSR_OFFSET 0x0e8
#define MS_PCTL_BYR_OFFSET 0x0ec
#define MS_PCTL_BFA_OFFSET 0x0f0
#define MS_PCTL_IDR_OFFSET 0x0f8
#define MS_PCTL_ERR_OFFSET 0x0fc
#define MS_WRAP_SCR_OFFSET 0x224
#define MS_WRAP_QCR_OFFSET 0x230
#define MS_WRAP_PCR_OFFSET 0x234
#define MS_WRAP_QTR0_OFFSET 0x240
#define MS_WRAP_QTR1_OFFSET 0x244
#define MS_WRAP_QTR2_OFFSET 0x248
#define MS_WRAP_QTR3_OFFSET 0x24c
#define MS_WRAP_QTR4_OFFSET 0x250
#define MS_WRAP_QTR5_OFFSET 0x254
#define MS_WRAP_QTR6_OFFSET 0x258
#define MS_WRAP_QTR7_OFFSET 0x25c
#define MS_WRAP_QTR8_OFFSET 0x260
#define MS_WRAP_QTR9_OFFSET 0x264
#define MS_WRAP_QTR10_OFFSET 0x268
#define MS_WRAP_QTR11_OFFSET 0x26c
#define MS_WRAP_QTR12_OFFSET 0x270
#define MS_WRAP_QTR13_OFFSET 0x274
#define MS_WRAP_QTR14_OFFSET 0x278
#define MS_WRAP_QTR15_OFFSET 0x27c
#define MS_PHY_DLY0 0x100
#define MS_PHY_DLY1_RST 0x104
#define MS_PHY_DLY_CLK 0x108
#define MS_PHY_DLY_ST 0x10c
#define MS_PHY_DLY_NUM 0x100
#define PCTL_CCR_INIT_BFO 0
#define PCTL_CCR_INIT_BFW 1
#define PCTL_CCR_DTT_BFO 1
#define PCTL_CCR_DTT_BFW 1
#define PCTL_CCR_BTT_BFO 2
#define PCTL_CCR_BTT_BFW 1
#define PCTL_CCR_DPIT_BFO 3
#define PCTL_CCR_DPIT_BFW 1
#define PCTL_CCR_FLUSH_FIFO_BFO 8
#define PCTL_CCR_FLUSH_FIFO_BFW 1
#define PCTL_DCR_DDR3_BFO 0
#define PCTL_DCR_DDR3_BFW 1
#define PCTL_DCR_SDR_BFO 1
#define PCTL_DCR_SDR_BFW 1
#define PCTL_DCR_DQ32_BFO 4
#define PCTL_DCR_DQ32_BFW 1
#define PCTL_DCR_DFI_RATE_BFO 8
#define PCTL_DCR_DFI_RATE_BFW 3
#define PCTL_IOCR_RD_PIPE_BFO 8
#define PCTL_IOCR_RD_PIPE_BFW 4
#define PCTL_IOCR_TPHY_WD_BFO 12
#define PCTL_IOCR_TPHY_WD_BFW 5
#define PCTL_IOCR_TPHY_WL_BFO 17
#define PCTL_IOCR_TPHY_WL_BFW 3
#define PCTL_IOCR_TPHY_RD_EN_BFO 20
#define PCTL_IOCR_TPHY_RD_EN_BFW 5
#define PCTL_CSR_MEM_IDLE_BFO 8
#define PCTL_CSR_MEM_IDLE_BFW 1
#define PCTL_CSR_DT_IDLE_BFO 9
#define PCTL_CSR_DT_IDLE_BFW 1
#define PCTL_CSR_BIST_IDLE_BFO 10
#define PCTL_CSR_BIST_IDLE_BFW 1
#define PCTL_CSR_DT_FAIL_BFO 11
#define PCTL_CSR_DT_FAIL_BFW 1
#define PCTL_CSR_BT_FAIL_BFO 12
#define PCTL_CSR_BT_FAIL_BFW 1
#define PCTL_DRR_TRFC_BFO 0
#define PCTL_DRR_TRFC_BFW 7
#define PCTL_DRR_TREF_BFO 8
#define PCTL_DRR_TREF_BFW 24
#define PCTL_DRR_REF_NUM_BFO 24
#define PCTL_DRR_REF_NUM_BFW 4
#define PCTL_DRR_REF_DIS_BFO 28
#define PCTL_DRR_REF_DIS_BFW 1
#define PCTL_TPR0_TRP_BFO 0
#define PCTL_TPR0_TRP_BFW 4
#define PCTL_TPR0_TRAS_BFO 4
#define PCTL_TPR0_TRAS_BFW 5
#define PCTL_TPR0_TWR_BFO 9
#define PCTL_TPR0_TWR_BFW 4
#define PCTL_TPR0_TRTP_BFO 13
#define PCTL_TPR0_TRTP_BFW 3
#define PCTL_TPR1_TRRD_BFO 0
#define PCTL_TPR1_TRRD_BFW 4
#define PCTL_TPR1_TRC_BFO 4
#define PCTL_TPR1_TRC_BFW 6
#define PCTL_TPR1_TRCD_BFO 10
#define PCTL_TPR1_TRCD_BFW 4
#define PCTL_TPR1_TCCD_BFO 14
#define PCTL_TPR1_TCCD_BFW 3
#define PCTL_TPR1_TWTR_BFO 17
#define PCTL_TPR1_TWTR_BFW 3
#define PCTL_TPR1_TRTW_BFO 20
#define PCTL_TPR1_TRTW_BFW 4
#define PCTL_TPR2_INIT_REF_NUM_BFO 0
#define PCTL_TPR2_INIT_REF_NUM_BFW 4
#define PCTL_TPR2_INIT_NS_EN_BFO 4
#define PCTL_TPR2_INIT_NS_EN_BFW 1
#define PCTL_TPR2_TMRD_BFO 5
#define PCTL_TPR2_TMRD_BFW 2
#define PCTL_MR_BL_BFO 0
#define PCTL_MR_BL_BFW 3
#define PCTL_MR_BT_BFO 3
#define PCTL_MR_BT_BFW 1
#define PCTL_MR_CAS_BFO 4
#define PCTL_MR_CAS_BFW 3
#define PCTL_MR_OP_BFO 8
#define PCTL_MR_OP_BFW 12
#define PCTL_EMR1_ADDLAT_BFO 3
#define PCTL_EMR1_ADDLAT_BFW 3
#define PCTL_CMD_DPIN_RSTN_BFO 0
#define PCTL_CMD_DPIN_RSTN_BFW 1
#define PCTL_CMD_DPIN_CKE_BFO 1
#define PCTL_CMD_DPIN_CKE_BFW 1
#define PCTL_CMD_DPIN_ODT_BFO 2
#define PCTL_CMD_DPIN_ODT_BFW 1
#define PCTL_BCR_STOP_BFO 0
#define PCTL_BCR_STOP_BFW 1
#define PCTL_BCR_CMP_BFO 1
#define PCTL_BCR_CMP_BFW 1
#define PCTL_BCR_LOOP_BFO 2
#define PCTL_BCR_LOOP_BFW 1
#define PCTL_BCR_DIS_MASK_BFO 3
#define PCTL_BCR_DIS_MASK_BFW 1
#define PCTL_BCR_AT_STOP_BFO 4
#define PCTL_BCR_AT_STOP_BFW 1
#define PCTL_BCR_FLUSH_CMD_BFO 8
#define PCTL_BCR_FLUSH_CMD_BFW 1
#define PCTL_BCR_FLUSH_WD_BFO 9
#define PCTL_BCR_FLUSH_WD_BFW 1
#define PCTL_BCR_FLUSH_RGD_BFO 10
#define PCTL_BCR_FLUSH_RGD_BFW 1
#define PCTL_BCR_FLUSH_RD_BFO 11
#define PCTL_BCR_FLUSH_RD_BFW 1
#define PCTL_BCR_FLUSH_RD_EXPC_BFO 16
#define PCTL_BCR_FLUSH_RD_EXPC_BFW 14
#define PCTL_BST_ERR_FST_TH_BFO 0
#define PCTL_BST_ERR_FST_TH_BFW 12
#define PCTL_BST_ERR_CNT_BFO 16
#define PCTL_BST_ERR_CNT_BFW 14
#define PCTL_BSRAM0_CMD_LEVEL_BFO 0
#define PCTL_BSRAM0_CMD_LEVEL_BFW 12
#define PCTL_BSRAM0_WD_LEVEL_BFO 16
#define PCTL_BSRAM0_WD_LEVEL_BFW 14
#define PCTL_BSRAM1_RG_LEVEL_BFO 0
#define PCTL_BSRAM1_RG_LEVEL_BFW 14
#define PCTL_BSRAM1_RD_LEVEL_BFO 16
#define PCTL_BSRAM1_RD_LEVEL_BFW 14
#define WRAP_MISC_PAGE_SIZE_BFO 0
#define WRAP_MISC_PAGE_SIZE_BFW 4
#define WRAP_MISC_BANK_SIZE_BFO 4
#define WRAP_MISC_BANK_SIZE_BFW 2
#define WRAP_MISC_BST_SIZE_BFO 6
#define WRAP_MISC_BST_SIZE_BFW 2
#define WRAP_MISC_DDR_PARAL_BFO 8
#define WRAP_MISC_DDR_PARAL_BFW 1
struct ms_rxi310_portmap {
volatile unsigned int ccr; /* 0x000 */
volatile unsigned int dcr; /* 0x004 */
volatile unsigned int iocr; /* 0x008 */
volatile unsigned int csr; /* 0x00c */
volatile unsigned int drr; /* 0x010 */
volatile unsigned int tpr0; /* 0x014 */
volatile unsigned int tpr1; /* 0x018 */
volatile unsigned int tpr2; /* 0x01c */
volatile unsigned int mr; /* 0x020 */
volatile unsigned int emr1; /* 0x024 */
volatile unsigned int emr2; /* 0x028 */
volatile unsigned int emr3; /* 0x02c */
volatile unsigned int cdpin; /* 0x030 */
volatile unsigned int tdpin; /* 0x034 */
volatile unsigned int dtr2; /* 0x038 */
volatile unsigned int dtr3; /* 0x03c */
volatile unsigned int gdllcr; /* 0x040 */
volatile unsigned int dllcr0; /* 0x044 */
volatile unsigned int dllcr1; /* 0x048 */
volatile unsigned int dllcr2; /* 0x04c */
volatile unsigned int dllcr3; /* 0x050 */
volatile unsigned int dllcr4; /* 0x054 */
volatile unsigned int dllcr5; /* 0x058 */
volatile unsigned int dllcr6; /* 0x05c */
volatile unsigned int dllcr7; /* 0x060 */
volatile unsigned int dllcr8; /* 0x064 */
volatile unsigned int dqtr0; /* 0x068 */
volatile unsigned int dqtr1; /* 0x06c */
volatile unsigned int dqtr2; /* 0x070 */
volatile unsigned int dqtr3; /* 0x074 */
volatile unsigned int dqtr4; /* 0x078 */
volatile unsigned int dqtr5; /* 0x07c */
volatile unsigned int dqtr6; /* 0x080 */
volatile unsigned int dqtr7; /* 0x084 */
volatile unsigned int dqstr; /* 0x088 */
volatile unsigned int dqsbtr; /* 0x08c */
volatile unsigned int odtcr; /* 0x090 */
volatile unsigned int dtr0; /* 0x094 */
volatile unsigned int dtr1; /* 0x098 */
volatile unsigned int dtar; /* 0x09c */
volatile unsigned int zqcr0; /* 0x0a0 */
volatile unsigned int zqcr1; /* 0x0a4 */
volatile unsigned int zqsr; /* 0x0a8 */
volatile unsigned int rslr0; /* 0x0ac */
volatile unsigned int rslr1; /* 0x0b0 */
volatile unsigned int rslr2; /* 0x0b4 */
volatile unsigned int rslr3; /* 0x0b8 */
volatile unsigned int rdgr0; /* 0x0bc */
volatile unsigned int rdgr1; /* 0x0c0 */
volatile unsigned int rdgr2; /* 0x0c4 */
volatile unsigned int rdgr3; /* 0x0c8 */
volatile unsigned int mxsl; /* 0x0cc */
volatile unsigned int bcr; /* 0x0d0 */
volatile unsigned int bst; /* 0x0d4 */
volatile unsigned int bsram0; /* 0x0d8 */
volatile unsigned int bsram1; /* 0x0dc */
volatile unsigned int bdr1; /* 0x0e0 */
volatile unsigned int bbr; /* 0x0e4 */
volatile unsigned int bsr; /* 0x0e8 */
volatile unsigned int byr; /* 0x0ec */
volatile unsigned int bfa; /* 0x0f0 */
volatile unsigned int pctl_svn; /* 0x0f4 */
volatile unsigned int pctl_idr; /* 0x0f8 */
volatile unsigned int err; /* 0x0fc */
// SDR_PHY CONTROL REGISTER
volatile unsigned int phy_dly0; /* 0x100 */
volatile unsigned int phy_dly1_rst; /* 0x104 */
volatile unsigned int phy_dly_clk; /* 0x108 */
volatile unsigned int phy_dly_st; /* 0x10c */
volatile unsigned int phy_dly_num; /* 0x110 */
volatile unsigned int reserved0[68];
// WRAP CONTROL REGISTER
volatile unsigned int misc; /* 0x224 */
volatile unsigned int cq_ver; /* 0x228 */
volatile unsigned int cq_mon; /* 0x22c */
volatile unsigned int wq_ver; /* 0x230 */
volatile unsigned int wq_mon; /* 0x234 */
volatile unsigned int rq_ver; /* 0x240 */
volatile unsigned int rq_mon; /* 0x244 */
volatile unsigned int reserved1[22];
volatile unsigned int wwrap_idr; /* 0x2a0 */
volatile unsigned int wrap_svn; /* 0x2a4 */
}; //ms_rxi310_portmap
#define QFIFO_CMD_BANK_BFO (35 - QFIFO_CMD_WRRD_BFO) // [38:35]
#define QFIFO_CMD_BANK_BFW 4
#define QFIFO_CMD_PAGE_BFO (20 - QFIFO_CMD_WRRD_BFO) // [34:20]
#define QFIFO_CMD_PAGE_BFW 15
#define QFIFO_CMD_COLU_BFO (7 - QFIFO_CMD_WRRD_BFO) // [19: 7]
#define QFIFO_CMD_COLU_BFW 13 // [19: 7]
#define QFIFO_BST_LEN_BFO (3 - QFIFO_CMD_WRRD_BFO) // [6:3]
#define QFIFO_BST_LEN_BFW 4 // [6:3]
#define QFIFO_CMD_WRRD_BFO 2 // [2], remove bit[1:0]
#define QFIFO_CMD_WRRD_BFW 1 // [2], remove bit[1:0]
//====================================================//
#define REG_SDR_CCR 0x00
#define REG_SDR_DCR 0x04
#define REG_SDR_IOCR 0x08
#define REG_SDR_CSR 0x0C
#define REG_SDR_DRR 0x10
#define REG_SDR_TPR0 0x14
#define REG_SDR_TPR1 0x18
#define REG_SDR_TPR2 0x1C
#define REG_SDR_MR 0x20
#define REG_SDR_EMR1 0x24
#define REG_SDR_EMR2 0x28
#define REG_SDR_EMR3 0x2C
#define REG_SDR_CMD_DPIN 0x30
#define REG_SDR_TIE_DPIN 0x34
#define REG_SDR_BCR 0xD0
#define REG_SDR_BST 0xD4
#define REG_SDR_BSRAM0 0xD8
#define REG_SDR_BSRAM1 0xDC
#define REG_SDR_PCTL_SVN_ID 0xF4
#define REG_SDR_PCTL_IDR 0xF8
#define REG_SDR_DLY0 0x100
#define REG_SDR_DLY1 0x104
#define REG_SDR_DCM_RST 0x104
#define REG_SDR_DLY_CLK_PHA 0x108
#define REG_SDR_DLY_ST 0x10C
#define REG_SDR_MISC 0x224
#define REG_SDR_OCP_WRAP_IDR 0x2A0
#define REG_SDR_OCP_WRAP_VERSION 0x2A4
#endif // end of "#ifndef _RTL8195A_SDR_H"

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#ifndef _RTL8195A_SPI_FLASH_H
#define _RTL8195A_SPI_FLASH_H
#define CPU_OPT_WIDTH 0x1F
//2 REG_NOT_VALID
//2 REG_SPIC_CTRLR0
#define BIT_SHIFT_CK_MTIMES 23
#define BIT_MASK_CK_MTIMES 0x1f
#define BIT_CK_MTIMES(x) (((x) & BIT_MASK_CK_MTIMES) << BIT_SHIFT_CK_MTIMES)
#define BIT_CTRL_CK_MTIMES(x) (((x) & BIT_MASK_CK_MTIMES) << BIT_SHIFT_CK_MTIMES)
#define BIT_GET_CK_MTIMES(x) (((x) >> BIT_SHIFT_CK_MTIMES) & BIT_MASK_CK_MTIMES)
#define BIT_FAST_RD BIT(22)
#define BIT_SHIFT_FAST_RD 22
#define BIT_MASK_FAST_RD 0x1
#define BIT_CTRL_FAST_RD(x) (((x) & BIT_MASK_FAST_RD) << BIT_SHIFT_FAST_RD)
#define BIT_SHIFT_CMD_CH 20
#define BIT_MASK_CMD_CH 0x3
#define BIT_CMD_CH(x) (((x) & BIT_MASK_CMD_CH) << BIT_SHIFT_CMD_CH)
#define BIT_CTRL_CMD_CH(x) (((x) & BIT_MASK_CMD_CH) << BIT_SHIFT_CMD_CH)
#define BIT_GET_CMD_CH(x) (((x) >> BIT_SHIFT_CMD_CH) & BIT_MASK_CMD_CH)
#define BIT_SHIFT_DATA_CH 18
#define BIT_MASK_DATA_CH 0x3
#define BIT_DATA_CH(x) (((x) & BIT_MASK_DATA_CH) << BIT_SHIFT_DATA_CH)
#define BIT_CTRL_DATA_CH(x) (((x) & BIT_MASK_DATA_CH) << BIT_SHIFT_DATA_CH)
#define BIT_GET_DATA_CH(x) (((x) >> BIT_SHIFT_DATA_CH) & BIT_MASK_DATA_CH)
#define BIT_SHIFT_ADDR_CH 16
#define BIT_MASK_ADDR_CH 0x3
#define BIT_ADDR_CH(x) (((x) & BIT_MASK_ADDR_CH) << BIT_SHIFT_ADDR_CH)
#define BIT_CTRL_ADDR_CH(x) (((x) & BIT_MASK_ADDR_CH) << BIT_SHIFT_ADDR_CH)
#define BIT_GET_ADDR_CH(x) (((x) >> BIT_SHIFT_ADDR_CH) & BIT_MASK_ADDR_CH)
#define BIT_SHIFT_TMOD 8
#define BIT_MASK_TMOD 0x3
#define BIT_TMOD(x) (((x) & BIT_MASK_TMOD) << BIT_SHIFT_TMOD)
#define BIT_CTRL_TMOD(x) (((x) & BIT_MASK_TMOD) << BIT_SHIFT_TMOD)
#define BIT_GET_TMOD(x) (((x) >> BIT_SHIFT_TMOD) & BIT_MASK_TMOD)
#define BIT_SCPOL BIT(7)
#define BIT_SHIFT_SCPOL 7
#define BIT_MASK_SCPOL 0x1
#define BIT_CTRL_SCPOL(x) (((x) & BIT_MASK_SCPOL) << BIT_SHIFT_SCPOL)
#define BIT_SCPH BIT(6)
#define BIT_SHIFT_SCPH 6
#define BIT_MASK_SCPH 0x1
#define BIT_CTRL_SCPH(x) (((x) & BIT_MASK_SCPH) << BIT_SHIFT_SCPH)
//2 REG_SPIC_CTRLR1
#define BIT_SHIFT_NDF 0
#define BIT_MASK_NDF 0xfff
#define BIT_NDF(x) (((x) & BIT_MASK_NDF) << BIT_SHIFT_NDF)
#define BIT_CTRL_NDF(x) (((x) & BIT_MASK_NDF) << BIT_SHIFT_NDF)
#define BIT_GET_NDF(x) (((x) >> BIT_SHIFT_NDF) & BIT_MASK_NDF)
//2 REG_SPIC_SSIENR
#define BIT_ATCK_CMD BIT(1)
#define BIT_SHIFT_ATCK_CMD 1
#define BIT_MASK_ATCK_CMD 0x1
#define BIT_CTRL_ATCK_CMD(x) (((x) & BIT_MASK_ATCK_CMD) << BIT_SHIFT_ATCK_CMD)
#define BIT_SPIC_EN BIT(0)
#define BIT_SHIFT_SPIC_EN 0
#define BIT_MASK_SPIC_EN 0x1
#define BIT_CTRL_SPIC_EN(x) (((x) & BIT_MASK_SPIC_EN) << BIT_SHIFT_SPIC_EN)
//2 REG_SPIC_MWCR
//2 REG_SPIC_SER
#define BIT_SER BIT(0)
#define BIT_SHIFT_SER 0
#define BIT_MASK_SER 0x1
#define BIT_CTRL_SER(x) (((x) & BIT_MASK_SER) << BIT_SHIFT_SER)
//2 REG_SPIC_BAUDR
#define BIT_SHIFT_SCKDV 0
#define BIT_MASK_SCKDV 0xffff
#define BIT_SCKDV(x) (((x) & BIT_MASK_SCKDV) << BIT_SHIFT_SCKDV)
#define BIT_CTRL_SCKDV(x) (((x) & BIT_MASK_SCKDV) << BIT_SHIFT_SCKDV)
#define BIT_GET_SCKDV(x) (((x) >> BIT_SHIFT_SCKDV) & BIT_MASK_SCKDV)
//2 REG_SPIC_TXFTLR
#define BIT_SHIFT_TFT 0
#define BIT_MASK_TFT 0x1f
#define BIT_TFT(x) (((x) & BIT_MASK_TFT) << BIT_SHIFT_TFT)
#define BIT_CTRL_TFT(x) (((x) & BIT_MASK_TFT) << BIT_SHIFT_TFT)
#define BIT_GET_TFT(x) (((x) >> BIT_SHIFT_TFT) & BIT_MASK_TFT)
//2 REG_SPIC_RXFTLR
#define BIT_SHIFT_RFT 0
#define BIT_MASK_RFT 0x1f
#define BIT_RFT(x) (((x) & BIT_MASK_RFT) << BIT_SHIFT_RFT)
#define BIT_CTRL_RFT(x) (((x) & BIT_MASK_RFT) << BIT_SHIFT_RFT)
#define BIT_GET_RFT(x) (((x) >> BIT_SHIFT_RFT) & BIT_MASK_RFT)
//2 REG_SPIC_TXFLR
#define BIT_SHIFT_TXFL 0
#define BIT_MASK_TXFL 0x3f
#define BIT_TXFL(x) (((x) & BIT_MASK_TXFL) << BIT_SHIFT_TXFL)
#define BIT_CTRL_TXFL(x) (((x) & BIT_MASK_TXFL) << BIT_SHIFT_TXFL)
#define BIT_GET_TXFL(x) (((x) >> BIT_SHIFT_TXFL) & BIT_MASK_TXFL)
//2 REG_SPIC_RXFLR
#define BIT_SHIFT_RXFL 0
#define BIT_MASK_RXFL 0x3f
#define BIT_RXFL(x) (((x) & BIT_MASK_RXFL) << BIT_SHIFT_RXFL)
#define BIT_CTRL_RXFL(x) (((x) & BIT_MASK_RXFL) << BIT_SHIFT_RXFL)
#define BIT_GET_RXFL(x) (((x) >> BIT_SHIFT_RXFL) & BIT_MASK_RXFL)
//2 REG_SPIC_SR
#define BIT_TXE BIT(5)
#define BIT_SHIFT_TXE 5
#define BIT_MASK_TXE 0x1
#define BIT_CTRL_TXE(x) (((x) & BIT_MASK_TXE) << BIT_SHIFT_TXE)
#define BIT_RFF BIT(4)
#define BIT_SHIFT_RFF 4
#define BIT_MASK_RFF 0x1
#define BIT_CTRL_RFF(x) (((x) & BIT_MASK_RFF) << BIT_SHIFT_RFF)
#define BIT_RFNE BIT(3)
#define BIT_SHIFT_RFNE 3
#define BIT_MASK_RFNE 0x1
#define BIT_CTRL_RFNE(x) (((x) & BIT_MASK_RFNE) << BIT_SHIFT_RFNE)
#define BIT_TFE BIT(2)
#define BIT_SHIFT_TFE 2
#define BIT_MASK_TFE 0x1
#define BIT_CTRL_TFE(x) (((x) & BIT_MASK_TFE) << BIT_SHIFT_TFE)
#define BIT_TFNF BIT(1)
#define BIT_SHIFT_TFNF 1
#define BIT_MASK_TFNF 0x1
#define BIT_CTRL_TFNF(x) (((x) & BIT_MASK_TFNF) << BIT_SHIFT_TFNF)
#define BIT_BUSY BIT(0)
#define BIT_SHIFT_BUSY 0
#define BIT_MASK_BUSY 0x1
#define BIT_CTRL_BUSY(x) (((x) & BIT_MASK_BUSY) << BIT_SHIFT_BUSY)
//2 REG_SPIC_IMR
#define BIT_TXSIM BIT(9)
#define BIT_SHIFT_TXSIM 9
#define BIT_MASK_TXSIM 0x1
#define BIT_CTRL_TXSIM(x) (((x) & BIT_MASK_TXSIM) << BIT_SHIFT_TXSIM)
#define BIT_ACEIM BIT(8)
#define BIT_SHIFT_ACEIM 8
#define BIT_MASK_ACEIM 0x1
#define BIT_CTRL_ACEIM(x) (((x) & BIT_MASK_ACEIM) << BIT_SHIFT_ACEIM)
#define BIT_BYEIM BIT(7)
#define BIT_SHIFT_BYEIM 7
#define BIT_MASK_BYEIM 0x1
#define BIT_CTRL_BYEIM(x) (((x) & BIT_MASK_BYEIM) << BIT_SHIFT_BYEIM)
#define BIT_WBEIM BIT(6)
#define BIT_SHIFT_WBEIM 6
#define BIT_MASK_WBEIM 0x1
#define BIT_CTRL_WBEIM(x) (((x) & BIT_MASK_WBEIM) << BIT_SHIFT_WBEIM)
#define BIT_FSEIM BIT(5)
#define BIT_SHIFT_FSEIM 5
#define BIT_MASK_FSEIM 0x1
#define BIT_CTRL_FSEIM(x) (((x) & BIT_MASK_FSEIM) << BIT_SHIFT_FSEIM)
#define BIT_RXFIM BIT(4)
#define BIT_SHIFT_RXFIM 4
#define BIT_MASK_RXFIM 0x1
#define BIT_CTRL_RXFIM(x) (((x) & BIT_MASK_RXFIM) << BIT_SHIFT_RXFIM)
#define BIT_RXOIM BIT(3)
#define BIT_SHIFT_RXOIM 3
#define BIT_MASK_RXOIM 0x1
#define BIT_CTRL_RXOIM(x) (((x) & BIT_MASK_RXOIM) << BIT_SHIFT_RXOIM)
#define BIT_RXUIM BIT(2)
#define BIT_SHIFT_RXUIM 2
#define BIT_MASK_RXUIM 0x1
#define BIT_CTRL_RXUIM(x) (((x) & BIT_MASK_RXUIM) << BIT_SHIFT_RXUIM)
#define BIT_TXOIM BIT(1)
#define BIT_SHIFT_TXOIM 1
#define BIT_MASK_TXOIM 0x1
#define BIT_CTRL_TXOIM(x) (((x) & BIT_MASK_TXOIM) << BIT_SHIFT_TXOIM)
#define BIT_TXEIM BIT(0)
#define BIT_SHIFT_TXEIM 0
#define BIT_MASK_TXEIM 0x1
#define BIT_CTRL_TXEIM(x) (((x) & BIT_MASK_TXEIM) << BIT_SHIFT_TXEIM)
//2 REG_SPIC_ISR
#define BIT_TXSIS BIT(9)
#define BIT_SHIFT_TXSIS 9
#define BIT_MASK_TXSIS 0x1
#define BIT_CTRL_TXSIS(x) (((x) & BIT_MASK_TXSIS) << BIT_SHIFT_TXSIS)
#define BIT_ACEIS BIT(8)
#define BIT_SHIFT_ACEIS 8
#define BIT_MASK_ACEIS 0x1
#define BIT_CTRL_ACEIS(x) (((x) & BIT_MASK_ACEIS) << BIT_SHIFT_ACEIS)
#define BIT_BYEIS BIT(7)
#define BIT_SHIFT_BYEIS 7
#define BIT_MASK_BYEIS 0x1
#define BIT_CTRL_BYEIS(x) (((x) & BIT_MASK_BYEIS) << BIT_SHIFT_BYEIS)
#define BIT_WBEIS BIT(6)
#define BIT_SHIFT_WBEIS 6
#define BIT_MASK_WBEIS 0x1
#define BIT_CTRL_WBEIS(x) (((x) & BIT_MASK_WBEIS) << BIT_SHIFT_WBEIS)
#define BIT_FSEIS BIT(5)
#define BIT_SHIFT_FSEIS 5
#define BIT_MASK_FSEIS 0x1
#define BIT_CTRL_FSEIS(x) (((x) & BIT_MASK_FSEIS) << BIT_SHIFT_FSEIS)
#define BIT_RXFIS BIT(4)
#define BIT_SHIFT_RXFIS 4
#define BIT_MASK_RXFIS 0x1
#define BIT_CTRL_RXFIS(x) (((x) & BIT_MASK_RXFIS) << BIT_SHIFT_RXFIS)
#define BIT_RXOIS BIT(3)
#define BIT_SHIFT_RXOIS 3
#define BIT_MASK_RXOIS 0x1
#define BIT_CTRL_RXOIS(x) (((x) & BIT_MASK_RXOIS) << BIT_SHIFT_RXOIS)
#define BIT_RXUIS BIT(2)
#define BIT_SHIFT_RXUIS 2
#define BIT_MASK_RXUIS 0x1
#define BIT_CTRL_RXUIS(x) (((x) & BIT_MASK_RXUIS) << BIT_SHIFT_RXUIS)
#define BIT_TXOIS BIT(1)
#define BIT_SHIFT_TXOIS 1
#define BIT_MASK_TXOIS 0x1
#define BIT_CTRL_TXOIS(x) (((x) & BIT_MASK_TXOIS) << BIT_SHIFT_TXOIS)
#define BIT_TXEIS BIT(0)
#define BIT_SHIFT_TXEIS 0
#define BIT_MASK_TXEIS 0x1
#define BIT_CTRL_TXEIS(x) (((x) & BIT_MASK_TXEIS) << BIT_SHIFT_TXEIS)
//2 REG_SPIC_RISR
#define BIT_ACEIR BIT(8)
#define BIT_SHIFT_ACEIR 8
#define BIT_MASK_ACEIR 0x1
#define BIT_CTRL_ACEIR(x) (((x) & BIT_MASK_ACEIR) << BIT_SHIFT_ACEIR)
#define BIT_BYEIR BIT(7)
#define BIT_SHIFT_BYEIR 7
#define BIT_MASK_BYEIR 0x1
#define BIT_CTRL_BYEIR(x) (((x) & BIT_MASK_BYEIR) << BIT_SHIFT_BYEIR)
#define BIT_WBEIR BIT(6)
#define BIT_SHIFT_WBEIR 6
#define BIT_MASK_WBEIR 0x1
#define BIT_CTRL_WBEIR(x) (((x) & BIT_MASK_WBEIR) << BIT_SHIFT_WBEIR)
#define BIT_FSEIR BIT(5)
#define BIT_SHIFT_FSEIR 5
#define BIT_MASK_FSEIR 0x1
#define BIT_CTRL_FSEIR(x) (((x) & BIT_MASK_FSEIR) << BIT_SHIFT_FSEIR)
#define BIT_RXFIR BIT(4)
#define BIT_SHIFT_RXFIR 4
#define BIT_MASK_RXFIR 0x1
#define BIT_CTRL_RXFIR(x) (((x) & BIT_MASK_RXFIR) << BIT_SHIFT_RXFIR)
#define BIT_RXOIR BIT(3)
#define BIT_SHIFT_RXOIR 3
#define BIT_MASK_RXOIR 0x1
#define BIT_CTRL_RXOIR(x) (((x) & BIT_MASK_RXOIR) << BIT_SHIFT_RXOIR)
#define BIT_RXUIR BIT(2)
#define BIT_SHIFT_RXUIR 2
#define BIT_MASK_RXUIR 0x1
#define BIT_CTRL_RXUIR(x) (((x) & BIT_MASK_RXUIR) << BIT_SHIFT_RXUIR)
#define BIT_TXOIR BIT(1)
#define BIT_SHIFT_TXOIR 1
#define BIT_MASK_TXOIR 0x1
#define BIT_CTRL_TXOIR(x) (((x) & BIT_MASK_TXOIR) << BIT_SHIFT_TXOIR)
#define BIT_TXEIR BIT(0)
#define BIT_SHIFT_TXEIR 0
#define BIT_MASK_TXEIR 0x1
#define BIT_CTRL_TXEIR(x) (((x) & BIT_MASK_TXEIR) << BIT_SHIFT_TXEIR)
//2 REG_SPIC_TXOICR
#define BIT_TXOICR BIT(0)
#define BIT_SHIFT_TXOICR 0
#define BIT_MASK_TXOICR 0x1
#define BIT_CTRL_TXOICR(x) (((x) & BIT_MASK_TXOICR) << BIT_SHIFT_TXOICR)
//2 REG_SPIC_RXOICR
#define BIT_RXOCIR BIT(0)
#define BIT_SHIFT_RXOCIR 0
#define BIT_MASK_RXOCIR 0x1
#define BIT_CTRL_RXOCIR(x) (((x) & BIT_MASK_RXOCIR) << BIT_SHIFT_RXOCIR)
//2 REG_SPC_RXUICR
#define BIT_RXUICR BIT(0)
#define BIT_SHIFT_RXUICR 0
#define BIT_MASK_RXUICR 0x1
#define BIT_CTRL_RXUICR(x) (((x) & BIT_MASK_RXUICR) << BIT_SHIFT_RXUICR)
//2 REG_SPIC_MSTICR
#define BIT_MSTICR BIT(0)
#define BIT_SHIFT_MSTICR 0
#define BIT_MASK_MSTICR 0x1
#define BIT_CTRL_MSTICR(x) (((x) & BIT_MASK_MSTICR) << BIT_SHIFT_MSTICR)
//2 REG_SPIC_ICR
#define BIT_SHIFT_ICR 0
#define BIT_MASK_ICR 0xff
#define BIT_ICR(x) (((x) & BIT_MASK_ICR) << BIT_SHIFT_ICR)
#define BIT_CTRL_ICR(x) (((x) & BIT_MASK_ICR) << BIT_SHIFT_ICR)
#define BIT_GET_ICR(x) (((x) >> BIT_SHIFT_ICR) & BIT_MASK_ICR)
//2 REG_SPIC_DMACR
//2 REG_SPIC_DMATDLR0
//2 REG_SPIC_DMATDLR1
//2 REG_SPIC_IDR
#define BIT_SHIFT_IDCODE 0
#define BIT_MASK_IDCODE 0xffffffffL
#define BIT_IDCODE(x) (((x) & BIT_MASK_IDCODE) << BIT_SHIFT_IDCODE)
#define BIT_CTRL_IDCODE(x) (((x) & BIT_MASK_IDCODE) << BIT_SHIFT_IDCODE)
#define BIT_GET_IDCODE(x) (((x) >> BIT_SHIFT_IDCODE) & BIT_MASK_IDCODE)
//2 REG_SPIC_VERSION
#define BIT_SHIFT_SPIC_VERSION 0
#define BIT_MASK_SPIC_VERSION 0xffffffffL
#define BIT_SPIC_VERSION(x) (((x) & BIT_MASK_SPIC_VERSION) << BIT_SHIFT_SPIC_VERSION)
#define BIT_CTRL_SPIC_VERSION(x) (((x) & BIT_MASK_SPIC_VERSION) << BIT_SHIFT_SPIC_VERSION)
#define BIT_GET_SPIC_VERSION(x) (((x) >> BIT_SHIFT_SPIC_VERSION) & BIT_MASK_SPIC_VERSION)
//2 REG_SPIC_DR0
#define BIT_SHIFT_DR0 0
#define BIT_MASK_DR0 0xffffffffL
#define BIT_DR0(x) (((x) & BIT_MASK_DR0) << BIT_SHIFT_DR0)
#define BIT_CTRL_DR0(x) (((x) & BIT_MASK_DR0) << BIT_SHIFT_DR0)
#define BIT_GET_DR0(x) (((x) >> BIT_SHIFT_DR0) & BIT_MASK_DR0)
//2 REG_SPIC_DR1
#define BIT_SHIFT_DR1 0
#define BIT_MASK_DR1 0xffffffffL
#define BIT_DR1(x) (((x) & BIT_MASK_DR1) << BIT_SHIFT_DR1)
#define BIT_CTRL_DR1(x) (((x) & BIT_MASK_DR1) << BIT_SHIFT_DR1)
#define BIT_GET_DR1(x) (((x) >> BIT_SHIFT_DR1) & BIT_MASK_DR1)
//2 REG_SPIC_DR2
#define BIT_SHIFT_DR2 0
#define BIT_MASK_DR2 0xffffffffL
#define BIT_DR2(x) (((x) & BIT_MASK_DR2) << BIT_SHIFT_DR2)
#define BIT_CTRL_DR2(x) (((x) & BIT_MASK_DR2) << BIT_SHIFT_DR2)
#define BIT_GET_DR2(x) (((x) >> BIT_SHIFT_DR2) & BIT_MASK_DR2)
//2 REG_SPIC_DR3
#define BIT_SHIFT_DR3 0
#define BIT_MASK_DR3 0xffffffffL
#define BIT_DR3(x) (((x) & BIT_MASK_DR3) << BIT_SHIFT_DR3)
#define BIT_CTRL_DR3(x) (((x) & BIT_MASK_DR3) << BIT_SHIFT_DR3)
#define BIT_GET_DR3(x) (((x) >> BIT_SHIFT_DR3) & BIT_MASK_DR3)
//2 REG_SPIC_DR4
#define BIT_SHIFT_DR4 0
#define BIT_MASK_DR4 0xffffffffL
#define BIT_DR4(x) (((x) & BIT_MASK_DR4) << BIT_SHIFT_DR4)
#define BIT_CTRL_DR4(x) (((x) & BIT_MASK_DR4) << BIT_SHIFT_DR4)
#define BIT_GET_DR4(x) (((x) >> BIT_SHIFT_DR4) & BIT_MASK_DR4)
//2 REG_SPIC_DR5
#define BIT_SHIFT_DR5 0
#define BIT_MASK_DR5 0xffffffffL
#define BIT_DR5(x) (((x) & BIT_MASK_DR5) << BIT_SHIFT_DR5)
#define BIT_CTRL_DR5(x) (((x) & BIT_MASK_DR5) << BIT_SHIFT_DR5)
#define BIT_GET_DR5(x) (((x) >> BIT_SHIFT_DR5) & BIT_MASK_DR5)
//2 REG_SPIC_DR6
#define BIT_SHIFT_DR6 0
#define BIT_MASK_DR6 0xffffffffL
#define BIT_DR6(x) (((x) & BIT_MASK_DR6) << BIT_SHIFT_DR6)
#define BIT_CTRL_DR6(x) (((x) & BIT_MASK_DR6) << BIT_SHIFT_DR6)
#define BIT_GET_DR6(x) (((x) >> BIT_SHIFT_DR6) & BIT_MASK_DR6)
//2 REG_SPIC_DR7
#define BIT_SHIFT_DR7 0
#define BIT_MASK_DR7 0xffffffffL
#define BIT_DR7(x) (((x) & BIT_MASK_DR7) << BIT_SHIFT_DR7)
#define BIT_CTRL_DR7(x) (((x) & BIT_MASK_DR7) << BIT_SHIFT_DR7)
#define BIT_GET_DR7(x) (((x) >> BIT_SHIFT_DR7) & BIT_MASK_DR7)
//2 REG_SPIC_DR8
#define BIT_SHIFT_DR8 0
#define BIT_MASK_DR8 0xffffffffL
#define BIT_DR8(x) (((x) & BIT_MASK_DR8) << BIT_SHIFT_DR8)
#define BIT_CTRL_DR8(x) (((x) & BIT_MASK_DR8) << BIT_SHIFT_DR8)
#define BIT_GET_DR8(x) (((x) >> BIT_SHIFT_DR8) & BIT_MASK_DR8)
//2 REG_SPIC_DR9
#define BIT_SHIFT_DR9 0
#define BIT_MASK_DR9 0xffffffffL
#define BIT_DR9(x) (((x) & BIT_MASK_DR9) << BIT_SHIFT_DR9)
#define BIT_CTRL_DR9(x) (((x) & BIT_MASK_DR9) << BIT_SHIFT_DR9)
#define BIT_GET_DR9(x) (((x) >> BIT_SHIFT_DR9) & BIT_MASK_DR9)
//2 REG_SPIC_DR10
#define BIT_SHIFT_DR10 0
#define BIT_MASK_DR10 0xffffffffL
#define BIT_DR10(x) (((x) & BIT_MASK_DR10) << BIT_SHIFT_DR10)
#define BIT_CTRL_DR10(x) (((x) & BIT_MASK_DR10) << BIT_SHIFT_DR10)
#define BIT_GET_DR10(x) (((x) >> BIT_SHIFT_DR10) & BIT_MASK_DR10)
//2 REG_SPIC_DR11
#define BIT_SHIFT_DR11 0
#define BIT_MASK_DR11 0xffffffffL
#define BIT_DR11(x) (((x) & BIT_MASK_DR11) << BIT_SHIFT_DR11)
#define BIT_CTRL_DR11(x) (((x) & BIT_MASK_DR11) << BIT_SHIFT_DR11)
#define BIT_GET_DR11(x) (((x) >> BIT_SHIFT_DR11) & BIT_MASK_DR11)
//2 REG_SPIC_DR12
#define BIT_SHIFT_DR12 0
#define BIT_MASK_DR12 0xffffffffL
#define BIT_DR12(x) (((x) & BIT_MASK_DR12) << BIT_SHIFT_DR12)
#define BIT_CTRL_DR12(x) (((x) & BIT_MASK_DR12) << BIT_SHIFT_DR12)
#define BIT_GET_DR12(x) (((x) >> BIT_SHIFT_DR12) & BIT_MASK_DR12)
//2 REG_SPIC_DR13
#define BIT_SHIFT_DR13 0
#define BIT_MASK_DR13 0xffffffffL
#define BIT_DR13(x) (((x) & BIT_MASK_DR13) << BIT_SHIFT_DR13)
#define BIT_CTRL_DR13(x) (((x) & BIT_MASK_DR13) << BIT_SHIFT_DR13)
#define BIT_GET_DR13(x) (((x) >> BIT_SHIFT_DR13) & BIT_MASK_DR13)
//2 REG_SPIC_DR14
#define BIT_SHIFT_DR14 0
#define BIT_MASK_DR14 0xffffffffL
#define BIT_DR14(x) (((x) & BIT_MASK_DR14) << BIT_SHIFT_DR14)
#define BIT_CTRL_DR14(x) (((x) & BIT_MASK_DR14) << BIT_SHIFT_DR14)
#define BIT_GET_DR14(x) (((x) >> BIT_SHIFT_DR14) & BIT_MASK_DR14)
//2 REG_SPIC_DR15
#define BIT_SHIFT_DR15 0
#define BIT_MASK_DR15 0xffffffffL
#define BIT_DR15(x) (((x) & BIT_MASK_DR15) << BIT_SHIFT_DR15)
#define BIT_CTRL_DR15(x) (((x) & BIT_MASK_DR15) << BIT_SHIFT_DR15)
#define BIT_GET_DR15(x) (((x) >> BIT_SHIFT_DR15) & BIT_MASK_DR15)
//2 REG_SPIC_DR16
#define BIT_SHIFT_DR16 0
#define BIT_MASK_DR16 0xffffffffL
#define BIT_DR16(x) (((x) & BIT_MASK_DR16) << BIT_SHIFT_DR16)
#define BIT_CTRL_DR16(x) (((x) & BIT_MASK_DR16) << BIT_SHIFT_DR16)
#define BIT_GET_DR16(x) (((x) >> BIT_SHIFT_DR16) & BIT_MASK_DR16)
//2 REG_SPIC_DR17
#define BIT_SHIFT_DR17 0
#define BIT_MASK_DR17 0xffffffffL
#define BIT_DR17(x) (((x) & BIT_MASK_DR17) << BIT_SHIFT_DR17)
#define BIT_CTRL_DR17(x) (((x) & BIT_MASK_DR17) << BIT_SHIFT_DR17)
#define BIT_GET_DR17(x) (((x) >> BIT_SHIFT_DR17) & BIT_MASK_DR17)
//2 REG_SPIC_DR18
#define BIT_SHIFT_DR18 0
#define BIT_MASK_DR18 0xffffffffL
#define BIT_DR18(x) (((x) & BIT_MASK_DR18) << BIT_SHIFT_DR18)
#define BIT_CTRL_DR18(x) (((x) & BIT_MASK_DR18) << BIT_SHIFT_DR18)
#define BIT_GET_DR18(x) (((x) >> BIT_SHIFT_DR18) & BIT_MASK_DR18)
//2 REG_SPIC_DR19
#define BIT_SHIFT_DR19 0
#define BIT_MASK_DR19 0xffffffffL
#define BIT_DR19(x) (((x) & BIT_MASK_DR19) << BIT_SHIFT_DR19)
#define BIT_CTRL_DR19(x) (((x) & BIT_MASK_DR19) << BIT_SHIFT_DR19)
#define BIT_GET_DR19(x) (((x) >> BIT_SHIFT_DR19) & BIT_MASK_DR19)
//2 REG_SPIC_DR20
#define BIT_SHIFT_DR20 0
#define BIT_MASK_DR20 0xffffffffL
#define BIT_DR20(x) (((x) & BIT_MASK_DR20) << BIT_SHIFT_DR20)
#define BIT_CTRL_DR20(x) (((x) & BIT_MASK_DR20) << BIT_SHIFT_DR20)
#define BIT_GET_DR20(x) (((x) >> BIT_SHIFT_DR20) & BIT_MASK_DR20)
//2 REG_SPIC_DR21
#define BIT_SHIFT_DR21 0
#define BIT_MASK_DR21 0xffffffffL
#define BIT_DR21(x) (((x) & BIT_MASK_DR21) << BIT_SHIFT_DR21)
#define BIT_CTRL_DR21(x) (((x) & BIT_MASK_DR21) << BIT_SHIFT_DR21)
#define BIT_GET_DR21(x) (((x) >> BIT_SHIFT_DR21) & BIT_MASK_DR21)
//2 REG_SPIC_DR22
#define BIT_SHIFT_DR22 0
#define BIT_MASK_DR22 0xffffffffL
#define BIT_DR22(x) (((x) & BIT_MASK_DR22) << BIT_SHIFT_DR22)
#define BIT_CTRL_DR22(x) (((x) & BIT_MASK_DR22) << BIT_SHIFT_DR22)
#define BIT_GET_DR22(x) (((x) >> BIT_SHIFT_DR22) & BIT_MASK_DR22)
//2 REG_SPIC_DR23
#define BIT_SHIFT_DR23 0
#define BIT_MASK_DR23 0xffffffffL
#define BIT_DR23(x) (((x) & BIT_MASK_DR23) << BIT_SHIFT_DR23)
#define BIT_CTRL_DR23(x) (((x) & BIT_MASK_DR23) << BIT_SHIFT_DR23)
#define BIT_GET_DR23(x) (((x) >> BIT_SHIFT_DR23) & BIT_MASK_DR23)
//2 REG_SPIC_DR24
#define BIT_SHIFT_DR24 0
#define BIT_MASK_DR24 0xffffffffL
#define BIT_DR24(x) (((x) & BIT_MASK_DR24) << BIT_SHIFT_DR24)
#define BIT_CTRL_DR24(x) (((x) & BIT_MASK_DR24) << BIT_SHIFT_DR24)
#define BIT_GET_DR24(x) (((x) >> BIT_SHIFT_DR24) & BIT_MASK_DR24)
//2 REG_SPIC_DR25
#define BIT_SHIFT_DR25 0
#define BIT_MASK_DR25 0xffffffffL
#define BIT_DR25(x) (((x) & BIT_MASK_DR25) << BIT_SHIFT_DR25)
#define BIT_CTRL_DR25(x) (((x) & BIT_MASK_DR25) << BIT_SHIFT_DR25)
#define BIT_GET_DR25(x) (((x) >> BIT_SHIFT_DR25) & BIT_MASK_DR25)
//2 REG_SPIC_DR26
#define BIT_SHIFT_DR26 0
#define BIT_MASK_DR26 0xffffffffL
#define BIT_DR26(x) (((x) & BIT_MASK_DR26) << BIT_SHIFT_DR26)
#define BIT_CTRL_DR26(x) (((x) & BIT_MASK_DR26) << BIT_SHIFT_DR26)
#define BIT_GET_DR26(x) (((x) >> BIT_SHIFT_DR26) & BIT_MASK_DR26)
//2 REG_SPIC_DR27
#define BIT_SHIFT_DR27 0
#define BIT_MASK_DR27 0xffffffffL
#define BIT_DR27(x) (((x) & BIT_MASK_DR27) << BIT_SHIFT_DR27)
#define BIT_CTRL_DR27(x) (((x) & BIT_MASK_DR27) << BIT_SHIFT_DR27)
#define BIT_GET_DR27(x) (((x) >> BIT_SHIFT_DR27) & BIT_MASK_DR27)
//2 REG_SPIC_DR28
#define BIT_SHIFT_DR28 0
#define BIT_MASK_DR28 0xffffffffL
#define BIT_DR28(x) (((x) & BIT_MASK_DR28) << BIT_SHIFT_DR28)
#define BIT_CTRL_DR28(x) (((x) & BIT_MASK_DR28) << BIT_SHIFT_DR28)
#define BIT_GET_DR28(x) (((x) >> BIT_SHIFT_DR28) & BIT_MASK_DR28)
//2 REG_SPIC_DR29
#define BIT_SHIFT_DR29 0
#define BIT_MASK_DR29 0xffffffffL
#define BIT_DR29(x) (((x) & BIT_MASK_DR29) << BIT_SHIFT_DR29)
#define BIT_CTRL_DR29(x) (((x) & BIT_MASK_DR29) << BIT_SHIFT_DR29)
#define BIT_GET_DR29(x) (((x) >> BIT_SHIFT_DR29) & BIT_MASK_DR29)
//2 REG_SPIC_DR30
#define BIT_SHIFT_DR30 0
#define BIT_MASK_DR30 0xffffffffL
#define BIT_DR30(x) (((x) & BIT_MASK_DR30) << BIT_SHIFT_DR30)
#define BIT_CTRL_DR30(x) (((x) & BIT_MASK_DR30) << BIT_SHIFT_DR30)
#define BIT_GET_DR30(x) (((x) >> BIT_SHIFT_DR30) & BIT_MASK_DR30)
//2 REG_SPIC_DR31
#define BIT_SHIFT_DR31 0
#define BIT_MASK_DR31 0xffffffffL
#define BIT_DR31(x) (((x) & BIT_MASK_DR31) << BIT_SHIFT_DR31)
#define BIT_CTRL_DR31(x) (((x) & BIT_MASK_DR31) << BIT_SHIFT_DR31)
#define BIT_GET_DR31(x) (((x) >> BIT_SHIFT_DR31) & BIT_MASK_DR31)
//2 REG_SPIC_READ_FAST_SINGLE
#define BIT_SHIFT_FRD_CMD 0
#define BIT_MASK_FRD_CMD 0xff
#define BIT_FRD_CMD(x) (((x) & BIT_MASK_FRD_CMD) << BIT_SHIFT_FRD_CMD)
#define BIT_CTRL_FRD_CMD(x) (((x) & BIT_MASK_FRD_CMD) << BIT_SHIFT_FRD_CMD)
#define BIT_GET_FRD_CMD(x) (((x) >> BIT_SHIFT_FRD_CMD) & BIT_MASK_FRD_CMD)
//2 REG_SPIC_READ_DUAL_DATA
#define BIT_SHIFT_RD_DUAL_O_CMD 0
#define BIT_MASK_RD_DUAL_O_CMD 0xff
#define BIT_RD_DUAL_O_CMD(x) (((x) & BIT_MASK_RD_DUAL_O_CMD) << BIT_SHIFT_RD_DUAL_O_CMD)
#define BIT_CTRL_RD_DUAL_O_CMD(x) (((x) & BIT_MASK_RD_DUAL_O_CMD) << BIT_SHIFT_RD_DUAL_O_CMD)
#define BIT_GET_RD_DUAL_O_CMD(x) (((x) >> BIT_SHIFT_RD_DUAL_O_CMD) & BIT_MASK_RD_DUAL_O_CMD)
//2 REG_SPIC_READ_DUAL_ADDR_DATA
#define BIT_SHIFT_RD_DUAL_IO_CMD 0
#define BIT_MASK_RD_DUAL_IO_CMD 0xff
#define BIT_RD_DUAL_IO_CMD(x) (((x) & BIT_MASK_RD_DUAL_IO_CMD) << BIT_SHIFT_RD_DUAL_IO_CMD)
#define BIT_CTRL_RD_DUAL_IO_CMD(x) (((x) & BIT_MASK_RD_DUAL_IO_CMD) << BIT_SHIFT_RD_DUAL_IO_CMD)
#define BIT_GET_RD_DUAL_IO_CMD(x) (((x) >> BIT_SHIFT_RD_DUAL_IO_CMD) & BIT_MASK_RD_DUAL_IO_CMD)
//2 REG_SPIC_READ_QUAD_DATA
#define BIT_SHIFT_RD_QUAD_O_CMD 0
#define BIT_MASK_RD_QUAD_O_CMD 0xff
#define BIT_RD_QUAD_O_CMD(x) (((x) & BIT_MASK_RD_QUAD_O_CMD) << BIT_SHIFT_RD_QUAD_O_CMD)
#define BIT_CTRL_RD_QUAD_O_CMD(x) (((x) & BIT_MASK_RD_QUAD_O_CMD) << BIT_SHIFT_RD_QUAD_O_CMD)
#define BIT_GET_RD_QUAD_O_CMD(x) (((x) >> BIT_SHIFT_RD_QUAD_O_CMD) & BIT_MASK_RD_QUAD_O_CMD)
//2 REG_SPIC_READ_QUAD_ADDR_DATA
#define BIT_SHIFT_RD_QUAD_IO_CMD 0
#define BIT_MASK_RD_QUAD_IO_CMD 0xff
#define BIT_RD_QUAD_IO_CMD(x) (((x) & BIT_MASK_RD_QUAD_IO_CMD) << BIT_SHIFT_RD_QUAD_IO_CMD)
#define BIT_CTRL_RD_QUAD_IO_CMD(x) (((x) & BIT_MASK_RD_QUAD_IO_CMD) << BIT_SHIFT_RD_QUAD_IO_CMD)
#define BIT_GET_RD_QUAD_IO_CMD(x) (((x) >> BIT_SHIFT_RD_QUAD_IO_CMD) & BIT_MASK_RD_QUAD_IO_CMD)
//2 REG_SPIC_WRITE_SIGNLE
#define BIT_SHIFT_WR_CMD 0
#define BIT_MASK_WR_CMD 0xff
#define BIT_WR_CMD(x) (((x) & BIT_MASK_WR_CMD) << BIT_SHIFT_WR_CMD)
#define BIT_CTRL_WR_CMD(x) (((x) & BIT_MASK_WR_CMD) << BIT_SHIFT_WR_CMD)
#define BIT_GET_WR_CMD(x) (((x) >> BIT_SHIFT_WR_CMD) & BIT_MASK_WR_CMD)
//2 REG_SPIC_WRITE_DUAL_DATA
#define BIT_SHIFT_WR_DUAL_I_CMD 0
#define BIT_MASK_WR_DUAL_I_CMD 0xff
#define BIT_WR_DUAL_I_CMD(x) (((x) & BIT_MASK_WR_DUAL_I_CMD) << BIT_SHIFT_WR_DUAL_I_CMD)
#define BIT_CTRL_WR_DUAL_I_CMD(x) (((x) & BIT_MASK_WR_DUAL_I_CMD) << BIT_SHIFT_WR_DUAL_I_CMD)
#define BIT_GET_WR_DUAL_I_CMD(x) (((x) >> BIT_SHIFT_WR_DUAL_I_CMD) & BIT_MASK_WR_DUAL_I_CMD)
//2 REG_SPIC_WRITE_DUAL_ADDR_DATA
#define BIT_SHIFT_WR_DUAL_II_CMD 0
#define BIT_MASK_WR_DUAL_II_CMD 0xff
#define BIT_WR_DUAL_II_CMD(x) (((x) & BIT_MASK_WR_DUAL_II_CMD) << BIT_SHIFT_WR_DUAL_II_CMD)
#define BIT_CTRL_WR_DUAL_II_CMD(x) (((x) & BIT_MASK_WR_DUAL_II_CMD) << BIT_SHIFT_WR_DUAL_II_CMD)
#define BIT_GET_WR_DUAL_II_CMD(x) (((x) >> BIT_SHIFT_WR_DUAL_II_CMD) & BIT_MASK_WR_DUAL_II_CMD)
//2 REG_SPIC_WRITE_QUAD_DATA
#define BIT_SHIFT_WR_QUAD_I_CMD 0
#define BIT_MASK_WR_QUAD_I_CMD 0xff
#define BIT_WR_QUAD_I_CMD(x) (((x) & BIT_MASK_WR_QUAD_I_CMD) << BIT_SHIFT_WR_QUAD_I_CMD)
#define BIT_CTRL_WR_QUAD_I_CMD(x) (((x) & BIT_MASK_WR_QUAD_I_CMD) << BIT_SHIFT_WR_QUAD_I_CMD)
#define BIT_GET_WR_QUAD_I_CMD(x) (((x) >> BIT_SHIFT_WR_QUAD_I_CMD) & BIT_MASK_WR_QUAD_I_CMD)
//2 REG_SPIC_WRITE_QUAD_ADDR_DATA
#define BIT_SHIFT_WR_QUAD_II_CMD 0
#define BIT_MASK_WR_QUAD_II_CMD 0xff
#define BIT_WR_QUAD_II_CMD(x) (((x) & BIT_MASK_WR_QUAD_II_CMD) << BIT_SHIFT_WR_QUAD_II_CMD)
#define BIT_CTRL_WR_QUAD_II_CMD(x) (((x) & BIT_MASK_WR_QUAD_II_CMD) << BIT_SHIFT_WR_QUAD_II_CMD)
#define BIT_GET_WR_QUAD_II_CMD(x) (((x) >> BIT_SHIFT_WR_QUAD_II_CMD) & BIT_MASK_WR_QUAD_II_CMD)
//2 REG_SPIC_WRITE_ENABLE
#define BIT_SHIFT_WR_EN_CMD 0
#define BIT_MASK_WR_EN_CMD 0xff
#define BIT_WR_EN_CMD(x) (((x) & BIT_MASK_WR_EN_CMD) << BIT_SHIFT_WR_EN_CMD)
#define BIT_CTRL_WR_EN_CMD(x) (((x) & BIT_MASK_WR_EN_CMD) << BIT_SHIFT_WR_EN_CMD)
#define BIT_GET_WR_EN_CMD(x) (((x) >> BIT_SHIFT_WR_EN_CMD) & BIT_MASK_WR_EN_CMD)
//2 REG_SPIC_READ_STATUS
#define BIT_SHIFT_RD_ST_CMD 0
#define BIT_MASK_RD_ST_CMD 0xff
#define BIT_RD_ST_CMD(x) (((x) & BIT_MASK_RD_ST_CMD) << BIT_SHIFT_RD_ST_CMD)
#define BIT_CTRL_RD_ST_CMD(x) (((x) & BIT_MASK_RD_ST_CMD) << BIT_SHIFT_RD_ST_CMD)
#define BIT_GET_RD_ST_CMD(x) (((x) >> BIT_SHIFT_RD_ST_CMD) & BIT_MASK_RD_ST_CMD)
//2 REG_SPIC_CTRLR2
#define BIT_SHIFT_FIFO_ENTRY 4
#define BIT_MASK_FIFO_ENTRY 0xf
#define BIT_FIFO_ENTRY(x) (((x) & BIT_MASK_FIFO_ENTRY) << BIT_SHIFT_FIFO_ENTRY)
#define BIT_CTRL_FIFO_ENTRY(x) (((x) & BIT_MASK_FIFO_ENTRY) << BIT_SHIFT_FIFO_ENTRY)
#define BIT_GET_FIFO_ENTRY(x) (((x) >> BIT_SHIFT_FIFO_ENTRY) & BIT_MASK_FIFO_ENTRY)
#define BIT_WR_SEQ BIT(3)
#define BIT_SHIFT_WR_SEQ 3
#define BIT_MASK_WR_SEQ 0x1
#define BIT_CTRL_WR_SEQ(x) (((x) & BIT_MASK_WR_SEQ) << BIT_SHIFT_WR_SEQ)
#define BIT_WPN_DNUM BIT(2)
#define BIT_SHIFT_WPN_DNUM 2
#define BIT_MASK_WPN_DNUM 0x1
#define BIT_CTRL_WPN_DNUM(x) (((x) & BIT_MASK_WPN_DNUM) << BIT_SHIFT_WPN_DNUM)
#define BIT_WPN_SET BIT(1)
#define BIT_SHIFT_WPN_SET 1
#define BIT_MASK_WPN_SET 0x1
#define BIT_CTRL_WPN_SET(x) (((x) & BIT_MASK_WPN_SET) << BIT_SHIFT_WPN_SET)
#define BIT_SO_DUM BIT(0)
#define BIT_SHIFT_SO_DUM 0
#define BIT_MASK_SO_DUM 0x1
#define BIT_CTRL_SO_DUM(x) (((x) & BIT_MASK_SO_DUM) << BIT_SHIFT_SO_DUM)
//2 REG_SPIC_FBAUDR
#define BIT_SHIFT_FSCKDV 0
#define BIT_MASK_FSCKDV 0xfff
#define BIT_FSCKDV(x) (((x) & BIT_MASK_FSCKDV) << BIT_SHIFT_FSCKDV)
#define BIT_CTRL_FSCKDV(x) (((x) & BIT_MASK_FSCKDV) << BIT_SHIFT_FSCKDV)
#define BIT_GET_FSCKDV(x) (((x) >> BIT_SHIFT_FSCKDV) & BIT_MASK_FSCKDV)
//2 REG_SPIC_ADDR_LENGTH
#define BIT_SHIFT_ADDR_PHASE_LENGTH 0
#define BIT_MASK_ADDR_PHASE_LENGTH 0x3
#define BIT_ADDR_PHASE_LENGTH(x) (((x) & BIT_MASK_ADDR_PHASE_LENGTH) << BIT_SHIFT_ADDR_PHASE_LENGTH)
#define BIT_CTRL_ADDR_PHASE_LENGTH(x) (((x) & BIT_MASK_ADDR_PHASE_LENGTH) << BIT_SHIFT_ADDR_PHASE_LENGTH)
#define BIT_GET_ADDR_PHASE_LENGTH(x) (((x) >> BIT_SHIFT_ADDR_PHASE_LENGTH) & BIT_MASK_ADDR_PHASE_LENGTH)
//2 REG_SPIC_AUTO_LENGTH
#define BIT_SHIFT_CS_H_WR_DUM_LEN 28
#define BIT_MASK_CS_H_WR_DUM_LEN 0xf
#define BIT_CS_H_WR_DUM_LEN(x) (((x) & BIT_MASK_CS_H_WR_DUM_LEN) << BIT_SHIFT_CS_H_WR_DUM_LEN)
#define BIT_CTRL_CS_H_WR_DUM_LEN(x) (((x) & BIT_MASK_CS_H_WR_DUM_LEN) << BIT_SHIFT_CS_H_WR_DUM_LEN)
#define BIT_GET_CS_H_WR_DUM_LEN(x) (((x) >> BIT_SHIFT_CS_H_WR_DUM_LEN) & BIT_MASK_CS_H_WR_DUM_LEN)
#define BIT_SHIFT_CS_H_RD_DUM_LEN 26
#define BIT_MASK_CS_H_RD_DUM_LEN 0x3
#define BIT_CS_H_RD_DUM_LEN(x) (((x) & BIT_MASK_CS_H_RD_DUM_LEN) << BIT_SHIFT_CS_H_RD_DUM_LEN)
#define BIT_CTRL_CS_H_RD_DUM_LEN(x) (((x) & BIT_MASK_CS_H_RD_DUM_LEN) << BIT_SHIFT_CS_H_RD_DUM_LEN)
#define BIT_GET_CS_H_RD_DUM_LEN(x) (((x) >> BIT_SHIFT_CS_H_RD_DUM_LEN) & BIT_MASK_CS_H_RD_DUM_LEN)
#define BIT_SHIFT_AUTO_DUM_LEN 18
#define BIT_MASK_AUTO_DUM_LEN 0xff
#define BIT_AUTO_DUM_LEN(x) (((x) & BIT_MASK_AUTO_DUM_LEN) << BIT_SHIFT_AUTO_DUM_LEN)
#define BIT_CTRL_AUTO_DUM_LEN(x) (((x) & BIT_MASK_AUTO_DUM_LEN) << BIT_SHIFT_AUTO_DUM_LEN)
#define BIT_GET_AUTO_DUM_LEN(x) (((x) >> BIT_SHIFT_AUTO_DUM_LEN) & BIT_MASK_AUTO_DUM_LEN)
#define BIT_SHIFT_AUTO_ADDR__LENGTH 16
#define BIT_MASK_AUTO_ADDR__LENGTH 0x3
#define BIT_AUTO_ADDR__LENGTH(x) (((x) & BIT_MASK_AUTO_ADDR__LENGTH) << BIT_SHIFT_AUTO_ADDR__LENGTH)
#define BIT_CTRL_AUTO_ADDR__LENGTH(x) (((x) & BIT_MASK_AUTO_ADDR__LENGTH) << BIT_SHIFT_AUTO_ADDR__LENGTH)
#define BIT_GET_AUTO_ADDR__LENGTH(x) (((x) >> BIT_SHIFT_AUTO_ADDR__LENGTH) & BIT_MASK_AUTO_ADDR__LENGTH)
#define BIT_SHIFT_RD_DUMMY_LENGTH 0
#define BIT_MASK_RD_DUMMY_LENGTH 0xffff
#define BIT_RD_DUMMY_LENGTH(x) (((x) & BIT_MASK_RD_DUMMY_LENGTH) << BIT_SHIFT_RD_DUMMY_LENGTH)
#define BIT_CTRL_RD_DUMMY_LENGTH(x) (((x) & BIT_MASK_RD_DUMMY_LENGTH) << BIT_SHIFT_RD_DUMMY_LENGTH)
#define BIT_GET_RD_DUMMY_LENGTH(x) (((x) >> BIT_SHIFT_RD_DUMMY_LENGTH) & BIT_MASK_RD_DUMMY_LENGTH)
//2 REG_SPIC_VALID_CMD
#define BIT_WR_BLOCKING BIT(9)
#define BIT_SHIFT_WR_BLOCKING 9
#define BIT_MASK_WR_BLOCKING 0x1
#define BIT_CTRL_WR_BLOCKING(x) (((x) & BIT_MASK_WR_BLOCKING) << BIT_SHIFT_WR_BLOCKING)
#define BIT_WR_QUAD_II BIT(8)
#define BIT_SHIFT_WR_QUAD_II 8
#define BIT_MASK_WR_QUAD_II 0x1
#define BIT_CTRL_WR_QUAD_II(x) (((x) & BIT_MASK_WR_QUAD_II) << BIT_SHIFT_WR_QUAD_II)
#define BIT_WR_QUAD_I BIT(7)
#define BIT_SHIFT_WR_QUAD_I 7
#define BIT_MASK_WR_QUAD_I 0x1
#define BIT_CTRL_WR_QUAD_I(x) (((x) & BIT_MASK_WR_QUAD_I) << BIT_SHIFT_WR_QUAD_I)
#define BIT_WR_DUAL_II BIT(6)
#define BIT_SHIFT_WR_DUAL_II 6
#define BIT_MASK_WR_DUAL_II 0x1
#define BIT_CTRL_WR_DUAL_II(x) (((x) & BIT_MASK_WR_DUAL_II) << BIT_SHIFT_WR_DUAL_II)
#define BIT_WR_DUAL_I BIT(5)
#define BIT_SHIFT_WR_DUAL_I 5
#define BIT_MASK_WR_DUAL_I 0x1
#define BIT_CTRL_WR_DUAL_I(x) (((x) & BIT_MASK_WR_DUAL_I) << BIT_SHIFT_WR_DUAL_I)
#define BIT_RD_QUAD_IO BIT(4)
#define BIT_SHIFT_RD_QUAD_IO 4
#define BIT_MASK_RD_QUAD_IO 0x1
#define BIT_CTRL_RD_QUAD_IO(x) (((x) & BIT_MASK_RD_QUAD_IO) << BIT_SHIFT_RD_QUAD_IO)
#define BIT_RD_QUAD_O BIT(3)
#define BIT_SHIFT_RD_QUAD_O 3
#define BIT_MASK_RD_QUAD_O 0x1
#define BIT_CTRL_RD_QUAD_O(x) (((x) & BIT_MASK_RD_QUAD_O) << BIT_SHIFT_RD_QUAD_O)
#define BIT_RD_DUAL_IO BIT(2)
#define BIT_SHIFT_RD_DUAL_IO 2
#define BIT_MASK_RD_DUAL_IO 0x1
#define BIT_CTRL_RD_DUAL_IO(x) (((x) & BIT_MASK_RD_DUAL_IO) << BIT_SHIFT_RD_DUAL_IO)
#define BIT_RD_DUAL_I BIT(1)
#define BIT_SHIFT_RD_DUAL_I 1
#define BIT_MASK_RD_DUAL_I 0x1
#define BIT_CTRL_RD_DUAL_I(x) (((x) & BIT_MASK_RD_DUAL_I) << BIT_SHIFT_RD_DUAL_I)
#define BIT_FRD_SINGEL BIT(0)
#define BIT_SHIFT_FRD_SINGEL 0
#define BIT_MASK_FRD_SINGEL 0x1
#define BIT_CTRL_FRD_SINGEL(x) (((x) & BIT_MASK_FRD_SINGEL) << BIT_SHIFT_FRD_SINGEL)
//2 REG_SPIC_FLASE_SIZE
#define BIT_SHIFT_FLASE_SIZE 0
#define BIT_MASK_FLASE_SIZE 0xf
#define BIT_FLASE_SIZE(x) (((x) & BIT_MASK_FLASE_SIZE) << BIT_SHIFT_FLASE_SIZE)
#define BIT_CTRL_FLASE_SIZE(x) (((x) & BIT_MASK_FLASE_SIZE) << BIT_SHIFT_FLASE_SIZE)
#define BIT_GET_FLASE_SIZE(x) (((x) >> BIT_SHIFT_FLASE_SIZE) & BIT_MASK_FLASE_SIZE)
//2 REG_SPIC_FLUSH_FIFO
#define BIT_FLUSH_FIFO BIT(0)
#define BIT_SHIFT_FLUSH_FIFO 0
#define BIT_MASK_FLUSH_FIFO 0x1
#define BIT_CTRL_FLUSH_FIFO(x) (((x) & BIT_MASK_FLUSH_FIFO) << BIT_SHIFT_FLUSH_FIFO)
//=================== Register Address Definition ============================//
#define REG_SPIC_CTRLR0 0x0000//O
#define REG_SPIC_CTRLR1 0x0004//O
#define REG_SPIC_SSIENR 0x0008//O
#define REG_SPIC_MWCR 0x000C
#define REG_SPIC_SER 0x0010//O
#define REG_SPIC_BAUDR 0x0014//O
#define REG_SPIC_TXFTLR 0x0018
#define REG_SPIC_RXFTLR 0x001C//O
#define REG_SPIC_TXFLR 0x0020//O
#define REG_SPIC_RXFLR 0x0024
#define REG_SPIC_SR 0x0028
#define REG_SPIC_IMR 0x002C//O
#define REG_SPIC_ISR 0x0030
#define REG_SPIC_RISR 0x0034
#define REG_SPIC_TXOICR 0x0038
#define REG_SPIC_RXOICR 0x003C
#define REG_SPC_RXUICR 0x0040
#define REG_SPIC_MSTICR 0x0044
#define REG_SPIC_ICR 0x0048
#define REG_SPIC_DMACR 0x004C
#define REG_SPIC_DMATDLR0 0x0050
#define REG_SPIC_DMATDLR1 0x0054
#define REG_SPIC_IDR 0x0058
#define REG_SPIC_VERSION 0x005C
#define REG_SPIC_DR0 0x0060
#define REG_SPIC_DR1 0x0064
#define REG_SPIC_DR2 0x0068
#define REG_SPIC_DR3 0x006C
#define REG_SPIC_DR4 0x0070
#define REG_SPIC_DR5 0x0074
#define REG_SPIC_DR6 0x0078
#define REG_SPIC_DR7 0x007C
#define REG_SPIC_DR8 0x0080
#define REG_SPIC_DR9 0x0084
#define REG_SPIC_DR10 0x0088
#define REG_SPIC_DR11 0x008C
#define REG_SPIC_DR12 0x0090
#define REG_SPIC_DR13 0x0094
#define REG_SPIC_DR14 0x0098
#define REG_SPIC_DR15 0x009C
#define REG_SPIC_DR16 0x00A0
#define REG_SPIC_DR17 0x00A4
#define REG_SPIC_DR18 0x00A8
#define REG_SPIC_DR19 0x00AC
#define REG_SPIC_DR20 0x00B0
#define REG_SPIC_DR21 0x00B4
#define REG_SPIC_DR22 0x00B8
#define REG_SPIC_DR23 0x00BC
#define REG_SPIC_DR24 0x00C0
#define REG_SPIC_DR25 0x00C4
#define REG_SPIC_DR26 0x00C8
#define REG_SPIC_DR27 0x00CC
#define REG_SPIC_DR28 0x00D0
#define REG_SPIC_DR29 0x00D4
#define REG_SPIC_DR30 0x00D8
#define REG_SPIC_DR31 0x00DC
#define REG_SPIC_READ_FAST_SINGLE 0x00E0//O
#define REG_SPIC_READ_DUAL_DATA 0x00E4//O
#define REG_SPIC_READ_DUAL_ADDR_DATA 0x00E8//O
#define REG_SPIC_READ_QUAD_DATA 0x00EC//O
#define REG_SPIC_READ_QUAD_ADDR_DATA 0x00F0//O
#define REG_SPIC_WRITE_SIGNLE 0x00F4//O
#define REG_SPIC_WRITE_DUAL_DATA 0x00F8//O
#define REG_SPIC_WRITE_DUAL_ADDR_DATA 0x00FC//O
#define REG_SPIC_WRITE_QUAD_DATA 0x0100//O
#define REG_SPIC_WRITE_QUAD_ADDR_DATA 0x0104//O
#define REG_SPIC_WRITE_ENABLE 0x0108//O
#define REG_SPIC_READ_STATUS 0x010C//O
#define REG_SPIC_CTRLR2 0x0110//O
#define REG_SPIC_FBAUDR 0x0114//O
#define REG_SPIC_ADDR_LENGTH 0x0118//O
#define REG_SPIC_AUTO_LENGTH 0x011C//O
#define REG_SPIC_VALID_CMD 0x0120//O
#define REG_SPIC_FLASE_SIZE 0x0124//O
#define REG_SPIC_FLUSH_FIFO 0x0128//O
#endif // end of "#ifndef _RTL8195A_SPI_FLASH_H"

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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_ssi.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_SSI_H_
#define _RTL8195A_SSI_H_
#define SSI_DUMMY_DATA 0x00 // for master mode, we need to push a Dummy data to TX FIFO for read
#define SSI_CLK_SPI1 (PLATFORM_CLOCK/2)
#define SSI_CLK_SPI0_2 (PLATFORM_CLOCK/4)
/* Parameters of DW_apb_ssi for RTL8195A */
#define SSI_TX_FIFO_DEPTH 64
#define TX_ABW 6 // 1-8, log2(SSI_TX_FIFO_DEPTH)
#define SSI_RX_FIFO_DEPTH 64
#define RX_ABW 6 // 1-8, log2(SSI_RX_FIFO_DEPTH)
#define SSI0_REG_BASE 0x40042000
#define SSI1_REG_BASE 0x40042400
#define SSI2_REG_BASE 0x40042800
/* Memory Map of DW_apb_ssi */
#define REG_DW_SSI_CTRLR0 0x00 // 16 bits
#define REG_DW_SSI_CTRLR1 0x04 // 16 bits
#define REG_DW_SSI_SSIENR 0x08 // 1 bit
#define REG_DW_SSI_MWCR 0x0C // 3 bits
#define REG_DW_SSI_SER 0x10 //
#define REG_DW_SSI_BAUDR 0x14 // 16 bits
#define REG_DW_SSI_TXFTLR 0x18 // TX_ABW
#define REG_DW_SSI_RXFTLR 0x1C // RX_ABW
#define REG_DW_SSI_TXFLR 0x20 //
#define REG_DW_SSI_RXFLR 0x24 //
#define REG_DW_SSI_SR 0x28 // 7 bits
#define REG_DW_SSI_IMR 0x2C //
#define REG_DW_SSI_ISR 0x30 // 6 bits
#define REG_DW_SSI_RISR 0x34 // 6 bits
#define REG_DW_SSI_TXOICR 0x38 // 1 bits
#define REG_DW_SSI_RXOICR 0x3C // 1 bits
#define REG_DW_SSI_RXUICR 0x40 // 1 bits
#define REG_DW_SSI_MSTICR 0x44 // 1 bits
#define REG_DW_SSI_ICR 0x48 // 1 bits
#define REG_DW_SSI_DMACR 0x4C // 2 bits
#define REG_DW_SSI_DMATDLR 0x50 // TX_ABW
#define REG_DW_SSI_DMARDLR 0x54 // RX_ABW
#define REG_DW_SSI_IDR 0x58 // 32 bits
#define REG_DW_SSI_COMP_VERSION 0x5C // 32 bits
#define REG_DW_SSI_DR 0x60 // 16 bits 0x60-0xEC
#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits
#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits
#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits
#define REG_DW_SSI_RSVD_2 0xFC // 32 bits
// CTRLR0 0x00 // 16 bits, 6.2.1
// DFS Reset Value: 0x7
#define BIT_SHIFT_CTRLR0_DFS 0
#define BIT_MASK_CTRLR0_DFS 0xF
#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS)
#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS))
#define BIT_SHIFT_CTRLR0_FRF 4
#define BIT_MASK_CTRLR0_FRF 0x3
#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF)
#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF))
#define BIT_SHIFT_CTRLR0_SCPH 6
#define BIT_MASK_CTRLR0_SCPH 0x1
#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH)
#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH))
#define BIT_SHIFT_CTRLR0_SCPOL 7
#define BIT_MASK_CTRLR0_SCPOL 0x1
#define BIT_CTRLR0_SCPOL(x)(((x) & BIT_MASK_CTRLR0_SCPOL) << BIT_SHIFT_CTRLR0_SCPOL)
#define BIT_INVC_CTRLR0_SCPOL (~(BIT_MASK_CTRLR0_SCPOL << BIT_SHIFT_CTRLR0_SCPOL))
#define BIT_SHIFT_CTRLR0_TMOD 8
#define BIT_MASK_CTRLR0_TMOD 0x3
#define BIT_CTRLR0_TMOD(x)(((x) & BIT_MASK_CTRLR0_TMOD) << BIT_SHIFT_CTRLR0_TMOD)
#define BIT_INVC_CTRLR0_TMOD (~(BIT_MASK_CTRLR0_TMOD << BIT_SHIFT_CTRLR0_TMOD))
#define BIT_SHIFT_CTRLR0_SLV_OE 10
#define BIT_MASK_CTRLR0_SLV_OE 0x1
#define BIT_CTRLR0_SLV_OE(x)(((x) & BIT_MASK_CTRLR0_SLV_OE) << BIT_SHIFT_CTRLR0_SLV_OE)
#define BIT_INVC_CTRLR0_SLV_OE (~(BIT_MASK_CTRLR0_SLV_OE << BIT_SHIFT_CTRLR0_SLV_OE))
#define BIT_SHIFT_CTRLR0_SRL 11
#define BIT_MASK_CTRLR0_SRL 0x1
#define BIT_CTRLR0_SRL(x)(((x) & BIT_MASK_CTRLR0_SRL) << BIT_SHIFT_CTRLR0_SRL)
#define BIT_INVC_CTRLR0_SRL (~(BIT_MASK_CTRLR0_SRL << BIT_SHIFT_CTRLR0_SRL))
#define BIT_SHIFT_CTRLR0_CFS 12
#define BIT_MASK_CTRLR0_CFS 0xF
#define BIT_CTRLR0_CFS(x)(((x) & BIT_MASK_CTRLR0_CFS) << BIT_SHIFT_CTRLR0_CFS)
#define BIT_INVC_CTRLR0_CFS (~(BIT_MASK_CTRLR0_CFS << BIT_SHIFT_CTRLR0_CFS))
// CTRLR1 0x04 // 16 bits
#define BIT_SHIFT_CTRLR1_NDF 0
#define BIT_MASK_CTRLR1_NDF 0xFFFF
#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF)
#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF))
// SSIENR 0x08 // 1 bit
#define BIT_SHIFT_SSIENR_SSI_EN 0
#define BIT_MASK_SSIENR_SSI_EN 0x1
#define BIT_SSIENR_SSI_EN(x)(((x) & BIT_MASK_SSIENR_SSI_EN) << BIT_SHIFT_SSIENR_SSI_EN)
#define BIT_INVC_SSIENR_SSI_EN (~(BIT_MASK_SSIENR_SSI_EN << BIT_SHIFT_SSIENR_SSI_EN))
// MWCR 0x0c // 3 bits
#define BIT_SHIFT_MWCR_MWMOD 0
#define BIT_MASK_MWCR_MWMOD 0x1
#define BIT_MWCR_MWMOD(x)(((x) & BIT_MASK_MWCR_MWMOD) << BIT_SHIFT_MWCR_MWMOD)
#define BIT_INVC_MWCR_MWMOD (~(BIT_MASK_MWCR_MWMOD << BIT_SHIFT_MWCR_MWMOD))
#define BIT_SHIFT_MWCR_MDD 1
#define BIT_MASK_MWCR_MDD 0x1
#define BIT_MWCR_MDD(x)(((x) & BIT_MASK_MWCR_MDD) << BIT_SHIFT_MWCR_MDD)
#define BIT_INVC_MWCR_MDD (~(BIT_MASK_MWCR_MDD << BIT_SHIFT_MWCR_MDD))
#define BIT_SHIFT_MWCR_MHS 2
#define BIT_MASK_MWCR_MHS 0x1
#define BIT_MWCR_MHS(x)(((x) & BIT_MASK_MWCR_MHS) << BIT_SHIFT_MWCR_MHS)
#define BIT_INVC_MWCR_MHS (~(BIT_MASK_MWCR_MHS << BIT_SHIFT_MWCR_MHS))
// SER 0x10 // Variable Length
#define BIT_SHIFT_SER_SER 0
#define BIT_MASK_SER_SER 0xFF
#define BIT_SER_SER(x)(((x) & BIT_MASK_SER_SER) << BIT_SHIFT_SER_SER)
#define BIT_INVC_SER_SER (~(BIT_MASK_SER_SER << BIT_SHIFT_SER_SER))
// BAUDR 0x14 // 16 bits
#define BIT_SHIFT_BAUDR_SCKDV 0
#define BIT_MASK_BAUDR_SCKDV 0xFFFF
#define BIT_BAUDR_SCKDV(x)(((x) & BIT_MASK_BAUDR_SCKDV) << BIT_SHIFT_BAUDR_SCKDV)
#define BIT_INVC_BAUDR_SCKDV (~(BIT_MASK_BAUDR_SCKDV << BIT_SHIFT_BAUDR_SCKDV))
// TXFLTR 0x18 // Variable Length
#define BIT_SHIFT_TXFTLR_TFT 0
#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0
#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT)
#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT))
// RXFLTR 0x1c // Variable Length
#define BIT_SHIFT_RXFTLR_RFT 0
#define BIT_MASK_RXFTLR_RFT 0x3F // (RX_ABW-1):0
#define BIT_RXFTLR_RFT(x)(((x) & BIT_MASK_RXFTLR_RFT) << BIT_SHIFT_RXFTLR_RFT)
#define BIT_INVC_RXFTLR_RFT (~(BIT_MASK_RXFTLR_RFT << BIT_SHIFT_RXFTLR_RFT))
// TXFLR 0x20 // see [READ ONLY]
#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0
// RXFLR 0x24 // see [READ ONLY]
#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0
// SR 0x28 // 7 bits [READ ONLY]
#define BIT_SR_BUSY BIT0
#define BIT_SR_TFNF BIT1
#define BIT_SR_TFE BIT2
#define BIT_SR_RFNE BIT3
#define BIT_SR_RFF BIT4
#define BIT_SR_TXE BIT5
#define BIT_SR_DCOL BIT6
// IMR 0x2c // see
#define BIT_SHIFT_IMR_TXEIM 0
#define BIT_MASK_IMR_TXEIM 0x1
// #define BIT_IMR_TXEIM(x)(((x) & BIT_MASK_IMR_TXEIM) << BIT_SHIFT_IMR_TXEIM)
#define BIT_INVC_IMR_TXEIM (~(BIT_MASK_IMR_TXEIM << BIT_SHIFT_IMR_TXEIM))
#define BIT_SHIFT_IMR_TXOIM 1
#define BIT_MASK_IMR_TXOIM 0x1
// #define BIT_IMR_TXOIM(x)(((x) & BIT_MASK_IMR_TXOIM) << BIT_SHIFT_IMR_TXOIM)
#define BIT_INVC_IMR_TXOIM (~(BIT_MASK_IMR_TXOIM << BIT_SHIFT_IMR_TXOIM))
#define BIT_SHIFT_IMR_RXUIM 2
#define BIT_MASK_IMR_RXUIM 0x1
// #define BIT_IMR_RXUIM(x)(((x) & BIT_MASK_IMR_RXUIM) << BIT_SHIFT_IMR_RXUIM)
#define BIT_INVC_IMR_RXUIM (~(BIT_MASK_IMR_RXUIM << BIT_SHIFT_IMR_RXUIM))
#define BIT_SHIFT_IMR_RXOIM 3
#define BIT_MASK_IMR_RXOIM 0x1
// #define BIT_IMR_RXOIM(x)(((x) & BIT_MASK_IMR_RXOIM) << BIT_SHIFT_IMR_RXOIM)
#define BIT_INVC_IMR_RXOIM (~(BIT_MASK_IMR_RXOIM << BIT_SHIFT_IMR_RXOIM))
#define BIT_SHIFT_IMR_RXFIM 4
#define BIT_MASK_IMR_RXFIM 0x1
// #define BIT_IMR_RXFIM(x)(((x) & BIT_MASK_IMR_RXFIM) << BIT_SHIFT_IMR_RXFIM)
#define BIT_INVC_IMR_RXFIM (~(BIT_MASK_IMR_RXFIM << BIT_SHIFT_IMR_RXFIM))
#define BIT_SHIFT_IMR_MSTIM 5
#define BIT_MASK_IMR_MSTIM 0x1
// #define BIT_IMR_MSTIM(x)(((x) & BIT_MASK_IMR_MSTIM) << BIT_SHIFT_IMR_MSTIM)
#define BIT_INVC_IMR_MSTIM (~(BIT_MASK_IMR_MSTIM << BIT_SHIFT_IMR_MSTIM))
#define BIT_IMR_TXEIM BIT0
#define BIT_IMR_TXOIM BIT1
#define BIT_IMR_RXUIM BIT2
#define BIT_IMR_RXOIM BIT3
#define BIT_IMR_RXFIM BIT4
#define BIT_IMR_MSTIM BIT5
// ISR 0x30 // 6 bits [READ ONLY]
#define BIT_ISR_TXEIS BIT0
#define BIT_ISR_TXOIS BIT1
#define BIT_ISR_RXUIS BIT2
#define BIT_ISR_RXOIS BIT3
#define BIT_ISR_RXFIS BIT4
#define BIT_ISR_MSTIS BIT5
// RISR 0x34 // 6 bits [READ ONLY]
#define BIT_RISR_TXEIR BIT0
#define BIT_RISR_TXOIR BIT1
#define BIT_RISR_RXUIR BIT2
#define BIT_RISR_RXOIR BIT3
#define BIT_RISR_RXFIR BIT4
#define BIT_RISR_MSTIR BIT5
// TXOICR 0x38 // 1 bits [READ ONLY]
// RXOICR 0x3c // 1 bits [READ ONLY]
// RXUICR 0x40 // 1 bits [READ ONLY]
// MSTICR 0x44 // 1 bits [READ ONLY]
// ICR 0x48 // 1 bits [READ ONLY]
// DMACR 0x4c // 2 bits
#define BIT_SHIFT_DMACR_RDMAE 0
#define BIT_MASK_DMACR_RDMAE 0x1
#define BIT_DMACR_RDMAE(x)(((x) & BIT_MASK_DMACR_RDMAE) << BIT_SHIFT_DMACR_RDMAE)
#define BIT_INVC_DMACR_RDMAE (~(BIT_MASK_DMACR_RDMAE << BIT_SHIFT_DMACR_RDMAE))
#define BIT_SHIFT_DMACR_TDMAE 1
#define BIT_MASK_DMACR_TDMAE 0x1
#define BIT_DMACR_TDMAE(x)(((x) & BIT_MASK_DMACR_TDMAE) << BIT_SHIFT_DMACR_TDMAE)
#define BIT_INVC_DMACR_TDMAE (~(BIT_MASK_DMACR_TDMAE << BIT_SHIFT_DMACR_TDMAE))
// DMATDLR 0x50
#define BIT_SHIFT_DMATDLR_DMATDL 0
#define BIT_MASK_DMATDLR_DMATDL 0x3F // (TX_ABW-1):0
#define BIT_DMATDLR_DMATDL(x)(((x) & BIT_MASK_DMATDLR_DMATDL) << BIT_SHIFT_DMATDLR_DMATDL)
#define BIT_INVC_DMATDLR_DMATDL (~(BIT_MASK_DMATDLR_DMATDL << BIT_SHIFT_DMATDLR_DMATDL))
// DMARDLR 0x54
#define BIT_SHIFT_DMARDLR_DMARDL 0
#define BIT_MASK_DMARDLR_DMARDL 0x3F // (RX_ABW-1):0
#define BIT_DMARDLR_DMARDL(x)(((x) & BIT_MASK_DMARDLR_DMARDL) << BIT_SHIFT_DMARDLR_DMARDL)
#define BIT_INVC_DMARDLR_DMARDL (~(BIT_MASK_DMARDLR_DMARDL << BIT_SHIFT_DMARDLR_DMARDL))
// IDR 0x58 // 32 bits [READ ONLY]
// COMP_VERSION 0x5c // 32 bits [READ ONLY]
// DR 0x60 // 16 bits 0x60-0xEC
#define BIT_SHIFT_DR_DR 0
#define BIT_MASK_DR_DR 0xFFFF
#define BIT_DR_DR(x)(((x) & BIT_MASK_DR_DR) << BIT_SHIFT_DR_DR)
#define BIT_INVC_DR_DR (~(BIT_MASK_DR_DR << BIT_SHIFT_DR_DR))
// RX_SAMPLE_DLY 0xF0 // 8 bits
#define BIT_SHIFT_RX_SAMPLE_DLY_RSD 0
#define BIT_MASK_RX_SAMPLE_DLY_RSD 0xFFFF
#define BIT_RX_SAMPLE_DLY_RSD(x)(((x) & BIT_MASK_RX_SAMPLE_DLY_RSD) << BIT_SHIFT_RX_SAMPLE_DLY_RSD)
#define BIT_INVC_RX_SAMPLE_DLY_RSD (~(BIT_MASK_RX_SAMPLE_DLY_RSD << BIT_SHIFT_RX_SAMPLE_DLY_RSD))
// RSVD_0 0xF4 // 32 bits
// RSVD_1 0xF8 // 32 bits
// RSVD_2 0xFC // 32 bits
// SSI0 Pinmux
#define BIT_SHIFT_SSI0_PIN_EN 0
#define BIT_MASK_SSI0_PIN_EN 0x1
#define BIT_SSI0_PIN_EN(x)(((x) & BIT_MASK_SSI0_PIN_EN) << BIT_SHIFT_SSI0_PIN_EN)
#define BIT_INVC_SSI0_PIN_EN (~(BIT_MASK_SSI0_PIN_EN << BIT_SHIFT_SSI0_PIN_EN))
#define BIT_SHIFT_SSI0_PIN_SEL 1
#define BIT_MASK_SSI0_PIN_SEL 0x7
#define BIT_SSI0_PIN_SEL(x)(((x) & BIT_MASK_SSI0_PIN_SEL) << BIT_SHIFT_SSI0_PIN_SEL)
#define BIT_INVC_SSI0_PIN_SEL (~(BIT_MASK_SSI0_PIN_SEL << BIT_SHIFT_SSI0_PIN_SEL))
// SSI1 Pinmux
#define BIT_SHIFT_SSI1_PIN_EN 4
#define BIT_MASK_SSI1_PIN_EN 0x1
#define BIT_SSI1_PIN_EN(x)(((x) & BIT_MASK_SSI1_PIN_EN) << BIT_SHIFT_SSI1_PIN_EN)
#define BIT_INVC_SSI1_PIN_EN (~(BIT_MASK_SSI1_PIN_EN << BIT_SHIFT_SSI1_PIN_EN))
#define BIT_SHIFT_SSI1_PIN_SEL 5
#define BIT_MASK_SSI1_PIN_SEL 0x7
#define BIT_SSI1_PIN_SEL(x)(((x) & BIT_MASK_SSI1_PIN_SEL) << BIT_SHIFT_SSI1_PIN_SEL)
#define BIT_INVC_SSI1_PIN_SEL (~(BIT_MASK_SSI1_PIN_SEL << BIT_SHIFT_SSI1_PIN_SEL))
// SSI2 Pinmux
#define BIT_SHIFT_SSI2_PIN_EN 8
#define BIT_MASK_SSI2_PIN_EN 0x1
#define BIT_SSI2_PIN_EN(x)(((x) & BIT_MASK_SSI2_PIN_EN) << BIT_SHIFT_SSI2_PIN_EN)
#define BIT_INVC_SSI2_PIN_EN (~(BIT_MASK_SSI2_PIN_EN << BIT_SHIFT_SSI2_PIN_EN))
#define BIT_SHIFT_SSI2_PIN_SEL 9
#define BIT_MASK_SSI2_PIN_SEL 0x7
#define BIT_SSI2_PIN_SEL(x)(((x) & BIT_MASK_SSI2_PIN_SEL) << BIT_SHIFT_SSI2_PIN_SEL)
#define BIT_INVC_SSI2_PIN_SEL (~(BIT_MASK_SSI2_PIN_SEL << BIT_SHIFT_SSI2_PIN_SEL))
// SSI0 Multiple Chip Selection (Pinmux Select is controlled by BIT_SSI0_PIN_SEL)
#define BIT_SHIFT_SSI0_MULTI_CS_EN 28
#define BIT_MASK_SSI0_MULTI_CS_EN 0x1
#define BIT_SSI0_MULTI_CS_EN(x)(((x) & BIT_MASK_SSI0_MULTI_CS_EN) << BIT_SHIFT_SSI0_MULTI_CS_EN)
#define BIT_INVC_SSI0_MULTI_CS_EN (~(BIT_MASK_SSI0_MULTI_CS_EN << BIT_SHIFT_SSI0_MULTI_CS_EN))
#define HAL_SSI_READ32(SsiIndex, addr) \
HAL_READ32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE32(SsiIndex, addr, value) \
HAL_WRITE32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
#define HAL_SSI_READ16(SsiIndex, addr) \
HAL_READ16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE16(SsiIndex, addr, value) \
HAL_WRITE16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
#define HAL_SSI_READ8(SsiIndex, addr) \
HAL_READ8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE8(SsiIndex, addr, value) \
HAL_WRITE8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
// SSI Pinmux Select
typedef enum _SSI0_PINMUX_SELECT_ {
SSI0_MUX_TO_GPIOE = S0,
SSI0_MUX_TO_GPIOC = S1
}SSI0_PINMUX_SELECT, *PSSI0_PINMUX_SELECT;
typedef enum _SSI1_PINMUX_SELECT_ {
SSI1_MUX_TO_GPIOA = S0,
SSI1_MUX_TO_GPIOB = S1,
SSI1_MUX_TO_GPIOD = S2
}SSI1_PINMUX_SELECT, *PSSI1_PINMUX_SELECT;
typedef enum _SSI2_PINMUX_SELECT_ {
SSI2_MUX_TO_GPIOG = S0,
SSI2_MUX_TO_GPIOE = S1,
SSI2_MUX_TO_GPIOD = S2
}SSI2_PINMUX_SELECT, *PSSI2_PINMUX_SELECT;
typedef enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
SSI0_CS_MUX_TO_GPIOE = S0,
SSI0_CS_MUX_TO_GPIOC = S1
}SSI0_MULTI_CS_PINMUX_SELECT, *PSSI0_MULTI_CS_PINMUX_SELECT;
typedef enum _SSI_CTRLR0_TMOD_ {
TMOD_TR = 0,
TMOD_TO = 1,
TMOD_RO = 2,
TMOD_EEPROM_R = 3
}SSI_CTRLR0_TMOD, *PSSI_CTRLR0_TMOD;
typedef enum _SSI_CTRLR0_SCPOL_ {
SCPOL_INACTIVE_IS_LOW = 0,
SCPOL_INACTIVE_IS_HIGH = 1
}SSI_CTRLR0_SCPOL, *PSSI_CTRLR0_SCPOL;
typedef enum _SSI_CTRLR0_SCPH_ {
SCPH_TOGGLES_IN_MIDDLE = 0,
SCPH_TOGGLES_AT_START = 1
}SSI_CTRLR0_SCPH, *PSSI_CTRLR0_SCPH;
typedef enum _SSI_CTRLR0_DFS_ {
DFS_4_BITS = 3,
DFS_5_BITS = 4,
DFS_6_BITS = 5,
DFS_7_BITS = 6,
DFS_8_BITS = 7,
DFS_9_BITS = 8,
DFS_10_BITS = 9,
DFS_11_BITS = 10,
DFS_12_BITS = 11,
DFS_13_BITS = 12,
DFS_14_BITS = 13,
DFS_15_BITS = 14,
DFS_16_BITS = 15,
}SSI_CTRLR0_DFS, *PSSI_CTRLR0_DFS;
typedef enum _SSI_CTRLR0_CFS_ {
CFS_1_BIT = 0,
CFS_2_BITS = 1,
CFS_3_BITS = 2,
CFS_4_BITS = 3,
CFS_5_BITS = 4,
CFS_6_BITS = 5,
CFS_7_BITS = 6,
CFS_8_BITS = 7,
CFS_9_BITS = 8,
CFS_10_BITS = 9,
CFS_11_BITS = 10,
CFS_12_BITS = 11,
CFS_13_BITS = 12,
CFS_14_BITS = 13,
CFS_15_BITS = 14,
CFS_16_BITS = 15
}SSI_CTRLR0_CFS, *PSSI_CTRLR0_CFS;
typedef enum _SSI_CTRLR0_SLV_OE_ {
SLV_TXD_ENABLE = 0,
SLV_TXD_DISABLE = 1
}SSI_CTRLR0_SLV_OE, *PSSI_CTRLR0_SLV_OE;
typedef enum _SSI_ROLE_SELECT_ {
SSI_SLAVE = 0,
SSI_MASTER = 1
}SSI_ROLE_SELECT, *PSSI_ROLE_SELECT;
typedef enum _SSI_FRAME_FORMAT_ {
FRF_MOTOROLA_SPI = 0,
FRF_TI_SSP = 1,
FRF_NS_MICROWIRE = 2,
FRF_RSVD = 3
}SSI_FRAME_FORMAT, *PSSI_FRAME_FORMAT;
typedef enum _SSI_DMACR_ENABLE_ {
SSI_NODMA = 0,
SSI_RXDMA_ENABLE = 1,
SSI_TXDMA_ENABLE = 2,
SSI_TRDMA_ENABLE = 3
}SSI_DMACR_ENABLE, *PSSI_DMACR_ENABLE;
typedef enum _SSI_MWCR_HANDSHAKE_ {
MW_HANDSHAKE_DISABLE = 0,
MW_HANDSHAKE_ENABLE = 1
}SSI_MWCR_HANDSHAKE, *PSSI_MWCR_HANDSHAKE;
typedef enum _SSI_MWCR_DIRECTION_ {
MW_DIRECTION_SLAVE_TO_MASTER = 0,
MW_DIRECTION_MASTER_TO_SLAVE = 1
}SSI_MWCR_DIRECTION, *PSSI_MWCR_DIRECTION;
typedef enum _SSI_MWCR_TMOD_ {
MW_TMOD_NONSEQUENTIAL = 0,
MW_TMOD_SEQUENTIAL = 1
}SSI_MWCR_TMOD, *PSSI_MWCR_TMOD;
typedef enum _SSI_DATA_TRANSFER_MECHANISM_ {
SSI_DTM_BASIC,
SSI_DTM_INTERRUPT,
SSI_DTM_DMA
}SSI_DATA_TRANSFER_MECHANISM, *PSSI_DATA_TRANSFER_MECHANISM;
_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiDisableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetSclkPolarityRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetSclkPhaseRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiWriteRtl8195a(VOID *Adaptor, u32 value);
_LONG_CALL_ HAL_Status HalSsiLoadSettingRtl8195a(VOID *Adaptor, VOID *Setting);
_LONG_CALL_ HAL_Status HalSsiSetInterruptMaskRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetDeviceRoleRtl8195a(VOID *Adaptor, u32 Role);
_LONG_CALL_ HAL_Status HalSsiInterruptEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiInterruptDisableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiReadInterruptRtl8195a(VOID *Adaptor, VOID *RxData, u32 Length);
_LONG_CALL_ HAL_Status HalSsiSetRxFifoThresholdLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetTxFifoThresholdLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiWriteInterruptRtl8195a(VOID *Adaptor, VOID *TxData, u32 Length);
_LONG_CALL_ HAL_Status HalSsiSetSlaveEnableRegisterRtl8195a(VOID *Adaptor, u32 SlaveIndex);
_LONG_CALL_ u32 HalSsiBusyRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiWriteableRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiReadableRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetInterruptMaskRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetRxFifoLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetTxFifoLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetInterruptStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiReadRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetRawInterruptStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetSlaveEnableRegisterRtl8195a(VOID *Adaptor);
_LONG_CALL_ VOID _SsiReadInterrupt(VOID *Adaptor);
_LONG_CALL_ VOID _SsiWriteInterrupt(VOID *Adaptor);
_LONG_CALL_ u32 _SsiIrqHandle(VOID *Adaptor);
// ROM code patch
VOID _SsiReadInterruptRtl8195a(VOID *Adapter);
VOID _SsiWriteInterruptRtl8195a(VOID *Adapter);
HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
#ifdef CONFIG_GDMA_EN
VOID HalSsiTxGdmaLoadDefRtl8195a(VOID *Adapter);
VOID HalSsiRxGdmaLoadDefRtl8195a(VOID *Adapter);
VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
HAL_Status HalSsiDmaSendRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
HAL_Status HalSsiDmaRecvRtl8195a(VOID *Adapter, u8 *pRxData, u32 Length);
#endif // end of "#ifdef CONFIG_GDMA_EN"
#endif

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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h Normal file
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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_TIMER_H_
#define _RTL8195A_TIMER_H_
#define TIMER_TICK_US 31
#define TIMER_LOAD_COUNT_OFF 0x00
#define TIMER_CURRENT_VAL_OFF 0x04
#define TIMER_CTL_REG_OFF 0x08
#define TIMER_EOI_OFF 0x0c
#define TIMER_INT_STATUS_OFF 0x10
#define TIMER_INTERVAL 0x14
#define TIMERS_INT_STATUS_OFF 0xa0
#define TIMERS_EOI_OFF 0xa4
#define TIMERS_RAW_INT_STATUS_OFF 0xa8
#define TIMERS_COMP_VER_OFF 0xac
#define MAX_TIMER_VECTOR_TABLE_NUM 6
#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value)
_LONG_CALL_ u32
HalGetTimerIdRtl8195a(
IN u32 *TimerID
);
_LONG_CALL_ BOOL
HalTimerInitRtl8195a(
IN VOID *Data
);
_LONG_CALL_ u32
HalTimerReadCountRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerIrqClearRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDisRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerEnRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDumpRegRtl8195a(
IN u32 TimerId
);
// ROM Code patch
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
);
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
);
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
);
#ifdef CONFIG_CHIP_C_CUT
__weak _LONG_CALL_
VOID
HalTimerIrq2To7HandleV02(
IN VOID *Data
);
__weak _LONG_CALL_
HAL_Status
HalTimerIrqRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
HAL_Status
HalTimerInitRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
u32
HalTimerReadCountRtl8195aV02(
IN u32 TimerId
);
__weak _LONG_CALL_
VOID
HalTimerReLoadRtl8195aV02(
IN u32 TimerId,
IN u32 LoadUs
);
__weak _LONG_CALL_
HAL_Status
HalTimerIrqUnRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
VOID
HalTimerDeInitRtl8195aV02(
IN VOID *Data
);
#endif // end of "#ifdef CONFIG_CHIP_C_CUT"
// HAL functions wrapper
static __inline HAL_Status
HalTimerInit(
IN VOID *Data
)
{
return (HalTimerInitRtl8195a_Patch(Data));
}
static __inline VOID
HalTimerEnable(
IN u32 TimerId
)
{
HalTimerIrqEnRtl8195a(TimerId);
HalTimerEnRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerDisable(
IN u32 TimerId
)
{
HalTimerDisRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerReLoad(
IN u32 TimerId,
IN u32 LoadUs
)
{
HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs);
}
#ifndef CONFIG_CHIP_C_CUT
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195a_Patch(Data);
}
#else
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195aV02(Data);
}
#endif // end of "#ifndef CONFIG_CHIP_C_CUT"
#endif //_RTL8195A_TIMER_H_

403
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_UART_H_
#define _RTL8195A_UART_H_
#define MAX_UART_INDEX 2
#define RUART_DLL_OFF 0x00
#define RUART_DLM_OFF 0x04 //RW, DLAB = 1
#define RUART_INTERRUPT_EN_REG_OFF 0x04
#define RUART_IER_ERBI 0x01 //BIT0, Enable Received Data Available Interrupt (rx trigger)
#define RUART_IER_ETBEI (1<<1) //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty)
#define RUART_IER_ELSI (1<<2) //BIT2, Enable Receiver Line Status Interrupt (receiver line status)
#define RUART_IER_EDSSI (1<<3) //BIT3, Enable Modem Status Interrupt (modem status transition)
#define RUART_INT_ID_REG_OFF 0x08 //[R]
#define RUART_IIR_INT_PEND 0x01
#define RUART_IIR_INT_ID (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0)
#define RUART_FIFO_CTL_REG_OFF 0x08 //[W]
#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO (1<<1) //BIT1, 0x02, Write 1 clear
#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO (1<<2) //BIT2, 0x04, Write 1 clear
#define RUART_FIFO_CTL_REG_DMA_ENABLE 0x08 //BIT3
#define FIFO_CTL_DEFAULT_WITH_FIFO_DMA 0xC9
#define FIFO_CTL_DEFAULT_WITH_FIFO 0xC1
#define RUART_MODEM_CTL_REG_OFF 0x10
#define RUART_MCR_RTS BIT1
#define RUART_MCL_AUTOFLOW_ENABLE (1<<5) //BIT5, 0x20
#define RUART_LINE_CTL_REG_OFF 0x0C
#define RUART_LINE_CTL_REG_DLAB_ENABLE (1<<7) //BIT7, 0x80
#define RUART_LINE_STATUS_REG_OFF 0x14
#define RUART_LINE_STATUS_REG_DR 0x01 //BIT0, Data Ready indicator
#define RUART_LINE_STATUS_ERR_OVERRUN (1<<1) //BIT1, Over Run
#define RUART_LINE_STATUS_ERR_PARITY (1<<2) //BIT2, Parity error
#define RUART_LINE_STATUS_ERR_FRAMING (1<<3) //BIT3, Framing error
#define RUART_LINE_STATUS_ERR_BREAK (1<<4) //BIT4, Break interrupt error
#define RUART_LINE_STATUS_REG_THRE (1<<5) //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable
#define RUART_LINE_STATUS_REG_TEMT (1<<6) //BIT6, 0x40, Transmitter Empty indicator(bit)
#define RUART_LINE_STATUS_ERR_RXFIFO (1<<7) //BIT7, RX FIFO error
#define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \
RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \
RUART_LINE_STATUS_ERR_RXFIFO) //Line status error
#define RUART_MODEM_STATUS_REG_OFF 0x18 //Modem Status Register
#define RUART_SCRATCH_PAD_REG_OFF 0x1C //Scratch Pad Register
#define RUART_SP_REG_RXBREAK_INT_STATUS (1<<7) //BIT7, 0x80, Write 1 clear
#define RUART_SP_REG_DBG_SEL 0x0F<<8 //[11:8], Debug port selection
#define RUART_SP_REG_XFACTOR_ADJ 0x7FF<<16 //[26:16]
#define RUART_STS_REG_OFF 0x20
#define RUART_STS_REG_RESET_RCV (1<<3) //BIT3, 0x08, Reset Uart Receiver
#define RUART_STS_REG_XFACTOR 0xF<<4
#define RUART_REV_BUF_REG_OFF 0x24 //Receiver Buffer Register
#define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register
#define RUART_MISC_CTL_REG_OFF 0x28
#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 //7:3
#define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 //12:8
#define RUART_DEBUG_REG_OFF 0x3C
// RUART_LINE_CTL_REG_OFF (0x0C)
#define BIT_SHIFT_LCR_WLS 0 // word length select: 0: 7 bits, 1: 8bits
#define BIT_MASK_LCR_WLS_8BITS 0x1
#define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS)
#define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS))
#define BIT_SHIFT_LCR_STB 2 // Stop bit select: 0: no stop bit, 1: 1 stop bit
#define BIT_MASK_LCR_STB_EN 0x1
#define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB)
#define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB))
#define BIT_SHIFT_LCR_PARITY_EN 3
#define BIT_MASK_LCR_PARITY_EN 0x1
#define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN)
#define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN))
#define BIT_SHIFT_LCR_PARITY_TYPE 4
#define BIT_MASK_LCR_PARITY_TYPE 0x1
#define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE)
#define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE))
#define BIT_SHIFT_LCR_STICK_PARITY_EN 5
#define BIT_MASK_LCR_STICK_PARITY_EN 0x1
#define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN)
#define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN))
#define BIT_SHIFT_LCR_BREAK_CTRL 6
#define BIT_MASK_LCR_BREAK_CTRL 0x1
#define BIT_UART_LCR_BREAK_CTRL ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL)
#define RUART_BAUD_RATE_2400 2400
#define RUART_BAUD_RATE_4800 4800
#define RUART_BAUD_RATE_9600 9600
#define RUART_BAUD_RATE_19200 19200
#define RUART_BAUD_RATE_38400 38400
#define RUART_BAUD_RATE_57600 57600
#define RUART_BAUD_RATE_115200 115200
#define RUART_BAUD_RATE_921600 921600
#define RUART_BAUD_RATE_1152000 1152000
#define HAL_RUART_READ32(UartIndex, addr) \
HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE32(UartIndex, addr, value) \
HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define HAL_RUART_READ16(UartIndex, addr) \
HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE16(UartIndex, addr, value) \
HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define HAL_RUART_READ8(UartIndex, addr) \
HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE8(UartIndex, addr, value) \
HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
typedef struct _RUART_SPEED_SETTING_ {
u32 BaudRate;
u32 Ovsr;
u32 Div;
u32 Ovsr_adj;
}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING;
typedef enum _UART_RXFIFO_TRIGGER_LEVEL_ {
OneByte = 0x00,
FourBytes = 0x01,
EightBytes = 0x10,
FourteenBytes = 0x11
}UART_RXFIFO_TRIGGER_LEVEL, *PUART_RXFIFO_TRIGGER_LEVEL;
typedef enum _RUART0_PINMUX_SELECT_ {
RUART0_MUX_TO_GPIOC = S0,
RUART0_MUX_TO_GPIOE = S1,
RUART0_MUX_TO_GPIOA = S2
}RUART0_PINMUX_SELECT, *PRUART0_PINMUX_SELECT;
typedef enum _RUART1_PINMUX_SELECT_ {
RUART1_MUX_TO_GPIOD = S0,
RUART1_MUX_TO_GPIOE = S1,
RUART1_MUX_TO_GPIOB = S2
}RUART1_PINMUX_SELECT, *PRUART1_PINMUX_SELECT;
typedef enum _RUART2_PINMUX_SELECT_ {
RUART2_MUX_TO_GPIOA = S0,
RUART2_MUX_TO_GPIOC = S1,
RUART2_MUX_TO_GPIOD = S2
}RUART2_PINMUX_SELECT, *PRUART2_PINMUX_SELECT;
typedef enum _RUART_FLOW_CONTROL_ {
AUTOFLOW_DISABLE = 0,
AUTOFLOW_ENABLE = 1
}RUART_FLOW_CONTROL, *PRUART_FLOW_CONTROL;
typedef enum _RUART_WORD_LEN_SEL_ {
RUART_WLS_7BITS = 0,
RUART_WLS_8BITS = 1
}RUART_WORD_LEN_SEL, *PRUART_WORD_LEN_SEL;
typedef enum _RUART_STOP_BITS_ {
RUART_NO_STOP_BIT = 0,
RUART_1_STOP_BIT = 1
}RUART_STOP_BITS, *PRUART_STOP_BITS;
typedef enum _RUART_PARITY_CONTROL_ {
RUART_PARITY_DISABLE = 0,
RUART_PARITY_ENABLE = 1
}RUART_PARITY_CONTROL, *PRUART_PARITY_CONTROL;
typedef enum _RUART_PARITY_TYPE_ {
RUART_ODD_PARITY = 0,
RUART_EVEN_PARITY = 1
}RUART_PARITY_TYPE, *PRUART_PARITY_TYPE;
typedef enum _RUART_STICK_PARITY_CONTROL_ {
RUART_STICK_PARITY_DISABLE = 0,
RUART_STICK_PARITY_ENABLE = 1
}RUART_STICK_PARITY_CONTROL, *PRUART_STICK_PARITY_CONTROL;
typedef enum _UART_INT_ID_ {
ModemStatus = 0,
TxFifoEmpty = 1,
ReceiverDataAvailable = 2,
ReceivLineStatus = 3,
TimeoutIndication = 6
}UART_INT_ID, *PUART_INT_ID;
typedef enum _HAL_UART_State_
{
HAL_UART_STATE_NULL = 0x00, // UART hardware not been initial yet
HAL_UART_STATE_READY = 0x10, // UART is initialed, ready to use
HAL_UART_STATE_BUSY = 0x20, // UART hardware is busy on configuration
HAL_UART_STATE_BUSY_TX = 0x21, // UART is buzy on TX
HAL_UART_STATE_BUSY_RX = 0x22, // UART is busy on RX
HAL_UART_STATE_BUSY_TX_RX = 0x23, // UART is busy on TX an RX
HAL_UART_STATE_TIMEOUT = 0x30, // Transfer timeout
HAL_UART_STATE_ERROR = 0x40 // UART Error
}HAL_UART_State, *PHAL_UART_State;
typedef enum _HAL_UART_Status_
{
HAL_UART_STATUS_OK = 0x00, // Transfer OK
HAL_UART_STATUS_TIMEOUT = 0x01, // Transfer Timeout
HAL_UART_STATUS_ERR_OVERRUN = 0x02, // RX Over run
HAL_UART_STATUS_ERR_PARITY = 0x04, // Parity error
HAL_UART_STATUS_ERR_FRAM = 0x08, // Framing Error
HAL_UART_STATUS_ERR_BREAK = 0x10, // Break Interrupt
HAL_UART_STATUS_ERR_PARA = 0x20, // Parameter error
HAL_UART_STATUS_ERR_RXFIFO = 0x80, // RX FIFO error
}HAL_UART_Status, *PHAL_UART_Status;
u32
HalRuartGetDebugValueRtl8195a(
IN VOID* Data,
IN u32 DbgSel
);
#if 0
u32
FindElementIndex(
u32 Element,
u32* Array
);
#endif
VOID
RuartResetRxFifoRtl8195a(
IN u8 UartIndex
);
#if 0
VOID
RuartBusDomainEnableRtl8195a(
IN u8 UartIndex
);
#endif
HAL_Status
HalRuartResetRxFifoRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartInitRtl8195a(
IN VOID *Data
);
VOID
HalRuartDeInitRtl8195a(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartPutCRtl8195a(
IN VOID *Data,
IN u8 TxData
);
u32
HalRuartSendRtl8195a(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length,
IN u32 Timeout
);
HAL_Status
HalRuartIntSendRtl8195a(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
HAL_Status
HalRuartDmaSendRtl8195a(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
HAL_Status
HalRuartStopSendRtl8195a(
IN VOID *Data // PHAL_RUART_ADAPTER
);
HAL_Status
HalRuartGetCRtl8195a(
IN VOID *Data,
OUT u8 *pRxByte
);
u32
HalRuartRecvRtl8195a(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length,
IN u32 Timeout
);
HAL_Status
HalRuartIntRecvRtl8195a(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
HAL_Status
HalRuartDmaRecvRtl8195a(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
HAL_Status
HalRuartStopRecvRtl8195a(
IN VOID *Data // PHAL_RUART_ADAPTER
);
u8
HalRuartGetIMRRtl8195a(
IN VOID *Data
);
_LONG_CALL_ VOID
HalRuartSetIMRRtl8195a(
IN VOID *Data
);
VOID
HalRuartDmaInitRtl8195a(
IN VOID *Data
);
VOID
HalRuartRTSCtrlRtl8195a(
IN VOID *Data,
IN BOOLEAN RtsCtrl
);
VOID
HalRuartRegIrqRtl8195a(
IN VOID *Data
);
VOID
HalRuartIntEnableRtl8195a(
IN VOID *Data
);
VOID
HalRuartIntDisableRtl8195a(
IN VOID *Data
);
VOID
HalRuartAdapterLoadDefRtl8195a(
IN VOID *pAdp,
IN u8 UartIdx
);
VOID
HalRuartTxGdmaLoadDefRtl8195a(
IN VOID *pAdp,
IN VOID *pCfg
);
VOID
HalRuartRxGdmaLoadDefRtl8195a(
IN VOID *pAdp,
IN VOID *pCfg
);
_LONG_CALL_ HAL_Status HalRuartIntSendRtl8195aV02(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
_LONG_CALL_ HAL_Status
HalRuartIntRecvRtl8195aV02(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
_LONG_CALL_ s32
FindElementIndex_v02(
u32 Element, ///< RUART Baudrate
u32* Array, ///< Pre-defined Baudrate Array
u32 ElementNo
);
_LONG_CALL_ HAL_Status HalRuartInitRtl8195a_v02(IN VOID *Data);
#endif

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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_wdt.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2014 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_WDT_H_
#define _RTL8195A_WDT_H_
#define WDGTIMERELY (10*1024) //us
typedef struct _WDG_REG_ {
u16 WdgScalar;
u8 WdgEnByte;
u8 WdgClear:1;
u8 WdgCunLimit:4;
u8 Rsvd:1;
u8 WdgMode:1;
u8 WdgToISR:1;
}WDG_REG, *PWDG_REG;
typedef struct _WDG_ADAPTER_ {
WDG_REG Ctrl;
IRQ_HANDLE IrqHandle;
TIMER_ADAPTER WdgGTimer;
VOID (*UserCallback)(u32 callback_id); // User callback function
u32 callback_id;
}WDG_ADAPTER, *PWDG_ADAPTER;
typedef enum _WDG_CNTLMT_ {
CNT1H = 0,
CNT3H = 1,
CNT7H = 2,
CNTFH = 3,
CNT1FH = 4,
CNT3FH = 5,
CNT7FH = 6,
CNTFFH = 7,
CNT1FFH = 8,
CNT3FFH = 9,
CNT7FFH = 10,
CNTFFFH = 11
}WDG_CNTLMT, *PWDG_CNTLMT;
typedef enum _WDG_MODE_ {
INT_MODE = 0,
RESET_MODE = 1
}WDG_MODE, *PWDG_MODE;
extern VOID
WDGInitial(
IN u32 Period
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGStop(
VOID
);
extern VOID
WDGRefresh(
VOID
);
extern VOID
WDGIrqCallBackReg(
IN VOID *CallBack,
IN u32 Id
);
#endif //_RTL8195A_WDT_H_

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component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_adc.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "platform_autoconf.h"
#include "diag.h"
#include "rtl8195a_adc.h"
#include "hal_adc.h"
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCInit8195a(
IN VOID *Data
)
{
PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
u32 AdcTempDat;
u8 AdcTempIdx = pHalAdcInitData->ADCIdx;
/* Enable ADC power cut */
/*
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat |= BIT_ADC_PWR_AUTO;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
*/
/* ADC Control register set-up*/
AdcTempDat = 0;
AdcTempDat |= (BIT_CTRL_ADC_COMP_ONLY(pHalAdcInitData->ADCCompOnly) |
BIT_CTRL_ADC_ONESHOT(pHalAdcInitData->ADCOneShotEn) |
BIT_CTRL_ADC_OVERWRITE(pHalAdcInitData->ADCOverWREn) |
BIT_CTRL_ADC_ENDIAN(pHalAdcInitData->ADCEndian) |
BIT_CTRL_ADC_BURST_SIZE(pHalAdcInitData->ADCBurstSz) |
BIT_CTRL_ADC_THRESHOLD(pHalAdcInitData->ADCOneShotTD) |
BIT_CTRL_ADC_DBG_SEL(pHalAdcInitData->ADCDbgSel));
HAL_ADC_WRITE32(REG_ADC_CONTROL,AdcTempDat);
DBG_8195A_ADC_LVL(HAL_ADC_LVL,"REG_ADC_CONTROL:%x\n", HAL_ADC_READ32(REG_ADC_CONTROL));
/* ADC compare value and compare method setting*/
switch (AdcTempIdx) {
case ADC0_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
AdcTempDat &= ~(BIT_ADC_COMP_TH_0(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_0(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
break;
case ADC1_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
AdcTempDat &= ~(BIT_ADC_COMP_TH_1(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_1(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
break;
case ADC2_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
AdcTempDat &= ~(BIT_ADC_COMP_TH_2(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_2(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
break;
case ADC3_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
AdcTempDat &= ~(BIT_ADC_COMP_TH_3(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_3(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
break;
default:
return _EXIT_FAILURE;
}
/* ADC compare mode setting */
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_SET);
AdcTempDat &= (~(0x01 << pHalAdcInitData->ADCIdx));
AdcTempDat |= (BIT_CTRL_ADC_COMP_0_EN(pHalAdcInitData->ADCCompCtrl) <<
pHalAdcInitData->ADCIdx);
HAL_ADC_WRITE32(REG_ADC_COMP_SET, AdcTempDat);
/* ADC audio mode set-up */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
AdcTempDat &= ~(BIT_ADC_AUDIO_EN);
AdcTempDat |= BIT_CTRL_ADC_AUDIO_EN(pHalAdcInitData->ADCAudioEn);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
/* ADC enable manually setting */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
AdcTempDat &= ~(BIT_ADC_EN_MANUAL);
AdcTempDat |= BIT_CTRL_ADC_EN_MANUAL(pHalAdcInitData->ADCEnManul);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
/* ADC analog parameter 0 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
AdcTempDat |= (BIT0);
if (pHalAdcInitData->ADCInInput == 1){
AdcTempDat &= (~BIT14);
}
else {
AdcTempDat |= (BIT14);
}
AdcTempDat &= (~(BIT3|BIT2));
/* Adjust VCM for C-Cut*/
#ifdef CONFIG_CHIP_C_CUT
AdcTempDat |= (BIT22);
#endif
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
/* ADC analog parameter 1 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
AdcTempDat &= (~BIT1);
AdcTempDat |= (BIT2|BIT0);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
DBG_ADC_INFO("AD1:%x\n", AdcTempDat);
/* ADC analog parameter 2 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
AdcTempDat = 0x67884400;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD2, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
/* ADC analog parameter 3 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
AdcTempDat = 0x77780039;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD3, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
/* ADC analog parameter 4 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
AdcTempDat = 0x0004d501;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD4, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
/* ADC analog parameter 5 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
AdcTempDat = 0x1E010800;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD5, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCDeInit8195a(
IN VOID *Data
)
{
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat &= ~(BIT_ADC_PWR_AUTO);
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCEnableRtl8195a(
IN VOID *Data
){
PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat &= (~BIT_ADC_PWR_AUTO);
AdcTempDat |= BIT_CTRL_ADC_PWR_AUTO(pHalAdcInitData->ADCEn);
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCIntrCtrl8195a(
IN VOID *Data
){
PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
HAL_ADC_WRITE32(REG_ADC_INTR_EN, pHalAdcInitData->ADCIntrMSK);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CReceiveRtl8195a
//
// Description:
// Directly read one data byte a I2C data fifo.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The first data fifo content.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
u32
HalADCReceiveRtl8195a(
IN VOID *Data
){
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(REG_ADC_FIFO_READ);
return (AdcTempDat);
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CReadRegRtl8195a
//
// Description:
// Directly read a I2C register according to the register offset.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
// [in] I2CReg -
// The I2C register offset.
//
// Return:
// The register content in u32 format.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
u32
HalADCReadRegRtl8195a(
IN VOID *Data,
IN u8 I2CReg
){
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(I2CReg);
return (AdcTempDat);
}

269
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_dac.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_dac.h"
#include "hal_dac.h"
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalDACInit8195a
//
// Description:
// To initialize DAC module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The DAC parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-15.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACInit8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
u32 DacTempDat;
u8 DacTempIdx = pHalDacInitData->DACIdx;
/* Enable DAC power cut */
DacTempDat = HAL_DAC_READ32(0, REG_DAC_PWR_CTRL);
DacTempDat |= BIT_DAC_PWR_AUTO;
HAL_DAC_WRITE32(0, REG_DAC_PWR_CTRL, DacTempDat);
/* Disable DAC module first */
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, 0);
/* Setup DAC module */
DacTempDat = 0;
DacTempDat |= (BIT_CTRL_DAC_SPEED(pHalDacInitData->DACDataRate) |
BIT_CTRL_DAC_ENDIAN(pHalDacInitData->DACEndian) |
BIT_CTRL_DAC_FILTER_SETTLE(pHalDacInitData->DACFilterSet) |
BIT_CTRL_DAC_BURST_SIZE(pHalDacInitData->DACBurstSz) |
BIT_CTRL_DAC_DBG_SEL(pHalDacInitData->DACDbgSel) |
BIT_CTRL_DAC_DSC_DBG_SEL(pHalDacInitData->DACDscDbgSel) |
BIT_CTRL_DAC_BYPASS_DSC(pHalDacInitData->DACBPDsc) |
BIT_CTRL_DAC_DELTA_SIGMA(pHalDacInitData->DACDeltaSig));
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACDeInit8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
u32 DacTempDat;
DacTempDat = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL);
DacTempDat &= (~BIT_DAC_FIFO_EN);
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL ,DacTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACEnableRtl8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
u32 DacTempDat;
u8 DacTempIdx = pHalDacInitData->DACIdx;
DacTempDat = HAL_DAC_READ32(DacTempIdx, REG_DAC_CTRL);
DacTempDat &= (~BIT_DAC_FIFO_EN);
DacTempDat |= BIT_CTRL_DAC_FIFO_EN(pHalDacInitData->DACEn);
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACIntrCtrl8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL, pHalDacInitData->DACIntrMSK);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CReceiveRtl8195a
//
// Description:
// Directly read one data byte a I2C data fifo.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The first data fifo content.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
u8
HalDACSendRtl8195a(
IN VOID *Data
){
return (0);
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalDACReadRegRtl8195a
//
// Description:
//
//
// Arguments:
// [in] VOID *Data -
// The DAC parameter data struct.
// [in] I2CReg -
// The DAC register offset.
//
// Return:
// The DAC register content in u32 format.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-15.
//
//---------------------------------------------------------------------------------------------------
u32
HalDACReadRegRtl8195a(
IN VOID *Data,
IN u8 I2CReg
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
//DBG_8195A_DAC("dac read reg idx:%x\n",pHalDacInitData->DACIdx);
//DBG_8195A_DAC("dac read reg offset:%x\n",I2CReg);
return (u32)HAL_DAC_READ32(pHalDacInitData->DACIdx, I2CReg);
}

243
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_gdma.h"
#include "hal_gdma.h"
#ifndef CONFIG_CHIP_D_CUT
BOOL
HalGdmaChBlockSetingRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pGdmaChLli;
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 ChEn = pHalGdmaAdapter->ChEn;
u8 GdmaChIsrBitmap = (ChEn & 0xFF);
u8 PendingIsrIndex;
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
//4 1) Check chanel is avaliable
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
//4 Disable Channel
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
HalGdmaChDisRtl8195a(Data);
}
//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
u32 PendRaw, PendStstus;
PendRaw = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
PendStstus = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
//4 Clear Pending Isr
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
(PendStstus & (GdmaChIsrBitmap))
);
}
}
//4 Fill in SARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChSar)
);
//4 Fill in DARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChDar)
);
//4 3) Process CTLx
CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
//4 Clear Config low register bits
CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
BIT_INVC_CTLX_LO_DST_TR_WIDTH &
BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
BIT_INVC_CTLX_LO_DINC &
BIT_INVC_CTLX_LO_SINC &
BIT_INVC_CTLX_LO_DEST_MSIZE &
BIT_INVC_CTLX_LO_SRC_MSIZE &
BIT_INVC_CTLX_LO_TT_FC &
BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
//4 Clear Config upper register bits
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
BIT_INVC_CTLX_UP_DONE);
CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
CtlxLow;
CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
CtlxUp;
//4 Fill in CTLx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
CtlxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
CtlxUp
);
//4 4) Program CFGx
CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
BIT_INVC_CFGX_LO_CH_SUSP &
BIT_INVC_CFGX_LO_HS_SEL_DST &
BIT_INVC_CFGX_LO_HS_SEL_SRC &
BIT_INVC_CFGX_LO_LOCK_CH_L &
BIT_INVC_CFGX_LO_LOCK_B_L &
BIT_INVC_CFGX_LO_LOCK_CH &
BIT_INVC_CFGX_LO_LOCK_B &
BIT_INVC_CFGX_LO_RELOAD_SRC &
BIT_INVC_CFGX_LO_RELOAD_DST);
CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
BIT_INVC_CFGX_UP_DS_UPD_EN &
BIT_INVC_CFGX_UP_SS_UPD_EN &
BIT_INVC_CFGX_UP_SRC_PER &
BIT_INVC_CFGX_UP_DEST_PER);
CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
CfgxLow;
CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
CfgxUp;
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
CfgxUp
);
//4 Check 4 Bytes Alignment
if ((u32)(pLliEle) & 0x3) {
DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n",
pHalGdmaAdapter->pLli);
return _FALSE;
}
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
pLliEle
);
//4 Update the first llp0
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
while (MultiBlockCount > 1) {
MultiBlockCount--;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pLliEle = pGdmaChLli->pLliEle;
if (NULL == pLliEle) {
DBG_8195A("pLliEle Null Point!!!!!\n");
return _FALSE;
}
//4 Clear the last element llp enable bit
if (1 == MultiBlockCount) {
if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 0){
CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
}
}
//4 Update block size for transfer
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
//4 Update tje Lli and Block size list point to next llp
pGdmaChLli = pGdmaChLli->pNextLli;
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
//4 Updatethe Llpx context
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = pGdmaChLli->pLliEle;
}
return _TRUE;
}
#endif

53
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gpio.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "hal_gpio.h"
#include "rtl8195a_gpio.h"
#include "gpio_irq_api.h"
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
/**
* @brief Clear the pending interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
HAL_Status
HAL_GPIO_ClearISR_8195a(
HAL_GPIO_PIN *GPIO_Pin
)
{
u8 port_num;
u8 pin_num;
HAL_GPIO_PIN_MODE pin_mode;
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
pin_mode = GPIO_Pin->pin_mode;
if ((pin_mode & HAL_GPIO_PIN_INT_MODE)==0 || (port_num != GPIO_PORT_A)) {
DBG_GPIO_ERR("HAL_GPIO_ClearISR_8195a: This pin(%x:%x) is'nt an interrupt pin\n", GPIO_Pin->pin_name, GPIO_Pin->pin_mode);
return HAL_ERR_PARA;
}
if (GPIO_Lock() != HAL_OK) {
return HAL_BUSY;
}
// Clear pending interrupt before unmask it
HAL_WRITE32(GPIO_REG_BASE, GPIO_PORTA_EOI, (1<<pin_num));
GPIO_UnLock();
return HAL_OK;
}

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component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_i2s.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_i2s.h"
#include "hal_i2s.h"
extern void *
_memset( void *s, int c, SIZE_T n );
RTK_STATUS
HalI2SInitRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u8 I2SEn;
u8 I2SMaster;
u8 I2SWordLen;
u8 I2SChNum;
u8 I2SPageNum;
u16 I2SPageSize;
u16 I2SRate;
u32 I2STxIntrMSK;
u32 I2SRxIntrMSK;
u8 I2STRxAct;
u8 *I2STxData;
u8 *I2SRxData;
u32 Tmp;
I2SIdx = pHalI2SInitData->I2SIdx;
I2SEn = pHalI2SInitData->I2SEn;
I2SMaster = pHalI2SInitData->I2SMaster;
I2SWordLen = pHalI2SInitData->I2SWordLen;
I2SChNum = pHalI2SInitData->I2SChNum;
I2SPageNum = pHalI2SInitData->I2SPageNum;
I2SPageSize = pHalI2SInitData->I2SPageSize;
I2SRate = pHalI2SInitData->I2SRate;
I2STRxAct = pHalI2SInitData->I2STRxAct;
I2STxData = pHalI2SInitData->I2STxData;
I2SRxData = pHalI2SInitData->I2SRxData;
/* Disable the I2S first, and reset to default */
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
BIT_CTRL_CTLX_I2S_SW_RSTN(1));
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
BIT_CTRL_CTLX_I2S_SW_RSTN(0));
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
BIT_CTRL_CTLX_I2S_SW_RSTN(1));
Tmp = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
Tmp |= BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(1);
if (I2SRate&0x10)
{
Tmp |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
}
Tmp |= (BIT_CTRL_CTLX_I2S_WL(I2SWordLen) | BIT_CTRL_CTLX_I2S_CH_NUM(I2SChNum) |
BIT_CTRL_CTLX_I2S_SLAVE_MODE(I2SMaster) | BIT_CTRL_CTLX_I2S_TRX_ACT(I2STRxAct));
/* set 44.1khz clock source, word length, channel number, master or slave, trx act */
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, Tmp);
Tmp = BIT_CTRL_SETTING_I2S_PAGE_SZ(I2SPageSize) | BIT_CTRL_SETTING_I2S_PAGE_NUM(I2SPageNum) |
BIT_CTRL_SETTING_I2S_SAMPLE_RATE(I2SRate);
/* set page size, page number, sample rate */
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, Tmp);
/* need tx rx buffer? need rx page own bit */
if (I2STxData != NULL) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (u32)I2STxData);
}
if (I2SRxData != NULL) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (u32)I2SRxData);
}
pHalI2SInitData->I2STxIdx = 0;
pHalI2SInitData->I2SRxIdx = 0;
pHalI2SInitData->I2SHWTxIdx = 0;
pHalI2SInitData->I2SHWRxIdx = 0;
/* I2S Clear all interrupts first */
HalI2SClrAllIntrRtl8195a(pHalI2SInitData);
/* I2S Disable all interrupts first */
I2STxIntrMSK = pHalI2SInitData->I2STxIntrMSK;
I2SRxIntrMSK = pHalI2SInitData->I2SRxIntrMSK;
pHalI2SInitData->I2STxIntrMSK = 0;
pHalI2SInitData->I2SRxIntrMSK = 0;
HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
pHalI2SInitData->I2STxIntrMSK = I2STxIntrMSK;
pHalI2SInitData->I2SRxIntrMSK = I2SRxIntrMSK;
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetRateRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_CLK_SRC << BIT_SHIFT_CTLX_I2S_CLK_SRC);
if (pHalI2SInitData->I2SRate&0x10)
{
reg_value |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
}
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_SAMPLE_RATE << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE);
reg_value |= BIT_CTRL_SETTING_I2S_SAMPLE_RATE(pHalI2SInitData->I2SRate);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetWordLenRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_WL << BIT_SHIFT_CTLX_I2S_WL);
reg_value |= BIT_CTRL_CTLX_I2S_WL(pHalI2SInitData->I2SWordLen);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetChNumRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_CH_NUM << BIT_SHIFT_CTLX_I2S_CH_NUM);
reg_value |= BIT_CTRL_CTLX_I2S_CH_NUM(pHalI2SInitData->I2SChNum);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetPageNumRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetPageSizeRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetDirectionRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_TRX_ACT << BIT_SHIFT_CTLX_I2S_TRX_ACT);
reg_value |= BIT_CTRL_CTLX_I2S_TRX_ACT(pHalI2SInitData->I2STRxAct);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetDMABufRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
u32 page_num;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
page_num = pHalI2SInitData->I2SPageNum + 1;
if (pHalI2SInitData->I2STxData) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2STxData);
pHalI2SInitData->I2STxIntrMSK = (1<<page_num) - 1;
} else {
pHalI2SInitData->I2STxIntrMSK = 0;
}
if (pHalI2SInitData->I2SRxData) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2SRxData);
pHalI2SInitData->I2SRxIntrMSK = (1<<page_num) - 1;
} else {
pHalI2SInitData->I2SRxIntrMSK = 0;
}
// According to the page number to modify the ISR mask
HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
return _EXIT_SUCCESS;
}
u8
HalI2SGetTxPageRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
u32 reg;
I2SIdx = pHalI2SInitData->I2SIdx;
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(I2STxIdx<<2));
if ((reg & (1<<31)) == 0) {
return I2STxIdx;
} else {
return 0xFF;
}
}
u8
HalI2SGetRxPageRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
u32 reg;
I2SIdx = pHalI2SInitData->I2SIdx;
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
if ((reg & (1<<31)) == 0) {
return I2SRxIdx;
} else {
return 0xFF;
}
}
RTK_STATUS
HalI2SPageSendRtl8195a(
IN VOID *Data,
IN u8 PageIdx
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
u8 I2SPageNum = pHalI2SInitData->I2SPageNum;
u8 I2SIdx;
if (I2STxIdx != PageIdx) {
DBG_I2S_ERR("HalI2SPageSendRtl8195a: UnExpected Page Index. TxPage=%d, Expected:%d\r\n",
PageIdx, I2STxIdx);
}
I2SIdx = pHalI2SInitData->I2SIdx;
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+4*PageIdx, 1<<31);
I2STxIdx = PageIdx+1;
if (I2STxIdx > I2SPageNum) {
I2STxIdx = 0;
}
pHalI2SInitData->I2STxIdx = I2STxIdx;
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SPageRecvRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
u8 I2SPageNum = pHalI2SInitData->I2SPageNum;
u32 reg;
u8 I2SIdx;
I2SIdx = pHalI2SInitData->I2SIdx;
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
if ((reg & (1<<31)) != 0) {
DBG_I2S_ERR("HalI2SPageRecvRtl8195a: No Idle Rx Page\r\n");
return _EXIT_FAILURE;
}
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx<<2), 1<<31);
I2SRxIdx += 1;
if (I2SRxIdx > I2SPageNum) {
I2SRxIdx = 0;
}
pHalI2SInitData->I2SRxIdx = I2SRxIdx;
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SClearAllOwnBitRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 i;
I2SIdx = pHalI2SInitData->I2SIdx;
for (i=0;i<4;i++) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(i<<2), 0);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(i<<2), 0);
}
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SDMACtrlRtl8195a(
IN VOID *Data
)
{
return _EXIT_SUCCESS;
}

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component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_mii.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_mii.h"
#include "hal_mii.h"
VOID MiiIrqHandle (IN VOID *Data);
VOID MiiIrqHandle (IN VOID *Data) {
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
u32 RegValue = HalMiiGmacGetInterruptStatusRtl8195a();
#ifdef CONFIG_MII_VERIFY
extern u8 isRxOK;
extern u8 isTxOK;
extern u8 RxIntCnt;
// DBG_8195A("ISR = 0x%08X\n", RegValue);
if(RegValue & GMAC_ISR_ROK) {
HalMiiGmacClearInterruptStatusRtl8195a(0x00410001);
isRxOK = 1;
RxIntCnt++;
}
if(RegValue & GMAC_ISR_TOK_TI) {
HalMiiGmacClearInterruptStatusRtl8195a(0x00410040);
isTxOK = 1;
}
#else
#endif
}
VOID
ConfigDebugPort_E4(u32 DebugSelect) {
u32 RegValue;
BOOL DebugMsg = _FALSE;
if (DebugMsg) {
LOGI(ANSI_COLOR_YELLOW"Debug Port Select (0xE4)\n"ANSI_COLOR_RESET);
LOGD2("[P] PERI_ON_010: %X\n", HAL_READ32(PERI_ON_BASE, REG_SOC_FUNC_EN));
LOGD2("[P] PERI_ON_014: %X\n", HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN));
}
RegValue = HAL_MII_READ32(REG_RTL_MII_CCR);
if (DebugMsg) {
LOGD2("[B] 0x00E4: %X\n", RegValue);
}
RegValue |= DebugSelect << 2;
if (DebugMsg) {
LOGD2("[B] RegValue: %X\n", RegValue);
}
HAL_MII_WRITE32(REG_RTL_MII_CCR, RegValue);
if (DebugMsg) {
LOGD2("[A] 0x00E4: %X\n", HAL_MII_READ32(REG_RTL_MII_CCR));
}
}
/**
* MII Initialize.
*
* MII Initialize.
*
* Initialization Steps:
* I. Rtl8195A Board Configurations:
* 1. MII Function Enable & AHB mux
*
* @return runtime status value.
*/
BOOL
HalMiiGmacInitRtl8195a(
IN VOID *Data
)
{
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
u32 RegValue;
/* 1. enable MII Pinmux & disable SDIO Host/Device mode Pinmux */
RegValue = HAL_READ32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL);
RegValue |= BIT24;
RegValue &= ~(BIT0 | BIT1); // Important!
HAL_WRITE32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL, RegValue);
/* 2. enable MII IP block (214, 12) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN);
RegValue |= BIT12;
HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, RegValue);
/* 3. Lexra2AHB Function Enable (304, 11) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL);
RegValue |= BIT11;
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue);
/* 4. enable MII bus clock (240, 24|25) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0);
RegValue |= (BIT24 | BIT25);
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0, RegValue);
/* 5. */
RegValue = HAL_READ32(SYSTEM_CTRL_BASE, 0x74) & 0xFFFFC7FF;
HAL_WRITE32(SYSTEM_CTRL_BASE, 0x74, (RegValue | 0x00003000));
/* 6. AHB mux: select MII (214, 13) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN);
RegValue |= BIT13;
HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, RegValue);
/* 7. Vendor Register Clock Enable (230, 6|7) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_CTRL);
RegValue |= (BIT6 | BIT7);
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_CLK_CTRL, RegValue);
/* 8. Enable GMAC Lexra Timeout (090, 16|17|18) */
RegValue = HAL_READ32(VENDOR_REG_BASE, 0x0090);
RegValue |= (BIT16 | BIT17 | BIT18);
HAL_WRITE32(VENDOR_REG_BASE, 0x0090, RegValue);
/* 9. Endian Swap Control (304, 12|13) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL);
RegValue |= (BIT12 | BIT13);
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue);
return _TRUE;
}
BOOL
HalMiiInitRtl8195a(
IN VOID *Data
)
{
DBG_ENTRANCE;
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
u32 RegValue;
return _TRUE;
}
BOOL
HalMiiGmacResetRtl8195a(
IN VOID *Data
)
{
HAL_MII_WRITE32(REG_RTL_MII_CR, (HAL_MII_READ32(REG_RTL_MII_CR) | BIT0));
return _TRUE;
}
BOOL
HalMiiGmacEnablePhyModeRtl8195a(
IN VOID *Data
)
{
return _TRUE;
}
u32
HalMiiGmacXmitRtl8195a(
IN VOID *Data
)
{
return 0;
}
VOID
HalMiiGmacCleanTxRingRtl8195a(
IN VOID *Data
)
{
}
VOID
HalMiiGmacFillTxInfoRtl8195a(
IN VOID *Data
)
{
DBG_ENTRANCE;
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
PTX_INFO pTx_Info = pMiiAdapter->pTx_Info;
VOID* TxBuffer = pMiiAdapter->TxBuffer;
u32 RegValue;
LOGI(ANSI_COLOR_GREEN"==[ Tx Descriptor Configuration ]======\n"ANSI_COLOR_RESET);
pTx_Info->opts1.dw = 0xBC8001FE;
/* pTx_Info->opts1.dw = 0xBC800080; // size: 128 */
pTx_Info->addr = (u32)TxBuffer;
pTx_Info->opts2.dw = 0x0400279F;
pTx_Info->opts3.dw = 0x00000000;
/* pTx_Info->opts4.dw = 0x57800000; */
pTx_Info->opts4.dw = 0x1FE00000;
LOGI("pTx_Info->addr: %X\n", pTx_Info->addr);
LOGI(ANSI_COLOR_YELLOW"TxFDP1 Register(0x%04X) (W: 0x%X)\n"ANSI_COLOR_RESET, REG_RTL_MII_TXFDP1, pTx_Info);
RegValue = HAL_MII_READ32(REG_RTL_MII_TXFDP1);
LOGD2("[B] REG_RTL_MII_TXFDP1: %X\n", RegValue);
HAL_MII_WRITE32(REG_RTL_MII_TXFDP1, pTx_Info);
LOGD2("[A] REG_RTL_MII_TXFDP1: %X\n", HAL_MII_READ32(REG_RTL_MII_TXFDP1));
}
VOID
HalMiiGmacFillRxInfoRtl8195a(
IN VOID *Data
)
{
DBG_ENTRANCE;
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
PRX_INFO pRx_Info = pMiiAdapter->pRx_Info;
VOID* RxBuffer = pMiiAdapter->RxBuffer;
u32 RegValue;
LOGI(ANSI_COLOR_GREEN"==[ Rx Descriptor Configuration ]======\n"ANSI_COLOR_RESET);
/* pRx_Info->opts1.dw = 0x80000200; //Data Length: 4095(FFF), 512(200) */
pRx_Info->opts1.dw = 0x800001FC; //Data Length: 4095(FFF), 512(200)
/* pRx_Info->opts1.dw = 0x8000007F; */
pRx_Info->addr = (u32)RxBuffer;
pRx_Info->opts2.dw = 0x00000000;
pRx_Info->opts3.dw = 0x00000000;
LOGI(ANSI_COLOR_YELLOW"RxFDP1 Register(0x%04X) (W: 0x%X)\n"ANSI_COLOR_RESET, REG_RTL_MII_RXFDP1, pRx_Info);
RegValue = HAL_MII_READ32(REG_RTL_MII_RXFDP1);
LOGD2("[B] REG_RTL_MII_RXFDP1: %X\n", RegValue);
HAL_MII_WRITE32(REG_RTL_MII_RXFDP1, pRx_Info);
LOGD2("[A] REG_RTL_MII_RXFDP1: %X\n", HAL_MII_READ32(REG_RTL_MII_RXFDP1));
}
VOID
HalMiiGmacTxRtl8195a(
IN VOID *Data
)
{
DBG_ENTRANCE;
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
PTX_INFO pTx_Info = pMiiAdapter->pTx_Info;
u32 RegValue;
LOGI(ANSI_COLOR_GREEN"==[ Tx ]===============================\n"ANSI_COLOR_RESET);
LOGI(ANSI_COLOR_YELLOW"REG_RTL_MII_IOCMD Register(0x%04X): Enable Tx (W: 0x10, BIT4)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD);
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
LOGD2("[B] REG_RTL_MII_IOCMD: %X\n", RegValue);
RegValue |= BIT_IOCMD_TXENABLE(1);
HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue);
LOGD2("[A] REG_RTL_MII_IOCMD: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD));
LOGD4("--> Tx Descriptor opts1: %X\n", HAL_READ32(pTx_Info, 0));
LOGI(ANSI_COLOR_YELLOW"REG_RTL_MII_IOCMD Register(0x%04X): Enable 1st Tx (W: 0x1, BIT0)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD);
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
LOGD2("[B] REG_RTL_MII_IOCMD: %X\n", RegValue);
RegValue |= BIT_IOCMD_FIRST_DMATX_ENABLE(1);
HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue);
LOGD2("[A] REG_RTL_MII_IOCMD: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD));
LOGD4("--> Tx Descriptor opts1: %X\n", HAL_READ32(pTx_Info, 0));
}
VOID
HalMiiGmacRxRtl8195a(
IN VOID *Data
)
{
DBG_ENTRANCE;
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
u32 RegValue;
LOGI(ANSI_COLOR_GREEN"==[ Rx ]===============================\n"ANSI_COLOR_RESET);
LOGI(ANSI_COLOR_YELLOW"Transmit (Tx) Configuration Register (0x%04X) (W: 0x00000C00)\n"ANSI_COLOR_RESET, REG_RTL_MII_TCR);
RegValue = HAL_MII_READ32(REG_RTL_MII_TCR);
LOGD2("[B] REG_RTL_MII_TCR: %X\n", RegValue);
HAL_MII_WRITE32(REG_RTL_MII_TCR, 0x00000D00); // loopback R2T mode
LOGD2("[A] REG_RTL_MII_TCR: %X\n", HAL_MII_READ32(REG_RTL_MII_TCR));
LOGI(ANSI_COLOR_YELLOW"Receive (Rx) Configuration Register (0x%04X) (W: 0x0000007F)\n"ANSI_COLOR_RESET, REG_RTL_MII_RCR);
RegValue = HAL_MII_READ32(REG_RTL_MII_RCR);
LOGD2("[B] REG_RTL_MII_RCR: %X\n", RegValue);
HAL_MII_WRITE32(REG_RTL_MII_RCR, 0x0000007F);
LOGD2("[A] REG_RTL_MII_RCR: %X\n", HAL_MII_READ32(REG_RTL_MII_RCR));
LOGI(ANSI_COLOR_YELLOW"EhtrntRxCPU_Des_Num1 (0x%04X) (W: 0x1F0A0F00)\n"ANSI_COLOR_RESET, REG_RTL_MII_ETNRXCPU1);
RegValue = HAL_MII_READ32(REG_RTL_MII_ETNRXCPU1);
LOGD2("[B] REG_RTL_MII_ETNRXCPU1: %X\n", RegValue);
HAL_MII_WRITE32(REG_RTL_MII_ETNRXCPU1, 0x1F0A0F00);
LOGD2("[A] REG_RTL_MII_ETNRXCPU1: %X\n", HAL_MII_READ32(REG_RTL_MII_ETNRXCPU1));
LOGI(ANSI_COLOR_YELLOW"Rx_Pse_Des_Thres_1_h (0x%04X) (W: 0x00000022)\n"ANSI_COLOR_RESET, REG_RTL_MII_RX_PSE1);
RegValue = HAL_MII_READ32(REG_RTL_MII_RX_PSE1);
LOGD2("[B] REG_RTL_MII_RX_PSE1: %X\n", RegValue);
HAL_MII_WRITE32(REG_RTL_MII_RX_PSE1, 0x00000022);
LOGD2("[A] REG_RTL_MII_RX_PSE1: %X\n", HAL_MII_READ32(REG_RTL_MII_RX_PSE1));
LOGI(ANSI_COLOR_YELLOW"Ethernet_IO_CMD1 Register(0x%04X): Enable Rx Ring1 (W: 0x10000, BIT16)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD1);
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1);
LOGD2("[B] REG_RTL_MII_IOCMD1: %X\n", RegValue);
RegValue |= BIT_IOCMD1_FIRST_DMARX_ENABLE(1);
HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, RegValue);
LOGD2("[A] REG_RTL_MII_IOCMD1: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD1));
LOGI(ANSI_COLOR_YELLOW"REG_RTL_MII_IOCMD Register(0x%04X): Enable Rx (W: 0x20, BIT5)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD);
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
LOGD2("[B] REG_RTL_MII_IOCMD: %X\n", RegValue);
RegValue |= BIT_IOCMD_RXENABLE(1);
HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue);
LOGD2("[A] REG_RTL_MII_IOCMD: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD));
}
VOID
HalMiiGmacSetDefaultEthIoCmdRtl8195a(
IN VOID *Data
)
{
DBG_ENTRANCE;
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
u32 RegValue;
LOGI(ANSI_COLOR_YELLOW"REG_RTL_MII_IOCMD Register(0x%04X) (W: CMD_CONFIG)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD);
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
LOGD2("[B] REG_RTL_MII_IOCMD: %X\n", RegValue);
HAL_MII_WRITE32(REG_RTL_MII_IOCMD, CMD_CONFIG);
LOGD2("[A] REG_RTL_MII_IOCMD: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD));
LOGI(ANSI_COLOR_YELLOW"Ethernet_IO_CMD1 Register(0x%04X) (W: CMD1_CONFIG)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD1);
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1);
LOGD2("[B] REG_RTL_MII_IOCMD1: %X\n", RegValue);
HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, CMD1_CONFIG);
LOGD2("[A] REG_RTL_MII_IOCMD1: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD1));
//2014-04-29 yclin (disable 0x40051438[27] r_en_precise_dma) {
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1);
RegValue = RegValue & 0xF7FFFFFF;
HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, RegValue);
// }
}
VOID
HalMiiGmacInitIrqRtl8195a(
IN VOID *Data
)
{
IRQ_HANDLE MiiIrqHandle_Master;
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
MiiIrqHandle_Master.Data = (u32) (pMiiAdapter);
MiiIrqHandle_Master.IrqNum = GMAC_IRQ;
MiiIrqHandle_Master.IrqFun = (IRQ_FUN) MiiIrqHandle;
MiiIrqHandle_Master.Priority = 0;
InterruptRegister(&MiiIrqHandle_Master);
InterruptEn(&MiiIrqHandle_Master);
}
u32
HalMiiGmacGetInterruptStatusRtl8195a(
VOID
)
{
DBG_ENTRANCE;
u32 RegValue;
RegValue = HAL_MII_READ32(REG_RTL_MII_IMRISR);
LOGD("REG_RTL_MII_IMRISR: %X\n", RegValue);
return RegValue;
}
VOID
HalMiiGmacClearInterruptStatusRtl8195a(
u32 IsrStatus
)
{
DBG_ENTRANCE;
HAL_MII_WRITE32(REG_RTL_MII_IMRISR, IsrStatus);
}

1919
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_nfc.c Normal file
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component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "platform_autoconf.h"
#include "diag.h"
#include "rtl8195a_pcm.h"
#include "hal_pcm.h"
extern void *
_memset( void *s, int c, SIZE_T n );
VOID
HalPcmOnOffRtl8195a (
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
//todo on off pcm
}
//default sampling rate 8khz, linear, 10ms frame size, time slot 0 , tx+rx
// master mode, enable endian swap
// Question: need local tx/rx page?
BOOL
HalPcmInitRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
_memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER));
//4 1) Initial PcmChCNR03 Register
pHalPcmAdapter->PcmChCNR03.CH0MuA = 0;
pHalPcmAdapter->PcmChCNR03.CH0Band = 0;
//4 1) Initial PcmTSR03 Register
pHalPcmAdapter->PcmTSR03.CH0TSA = 0;
//4 1) Initial PcmBSize03 Register
pHalPcmAdapter->PcmBSize03.CH0BSize = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte
//4 2) Initial Ctl Register
pHalPcmAdapter->PcmCtl.Pcm_En = 1;
pHalPcmAdapter->PcmCtl.SlaveMode = 0;
pHalPcmAdapter->PcmCtl.FsInv = 0;
pHalPcmAdapter->PcmCtl.LinearMode = 0;
pHalPcmAdapter->PcmCtl.LoopBack = 0;
pHalPcmAdapter->PcmCtl.EndianSwap = 1;
return _TRUE;
}
BOOL
HalPcmSettingRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03;
u32 Isr03;
PcmCh=0;
//4 1) Check Pcm index is avaliable
if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
//4 2) Check if there are the pending isr
Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03);
Isr03 &= 0xff000000;
//4 Clear Pending Isr
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03);
//}
//4 3) Process RegCtl
RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL);
//4 Clear Ctl register bits
RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL &
BIT_INV_CTLX_FSINV &
BIT_INV_CTLX_PCM_EN &
BIT_INV_CTLX_LINEARMODE &
BIT_INV_CTLX_LOOP_BACK &
BIT_INV_CTLX_ENDIAN_SWAP);
RegCtl = BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) |
BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) |
BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) |
BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) |
BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) |
BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) |
RegCtl;
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl);
//4 4) Program ChCNR03 Register
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE &
BIT_INV_CHCNR03_CH0TE &
BIT_INV_CHCNR03_CH0MUA &
BIT_INV_CHCNR03_CH0BAND);
RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) |
BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) |
BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) |
BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) |
RegChCNR03;
DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03);
// time slot
RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03);
RegTSR03 &= (BIT_INV_TSR03_CH0TSA);
RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) |
RegTSR03;
DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03);
// buffer size
RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03);
RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE);
RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) |
RegBSize03;
DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03);
return _TRUE;
}
BOOL
HalPcmEnRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 1;
//4 1) Check Pcm index is avaliable
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
if (RegChCNR03 & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25);
pHalPcmAdapter->PcmChCNR03.CH0RE = 1;
pHalPcmAdapter->PcmChCNR03.CH0TE = 1;
return _TRUE;
}
BOOL
HalPcmDisRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 0;
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25)));
pHalPcmAdapter->PcmChCNR03.CH0RE = 0;
pHalPcmAdapter->PcmChCNR03.CH0TE = 0;
return _TRUE;
}
BOOL
HalPcmIsrEnAndDisRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrMask, Addr, IsrCtrl;
u8 IsrTypeIndex = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
Addr = (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8);
IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr);
IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask):
((~pHalGdmaAdapter->ChEn) & IsrMask));
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
Addr,
IsrCtrl
);
}
}
*/
return _TRUE;
}
BOOL
HalPcmDumpRegRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
BOOL
HalPcmRtl8195a (
IN VOID *Data
)
{
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
~(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
/*
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrStatus;
u8 IsrTypeIndex = 0, IsrActBitMap = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8));
// DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus);
IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF));
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)),
(IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF))
);
IsrActBitMap |= BIT_(IsrTypeIndex);
}
}
return IsrActBitMap;
}
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
*/

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component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pwm.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "hal_peri_on.h"
#ifdef CONFIG_PWM_EN
#include "rtl8195a_pwm.h"
#include "hal_pwm.h"
extern HAL_PWM_ADAPTER PWMPin[];
extern HAL_TIMER_OP HalTimerOp;
/**
* @brief Configure a G-Timer to generate a tick with certain time.
*
* @param pwm_id: the PWM pin index
* @param tick_time: the time (micro-second) of a tick
*
* @retval None
*/
void
Pwm_SetTimerTick_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 tick_time
)
{
TIMER_ADAPTER TimerAdapter;
if (tick_time <= MIN_GTIMER_TIMEOUT) {
tick_time = MIN_GTIMER_TIMEOUT;
}
else {
tick_time = (((tick_time-1)/TIMER_TICK_US)+1) * TIMER_TICK_US;
}
// Initial a G-Timer for the PWM pin
if (pPwmAdapt->tick_time != tick_time) {
TimerAdapter.IrqDis = 1; // Disable Irq
TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) NULL;
TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ;
TimerAdapter.IrqHandle.Priority = 0;
TimerAdapter.IrqHandle.Data = (u32)NULL;
TimerAdapter.TimerId = pPwmAdapt->gtimer_id;
TimerAdapter.TimerIrqPriority = 0;
TimerAdapter.TimerLoadValueUs = tick_time-1;
TimerAdapter.TimerMode = 1; // auto-reload with user defined value
HalTimerOp.HalTimerInit((VOID*) &TimerAdapter);
pPwmAdapt->tick_time = tick_time;
DBG_PWM_INFO("%s: Timer_Id=%d Count=%d\n", __FUNCTION__, pPwmAdapt->gtimer_id, tick_time);
}
}
/**
* @brief Set the duty ratio of the PWM pin.
*
* @param pwm_id: the PWM pin index
* @param period: the period time, in micro-second.
* @param pulse_width: the pulse width time, in micro-second.
*
* @retval None
*/
void
HAL_Pwm_SetDuty_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
)
{
u32 RegAddr;
u32 RegValue;
u32 period_tick;
u32 pulsewidth_tick;
u32 tick_time;
u8 timer_id;
u8 pwm_id;
pwm_id = pPwmAdapt->pwm_id;
// Adjust the tick time to a proper value
if (period < (MIN_GTIMER_TIMEOUT*2)) {
DBG_PWM_ERR ("HAL_Pwm_SetDuty_8195a: Invalid PWM period(%d), too short!!\n", period);
tick_time = MIN_GTIMER_TIMEOUT;
period = MIN_GTIMER_TIMEOUT*2;
}
else {
tick_time = period / 0x3fc;
if (tick_time < MIN_GTIMER_TIMEOUT) {
tick_time = MIN_GTIMER_TIMEOUT;
}
}
Pwm_SetTimerTick_8195a(pPwmAdapt, tick_time);
tick_time = pPwmAdapt->tick_time;
#if 0
// Check if current tick time needs adjustment
if ((pPwmAdapt->tick_time << 12) <= period) {
// need a longger tick time
}
else if ((pPwmAdapt->tick_time >> 2) >= period) {
// need a shorter tick time
}
#endif
period_tick = period/tick_time;
if (period_tick == 0) {
period_tick = 1;
}
if (pulse_width >= period) {
// pulse_width = period-1;
pulse_width = period;
}
pulsewidth_tick = pulse_width/tick_time;
if (pulsewidth_tick == 0) {
// pulsewidth_tick = 1;
}
timer_id = pPwmAdapt->gtimer_id;
pPwmAdapt->period = period_tick & 0x3ff;
pPwmAdapt->pulsewidth = pulsewidth_tick & 0x3ff;
RegAddr = REG_PERI_PWM0_CTRL + (pwm_id*4);
RegValue = BIT31 | (timer_id<<24) | (pulsewidth_tick<<12) | period_tick;
HAL_WRITE32(PERI_ON_BASE, RegAddr, RegValue);
}
/**
* @brief Initializes and enable a PWM control pin.
*
* @param pwm_id: the PWM pin index
* @param sel: pin mux selection
* @param timer_id: the G-timer index assigned to this PWM
*
* @retval HAL_Status
*/
HAL_Status
HAL_Pwm_Init_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
)
{
u32 pwm_id;
u32 pin_sel;
pwm_id = pPwmAdapt->pwm_id;
pin_sel = pPwmAdapt->sel;
// Initial a G-Timer for the PWM pin
Pwm_SetTimerTick_8195a(pPwmAdapt, MIN_GTIMER_TIMEOUT);
// Set default duty ration
HAL_Pwm_SetDuty_8195a(pPwmAdapt, 20000, 10000);
// Configure the Pin Mux
PinCtrl((PWM0+pwm_id), pin_sel, 1);
return HAL_OK;
}
/**
* @brief Enable a PWM control pin.
*
* @param pwm_id: the PWM pin index
*
* @retval None
*/
void
HAL_Pwm_Enable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
)
{
u32 pwm_id;
pwm_id = pPwmAdapt->pwm_id;
// Configure the Pin Mux
if (!pPwmAdapt->enable) {
PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 1);
HalTimerOp.HalTimerEn(pPwmAdapt->gtimer_id);
pPwmAdapt->enable = 1;
}
}
/**
* @brief Disable a PWM control pin.
*
* @param pwm_id: the PWM pin index
*
* @retval None
*/
void
HAL_Pwm_Disable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
)
{
u32 pwm_id;
pwm_id = pPwmAdapt->pwm_id;
// Configure the Pin Mux
if (pPwmAdapt->enable) {
PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 0);
HalTimerOp.HalTimerDis(pPwmAdapt->gtimer_id);
pPwmAdapt->enable = 0;
}
}
#endif //CONFIG_PWM_EN

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component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_sdio_device.c Normal file
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component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_timer.h"
extern u32 gTimerRecord;
extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM];
#ifdef CONFIG_CHIP_C_CUT
extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#else
u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#endif
VOID
HalTimerIrq2To7Handle_Patch(
IN VOID *Data
)
{
u32 TimerIrqStatus = 0, CheckIndex;
IRQ_FUN pHandler;
TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF);
DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus);
for (CheckIndex = 2; CheckIndex<8; CheckIndex++) {
//3 Check IRQ status bit and Timer X IRQ enable bit
if ((TimerIrqStatus & BIT_(CheckIndex)) &&
(HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) {
//3 Execute Timer callback function
pHandler = Timer2To7VectorTable[CheckIndex-2];
if (pHandler != NULL) {
pHandler((void*)Timer2To7HandlerData[CheckIndex-2]);
}
//3 Clear Timer ISR
HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF);
}
}
}
HAL_Status
HalTimerIrqRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
IRQ_HANDLE TimerIrqHandle;
IRQ_FUN BackUpIrqFun = NULL;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
TimerIrqHandle.IrqNum = TIMER2_7_IRQ;
TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] =
(IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
Timer2To7HandlerData[pHalTimerAdap->TimerId-2] =
(uint32_t) pHalTimerAdap->IrqHandle.Data;
}
else {
TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
}
TimerIrqHandle.Data = (u32)pHalTimerAdap;
InterruptRegister(&TimerIrqHandle);
}
return HAL_OK;
}
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
u32 ControlReg = 0, LoadCount = 0;
u32 LoadUsX4;
if ((gTimerRecord & (1<<pHalTimerAdap->TimerId)) != 0) {
DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_BUSY;
}
ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2);
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
LoadUsX4 = pHalTimerAdap->TimerLoadValueUs << 2;
if (LoadUsX4 < TIMER_TICK_US_X4) {
DBG_TIMER_WARN("%s : Timer Load Count = 1!\r\n", __FUNCTION__);
LoadCount = 1;
}
else {
LoadCount = (LoadUsX4-(TIMER_TICK_US_X4>>1))/TIMER_TICK_US_X4; // to get the most closed integer
if (LoadCount == 0) {
LoadCount = 1;
}
}
}
else {
LoadCount = 0xFFFFFFFF;
}
//4 1) Config Timer Setting
/*
set TimerControlReg
0: Timer enable (0,disable; 1,enable)
1: Timer Mode (0, free-running mode; 1, user-defined count mode)
2: Timer Interrupt Mask (0, not masked; 1,masked)
*/
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
ControlReg);
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF),
LoadCount);
//4 2) Setting Timer IRQ
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
//4 2.1) Initial TimerIRQHandle
ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap);
if (HAL_OK != ret) {
DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return ret;
}
//4 2.2) Enable TimerIRQ for Platform
InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
}
else {
DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
}
//4 4) Enable Timer
// HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
// (ControlReg|0x1));
gTimerRecord |= (1<<pHalTimerAdap->TimerId);
return ret;
}
HAL_Status
HalTimerIrqUnRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
PIRQ_HANDLE pTimerIrqHandle;
u32 i;
pTimerIrqHandle = &pHalTimerAdap->IrqHandle;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
pTimerIrqHandle->IrqNum = TIMER2_7_IRQ;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL;
for (i=0;i<MAX_TIMER_VECTOR_TABLE_NUM;i++) {
if (Timer2To7VectorTable[i] != NULL) {
break;
}
}
if (i == MAX_TIMER_VECTOR_TABLE_NUM) {
// All timer UnRegister Interrupt
InterruptDis((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
InterruptUnRegister(pTimerIrqHandle);
}
}
else {
pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
InterruptUnRegister(pTimerIrqHandle);
}
}
return HAL_OK;
}
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
u32 timer_id;
timer_id = pHalTimerAdap->TimerId;
HalTimerDisRtl8195a (timer_id);
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap);
}
}
gTimerRecord &= ~(1<<pHalTimerAdap->TimerId);
}
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
)
{
u32 LoadCount = 0;
u32 LoadUsX4;
//User-defined Mode
LoadUsX4 = LoadUs << 2; // time 4
if (LoadUsX4 < TIMER_TICK_US_X4) {
DBG_TIMER_WARN("HalTimerReLoadRtl8195a Warning : Timer Load Count = 1!!!!!!!\n");
LoadCount = 1;
}
else {
LoadCount = (LoadUsX4-(TIMER_TICK_US_X4>>1))/TIMER_TICK_US_X4; // to get the most closed integer
if (LoadCount == 0) {
LoadCount = 1;
}
}
DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount);
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF),
LoadCount);
}
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
)
{
u32 TimerCountOld;
u32 TimerCountNew;
u32 TimerRDCnt;
TimerRDCnt = 0;
TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
while(1) {
TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
if (TimerCountOld == TimerCountNew) {
return (u32)TimerCountOld;
}
else {
TimerRDCnt++;
TimerCountOld = TimerCountNew;
if (TimerRDCnt >= 2){
return (u32)TimerCountOld;
}
}
}
}
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~(BIT2)));
}
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT2));
}
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT0));
}
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
)
{
// Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~BIT0));
}

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_uart.h"
#include "hal_uart.h"
#include "hal_gdma.h"
#if (CONFIG_CHIP_A_CUT | CONFIG_CHIP_B_CUT)
const u32 BAUDRATE_PATCH[] = {
1200, 2400, 4800, 9600,
14400, 19200, 28800, 38400,
57600, 76800, 115200, 128000,
153600, 230400, 460800, 500000,
921600, 1000000, 1382400, 1444400,
1500000, 1843200, 2000000, 2100000,
2764800, 3000000, 3250000, 3692300,
3750000, 4000000, 6000000,
// For UART to IR Carrier
66000, 72000, 73400, 76000,
80000, 112000
};
#if 0
const u32 OVSR_PATCH[] = {
11, 13, 19, 10,
20, 10, 20, 17,
11, 10, 17, 10,
10, 13, 18, 13,
20, 19, 13, 15,
13, 13, 15, 13,
12, 11, 11, 20,
13
};
const u32 DIV_PATCH[] = {
6105, 643, 293, 434,
142, 217, 71, 62,
65, 62, 31, 34,
17, 12, 5, 6,
3, 3, 4, 3,
3, 3, 2, 2,
2, 2, 2, 1,
1
};
const u32 OVSR_ADJ_PATCH[] = {
0x24A, 0x555, 0x3BB, 0x000,
0x24A, 0x000, 0x24A, 0x555,
0x008, 0x555, 0x555, 0x5AD,
0x5AD, 0x7EF, 0x020, 0x7EF,
0x020, 0x444, 0x7EF, 0x080,
0x7EF, 0x444, 0x080, 0x7EF,
0x6FB, 0x122, 0x010, 0x5F7,
0x7EF
};
#else
const u8 OVSR_PATCH[] = {
10, 10, 10, 15,
10, 13, 15, 11,
12, 11, 12, 11,
11, 18, 11, 18,
11, 10, 11, 11,
18, 11, 10, 13,
14, 13, 12, 11,
10, 10, 13,
// For UART to IR Carrier
11, 18, 14, 10,
10, 11
};
const u16 DIV_PATCH[] = {
6516, 3258, 1629, 543,
543, 311, 181, 188,
114, 94, 57, 57,
47, 19, 15, 9,
8, 8, 5, 5,
3, 4, 4, 3,
2, 2, 2, 2,
2, 2, 1,
// For UART to IR Carrier
111, 63, 79, 102,
98, 64
};
const u16 OVSR_ADJ_PATCH[] = {
0x555, 0x555, 0x555, 0x3BB,
0x555, 0x5DD, 0x3BB, 0x252,
0x555, 0x252, 0x555, 0x222,
0x252, 0x3BB, 0x7EF, 0x444,
0x008, 0x222, 0x7EF, 0x252,
0x444, 0x008, 0x222, 0x000,
0x5F7, 0x76D, 0x5AD, 0x010,
0x5FF, 0x222, 0x76D,
// For UART to IR Carrier
0x24A, 0x252, 0x252, 0x5DD,
0x5AD, 0x5AD
};
#endif
#if 0
static s32
FindElementIndex(
u32 Element, ///< RUART Baudrate
u32* Array ///< Pre-defined Baudrate Array
)
{
/* DBG_ENTRANCE; */
u32 BaudRateNumber = 29;
s32 Result = -1;
u32 Index = 0;
for (Index = 0; Index < BaudRateNumber && Result == -1; Index++) {
if (Element == Array[Index])
Result = Index;
}
return Result; //TODO: Error handling
}
#endif
s32
FindElementIndex_Patch(
u32 Element, ///< RUART Baudrate
u32* Array, ///< Pre-defined Baudrate Array
u32 ElementNo
)
{
/* DBG_ENTRANCE; */
s32 Result = -1;
u32 Index = 0;
for (Index = 0; Index < ElementNo && Result == -1; Index++) {
if (Element == Array[Index])
Result = Index;
}
return Result; //TODO: Error handling
}
HAL_Status
HalRuartInitRtl8195a_Patch(
IN VOID *Data ///< RUART Adapter
)
{
/* DBG_ENTRANCE; */
u32 RegValue;
u32 Divisor;
u32 Dll;
u32 Dlm;
u8 UartIndex;
s32 ElementIndex;
RUART_SPEED_SETTING RuartSpeedSetting;
u8 PinmuxSelect;
PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data;
UartIndex = pHalRuartAdapter->UartIndex;
PinmuxSelect = pHalRuartAdapter->PinmuxSelect;
if (UartIndex > 2) {
DBG_UART_ERR(ANSI_COLOR_MAGENTA"HalRuartInitRtl8195a: Invalid UART Index\n"ANSI_COLOR_RESET);
return HAL_ERR_PARA;
}
DBG_UART_INFO("%s==>\n", __FUNCTION__);
DBG_UART_INFO("HalRuartInitRtl8195a: [UART %d] PinSel=%d\n", UartIndex, PinmuxSelect);
if(( PinmuxSelect == RUART0_MUX_TO_GPIOE ) && ((UartIndex == 0) || (UartIndex == 1))) {
DBG_UART_WARN(ANSI_COLOR_MAGENTA"UART Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
}
// switch Pin from EEPROM to UART0
if(( PinmuxSelect == RUART0_MUX_TO_GPIOC ) && (UartIndex == 0)) {
RegValue = HAL_READ32(SYSTEM_CTRL_BASE, 0xa4);
if (RegValue & 0x10) {
DBG_UART_WARN("Disable EEPROM Pin for UART 0\n");
HAL_WRITE32(SYSTEM_CTRL_BASE, 0xa4, (RegValue & (~0x10)));
}
}
switch (UartIndex) {
case 0:
/* UART 0 */
ACTCK_UART0_CCTRL(ON);
SLPCK_UART0_CCTRL(ON);
PinCtrl(UART0, PinmuxSelect, ON);
UART0_FCTRL(ON);
UART0_BD_FCTRL(ON);
break;
case 1:
/* UART 1 */
ACTCK_UART1_CCTRL(ON);
SLPCK_UART1_CCTRL(ON);
PinCtrl(UART1, PinmuxSelect, ON);
UART1_FCTRL(ON);
UART1_BD_FCTRL(ON);
break;
case 2:
/* UART 1 */
ACTCK_UART2_CCTRL(ON);
SLPCK_UART2_CCTRL(ON);
PinCtrl(UART2, PinmuxSelect, ON);
UART2_FCTRL(ON);
UART2_BD_FCTRL(ON);
break;
default:
DBG_UART_ERR("Invalid UART Index(%d)\n", UartIndex);
return HAL_ERR_PARA;
}
/* Reset RX FIFO */
HalRuartResetRxFifoRtl8195a(Data);
DBG_UART_INFO(ANSI_COLOR_CYAN"HAL UART Init[UART %d]\n"ANSI_COLOR_RESET, UartIndex);
/* Disable all interrupts */
HAL_RUART_WRITE32(UartIndex, RUART_INTERRUPT_EN_REG_OFF, 0x00);
/* Set DLAB bit to 1 to access DLL/DLM */
RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF);
RegValue |= RUART_LINE_CTL_REG_DLAB_ENABLE;
HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue);
DBG_UART_INFO("[R] RUART_LINE_CTL_REG_OFF(0x0C) = %x\n", HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
/* Set Baudrate Division */
#if 1
ElementIndex = FindElementIndex_Patch(pHalRuartAdapter->BaudRate, (uint32_t*)BAUDRATE_PATCH, sizeof(BAUDRATE_PATCH)/sizeof(u32));
if (ElementIndex < 0) {
ElementIndex = 5;
DBG_UART_ERR("Invalid BaudRate(%d), Force it as default(%d)\n", pHalRuartAdapter->BaudRate, BAUDRATE_PATCH[ElementIndex]);
}
RuartSpeedSetting.BaudRate = BAUDRATE_PATCH[ElementIndex];
RuartSpeedSetting.Ovsr = OVSR_PATCH[ElementIndex];
RuartSpeedSetting.Div = DIV_PATCH[ElementIndex];
RuartSpeedSetting.Ovsr_adj = OVSR_ADJ_PATCH[ElementIndex];
#else
RuartSpeedSetting.BaudRate = 38400;
RuartSpeedSetting.Ovsr = 10;
RuartSpeedSetting.Div = 217;
RuartSpeedSetting.Ovsr_adj = 0x0;
#endif
DBG_UART_INFO("Baud %d, Ovsr %d, Div %d, OvsrAdj 0x%X\n",
RuartSpeedSetting.BaudRate,
RuartSpeedSetting.Ovsr,
RuartSpeedSetting.Div,
RuartSpeedSetting.Ovsr_adj
);
/* Divisor = (SYSTEM_CLK / ((ovsr + 5 + ovsr_adj/11) * (UartAdapter.BaudRate))); */
/* Set Divisor */
Divisor = RuartSpeedSetting.Div;
Dll = Divisor & 0xFF;
Dlm = (Divisor & 0xFF00) >> 8;
// DBG_UART_INFO("Calculated Dll, Dlm = %02x, %02x\n", Dll, Dlm);
// DBG_UART_INFO("---- Before setting baud rate ----\n");
// DBG_UART_INFO(" [R] RUART_DLL_OFF(0x00) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLL_OFF));
// DBG_UART_INFO(" [R] RUART_DLM_OFF(0x04) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLM_OFF));
HAL_RUART_WRITE32(UartIndex, RUART_DLL_OFF, Dll);
HAL_RUART_WRITE32(UartIndex, RUART_DLM_OFF, Dlm);
// DBG_UART_INFO("---- After setting baud rate ----\n");
// DBG_UART_INFO(" [R] RUART_DLL_OFF(0x00) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLL_OFF));
// DBG_UART_INFO(" [R] RUART_DLM_OFF(0x04) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLM_OFF));
// DBG_UART_INFO(ANSI_COLOR_CYAN"---- Befor OVSR & OVSR_ADJ ----\n"ANSI_COLOR_RESET);
// RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
// DBG_UART_INFO("UART%d SPR(0x1C) = %X\n", UartIndex, RegValue);
// RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF);
// DBG_UART_INFO("UART%d SIS(0x20) = %X\n", UartIndex, RegValue);
/**
* Clean Rx break signal interrupt status at initial stage.
*/
RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
RegValue |= RUART_SP_REG_RXBREAK_INT_STATUS;
HAL_RUART_WRITE32(UartIndex, RUART_SCRATCH_PAD_REG_OFF, RegValue);
/* Set OVSR(xfactor) */
RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF);
RegValue &= ~(RUART_STS_REG_XFACTOR);
RegValue |= (((RuartSpeedSetting.Ovsr - 5) << 4) & RUART_STS_REG_XFACTOR);
HAL_RUART_WRITE32(UartIndex, RUART_STS_REG_OFF, RegValue);
/* Set OVSR_ADJ[10:0] (xfactor_adj[26:16]) */
RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
RegValue &= ~(RUART_SP_REG_XFACTOR_ADJ);
RegValue |= ((RuartSpeedSetting.Ovsr_adj << 16) & RUART_SP_REG_XFACTOR_ADJ);
HAL_RUART_WRITE32(UartIndex, RUART_SCRATCH_PAD_REG_OFF, RegValue);
// DBG_UART_INFO(ANSI_COLOR_CYAN"---- After OVSR & OVSR_ADJ ----\n"ANSI_COLOR_RESET);
// RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
// DBG_UART_INFO("UART%d SPR(0x1C) = %X\n", UartIndex, RegValue);
// RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF);
// DBG_UART_INFO("UART%d SIS(0x20) = %X\n", UartIndex, RegValue);
/* clear DLAB bit */
RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF);
RegValue &= ~(RUART_LINE_CTL_REG_DLAB_ENABLE);
HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue);
// DBG_UART_INFO("[R] RUART_LINE_CTL_REG_OFF(0x0C) = %x\n", HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
// DBG_UART_INFO("[R] UART%d INT_EN(0x04) = %x\n", UartIndex, pHalRuartAdapter->Interrupts);
RegValue = ((pHalRuartAdapter->Interrupts) & 0xFF);
HAL_RUART_WRITE32(UartIndex, RUART_INTERRUPT_EN_REG_OFF, RegValue);
// DBG_UART_INFO("[W] UART%d INT_EN(0x04) = %x\n", UartIndex, RegValue);
/* Configure FlowControl */
if (pHalRuartAdapter->FlowControl == AUTOFLOW_ENABLE) {
RegValue = HAL_RUART_READ32(UartIndex, RUART_MODEM_CTL_REG_OFF);
RegValue |= RUART_MCL_AUTOFLOW_ENABLE;
HAL_RUART_WRITE32(UartIndex, RUART_MODEM_CTL_REG_OFF, RegValue);
}
/* RUART DMA Initialization */
HalRuartDmaInitRtl8195a(pHalRuartAdapter);
DBG_UART_INFO("[R] UART%d LCR(0x%02X): %X\n", UartIndex, RUART_LINE_CTL_REG_OFF, HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF);
/* PARITY CONTROL */
RegValue &= BIT_CLR_LCR_WLS;
RegValue |= BIT_LCR_WLS(pHalRuartAdapter->WordLen);
RegValue &= BIT_INVC_LCR_STB_EN;
RegValue |= BIT_LCR_STB_EN(pHalRuartAdapter->StopBit);
RegValue &= BIT_INVC_LCR_PARITY_EN;
RegValue |= BIT_LCR_PARITY_EN(pHalRuartAdapter->Parity);
/* PARITY TYPE SELECT */
RegValue &= BIT_INVC_LCR_PARITY_TYPE;
RegValue |= BIT_LCR_PARITY_TYPE(pHalRuartAdapter->ParityType);
/* STICK PARITY CONTROL */
RegValue &= BIT_INVC_LCR_STICK_PARITY_EN;
RegValue |= BIT_LCR_STICK_PARITY_EN(pHalRuartAdapter->StickParity);
HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue);
DBG_UART_INFO("[W] UART%d LCR(0x%02X): %X\n", UartIndex, RUART_LINE_CTL_REG_OFF, HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
/* Need to assert RTS during initial stage. */
if (pHalRuartAdapter->FlowControl == AUTOFLOW_ENABLE) {
HalRuartRTSCtrlRtl8195a(Data, 1);
}
pHalRuartAdapter->State = HAL_UART_STATE_READY;
return HAL_OK;
}
#endif
/**
* Reset RUART Tx FIFO.
*
* Reset RUART Receiver and Rx FIFO wrapper function.
* It will check LINE_STATUS_REG until reset action completion.
*
* @return BOOL
*/
HAL_Status
HalRuartResetTxFifoRtl8195a(
IN VOID *Data ///< RUART Adapter
)
{
PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data;
u8 UartIndex = pHalRuartAdapter->UartIndex;
u32 rx_trigger_lv;
u32 RegValue;
// Backup the RX FIFO trigger Level setting
rx_trigger_lv = HAL_RUART_READ32(UartIndex, RUART_FIFO_CTL_REG_OFF);
rx_trigger_lv &= 0xC0; // only keep the bit[7:6]
/* Step 2: Enable clear_txfifo */
RegValue = (FIFO_CTL_DEFAULT_WITH_FIFO_DMA | RUART_FIFO_CTL_REG_CLEAR_TXFIFO) & (~0xC0);
RegValue |= rx_trigger_lv;
HAL_RUART_WRITE32(UartIndex, RUART_FIFO_CTL_REG_OFF, RegValue);
//TODO: Check Defautl Value
RegValue = (FIFO_CTL_DEFAULT_WITH_FIFO_DMA & (~0xC0)) | rx_trigger_lv;
HAL_RUART_WRITE32(UartIndex, RUART_FIFO_CTL_REG_OFF, RegValue);
return HAL_OK;
}