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component/soc/realtek/8195a/cmsis/core_cmFunc.h

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+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

component/soc/realtek/8195a/cmsis/core_cmInstr.h

@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

component/soc/realtek/8195a/cmsis/device/app_start.c

@@ -0,0 +1,192 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#include "rtl8195a.h"
+#include "build_info.h"
+#ifdef PLATFORM_FREERTOS
+#include "FreeRTOS.h"
+#include "task.h"
+#endif
+
+#if defined (CONFIG_USB_EN) && defined(CONFIG_USB_HOST_ONLY)
+	extern void _usb_init(void);
+#endif
+
+#if defined(CONFIG_SDIO_DEVICE_EN) && defined(CONFIG_SDIO_DEVICE_NORMAL)
+extern VOID HalSdioInit(VOID);
+#endif
+
+#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK)
+extern void init_rom_wlan_ram_map(void);
+extern VOID wlan_network(VOID);
+#endif
+
+//3 Monitor App Function
+extern VOID RtlConsolInitRam(u32 Boot, u32 TBLSz, VOID *pTBL);
+#ifndef CONFIG_KERNEL
+extern VOID RtlConsolTaskRom(VOID *Data);
+#endif
+
+#ifndef CONFIG_WITHOUT_MONITOR
+extern COMMAND_TABLE    UartLogRamCmdTable[];
+extern u32 GetRamCmdNum(VOID);
+extern VOID UartLogIrqHandleRam(VOID * Data);
+#endif
+
+#ifdef CONFIG_APP_DEMO
+#define MAIN_APP_DEFAULT_STACK_SIZE         2048
+#define MAIN_APP_DEFAULT_PRIORITY           (tskIDLE_PRIORITY + 1)
+#endif
+
+#ifdef CONFIG_MBED_ENABLED
+extern void __libc_fini_array (void);
+extern void __libc_init_array (void);
+extern  void SVC_Handler (void);
+extern  void PendSV_Handler (void);
+extern  void SysTick_Handler (void);
+#endif
+
+#ifndef CONFIG_WITHOUT_MONITOR
+static 
+VOID
+ReRegisterPlatformLogUart(
+    VOID
+)
+{
+    IRQ_HANDLE          UartIrqHandle;
+    
+    //4 Register Log Uart Callback function
+    UartIrqHandle.Data = NULL;//(u32)&UartAdapter;
+    UartIrqHandle.IrqNum = UART_LOG_IRQ;
+    UartIrqHandle.IrqFun = (IRQ_FUN) UartLogIrqHandleRam;
+    UartIrqHandle.Priority = 0;
+
+    
+    //4 Register Isr handle
+    InterruptUnRegister(&UartIrqHandle); 
+    InterruptRegister(&UartIrqHandle); 
+#if !TASK_SCHEDULER_DISABLED    
+    RtlConsolInitRam((u32)RAM_STAGE,(u32)GetRamCmdNum(),(VOID*)&UartLogRamCmdTable);
+#else
+    RtlConsolInitRam((u32)ROM_STAGE,(u32)GetRamCmdNum(),(VOID*)&UartLogRamCmdTable);
+#endif
+}
+#endif  // end of "#ifndef CONFIG_WITHOUT_MONITOR"
+
+
+VOID ShowRamBuildInfo(VOID)
+{
+    /*
+    DBG_8195A("=========================================================\n\n");
+    //DBG_8195A("Build Time: "UTS_VERSION"\n");
+    DBG_8195A("Build Time: "RTL8195AFW_COMPILE_TIME"\n");
+    DBG_8195A("Build Author: "RTL8195AFW_COMPILE_BY"\n");    
+    DBG_8195A("Build Host: "RTL8195AFW_COMPILE_HOST"\n");    
+    DBG_8195A("Build ToolChain Version: "RTL195AFW_COMPILER"\n\n");    
+    DBG_8195A("=========================================================\n");
+    */
+}
+
+#ifdef CONFIG_APP_DEMO
+#include "device.h"
+#include "gpio_api.h"   // mbed
+
+_WEAK void main(void)
+{
+    gpio_t gpio_led;
+    
+#ifndef CONFIG_WITHOUT_MONITOR
+    ReRegisterPlatformLogUart();
+#endif
+
+    // Init LED control pin
+    gpio_init(&gpio_led, PC_5);
+    gpio_dir(&gpio_led, PIN_OUTPUT);    // Direction: Output
+    gpio_mode(&gpio_led, PullNone);     // No pull
+    while(1){
+        gpio_write(&gpio_led, !gpio_read(&gpio_led));
+        RtlMsleepOS(1000);
+    }
+}
+#else
+//default main
+_WEAK void main(void)
+{
+    // Init SDIO
+#if defined(CONFIG_SDIO_DEVICE_EN) && defined(CONFIG_SDIO_DEVICE_NORMAL)
+    HalSdioInit();
+#endif
+
+#ifndef CONFIG_WITHOUT_MONITOR
+    ReRegisterPlatformLogUart();
+#endif
+                
+#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK)
+	wlan_network();
+#else
+
+#if defined (CONFIG_USB_EN) && defined(CONFIG_USB_HOST_ONLY)
+	_usb_init();
+#endif
+
+#endif  // end of else of "#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK)"
+
+	//3 4)Enable Schedule
+#if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED
+    #ifdef PLATFORM_FREERTOS
+		vTaskStartScheduler();
+    #endif
+#else
+		RtlConsolTaskRom(NULL);
+#endif
+
+}
+#endif // end of #if CONFIG_APP_DEMO
+
+// The Main App entry point
+void _AppStart(void)
+{
+#ifdef CONFIG_MBED_ENABLED
+    InterruptForOSInit((VOID*)SVC_Handler,
+                       (VOID*)PendSV_Handler,
+                       (VOID*)SysTick_Handler);
+    __asm (
+        "ldr   r0, =SystemInit\n"
+        "blx   r0\n"
+        "ldr   r0, =_start\n"
+        "bx    r0\n"
+    );
+
+    for(;;);
+#else
+    // It's Not Mbed BSP
+#ifdef CONFIG_KERNEL
+#endif
+
+    // Disable debug info log of spiflash
+    DBG_INFO_MSG_OFF(_DBG_SPI_FLASH_);
+        
+#ifdef CONFIG_APP_DEMO
+#ifdef PLATFORM_FREERTOS
+    xTaskCreate( (TaskFunction_t)main, "MAIN_APP__TASK", (MAIN_APP_DEFAULT_STACK_SIZE/4), (void *)NULL, MAIN_APP_DEFAULT_PRIORITY, NULL);
+    vTaskStartScheduler();
+#endif
+#else
+	// force SP align to 8 byte not 4 byte (initial SP is 4 byte align)
+	__asm( 
+		  "mov r0, sp\n"
+		  "bic r0, r0, #7\n" 
+		  "mov sp, r0\n"
+	);
+	
+    main();
+#endif // end of #if CONFIG_APP_DEMO
+    
+#endif  // end of else of "#ifdef CONFIG_MBED_ENABLED"
+}

component/soc/realtek/8195a/cmsis/device/cmsis.h

@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "rtl8195a.h"
+#include "cmsis_nvic.h"
+
+#endif

component/soc/realtek/8195a/cmsis/device/cmsis_nvic.c

@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Vectors positioned at start of RAM
+#define NVIC_ROM_VECTOR_ADDRESS   (0x00000000)  // Initial vector position at start of ROM
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t *)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}

component/soc/realtek/8195a/cmsis/device/cmsis_nvic.h

@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 64 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ...
+// Total: 128 vectors = 512 bytes (0x200) to be reserved in RAM
+#define NVIC_NUM_VECTORS      128
+#define NVIC_USER_IRQ_OFFSET  64
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

component/soc/realtek/8195a/cmsis/device/diag.h

@@ -0,0 +1,808 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _DIAG_H_
+#define _DIAG_H_
+
+#include "platform_autoconf.h"
+#include "basic_types.h"
+
+#include <stddef.h> /* for size_t */
+
+extern u32 ConfigDebugErr;
+extern u32 ConfigDebugInfo;
+extern u32 ConfigDebugWarn;
+
+extern u32 CfgSysDebugErr;
+extern u32 CfgSysDebugInfo;
+extern u32 CfgSysDebugWarn;
+
+#define DBG_ERR_MSG_ON(x)       (ConfigDebugErr |= (x))
+#define DBG_WARN_MSG_ON(x)      (ConfigDebugWarn |= (x))
+#define DBG_INFO_MSG_ON(x)      (ConfigDebugInfo |= (x))
+
+#define DBG_ERR_MSG_OFF(x)      (ConfigDebugErr &= ~(x))
+#define DBG_WARN_MSG_OFF(x)     (ConfigDebugWarn &= ~(x))
+#define DBG_INFO_MSG_OFF(x)     (ConfigDebugInfo &= ~(x))
+
+// Define debug group
+#define	_DBG_BOOT_          	0x00000001
+#define	_DBG_GDMA_          	0x00000002
+#define	_DBG_GPIO_			0x00000004
+#define	_DBG_TIMER_         	0x00000008
+#define	_DBG_I2C_           	0x00000010
+#define	_DBG_I2S_           	0x00000020
+#define	_DBG_MII_           	0x00000040
+#define	_DBG_NFC_           	0x00000080
+#define	_DBG_PCM_           	0x00000100
+#define	_DBG_PWM_           	0x00000200
+#define	_DBG_SDIO_          	0x00000400
+#define	_DBG_SSI_           	0x00000800
+#define	_DBG_SPI_FLASH_     0x00001000
+#define	_DBG_SDR_           	0x00002000
+#define	_DBG_UART_          	0x00004000
+#define	_DBG_USB_OTG_       0x00008000
+#define	_DBG_USB_CORE_     0x00010000
+#define	_DBG_CRYPTO_        	0x00020000
+#define	_DBG_ADC_           	0x00040000
+#define 	_DBG_DAC_           	0x00080000
+
+#define 	_DBG_MISC_          	0x40000000
+#define	_DBG_FAULT_        	0x80000000
+
+typedef enum _SYSTEM_DBG_DEFINE_ {
+    _SYSDBG_MISC_       = 1<<0,
+    _SYSDBG_MAILBOX_    = 1<<1,
+    _SYSDBG_TIMER_      = 1<<2
+
+} SYSTEM_DBG;
+
+extern
+_LONG_CALL_ u32
+DiagPrintf(
+    IN  const char *fmt, ...
+);
+
+u32
+DiagSPrintf(
+    IN  u8 *buf,
+    IN  const char *fmt, ...
+);
+
+int
+prvDiagPrintf(
+    IN  const char *fmt, ...
+);
+
+int
+prvDiagSPrintf(
+    IN char *buf,
+    IN  const char *fmt, ...
+);
+
+
+#define _DbgDump  DiagPrintf
+
+#define DRIVER_PREFIX	"RTL8195A[Driver]: "
+#define HAL_PREFIX      "RTL8195A[HAL]: "
+#define DMA_PREFIX      "RTL8195A[DMA]: "
+#define SDIO_PREFIX     "RTL8195A[SDIO]"
+#define MBOX_PREFIX		"[OS-MBOX]"
+#define TIMER_PREFIX	"[OS-TMR]"
+
+#define BOOT_ERR_PREFIX         "[BOOT Err]"
+#define BOOT_WARN_PREFIX        "[BOOT Wrn]"
+#define BOOT_INFO_PREFIX        "[BOOT Inf]"
+
+#define GDMA_ERR_PREFIX         "[GDMA Err]"
+#define GDMA_WARN_PREFIX        "[GDMA Wrn]"
+#define GDMA_INFO_PREFIX        "[GDMA Inf]"
+
+#define GPIO_ERR_PREFIX         "[GPIO Err]"
+#define GPIO_WARN_PREFIX        "[GPIO Wrn]"
+#define GPIO_INFO_PREFIX        "[GPIO Inf]"
+
+#define TIMER_ERR_PREFIX        "[TIMR Err]"
+#define TIMER_WARN_PREFIX       "[TIMR Wrn]"
+#define TIMER_INFO_PREFIX       "[TIMR Inf]"
+
+#define I2C_ERR_PREFIX          "[I2C  Err]"
+#define I2C_WARN_PREFIX         "[I2C  Wrn]"
+#define I2C_INFO_PREFIX         "[I2C  Inf]"
+
+#define I2S_ERR_PREFIX          "[I2S  Err]"
+#define I2S_WARN_PREFIX         "[I2S  Wrn]"
+#define I2S_INFO_PREFIX         "[I2S  Inf]"
+
+#define MII_ERR_PREFIX          "[MII  Err]"
+#define MII_WARN_PREFIX         "[MII  Wrn]"
+#define MII_INFO_PREFIX         "[MII  Inf]"
+
+#define NFC_ERR_PREFIX          "[NFC  Err]"
+#define NFC_WARN_PREFIX         "[NFC  Wrn]"
+#define NFC_INFO_PREFIX         "[NFC  Inf]"
+
+#define PCM_ERR_PREFIX          "[PCM  Err]"
+#define PCM_WARN_PREFIX         "[PCM  Wrn]"
+#define PCM_INFO_PREFIX         "[PCM  Inf]"
+
+#define PWM_ERR_PREFIX          "[PWM  Err]"
+#define PWM_WARN_PREFIX         "[PWM  Wrn]"
+#define PWM_INFO_PREFIX         "[PWM  Inf]"
+
+#define SSI_ERR_PREFIX          "[SSI  Err]"
+#define SSI_WARN_PREFIX         "[SSI  Wrn]"
+#define SSI_INFO_PREFIX         "[SSI  Inf]"
+
+#define SDIO_ERR_PREFIX         "[SDIO Err]"
+#define SDIO_WARN_PREFIX        "[SDIO Wrn]"
+#define SDIO_INFO_PREFIX        "[SDIO Inf]"
+
+#define SPIF_ERR_PREFIX         "[SPIF Err]"
+#define SPIF_WARN_PREFIX        "[SPIF Wrn]"
+#define SPIF_INFO_PREFIX        "[SPIF Inf]"
+
+#define SDR_ERR_PREFIX          "[SDR  Err]"
+#define SDR_WARN_PREFIX         "[SDR  Wrn]"
+#define SDR_INFO_PREFIX         "[SDR  Inf]"
+
+#define UART_ERR_PREFIX         "[UART Err]"
+#define UART_WARN_PREFIX        "[UART Wrn]"
+#define UART_INFO_PREFIX        "[UART Inf]"
+
+#define USB_ERR_PREFIX          "[USB  Err]"
+#define USB_WARN_PREFIX         "[USB  Wrn]"
+#define USB_INFO_PREFIX         "[USB  Inf]"
+
+#define IPSEC_ERR_PREFIX        "[CRYP Err]"
+#define IPSEC_WARN_PREFIX       "[CRYP Wrn]"
+#define IPSEC_INFO_PREFIX       "[CRYP Inf]"
+
+#define ADC_ERR_PREFIX          "[ADC  Err]"
+#define ADC_WARN_PREFIX         "[ADC  Wrn]"
+#define ADC_INFO_PREFIX         "[ADC  Inf]"
+
+#define DAC_ERR_PREFIX          "[DAC  Err]"
+#define DAC_WARN_PREFIX         "[DAC  Wrn]"
+#define DAC_INFO_PREFIX         "[DAC  Inf]"
+
+#define MISC_ERR_PREFIX         "[MISC Err]"
+#define MISC_WARN_PREFIX        "[MISC Wrn]"
+#define MISC_INFO_PREFIX        "[MISC Inf]"
+
+#define OTG_ERR_PREFIX         "[OTG Err]"
+#define OTG_WARN_PREFIX        "[OTG Wrn]"
+#define OTG_INFO_PREFIX        "[OTG Inf]"
+
+#define OTG_PREFIX      "RTL8195A[OTG]: "
+#define OTG_PREFIX_LVL  "RTL8195A[OTG_LVL_%2x]: "
+
+//#ifdef
+#define CONFIG_DEBUG_ERROR      1
+#define CONFIG_DEBUG_WARN       1
+#define CONFIG_DEBUG_INFO       1
+
+#ifndef likely
+#define likely(x)               (x)
+#define unlikely(x)             (x)
+#endif
+
+#ifdef CONFIG_DEBUG_LOG
+
+#if CONFIG_DEBUG_ERROR      // if Build-In Debug Error Message
+
+#define DBG_BOOT_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_BOOT_)) \
+        _DbgDump("\r"BOOT_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GDMA_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_GDMA_)) \
+        _DbgDump("\r"GDMA_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GPIO_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_GPIO_)) \
+        _DbgDump("\r"GPIO_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_TIMER_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_TIMER_)) \
+        _DbgDump("\r"TIMER_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2C_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_I2C_)) \
+        _DbgDump("\r"I2C_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2S_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_I2S_)) \
+        _DbgDump("\r"I2S_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MII_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_MII_)) \
+        _DbgDump("\r"MII_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_NFC_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_NFC_)) \
+        _DbgDump("\r"NFC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PCM_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_PCM_)) \
+        _DbgDump("\r"PCM_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PWM_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_PWM_)) \
+        _DbgDump("\r"PWM_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SSI_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_SSI_)) \
+        _DbgDump("\r"SSI_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDIO_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_SDIO_)) \
+        _DbgDump("\r"SDIO_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SPIF_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_SPI_FLASH_)) \
+        _DbgDump("\r"SPIF_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDR_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_SDR_)) \
+        _DbgDump("\r"SDR_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_UART_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_UART_)) \
+        _DbgDump("\r"UART_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBOTG_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_USB_OTG_)) \
+        _DbgDump("\r" __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBCOR_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_USB_CORE_)) \
+        _DbgDump("\r"USB_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_CRYPTO_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_CRYPTO_)) \
+        _DbgDump("\r"IPSEC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_ADC_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_ADC_)) \
+        _DbgDump("\r"ADC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_DAC_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_DAC_)) \
+        _DbgDump("\r"DAC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_MBOX_ERR(...)     do {\
+    if (likely(CfgSysDebugErr & _SYSDBG_MAILBOX_)) \
+        _DbgDump("\r"MBOX_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_TIMER_ERR(...)     do {\
+    if (likely(CfgSysDebugErr & _SYSDBG_TIMER_)) \
+        _DbgDump("\r"TIMER_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A_OTG(...)  do{\
+                if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
+                    _DbgDump("\r"OTG_PREFIX __VA_ARGS__);\
+            }while(0)
+    
+            
+#define DBG_8195A_OTG_LVL(LVL,...)  do{\
+                    if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)){ \
+                        _DbgDump("\r"OTG_PREFIX_LVL,LVL);\
+                        _DbgDump(__VA_ARGS__);\
+                    }\
+                }while(0)
+
+#else   // else of "#if CONFIG_DEBUG_ERROR"
+
+#define DBG_BOOT_ERR(...)
+#define DBG_GDMA_ERR(...)
+#define DBG_GPIO_ERR(...)
+#define DBG_TIMER_ERR(...)
+#define DBG_I2C_ERR(...)
+#define DBG_I2S_ERR(...)
+#define DBG_MII_ERR(...)
+#define DBG_NFC_ERR(...)
+#define DBG_PCM_ERR(...)
+#define DBG_PWM_ERR(...)
+#define DBG_SSI_ERR(...)
+#define DBG_SDIO_ERR(...)
+#define DBG_SPIF_ERR(...)
+#define DBG_SDR_ERR(...)
+#define DBG_UART_ERR(...)
+#define DBG_USBOTG_ERR(...)
+#define DBG_USBCOR_ERR(...)
+#define DBG_CRYPTO_ERR(...)
+#define DBG_ADC_ERR(...)
+#define DBG_DAC_ERR(...)
+
+#define MSG_MBOX_ERR(...)
+#define MSG_TIMER_ERR(...)
+#define DBG_8195A_OTG(...)
+#define DBG_8195A_OTG_LVL(LVL,...)
+
+#endif  // end of else of "#if CONFIG_DEBUG_ERROR"
+
+// =============================================================
+
+#if CONFIG_DEBUG_WARN     // if Build-In Debug Warring Message
+
+#define DBG_BOOT_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn& _DBG_BOOT_)) \
+        _DbgDump("\r"BOOT_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GDMA_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_GDMA_)) \
+        _DbgDump("\r"GDMA_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GPIO_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_GPIO_)) \
+        _DbgDump("\r"GPIO_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_TIMER_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_TIMER_)) \
+        _DbgDump("\r"TIMER_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2C_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_I2C_)) \
+        _DbgDump("\r"I2C_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2S_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_I2S_)) \
+        _DbgDump("\r"I2S_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MII_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_MII_)) \
+        _DbgDump("\r"MII_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_NFC_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_NFC_)) \
+        _DbgDump("\r"NFC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PCM_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_PCM_)) \
+        _DbgDump("\r"PCM_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PWM_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_PWM_)) \
+        _DbgDump("\r"PWM_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SSI_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_SSI_)) \
+        _DbgDump("\r"SSI_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDIO_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_SDIO_)) \
+        _DbgDump("\r"SDIO_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SPIF_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_SPI_FLASH_)) \
+        _DbgDump("\r"SPIF_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDR_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_SDR_)) \
+        _DbgDump("\r"SDR_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_UART_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_UART_)) \
+        _DbgDump("\r"UART_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBOTG_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \
+        _DbgDump("\r" __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBCOR_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_USB_CORE_)) \
+        _DbgDump("\r"USB_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_CRYPTO_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_CRYPTO_)) \
+        _DbgDump("\r"IPSEC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_ADC_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_ADC_)) \
+        _DbgDump("\r"ADC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_DAC_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_DAC_)) \
+        _DbgDump("\r"DAC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_MBOX_WARN(...)     do {\
+    if (unlikely(CfgSysDebugWarn& _SYSDBG_MAILBOX_)) \
+        _DbgDump("\r"MBOX_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_TIMER_WARN(...)     do {\
+    if (unlikely(CfgSysDebugWarn & _SYSDBG_TIMER_)) \
+        _DbgDump("\r"TIMER_PREFIX __VA_ARGS__);\
+}while(0)
+
+#else   // else of "#if CONFIG_DEBUG_WARN"
+
+#define DBG_BOOT_WARN(...)
+#define DBG_GDMA_WARN(...)
+#define DBG_GPIO_WARN(...)
+#define DBG_TIMER_WARN(...)
+#define DBG_I2C_WARN(...)
+#define DBG_I2S_WARN(...)
+#define DBG_MII_WARN(...)
+#define DBG_NFC_WARN(...)
+#define DBG_PCM_WARN(...)
+#define DBG_PWM_WARN(...)
+#define DBG_SSI_WARN(...)
+#define DBG_SDIO_WARN(...)
+#define DBG_SPIF_WARN(...)
+#define DBG_SDR_WARN(...)
+#define DBG_UART_WARN(...)
+#define DBG_USBOTG_WARN(...)
+#define DBG_USBCOR_WARN(...)
+#define DBG_CRYPTO_WARN(...)
+#define DBG_ADC_WARN(...)
+#define DBG_DAC_WARN(...)
+
+#define MSG_MBOX_WARN(...)
+#define MSG_TIMER_WARN(...)
+
+#endif  // end of else of "#if CONFIG_DEBUG_WARN"
+
+// =============================================================
+
+#if CONFIG_DEBUG_INFO     // if Build-In Debug Information Message
+
+#define DBG_BOOT_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_BOOT_)) \
+        _DbgDump("\r"BOOT_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GDMA_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_GDMA_)) \
+        _DbgDump("\r"GDMA_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GPIO_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_GPIO_)) \
+        _DbgDump("\r"GPIO_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_TIMER_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_TIMER_)) \
+        _DbgDump("\r"TIMER_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2C_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_I2C_)) \
+        _DbgDump("\r"I2C_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2S_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_I2S_)) \
+        _DbgDump("\r"I2S_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MII_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_MII_)) \
+        _DbgDump("\r"MII_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_NFC_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_NFC_)) \
+        _DbgDump("\r"NFC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PCM_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_PCM_)) \
+        _DbgDump("\r"PCM_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PWM_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_PWM_)) \
+        _DbgDump("\r"PWM_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SSI_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_SSI_)) \
+        _DbgDump("\r"SSI_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDIO_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_SDIO_)) \
+        _DbgDump("\r"SDIO_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SPIF_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_SPI_FLASH_)) \
+        _DbgDump("\r"SPIF_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDR_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_SDR_)) \
+        _DbgDump("\r"SDR_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_UART_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_UART_)) \
+        _DbgDump("\r"UART_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBOTG_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
+        _DbgDump("\r" __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBCOR_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_USB_CORE_)) \
+        _DbgDump("\r"USB_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_CRYPTO_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_CRYPTO_)) \
+        _DbgDump("\r"IPSEC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_ADC_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_ADC_)) \
+        _DbgDump("\r"ADC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_DAC_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_DAC_)) \
+        _DbgDump("\r"DAC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_MBOX_INFO(...)     do {\
+    if (unlikely(CfgSysDebugInfo & _SYSDBG_MAILBOX_)) \
+        _DbgDump("\r"MBOX_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_TIMER_INFO(...)     do {\
+    if (unlikely(CfgSysDebugInfo & _SYSDBG_TIMER_)) \
+        _DbgDump("\r"TIMER_PREFIX __VA_ARGS__);\
+}while(0)
+
+#else   // else of "#if CONFIG_DEBUG_INFO"
+
+#define DBG_BOOT_INFO(...)
+#define DBG_GDMA_INFO(...)
+#define DBG_GPIO_INFO(...)
+#define DBG_TIMER_INFO(...)
+#define DBG_I2C_INFO(...)
+#define DBG_I2S_INFO(...)
+#define DBG_MII_INFO(...)
+#define DBG_NFC_INFO(...)
+#define DBG_PCM_INFO(...)
+#define DBG_PWM_INFO(...)
+#define DBG_SSI_INFO(...)
+#define DBG_SDIO_INFO(...)
+#define DBG_SPIF_INFO(...)
+#define DBG_SDR_INFO(...)
+#define DBG_UART_INFO(...)
+#define DBG_USBOTG_INFO(...)
+#define DBG_USBCOR_INFO(...)
+#define DBG_CRYPTO_INFO(...)
+#define DBG_ADC_INFO(...)
+#define DBG_DAC_INFO(...)
+
+#define MSG_MBOX_INFO(...)
+#define MSG_TIMER_INFO(...)
+
+#endif  // end of else of "#if CONFIG_DEBUG_INFO"
+
+#define DBG_8195A_DRIVER(...)     do {\
+    if (unlikely(ConfigDebugErr & (_DBG_I2S_|_DBG_PCM_|_DBG_TIMER_))) \
+        _DbgDump("\r"DRIVER_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A_HAL(...)     do {\
+    if (unlikely(ConfigDebugErr & (_DBG_SDR_|_DBG_MISC_))) \
+        _DbgDump("\r"HAL_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A_DMA(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_GDMA_)) \
+        _DbgDump("\r"DMA_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A_SDIO(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_SDIO_)) \
+        _DbgDump("\r"SDIO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_MISC_)) \
+        _DbgDump("\r" __VA_ARGS__);\
+}while(0)
+
+#define MONITOR_LOG(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_MISC_)) \
+        _DbgDump( __VA_ARGS__);\
+}while(0)
+
+#define DBG_ERROR_LOG(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_FAULT_)) \
+        _DbgDump( __VA_ARGS__);\
+}while(0)
+
+#ifdef __GNUC__
+#define DBG_ASSERT(x)     do {\
+        if (unlikely(!(x))) \
+            _DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\
+    }while(0)
+#endif
+
+#ifdef __ICCARM__
+#define DBG_ASSERT(x)     do {\
+        if (unlikely(!(x))) \
+            _DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\
+    }while(0)
+#endif
+
+#else   // else of "#if CONFIG_DEBUG_LOG"
+#define DBG_8195A_DRIVER(...)
+
+#define DBG_8195A_HAL(...)
+
+#define DBG_8195A(...)
+
+#define DBG_8195A_DMA(...)
+
+#define MONITOR_LOG(...)
+
+#define DBG_ERROR_LOG(...)
+
+#define DBG_8195A_SDIO(...)
+
+#define DBG_BOOT_ERR(...)
+#define DBG_GDMA_ERR(...)
+#define DBG_GPIO_ERR(...)
+#define DBG_TIMER_ERR(...)
+#define DBG_I2C_ERR(...)
+#define DBG_I2S_ERR(...)
+#define DBG_MII_ERR(...)
+#define DBG_NFC_ERR(...)
+#define DBG_PCM_ERR(...)
+#define DBG_PWM_ERR(...)
+#define DBG_SSI_ERR(...)
+#define DBG_SDIO_ERR(...)
+#define DBG_SPIF_ERR(...)
+#define DBG_SDR_ERR(...)
+#define DBG_UART_ERR(...)
+#define DBG_USBOTG_ERR(...)
+#define DBG_USBCOR_ERR(...)
+#define DBG_CRYPTO_ERR(...)
+#define DBG_ADC_ERR(...)
+#define DBG_DAC_ERR(...)
+#define MSG_MBOX_ERR(...)
+#define MSG_TIMER_ERR(...)
+
+#define DBG_BOOT_WARN(...)
+#define DBG_GDMA_WARN(...)
+#define DBG_GPIO_WARN(...)
+#define DBG_TIMER_WARN(...)
+#define DBG_I2C_WARN(...)
+#define DBG_I2S_WARN(...)
+#define DBG_MII_WARN(...)
+#define DBG_NFC_WARN(...)
+#define DBG_PCM_WARN(...)
+#define DBG_PWM_WARN(...)
+#define DBG_SSI_WARN(...)
+#define DBG_SDIO_WARN(...)
+#define DBG_SPIF_WARN(...)
+#define DBG_SDR_WARN(...)
+#define DBG_UART_WARN(...)
+#define DBG_USBOTG_WARN(...)
+#define DBG_USBCOR_WARN(...)
+#define DBG_CRYPTO_WARN(...)
+#define DBG_ADC_WARN(...)
+#define DBG_DAC_WARN(...)
+#define MSG_MBOX_WARN(...)
+#define MSG_TIMER_WARN(...)
+
+#define DBG_BOOT_INFO(...)
+#define DBG_GDMA_INFO(...)
+#define DBG_GPIO_INFO(...)
+#define DBG_TIMER_INFO(...)
+#define DBG_I2C_INFO(...)
+#define DBG_I2S_INFO(...)
+#define DBG_MII_INFO(...)
+#define DBG_NFC_INFO(...)
+#define DBG_PCM_INFO(...)
+#define DBG_PWM_INFO(...)
+#define DBG_SSI_INFO(...)
+#define DBG_SDIO_INFO(...)
+#define DBG_SPIF_INFO(...)
+#define DBG_SDR_INFO(...)
+#define DBG_UART_INFO(...)
+#define DBG_USBOTG_INFO(...)
+#define DBG_USBCOR_INFO(...)
+#define DBG_CRYPTO_INFO(...)
+#define DBG_ADC_INFO(...)
+#define DBG_DAC_INFO(...)
+
+#define MSG_MBOX_INFO(...)
+#define MSG_TIMER_INFO(...)
+
+#define DBG_ASSERT(x)
+
+#endif
+
+#define ANSI_COLOR_GREEN   "\x1b[32m"
+#define ANSI_COLOR_CYAN    "\x1b[36m"
+#define ANSI_COLOR_YELLOW  "\x1b[33m"
+#define ANSI_COLOR_MAGENTA "\x1b[35m"
+#define ANSI_COLOR_RED     "\x1b[31m"
+#define ANSI_COLOR_BLUE    "\x1b[34m"
+#define ANSI_COLOR_RESET   "\x1b[0m"
+
+#define IDENT_ONE_SPACE    " "
+#define IDENT_TWO_SPACE    "  "
+#define IDENT_FOUR_SPACE   "    "
+#define IDENT_SIX_SPACE    "      "
+#define IDENT_EIGHT_SPACE  "        "
+
+#ifdef CONFIG_DEBUG_LOG
+typedef enum _DBG_CFG_TYPE_ {
+	DBG_CFG_ERR=0,
+	DBG_CFG_WARN=1,
+	DBG_CFG_INFO=2
+} DBG_CFG_TYPE;
+
+typedef struct _DBG_CFG_CMD_ {
+	u8 cmd_name[16];
+	u32	cmd_type;
+} DBG_CFG_CMD, *PDBG_CFG_CMD;
+
+#endif
+
+typedef enum _CONSOLE_OP_STAGE_ {
+    ROM_STAGE = 0,
+    RAM_STAGE = 1
+}CONSOLE_OP_STAGE;
+
+#endif //_DIAG_H_

component/soc/realtek/8195a/cmsis/device/rand.h

@@ -0,0 +1,15 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+u32
+Rand (
+ VOID
+);
+
+

component/soc/realtek/8195a/cmsis/device/rtl_stdlib.h

@@ -0,0 +1,41 @@
+/*
+ *  Routines for standard lib access 
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL_STDLIB_H_
+#define _RTL_STDLIB_H_
+
+#include <basic_types.h>
+#include <strproc.h>
+#include <diag.h>
+
+//
+// string operation
+//
+#define strlen(str)						prvStrLen((const u8*)str)
+#define strcmp(str1, str2)				prvStrCmp((const u8*)str1, (const u8*)str2)
+#define sscanf(src, format...)				//TODO
+#define strtok(str, delim)				prvStrTok(str, delim)
+#define strcpy(dst, src)					prvStrCpy((u8 *)dst, (const u8*)src)
+#define atoi(str)						prvAtoi(str)
+#define strstr(str1, str2)					prvStrStr(str1, str2)							
+
+//
+// standard i/o
+//
+#define snprintf							DiagSnPrintf
+#define sprintf							prvDiagSPrintf
+#define printf 							prvDiagPrintf
+
+//
+// memory management
+//
+#define malloc 							pvPortMalloc
+#define free							vPortFree
+
+#endif //_RTL_STDLIB_H_

component/soc/realtek/8195a/cmsis/device/rtl_utility.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __RTL_UTILITY_H_
+#define __RTL_UTILITY_H_
+
+VOID RtlMemcpy(VOID* dec, VOID* sour, u32 sz);
+u32 RtlMemcmp(VOID *dst, VOID *src, u32 sz);
+VOID RtlMemset(VOID *pbuf, u32 c, u32 sz);
+
+s8 *
+RtlStrncpy(
+    IN  s8 *dest, 
+    IN  const s8 *src, 
+    IN  SIZE_T count
+);
+
+s8 *
+RtlStrcpy(
+    IN  s8 *dest, 
+    IN  const s8 *src
+);
+
+
+SIZE_T
+RtlStrlen(
+    IN  const s8 *s
+);
+
+
+SIZE_T
+RtlStrnlen(
+    IN  const s8 *s, 
+    IN  SIZE_T count
+);
+
+
+int 
+RtlStrcmp(
+    IN  const s8 *cs, 
+    IN  const s8 *ct
+
+);
+
+int
+RtlStrncmp(
+    IN  const s8 *cs, 
+    IN  const s8 *ct, 
+    IN  SIZE_T count
+);
+
+#endif
+
+

component/soc/realtek/8195a/cmsis/device/strproc.h

@@ -0,0 +1,104 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _STRPROC_H_
+#define _STRPROC_H_
+
+#include <stddef.h> /* for size_t */
+#include "va_list.h"
+
+#ifndef isprint
+#define in_range(c, lo, up)  ((u8)c >= lo && (u8)c <= up)
+#define isprint(c)           in_range(c, 0x20, 0x7f)
+#define isdigit(c)           in_range(c, '0', '9')
+#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
+#define islower(c)           in_range(c, 'a', 'z')
+#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v' || c == ',')
+#endif  
+
+
+extern _LONG_CALL_ char *_strncpy(char *dest, const char *src, size_t count);
+extern _LONG_CALL_ char *_strcpy(char *dest, const char *src);
+extern _LONG_CALL_ size_t _strlen(const char *s);
+extern _LONG_CALL_ size_t _strnlen(const char *s, size_t count);
+extern _LONG_CALL_ int _strcmp(const char *cs, const char *ct);
+extern _LONG_CALL_ int _strncmp(const char *cs, const char *ct, size_t count);
+extern _LONG_CALL_ int _sscanf(const char *buf, const char *fmt, ...);
+extern _LONG_CALL_ char *_strsep(char **s, const char *ct);
+extern _LONG_CALL_ char *skip_spaces(const char *str);
+extern _LONG_CALL_ int skip_atoi(const char **s);
+extern _LONG_CALL_ int _vsscanf(const char *buf, const char *fmt, va_list args);
+extern _LONG_CALL_ unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base);
+extern _LONG_CALL_ long simple_strtol(const char *cp, char **endp, unsigned int base);
+extern _LONG_CALL_ long long simple_strtoll(const char *cp, char **endp, unsigned int base);
+extern _LONG_CALL_ unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base);
+extern _LONG_CALL_ const char *_parse_integer_fixup_radix(const char *s, unsigned int *base);
+extern _LONG_CALL_ unsigned int _parse_integer(const char *s, unsigned int base, unsigned long long *p);
+extern _LONG_CALL_ u64 div_u64(u64 dividend, u32 divisor);
+extern _LONG_CALL_ s64 div_s64(s64 dividend, s32 divisor);
+extern _LONG_CALL_ u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder);
+extern _LONG_CALL_ s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder);
+extern _LONG_CALL_ char *_strpbrk(const char *cs, const char *ct);
+extern _LONG_CALL_ char *_strchr(const char *s, int c);
+
+
+extern _LONG_CALL_ VOID
+prvStrCpy(
+    IN  u8  *pDES,
+    IN  const u8  *pSRC
+);
+
+extern _LONG_CALL_ u32
+prvStrLen(
+    IN  const   u8  *pSRC
+);
+
+extern _LONG_CALL_  u8
+prvStrCmp(
+    IN  const   u8  *string1,
+    IN  const   u8  *string2
+);
+
+extern _LONG_CALL_ u8*
+StrUpr(
+    IN  u8  *string
+);
+
+extern _LONG_CALL_ int prvAtoi(
+	IN const char * s
+);
+
+extern _LONG_CALL_ const char * prvStrStr(
+	IN const char * str1, 
+	IN const char * str2
+);
+
+
+/*
+ * Fast implementation of tolower() for internal usage. Do not use in your
+ * code.
+ */
+static inline char _tolower(const char c)
+{
+    return c | 0x20;
+}
+
+/* Fast check for octal digit */
+static inline int isodigit(const char c)
+{
+    return c >= '0' && c <= '7';
+}
+#ifndef strtoul
+#define strtoul(str, endp, base)       simple_strtoul(str, endp, base)
+#endif
+#ifndef strtol
+#define strtol(str, endp, base)        simple_strtol(str, endp, base)
+#endif
+
+#endif

component/soc/realtek/8195a/cmsis/device/system_8195a.c

@@ -0,0 +1,139 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM3 Device Series
+ * @version  V1.08
+ * @date     23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#include "basic_types.h"
+#include "rtl8195a.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            ( 5000000UL)    /* Oscillator frequency             */
+
+//#define __SYSTEM_CLOCK    (5*__XTAL)
+#define __SYSTEM_CLOCK    (200000000UL/6*5)
+
+extern unsigned int rand_x;
+extern u32 HalGetCpuClk(VOID);
+
+#if CONFIG_CHIP_A_CUT
+const u32 SysCpkClkTbl[]= {
+    200000000,
+    100000000,
+    50000000,
+    25000000,
+    12500000,
+    4000000
+};
+#endif
+
+u32 Rand2(void)
+{
+    static unsigned int y = 362436;
+    static unsigned int z = 521288629;
+    static unsigned int c = 7654321;
+
+    unsigned long long t, a= 698769069;
+
+    rand_x = 69069 * rand_x + 12345;
+    y ^= (y << 13); y ^= (y >> 17); y ^= (y << 5);
+    t = a * z + c; c = (t >> 32); z = t;
+
+    return rand_x + y + z;
+}
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+u32
+SystemGetCpuClk(void)
+{
+#if CONFIG_CHIP_A_CUT
+
+    u32  CpuType = 0, CpuClk = 0, FreqDown = 0;
+
+    CpuType = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4);
+    FreqDown = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & BIT17;
+
+    CpuClk = SysCpkClkTbl[CpuType];
+
+    if ( !FreqDown ) {
+        if ( CpuClk > 4000000 ){
+            CpuClk = (CpuClk*5/6);
+        }
+    }
+
+    return CpuClk;
+#else
+    return HalGetCpuClk();
+#endif
+}
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+//  SystemCoreClock = __SYSTEM_CLOCK;
+  
+    SystemCoreClock = SystemGetCpuClk();
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+    // TODO: Hardware initial
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  //SystemCoreClock = __SYSTEM_CLOCK;
+  //SystemCoreClock = HalGetCpuClk();
+    SystemCoreClockUpdate();
+}

component/soc/realtek/8195a/cmsis/device/system_8195a.h

@@ -0,0 +1,77 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.h
+ * @brief    CMSIS Device System Header File for
+ *           ARMCM3 Device Series
+ * @version  V1.08
+ * @date     23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef _SYSTEM_8195A_H
+#define _SYSTEM_8195A_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+extern u32 SystemGetCpuClk(void);
+extern u32 Rand2(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_8195A_H */

component/soc/realtek/8195a/cmsis/device/va_list.h

@@ -0,0 +1,37 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _VA_LIST_H_
+#define _VA_LIST_H_
+
+#include "platform_autoconf.h"
+#include "basic_types.h"
+
+#ifndef va_arg //this part is adapted from linux (Linux/include/acpi/platform/acenv.h)
+
+typedef s32 acpi_native_int;//this definition is in (Linux/include/acpi/actypes.h)
+
+#ifndef _VALIST
+#define _VALIST
+    typedef char *va_list;
+#endif                          /* _VALIST */
+
+/* Storage alignment properties */
+#define  _AUPBND                (sizeof (acpi_native_int) - 1)
+#define  _ADNBND                (sizeof (acpi_native_int) - 1)
+
+/* Variable argument list macro definitions */
+#define _bnd(X, bnd)            (((sizeof (X)) + (bnd)) & (~(bnd)))
+#define va_arg(ap, T)           (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND))))
+#define va_end(ap)              (ap = (va_list) NULL)
+#define va_start(ap, A)         (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND))))
+
+#endif                          /* va_arg */
+
+#endif //_VA_LIST_H_

component/soc/realtek/8195a/fwlib/hal_adc.h

@@ -0,0 +1,317 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_ADC_H_
+#define _HAL_ADC_H_
+
+#include "rtl8195a.h"
+#include "rtl8195a_adc.h"
+#include "hal_gdma.h"
+
+//================ ADC Configuration  =========================
+#define ADC_INTR_OP_TYPE    1
+#define ADC_DMA_OP_TYPE     1
+
+// ADC SAL management macros
+#define SAL_ADC_USER_CB_NUM     (sizeof(SAL_ADC_USER_CB) / sizeof(PSAL_ADC_USERCB_ADPT))
+
+// ADC used module. 
+// Please set the ADC module flag to 1 to enable the related 
+#define ADC0_USED                   1
+#define ADC1_USED                   1
+#define ADC2_USED                   1
+#define ADC3_USED                   1
+
+
+//================ Debug MSG Definition =======================
+#define ADC_PREFIX      "RTL8195A[adc]: "
+#define ADC_PREFIX_LVL  "    [ADC_DBG]: "
+
+typedef enum _ADC_DBG_LVL_ {
+    HAL_ADC_LVL         =   0x01,
+    SAL_ADC_LVL         =   0x02,
+    VERI_ADC_LVL        =   0x04,
+}ADC_DBG_LVL,*PADC_DBG_LVL;
+
+#ifdef CONFIG_DEBUG_LOG
+#ifdef CONFIG_DEBUG_LOG_ADC_HAL
+
+    #define DBG_8195A_ADC(...)  do{ \
+        _DbgDump("\r"ADC_PREFIX __VA_ARGS__);\
+    }while(0)
+
+
+    #define ADCDBGLVL   0xFF   
+    #define DBG_8195A_ADC_LVL(LVL,...)  do{\
+            if (LVL&ADCDBGLVL){\
+                _DbgDump("\r"ADC_PREFIX_LVL __VA_ARGS__);\
+            }\
+    }while(0)
+#else
+    #define DBG_ADC_LOG_PERD    100
+    #define DBG_8195A_ADC(...)
+    #define DBG_8195A_ADC_LVL(...)
+#endif
+#endif
+
+
+//================ ADC HAL Related Enumeration ==================
+// ADC Module Selection 
+typedef enum _ADC_MODULE_SEL_ {
+        ADC0_SEL    =   0x0,
+        ADC1_SEL    =   0x1,
+        ADC2_SEL    =   0x2,
+        ADC3_SEL    =   0x3,
+}ADC_MODULE_SEL,*PADC_MODULE_SEL;
+
+// ADC module status 
+typedef enum _ADC_MODULE_STATUS_ {
+    ADC_DISABLE     =   0x0,
+    ADC_ENABLE      =   0x1,
+}ADC_MODULE_STATUS, *PADC_MODULE_STATUS;
+
+// ADC Data Endian
+typedef enum _ADC_DATA_ENDIAN_ {
+    ADC_DATA_ENDIAN_LITTLE      =   0x0,
+    ADC_DATA_ENDIAN_BIG         =   0x1,
+}ADC_DATA_ENDIAN,*PADC_DATA_ENDIAN;
+
+// ADC Debug Select
+typedef enum _ADC_DEBUG_SEL_ {
+    ADC_DBG_SEL_DISABLE         =   0x0,
+    ADC_DBG_SEL_ENABLE          =   0x1,
+}ADC_DEBUG_SEL,*PADC_DEBUG_SEL;
+
+typedef enum _ADC_COMPARE_SET_ {
+    ADC_COMP_SMALLER_THAN       =   0x0,
+    ADC_COMP_GREATER_THAN       =   0x1,
+}ADC_COMPARE_SET, *PADC_COMPARE_SET;
+
+// ADC feature status 
+typedef enum _ADC_FEATURE_STATUS_{
+    ADC_FEATURE_DISABLED    =   0,
+    ADC_FEATURE_ENABLED     =   1,
+}ADC_FEATURE_STATUS,*PADC_FEATURE_STATUS;
+
+// ADC operation type
+typedef enum _ADC_OP_TYPE_ {
+    ADC_RDREG_TYPE  =   0x0,
+    ADC_DMA_TYPE    =   0x1,
+    ADC_INTR_TYPE   =   0x2,
+}ADC_OP_TYPE, *PADC_OP_TYPE;
+
+// ADC device status 
+typedef enum _ADC_DEVICE_STATUS_ {
+    ADC_STS_UNINITIAL   =   0x00,
+    ADC_STS_INITIALIZED =   0x01,
+    ADC_STS_IDLE        =   0x02,
+    
+    ADC_STS_TX_READY    =   0x03,    
+    ADC_STS_TX_ING      =   0x04,
+    
+    ADC_STS_RX_READY    =   0x05,
+    ADC_STS_RX_ING      =   0x06,
+
+    ADC_STS_ERROR       =   0x07,
+    ADC_STS_FULL        =   0x08,
+}ADC_DEVICE_STATUS, *PADC_DEVICE_STATUS;
+
+// ADC error type
+typedef enum _ADC_ERR_TYPE_ {
+    ADC_ERR_FIFO_RD_ERROR           =   0x40,       //ADC FIFO read error
+}ADC_ERR_TYPE, *PADC_ERR_TYPE;
+
+// ADC initial status
+typedef enum _ADC_INITAIL_STATUS_ {
+    ADC0_INITED     =   0x1,
+    ADC1_INITED     =   0x2,
+    ADC2_INITED     =   0x4,
+    ADC3_INITED     =   0x8,
+}ADC_INITAIL_STATUS, *PADC_INITAIL_STATUS;
+
+
+//================ ADC HAL Data Structure ======================
+// ADC HAL initial data structure
+typedef struct _HAL_ADC_INIT_DAT_ {
+    u8                  ADCIdx;         //ADC index used
+    u8                  ADCEn;          //ADC module enable
+    u8                  ADCEndian;      //ADC endian selection, 
+                                        //but actually it's for 32-bit ADC data swap control
+                                        //1'b0: no swap, 
+                                        //1'b1: swap the upper 16-bit and the lower 16-bit
+    u8                  ADCBurstSz;     //ADC DMA operation threshold
+
+    u8                  ADCCompOnly;    //ADC compare mode only enable (without FIFO enable)
+    u8                  ADCOneShotEn;   //ADC one-shot mode enable
+    u8                  ADCOverWREn;    //ADC overwrite mode enable
+    u8                  ADCOneShotTD;   //ADC one shot mode threshold
+
+    u16                 ADCCompCtrl;    //ADC compare mode control,
+                                        //1'b0:less than the compare threshold
+                                        //1'b1:greater than the compare threshod
+    u16                 ADCCompTD;      //ADC compare mode threshold
+    
+    u8                  ADCDataRate;    //ADC down sample data rate, 
+    u8                  ADCAudioEn;     //ADC audio mode enable
+    u8                  ADCEnManul;     //ADC enable manually
+    u8                  ADCDbgSel;
+    
+    u32                  RSVD0;
+    
+    u32                 *ADCData;       //ADC data pointer
+    u32                 ADCPWCtrl;      //ADC0 power control
+    u32                 ADCIntrMSK;     //ADC Interrupt Mask
+    u32                 ADCAnaParAd3;   //ADC analog parameter 3
+    u32                 ADCInInput;     //ADC Input is internal?
+}HAL_ADC_INIT_DAT,*PHAL_ADC_INIT_DAT;
+
+// ADC HAL Operations
+typedef struct _HAL_ADC_OP_ {
+    RTK_STATUS  (*HalADCInit)       (VOID *Data);   //HAL ADC initialization
+    RTK_STATUS  (*HalADCDeInit)     (VOID *Data);   //HAL ADC de-initialization
+    RTK_STATUS  (*HalADCEnable)     (VOID *Data);   //HAL ADC de-initialization
+    u32         (*HalADCReceive)    (VOID *Data);   //HAL ADC receive
+    RTK_STATUS  (*HalADCIntrCtrl)   (VOID *Data);   //HAL ADC interrupt control
+    u32         (*HalADCReadReg)    (VOID *Data, u8 ADCReg);//HAL ADC read register
+}HAL_ADC_OP, *PHAL_ADC_OP;
+
+// ADC user callback adapter
+typedef struct _SAL_ADC_USERCB_ADPT_ {
+    VOID (*USERCB)      (VOID *Data);
+    u32  USERData;
+}SAL_ADC_USERCB_ADPT, *PSAL_ADC_USERCB_ADPT;
+
+// ADC user callback structure
+typedef struct _SAL_ADC_USER_CB_ {
+    PSAL_ADC_USERCB_ADPT    pTXCB;          //ADC Transmit Callback
+    PSAL_ADC_USERCB_ADPT    pTXCCB;         //ADC Transmit Complete Callback
+    PSAL_ADC_USERCB_ADPT    pRXCB;          //ADC Receive Callback
+    PSAL_ADC_USERCB_ADPT    pRXCCB;         //ADC Receive Complete Callback
+    PSAL_ADC_USERCB_ADPT    pRDREQCB;       //ADC Read Request Callback
+    PSAL_ADC_USERCB_ADPT    pERRCB;         //ADC Error Callback
+    PSAL_ADC_USERCB_ADPT    pDMATXCB;       //ADC DMA Transmit Callback
+    PSAL_ADC_USERCB_ADPT    pDMATXCCB;      //ADC DMA Transmit Complete Callback
+    PSAL_ADC_USERCB_ADPT    pDMARXCB;       //ADC DMA Receive Callback
+    PSAL_ADC_USERCB_ADPT    pDMARXCCB;      //ADC DMA Receive Complete Callback
+}SAL_ADC_USER_CB, *PSAL_ADC_USER_CB;
+
+// ADC Transmit Buffer
+typedef struct _SAL_ADC_TRANSFER_BUF_ {
+    u32     DataLen;                        //ADC Transmfer Length
+    u32     *pDataBuf;                      //ADC Transfer Buffer Pointer
+    u32     RSVD;                           //
+}SAL_ADC_TRANSFER_BUF,*PSAL_ADC_TRANSFER_BUF;
+
+typedef struct _SAL_ADC_DMA_USER_DEF_ {
+    
+    u8      TxDatSrcWdth;
+    u8      TxDatDstWdth;
+    u8      TxDatSrcBstSz;
+    u8      TxDatDstBstSz;
+
+    u8      TxChNo;
+    u8      LlpCtrl;
+    u16     RSVD0;
+
+    u32     MaxMultiBlk;    
+    u32     pLlix;
+    u32     pBlockSizeList;
+}SAL_ADC_DMA_USER_DEF, *PSAL_ADC_DMA_USER_DEF;
+
+// Software API Level ADC Handler 
+typedef struct _SAL_ADC_HND_ {
+    u8                      DevNum;             //ADC device number
+    u8                      PinMux;             //ADC pin mux seletion
+    u8                      OpType;             //ADC operation type selection
+    volatile u8             DevSts;             //ADC device status
+    
+    u32                     ADCExd;             //ADC extended options:
+                                                //bit 0: example
+                                                //bit 31~bit 1: Reserved
+    u32                     ErrType;            //
+    u32                     TimeOut;            //ADC IO Timeout count
+                                                                            
+    PHAL_ADC_INIT_DAT       pInitDat;           //Pointer to ADC initial data struct
+    PSAL_ADC_TRANSFER_BUF   pRXBuf;             //Pointer to ADC TX buffer
+    PSAL_ADC_USER_CB        pUserCB;            //Pointer to ADC User Callback
+}SAL_ADC_HND, *PSAL_ADC_HND;
+
+// ADC SAL handle private 
+typedef struct _SAL_ADC_HND_PRIV_ {
+    VOID            **ppSalADCHnd;              //Pointer to SAL_ADC_HND pointer
+    SAL_ADC_HND     SalADCHndPriv;              //Private SAL_ADC_HND
+}SAL_ADC_HND_PRIV, *PSAL_ADC_HND_PRIV;
+
+//ADC SAL management adapter
+typedef struct _SAL_ADC_MNGT_ADPT_ {
+    PSAL_ADC_HND_PRIV       pSalHndPriv;        //Pointer to SAL_ADC_HND
+    PHAL_ADC_INIT_DAT       pHalInitDat;        //Pointer to HAL ADC initial data( HAL_ADC_INIT_DAT )
+    PHAL_ADC_OP             pHalOp;             //Pointer to HAL ADC operation( HAL_ADC_OP )
+    VOID                    (*pHalOpInit)(VOID*);//Pointer to HAL ADC initialize function
+
+    PIRQ_HANDLE             pIrqHnd;            //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
+    VOID                    (*pSalIrqFunc)(VOID*);      //Used for SAL ADC interrupt function
+
+    PSAL_ADC_DMA_USER_DEF   pDMAConf;                   //Pointer to DAC User Define DMA config
+    PHAL_GDMA_ADAPTER       pHalGdmaAdp;
+    PHAL_GDMA_OP            pHalGdmaOp;
+    PIRQ_HANDLE             pIrqGdmaHnd;
+    VOID                    (*pHalGdmaOpInit)(VOID*);   //Pointer to HAL DAC initialize function    
+    PSAL_ADC_USER_CB        pUserCB;                    //Pointer to SAL user callbacks (SAL_ADC_USER_CB )
+    VOID                    (*pSalDMAIrqFunc)(VOID*);   //Used for SAL DAC interrupt function
+}SAL_ADC_MNGT_ADPT, *PSAL_ADC_MNGT_ADPT;
+
+
+//================ ADC HAL Function Prototype ===================
+// ADC HAL inline function
+// For checking I2C input index valid or not
+static inline RTK_STATUS
+RtkADCIdxChk(
+    IN  u8  ADCIdx
+)
+{
+#if !ADC0_USED
+    if (ADCIdx == ADC0_SEL)
+        return _EXIT_FAILURE;
+#endif
+
+#if !ADC1_USED
+    if (ADCIdx == ADC1_SEL)
+        return _EXIT_FAILURE;
+#endif
+
+#if !ADC2_USED
+    if (ADCIdx == ADC2_SEL)
+        return _EXIT_FAILURE;
+#endif
+
+#if !ADC3_USED
+        if (ADCIdx == ADC3_SEL)
+            return _EXIT_FAILURE;
+#endif
+
+    return _EXIT_SUCCESS;
+}
+
+VOID HalADCOpInit(IN VOID *Data);
+PSAL_ADC_HND RtkADCGetSalHnd(IN  u8  DACIdx);
+RTK_STATUS RtkADCFreeSalHnd(IN  PSAL_ADC_HND    pSalADCHND);
+RTK_STATUS RtkADCLoadDefault(IN  VOID *Data);
+RTK_STATUS RtkADCInit(IN  VOID *Data);
+RTK_STATUS RtkADCDeInit(IN  VOID *Data);
+//RTK_STATUS RtkADCReceive(IN  VOID *Data);
+u32 RtkADCReceive(IN  VOID *Data);
+u32 RtkADCReceiveBuf(IN  VOID *Data,IN  u32  *pBuf);
+
+PSAL_ADC_MNGT_ADPT RtkADCGetMngtAdpt(IN  u8  ADCIdx);
+RTK_STATUS RtkADCFreeMngtAdpt(IN  PSAL_ADC_MNGT_ADPT  pSalADCMngtAdpt);
+VOID ADCISRHandle(IN  VOID *Data);
+VOID ADCGDMAISRHandle(IN  VOID *Data);
+
+#endif

component/soc/realtek/8195a/fwlib/hal_api.h

@@ -0,0 +1,123 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+#ifndef _HAL_API_H_
+#define _HAL_API_H_
+
+#include "basic_types.h"
+#include "hal_irqn.h"
+
+#define HAL_READ32(base, addr)            \
+        rtk_le32_to_cpu(*((volatile u32*)(base + addr)))
+    
+#define HAL_WRITE32(base, addr, value32)  \
+        ((*((volatile u32*)(base + addr))) = rtk_cpu_to_le32(value32))
+
+
+#define HAL_READ16(base, addr)            \
+        rtk_le16_to_cpu(*((volatile u16*)(base + addr)))
+        
+#define HAL_WRITE16(base, addr, value)  \
+        ((*((volatile u16*)(base + addr))) = rtk_cpu_to_le16(value))
+    
+
+#define HAL_READ8(base, addr)            \
+        (*((volatile u8*)(base + addr)))
+            
+#define HAL_WRITE8(base, addr, value)  \
+        ((*((volatile u8*)(base + addr))) = value)
+
+#if 0
+// These "extern _LONG_CALL_" function declaration are for RAM code building only
+// For ROM code building, thses code should be marked off
+extern _LONG_CALL_ u8 
+HalPinCtrlRtl8195A(
+    IN u32  Function, 
+    IN u32  PinLocation, 
+    IN BOOL   Operation
+    );
+
+extern _LONG_CALL_ VOID 
+HalSerialPutcRtl8195a(
+    IN  u8 c
+    );
+
+extern _LONG_CALL_ u8 
+HalSerialGetcRtl8195a(
+    IN  BOOL    PullMode
+    );
+
+extern _LONG_CALL_ u32
+HalSerialGetIsrEnRegRtl8195a(VOID);
+
+extern _LONG_CALL_ VOID
+HalSerialSetIrqEnRegRtl8195a (
+    IN  u32 SetValue
+    );
+
+extern _LONG_CALL_  VOID
+VectorTableInitForOSRtl8195A(
+    IN  VOID *PortSVC,
+    IN  VOID *PortPendSVH,
+    IN  VOID *PortSysTick    
+    );
+
+extern _LONG_CALL_ BOOL
+VectorIrqRegisterRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+    );
+
+extern _LONG_CALL_ BOOL
+VectorIrqUnRegisterRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+    );
+
+extern _LONG_CALL_ VOID
+VectorIrqEnRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+    );
+
+extern _LONG_CALL_  VOID
+VectorIrqDisRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+    );
+#endif
+
+#define PinCtrl HalPinCtrlRtl8195A
+
+#define DiagPutChar	HalSerialPutcRtl8195a
+#define DiagGetChar HalSerialGetcRtl8195a
+#define DiagGetIsrEnReg HalSerialGetIsrEnRegRtl8195a
+#define DiagSetIsrEnReg HalSerialSetIrqEnRegRtl8195a
+
+#define InterruptForOSInit VectorTableInitForOSRtl8195A
+#define InterruptRegister VectorIrqRegisterRtl8195A
+#define InterruptUnRegister  VectorIrqUnRegisterRtl8195A
+
+#define InterruptEn VectorIrqEnRtl8195A
+#define InterruptDis VectorIrqDisRtl8195A
+
+#define SpicFlashInit SpicFlashInitRtl8195A
+#define Calibration32k En32KCalibration
+#define WDGInit InitWDGIRQ
+
+typedef enum  _HAL_Status
+{
+  HAL_OK            = 0x00,
+  HAL_BUSY          = 0x01,
+  HAL_TIMEOUT       = 0x02,
+  HAL_ERR_PARA      = 0x03,     // error with invaild parameters 
+  HAL_ERR_MEM       = 0x04,     // error with memory allocation failed
+  HAL_ERR_HW        = 0x05,     // error with hardware error
+
+  HAL_ERR_UNKNOWN   = 0xee      // unknown error
+  
+} HAL_Status;
+
+
+#endif //_HAL_API_H_

component/soc/realtek/8195a/fwlib/hal_common.h

@@ -0,0 +1,17 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_COMMON_H_
+#define _HAL_COMMON_H_
+
+//================= Function Prototype START  ===================
+HAL_Status HalCommonInit(void);
+//================= Function Prototype END     ===================
+
+#endif

component/soc/realtek/8195a/fwlib/hal_crypto.h

@@ -0,0 +1,213 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef __HAL_CRYPTO_H__
+#define __HAL_CRYPTO_H__
+
+
+#include "hal_api.h"
+#include "basic_types.h"
+
+
+#define CRYPTO_MAX_MSG_LENGTH		16000
+#define CRYPTO_MD5_DIGEST_LENGTH 	16
+#define CRYPTO_SHA1_DIGEST_LENGTH 	20
+#define CRYPTO_SHA2_DIGEST_LENGTH 	32
+
+
+typedef enum _SHA2_TYPE_ {
+		SHA2_NONE 	= 0,
+		SHA2_224 	= 224/8,
+		SHA2_256 	= 256/8,
+		SHA2_384 	= 384/8,
+		SHA2_512 	= 512/8
+} SHA2_TYPE;
+
+
+#define _ERRNO_CRYPTO_DESC_NUM_SET_OutRange 	-2
+#define _ERRNO_CRYPTO_BURST_NUM_SET_OutRange	-3
+#define _ERRNO_CRYPTO_NULL_POINTER				-4
+#define _ERRNO_CRYPTO_ENGINE_NOT_INIT			-5
+#define _ERRNO_CRYPTO_ADDR_NOT_4Byte_Aligned	-6
+#define _ERRNO_CRYPTO_KEY_OutRange				-7
+#define _ERRNO_CRYPTO_MSG_OutRange				-8
+#define _ERRNO_CRYPTO_IV_OutRange				-9
+#define _ERRNO_CRYPTO_AUTH_TYPE_NOT_MATCH		-10
+#define _ERRNO_CRYPTO_CIPHER_TYPE_NOT_MATCH 	-11
+#define _ERRNO_CRYPTO_KEY_IV_LEN_DIFF			-12
+
+
+
+//
+//	External API Functions
+//
+
+
+// Crypto Engine
+extern int rtl_cryptoEngine_init(void);
+extern void rtl_cryptoEngine_info(void);
+
+
+
+//
+// Authentication 
+//
+
+// md5
+
+extern int rtl_crypto_md5(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
+
+extern int rtl_crypto_md5_init(void);
+extern int rtl_crypto_md5_process(IN const u8* message, const IN u32 msglen, OUT u8* pDigest);
+
+
+// sha1
+extern int rtl_crypto_sha1(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
+
+extern int rtl_crypto_sha1_init(void);
+extern int rtl_crypto_sha1_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
+
+// sha2
+
+extern int rtl_crypto_sha2(IN const SHA2_TYPE sha2type, 
+								IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
+
+extern int rtl_crypto_sha2_init(IN const SHA2_TYPE sha2type);
+extern int rtl_crypto_sha2_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
+
+
+// HMAC-md5
+extern int rtl_crypto_hmac_md5(IN const u8* message, IN const u32 msglen, 
+									IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
+
+extern int rtl_crypto_hmac_md5_init(IN const u8* key, IN const u32 keylen);
+extern int rtl_crypto_hmac_md5_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
+
+
+// HMAC-sha1
+extern int rtl_crypto_hmac_sha1(IN const u8* message, IN const u32 msglen, 
+									IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
+
+extern int rtl_crypto_hmac_sha1_init(IN const u8* key, IN const u32 keylen);
+extern int rtl_crypto_hmac_sha1_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
+
+
+// HMAC-sha2
+extern int rtl_crypto_hmac_sha2(IN const SHA2_TYPE sha2type, IN const u8* message, IN const u32 msglen, 
+									IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
+
+extern int rtl_crypto_hmac_sha2_init(IN const SHA2_TYPE sha2type, IN const u8* key, IN const u32 keylen);
+extern int rtl_crypto_hmac_sha2_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
+
+
+//
+// Cipher Functions
+//
+
+// AES - CBC
+
+extern int rtl_crypto_aes_cbc_init(IN const u8* key, IN const u32 keylen);
+
+extern int rtl_crypto_aes_cbc_encrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+extern int rtl_crypto_aes_cbc_decrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+
+// AES - ECB
+
+extern int rtl_crypto_aes_ecb_init(IN const u8* key, IN const u32 keylen);
+
+extern int rtl_crypto_aes_ecb_encrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+extern int rtl_crypto_aes_ecb_decrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+
+// AES - CTR
+
+extern int rtl_crypto_aes_ctr_init(IN const u8* key, IN const u32 keylen);
+
+extern int rtl_crypto_aes_ctr_encrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+extern int rtl_crypto_aes_ctr_decrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+
+// 3DES - CBC
+
+extern int rtl_crypto_3des_cbc_init(IN const u8* key, IN const u32 keylen);
+
+extern int rtl_crypto_3des_cbc_encrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+extern int rtl_crypto_3des_cbc_decrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+
+// 3DES - ECB
+
+extern int rtl_crypto_3des_ecb_init(IN const u8* key, IN const u32 keylen);
+
+extern int rtl_crypto_3des_ecb_encrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+extern int rtl_crypto_3des_ecb_decrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+
+// DES - CBC
+
+extern int rtl_crypto_des_cbc_init(IN const u8* key, IN const u32 keylen);
+
+extern int rtl_crypto_des_cbc_encrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+extern int rtl_crypto_des_cbc_decrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+
+// DES - ECB
+
+extern int rtl_crypto_des_ecb_init(IN const u8* key, IN const u32 keylen);
+
+extern int rtl_crypto_des_ecb_encrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+extern int rtl_crypto_des_ecb_decrypt(
+	IN const u8* message, IN const u32 msglen, 
+	IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
+
+
+//
+// C functions in ROM
+//
+
+extern int rtl_memcmpb(const u8 *dst, const u8 *src, int bytes);
+extern int rtl_memcpyb(u8 *dst, const u8 *src, int bytes);
+
+#endif /* __HAL_CRYPTO_H__ */
+

component/soc/realtek/8195a/fwlib/hal_dac.h

@@ -0,0 +1,313 @@
+//======================================================
+//  Routines to access hardware
+//
+//  Copyright (c) 2013 Realtek Semiconductor Corp.
+//
+//  This module is a confidential and proprietary property of RealTek and
+//  possession or use of this module requires written permission of RealTek.
+//======================================================
+#ifndef _HAL_DAC_H_
+#define _HAL_DAC_H_
+
+#include "rtl8195a.h"
+#include "rtl8195a_dac.h"
+#include "hal_api.h"
+#include "hal_gdma.h"
+
+//================ DAC Configuration  =========================
+#define DAC_INTR_OP_TYPE    1
+#define DAC_DMA_OP_TYPE     1
+
+// DAC SAL management macros
+#define SAL_DAC_USER_CB_NUM     (sizeof(SAL_DAC_USER_CB) / sizeof(PSAL_DAC_USERCB_ADPT))
+
+// DAC SAL used module. 
+// Please set the DAC module flag to 1 to enable the related DAC module functions.
+#define DAC0_USED                   1
+#define DAC1_USED                   1
+
+
+//================ Debug MSG Definition =======================
+#define DAC_PREFIX      "RTL8195A[dac]: "
+#define DAC_PREFIX_LVL  "    [DAC_DBG]: "
+
+typedef enum _DAC_DBG_LVL_ {
+    HAL_DAC_LVL         =   0x00,
+    SAL_DAC_LVL         =   0x02,
+    VERI_DAC_LVL        =   0x04,
+}DAC_DBG_LVL,*PDAC_DBG_LVL;
+
+#ifdef CONFIG_DEBUG_LOG
+#ifdef CONFIG_DEBUG_LOG_DAC_HAL
+
+    #define DBG_8195A_DAC(...)  do{ \
+        _DbgDump("\r"DAC_PREFIX __VA_ARGS__);\
+    }while(0)
+
+
+    #define DACDBGLVL   0xFF   
+    #define DBG_8195A_DAC_LVL(LVL,...)  do{\
+            if (LVL&DACDBGLVL){\
+                _DbgDump("\r"DAC_PREFIX_LVL __VA_ARGS__);\
+            }\
+    }while(0)
+#else
+    #define DBG_DAC_LOG_PERD    100
+    #define DBG_8195A_DAC(...)
+    #define DBG_8195A_DAC_LVL(...)
+#endif
+#endif
+
+
+//================ DAC HAL Related Enumeration ==================
+// DAC Module Selection 
+typedef enum _DAC_MODULE_SEL_ {
+        DAC0_SEL    =   0x0,
+        DAC1_SEL    =   0x1,
+}DAC_MODULE_SEL,*PDAC_MODULE_SEL;
+
+// DAC module status 
+typedef enum _DAC_MODULE_STATUS_ {
+    DAC_DISABLE     =   0x0,
+    DAC_ENABLE      =   0x1,
+}DAC_MODULE_STATUS, *PDAC_MODULE_STATUS;
+
+// DAC Data Rate
+typedef enum _DAC_DATA_RATE_ {
+    DAC_DATA_RATE_10K   =   0x0,
+    DAC_DATA_RATE_250K  =   0x1,
+}DAC_DATA_RATE,*PDAC_DATA_RATE;
+
+// DAC Data Endian
+typedef enum _DAC_DATA_ENDIAN_ {
+    DAC_DATA_ENDIAN_LITTLE      =   0x0,
+    DAC_DATA_ENDIAN_BIG         =   0x1,
+}DAC_DATA_ENDIAN,*PDAC_DATA_ENDIAN;
+
+// DAC Debug Select
+typedef enum _DAC_DEBUG_SEL_ {
+    DAC_DBG_SEL_DISABLE         =   0x0,
+    DAC_DBG_SEL_ENABLE          =   0x1,
+}DAC_DEBUG_SEL,*PDAC_DEBUG_SEL;
+
+// DAC Dsc Debug Select
+typedef enum _DAC_DSC_DEBUG_SEL_ {
+    DAC_DSC_DBG_SEL_DISABLE         =   0x0,
+    DAC_DSC_DBG_SEL_ENABLE          =   0x1,
+}DAC_DSC_DEBUG_SEL,*PDAC_DSC_DEBUG_SEL;
+
+
+// DAC Bypass Dsc Debug Select
+typedef enum _DAC_BYPASS_DSC_SEL_ {
+    DAC_BYPASS_DSC_SEL_DISABLE          =   0x0,
+    DAC_BYPASS_DSC_SEL_ENABLE           =   0x1,
+}DAC_BYPASS_DSC_SEL,*PDAC_BYPASS_DSC_SEL;
+
+// DAC feature status 
+typedef enum _DAC_FEATURE_STATUS_{
+    DAC_FEATURE_DISABLED    =   0,
+    DAC_FEATURE_ENABLED     =   1,
+}DAC_FEATURE_STATUS,*PDAC_FEATURE_STATUS;
+
+// DAC operation type
+typedef enum _DAC_OP_TYPE_ {
+    DAC_POLL_TYPE   =   0x0,
+    DAC_DMA_TYPE    =   0x1,
+    DAC_INTR_TYPE   =   0x2,
+}DAC_OP_TYPE, *PDAC_OP_TYPE;
+
+// DAC device status 
+typedef enum _DAC_Device_STATUS_ {
+    DAC_STS_UNINITIAL   =   0x00,
+    DAC_STS_INITIALIZED =   0x01,
+    DAC_STS_IDLE        =   0x02,
+    
+    DAC_STS_TX_READY    =   0x03,    
+    DAC_STS_TX_ING      =   0x04,
+    
+    DAC_STS_RX_READY    =   0x05,
+    DAC_STS_RX_ING      =   0x06,
+
+    DAC_STS_ERROR       =   0x07,
+}DAC_Device_STATUS, *PDAC_Device_STATUS;
+
+//DAC device error type
+typedef enum _DAC_ERR_TYPE_ {
+    DAC_ERR_FIFO_OVER       =   0x04,       //DAC FIFO overflow.
+    DAC_ERR_FIFO_STOP       =   0x08,       //DAC FIFO is completely empty, and it will be stopped automatically.
+    DAC_ERR_FIFO_WRFAIL     =   0x10,       //When DAC is NOT enabled, a write operation attempts to access DAC register.
+    DAC_ERR_FIFO_DSC_OVER0  =   0x20,
+    DAC_ERR_FIFO_DSC_OVER1  =   0x40,
+}DAC_ERR_TYPE, *PDAC_ERR_TYPE;
+
+// DAC data input method
+typedef enum _DAC_INPUT_TYPE_{
+    DAC_INPUT_SINGLE_WR     =   0x1,        //DAC input by using single register write
+    DAC_INPUT_DMA_ONEBLK    =   0x2,        //DAC input by using single DMA block
+    DAC_INPUT_DMA_LLP       =   0x3,        //DAC input by using DMA linked list mode
+}DAC_INPUT_TYPE,*PDAC_INPUT_TYPE;
+
+
+
+
+//======================================================
+// DAC HAL initial data structure 
+typedef struct _HAL_DAC_INIT_DAT_ {
+    u8                  DACIdx;         //DAC index used
+    u8                  DACEn;          //DAC module enable
+    u8                  DACDataRate;    //DAC data rate, 1'b0:10KHz, 1'b1:250KHz
+    u8                  DACEndian;      //DAC endian selection, 
+                                        //but actually it's for 32-bit DAC data swap control
+                                        //1'b0: no swap, 
+                                        //1'b1: swap the upper 16-bit and the lower 16-bit
+    u8                  DACFilterSet;   //DAC filter settle
+    u8                  DACBurstSz;     //DAC burst size
+    u8                  DACDbgSel;      //DAC debug sel
+    u8                  DACDscDbgSel;   //DAC debug dsc sel
+    
+    u8                  DACBPDsc;       //DAC bypass delta sigma for loopback
+    u8                  DACDeltaSig;    //DAC bypass value of delta sigma
+    u16                 RSVD1;          
+
+
+    
+    u32                 *DACData;       //DAC data pointer
+    u32                 DACPWCtrl;      //DAC0 and DAC1 power control
+    u32                 DACAnaCtrl0;    //DAC anapar_da control 0
+    u32                 DACAnaCtrl1;    //DAC anapar_da control 1
+    u32                 DACIntrMSK;     //DAC Interrupt Mask
+}HAL_DAC_INIT_DAT,*PHAL_DAC_INIT_DAT;
+
+// DAC HAL Operations
+typedef struct _HAL_DAC_OP_ {
+    RTK_STATUS  (*HalDACInit)       (VOID *Data);   //HAL DAC initialization
+    RTK_STATUS  (*HalDACDeInit)     (VOID *Data);   //HAL DAC de-initialization
+    RTK_STATUS  (*HalDACEnable)     (VOID *Data);   //HAL DAC de-initialization
+    u8          (*HalDACSend)       (VOID *Data);   //HAL DAC receive
+    RTK_STATUS  (*HalDACIntrCtrl)   (VOID *Data);   //HAL DAC interrupt control
+    u32         (*HalDACReadReg)    (VOID *Data, u8 DACReg);//HAL DAC read register
+}HAL_DAC_OP, *PHAL_DAC_OP;
+
+// DAC user callback adapter
+typedef struct _SAL_DAC_USERCB_ADPT_ {
+    VOID (*USERCB)      (VOID *Data);
+    u32  USERData;
+}SAL_DAC_USERCB_ADPT, *PSAL_DAC_USERCB_ADPT;
+
+// DAC user callback structure
+typedef struct _SAL_DAC_USER_CB_ {
+    PSAL_DAC_USERCB_ADPT    pTXCB;          //DAC Transmit Callback
+    PSAL_DAC_USERCB_ADPT    pTXCCB;         //DAC Transmit Complete Callback
+    PSAL_DAC_USERCB_ADPT    pRXCB;          //DAC Receive Callback
+    PSAL_DAC_USERCB_ADPT    pRXCCB;         //DAC Receive Complete Callback
+    PSAL_DAC_USERCB_ADPT    pRDREQCB;       //DAC Read Request Callback
+    PSAL_DAC_USERCB_ADPT    pERRCB;         //DAC Error Callback
+    PSAL_DAC_USERCB_ADPT    pDMATXCB;       //DAC DMA Transmit Callback
+    PSAL_DAC_USERCB_ADPT    pDMATXCCB;      //DAC DMA Transmit Complete Callback
+    PSAL_DAC_USERCB_ADPT    pDMARXCB;       //DAC DMA Receive Callback
+    PSAL_DAC_USERCB_ADPT    pDMARXCCB;      //DAC DMA Receive Complete Callback
+}SAL_DAC_USER_CB, *PSAL_DAC_USER_CB;
+
+// DAC Transmit Buffer
+typedef struct _SAL_DAC_TRANSFER_BUF_ {
+    u32     DataLen;                        //DAC Transmfer Length
+    u32     *pDataBuf;                      //DAC Transfer Buffer Pointer
+    u32     RSVD;                           //
+}SAL_DAC_TRANSFER_BUF,*PSAL_DAC_TRANSFER_BUF;
+
+typedef struct _SAL_DAC_DMA_USER_DEF_ {
+    
+    u8      TxDatSrcWdth;
+    u8      TxDatDstWdth;
+    u8      TxDatSrcBstSz;
+    u8      TxDatDstBstSz;
+
+    u8      TxChNo;
+    u8      LlpCtrl;
+    u16     RSVD0;
+
+    u32     MaxMultiBlk;    
+    u32     pLlix;
+    u32     pBlockSizeList;
+}SAL_DAC_DMA_USER_DEF, *PSAL_DAC_DMA_USER_DEF;
+
+// Software API Level DAC Handler 
+typedef struct _SAL_DAC_HND_ {
+    u8                      DevNum;             //DAC device number
+    u8                      PinMux;             //DAC pin mux seletion
+    u8                      OpType;             //DAC operation type selection
+    volatile u8             DevSts;             //DAC device status
+
+    u8                      DACInType;          //DAC input type
+    u8                      RSVD0;
+    u16                     RSVD1;
+    
+    u32                     DACExd;             //DAC extended options:
+                                                //bit 0: example
+                                                //bit 31~bit 1: Reserved
+    u32                     ErrType;            //
+    u32                     TimeOut;            //DAC IO Timeout count
+                                                                            
+    PHAL_DAC_INIT_DAT       pInitDat;           //Pointer to DAC initial data struct
+    PSAL_DAC_TRANSFER_BUF   pTXBuf;             //Pointer to DAC TX buffer
+    PSAL_DAC_USER_CB        pUserCB;            //Pointer to DAC User Callback
+    PSAL_DAC_DMA_USER_DEF   pDMAConf;           //Pointer to DAC User Define DMA Config
+}SAL_DAC_HND, *PSAL_DAC_HND;
+
+// DAC SAL handle private 
+typedef struct _SAL_DAC_HND_PRIV_ {
+    VOID            **ppSalDACHnd;              //Pointer to SAL_DAC_HND pointer
+    SAL_DAC_HND     SalDACHndPriv;              //Private SAL_DAC_HND
+}SAL_DAC_HND_PRIV, *PSAL_DAC_HND_PRIV;
+
+//DAC SAL management adapter
+typedef struct _SAL_DAC_MNGT_ADPT_ {
+    PSAL_DAC_HND_PRIV       pSalHndPriv;                //Pointer to SAL_DAC_HND
+    PHAL_DAC_INIT_DAT       pHalInitDat;                //Pointer to HAL DAC initial data( HAL_I2C_INIT_DAT )
+    PHAL_DAC_OP             pHalOp;                     //Pointer to HAL DAC operation( HAL_DAC_OP )
+    VOID                    (*pHalOpInit)(VOID*);       //Pointer to HAL DAC initialize function
+    PIRQ_HANDLE             pIrqHnd;                    //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
+    PSAL_DAC_USER_CB        pUserCB;                    //Pointer to SAL user callbacks (SAL_DAC_USER_CB )
+    VOID                    (*pSalIrqFunc)(VOID*);      //Used for SAL DAC interrupt function
+
+    PSAL_DAC_DMA_USER_DEF   pDMAConf;                   //Pointer to DAC User Define DMA config
+    PHAL_GDMA_ADAPTER       pHalGdmaAdp;
+    PHAL_GDMA_OP            pHalGdmaOp;
+    VOID                    (*pHalGdmaOpInit)(VOID*);   //Pointer to HAL DAC initialize function    
+    PIRQ_HANDLE             pIrqGdmaHnd;
+    VOID                    (*pSalDMAIrqFunc)(VOID*);   //Used for SAL DAC interrupt function
+}SAL_DAC_MNGT_ADPT, *PSAL_DAC_MNGT_ADPT;
+
+
+//================ DAC HAL Function Prototype ===================
+// DAC HAL inline function
+// For checking DAC input index valid or not
+static inline RTK_STATUS
+RtkDACIdxChk(
+    IN  u8  DACIdx
+)
+{
+#if !DAC0_USED
+    if (DACIdx == DAC0_SEL)
+        return _EXIT_FAILURE;
+#endif
+
+#if !DAC1_USED
+    if (DACIdx == DAC1_SEL)
+        return _EXIT_FAILURE;
+#endif
+        
+    return _EXIT_SUCCESS;
+}
+
+VOID HalDACOpInit(IN VOID *Data);
+RTK_STATUS RtkDACLoadDefault(IN  VOID *Data);
+RTK_STATUS RtkDACInit(IN  VOID *Data);
+RTK_STATUS RtkDACDeInit(IN  VOID *Data);
+RTK_STATUS RtkDACSend(IN  VOID *Data);
+PSAL_DAC_HND RtkDACGetSalHnd(IN  u8  DACIdx);
+RTK_STATUS RtkDACFreeSalHnd(IN  PSAL_DAC_HND    pSalDACHND);
+PSAL_DAC_MNGT_ADPT RtkDACGetMngtAdpt(IN  u8  DACIdx);
+RTK_STATUS RtkDACFreeMngtAdpt(IN  PSAL_DAC_MNGT_ADPT  pSalDACMngtAdpt);
+
+#endif

component/soc/realtek/8195a/fwlib/hal_diag.h

@@ -0,0 +1,107 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_DIAG_H_
+#define _HAL_DIAG_H_
+
+
+//Register offset
+#define UART_REV_BUF_OFF            0x00
+#define UART_TRAN_HOLD_OFF          0x00
+#define UART_DLH_OFF                0x04
+#define UART_DLL_OFF                0x00
+#define UART_INTERRUPT_EN_REG_OFF   0x04
+#define UART_INTERRUPT_IDEN_REG_OFF 0x08
+#define UART_FIFO_CTL_REG_OFF       0x08
+#define UART_LINE_CTL_REG_OFF       0x0c
+#define UART_MODEM_CTL_REG_OFF      0x10
+#define UART_LINE_STATUS_REG_OFF    0x14
+#define UART_MODEM_STATUS_REG_OFF   0x18
+#define UART_FIFO_ACCESS_REG_OFF    0x70
+#define UART_STATUS_REG_OFF         0x7c
+#define UART_TFL_OFF                0x80
+#define UART_RFL_OFF                0x84
+
+
+//Buad rate
+#define UART_BAUD_RATE_2400         2400
+#define UART_BAUD_RATE_4800         4800
+#define UART_BAUD_RATE_9600         9600
+#define UART_BAUD_RATE_19200        19200
+#define UART_BAUD_RATE_38400        38400
+#define UART_BAUD_RATE_57600        57600
+#define UART_BAUD_RATE_115200       115200
+#define UART_BAUD_RATE_921600       921600
+#define UART_BAUD_RATE_1152000      1152000
+
+#define UART_PARITY_ENABLE          0x08
+#define UART_PARITY_DISABLE         0
+
+#define UART_DATA_LEN_5BIT          0x0
+#define UART_DATA_LEN_6BIT          0x1
+#define UART_DATA_LEN_7BIT          0x2
+#define UART_DATA_LEN_8BIT          0x3
+
+#define UART_STOP_1BIT              0x0
+#define UART_STOP_2BIT              0x4
+
+
+#define HAL_UART_READ32(addr)            HAL_READ32(LOG_UART_REG_BASE, addr)
+#define HAL_UART_WRITE32(addr, value)    HAL_WRITE32(LOG_UART_REG_BASE, addr, value)
+#define HAL_UART_READ16(addr)            HAL_READ16(LOG_UART_REG_BASE, addr)
+#define HAL_UART_WRITE16(addr, value)    HAL_WRITE16(LOG_UART_REG_BASE, addr, value)
+#define HAL_UART_READ8(addr)             HAL_READ8(LOG_UART_REG_BASE, addr)
+#define HAL_UART_WRITE8(addr, value)     HAL_WRITE8(LOG_UART_REG_BASE, addr, value)
+
+typedef struct _LOG_UART_ADAPTER_ {
+    u32     BaudRate;
+    u32     FIFOControl; 
+    u32     IntEnReg;
+    u8      Parity;
+    u8      Stop;
+    u8      DataLength;
+}LOG_UART_ADAPTER, *PLOG_UART_ADAPTER;
+
+typedef struct _COMMAND_TABLE_ {
+    const   u8* cmd;
+    u16     ArgvCnt;
+    u32     (*func)(u16 argc, u8* argv[]);
+    const   u8* msg;
+}COMMAND_TABLE, *PCOMMAND_TABLE;
+
+//VOID
+//HalLogUartHandle(void);
+
+
+extern _LONG_CALL_ u32 
+HalLogUartInit(
+    IN  LOG_UART_ADAPTER    UartAdapter
+    );
+
+
+extern _LONG_CALL_ VOID 
+HalSerialPutcRtl8195a(
+    IN  u8 c
+    );
+
+extern _LONG_CALL_ u8 
+HalSerialGetcRtl8195a(
+    IN  BOOL    PullMode
+    );
+
+extern _LONG_CALL_ u32
+HalSerialGetIsrEnRegRtl8195a(VOID);
+
+extern _LONG_CALL_ VOID
+HalSerialSetIrqEnRegRtl8195a (
+    IN  u32 SetValue
+);
+
+
+#endif//_HAL_DIAG_H_

component/soc/realtek/8195a/fwlib/hal_efuse.h

@@ -0,0 +1,28 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_EFUSE_H_
+#define _HAL_EFUSE_H_
+
+_LONG_CALL_ extern VOID HalEFUSEPowerSwitch8195AROM(IN u8 bWrite, IN u8 PwrState, IN u8 L25OutVoltage);
+_LONG_CALL_ extern u32 HALEFUSEOneByteReadROM(IN	u32 CtrlSetting, IN	u16 Addr, OUT u8 *Data, IN u8 L25OutVoltage);
+_LONG_CALL_ extern u32 HALEFUSEOneByteWriteROM(IN	u32 CtrlSetting, IN	u16 Addr, IN u8 Data, IN u8 L25OutVoltage);
+
+#define EFUSERead8     HALEFUSEOneByteReadROM
+#define EFUSEWrite8    HALEFUSEOneByteWriteROM
+
+#define L25EOUTVOLTAGE	7
+
+VOID HalEFUSEOpInit(
+    IN  VOID *Data
+);
+
+
+#endif
+

component/soc/realtek/8195a/fwlib/hal_gdma.h

@@ -0,0 +1,127 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_GDMA_H_
+#define _HAL_GDMA_H_
+
+#include "rtl8195a_gdma.h"
+
+typedef struct _GDMA_CH_LLI_ELE_ {
+    u32                   Sarx;
+    u32                   Darx;
+    u32                   Llpx;
+    u32                   CtlxLow;
+    u32                   CtlxUp;
+    u32                   Temp;
+}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
+#if 1
+#if 0
+typedef struct _GDMA_CH_LLI_ {
+    PGDMA_CH_LLI_ELE      pLliEle;
+    PGDMA_CH_LLI          pNextLli;
+}GDMA_CH_LLI, *PGDMA_CH_LLI;
+
+typedef struct _BLOCK_SIZE_LIST_ {
+    u32                  BlockSize;
+    PBLOCK_SIZE_LIST     pNextBlockSiz;
+}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
+#else
+struct GDMA_CH_LLI {
+    PGDMA_CH_LLI_ELE                pLliEle;
+    struct GDMA_CH_LLI             *pNextLli;
+};
+
+struct BLOCK_SIZE_LIST {
+    u32                             BlockSize;
+    struct BLOCK_SIZE_LIST          *pNextBlockSiz;
+};
+
+#endif
+
+#endif
+typedef struct _HAL_GDMA_ADAPTER_ {
+    u32                   ChSar;
+    u32                   ChDar;
+    GDMA_CHANNEL_NUM      ChEn;
+    GDMA_CTL_REG          GdmaCtl;
+    GDMA_CFG_REG          GdmaCfg;
+    u32                   PacketLen;
+    u32                   BlockLen;
+    u32                   MuliBlockCunt;
+    u32                   MaxMuliBlock;
+    struct GDMA_CH_LLI          *pLlix;
+    struct BLOCK_SIZE_LIST      *pBlockSizeList;
+
+    PGDMA_CH_LLI_ELE            pLli;
+    u32                         NextPlli;
+    u8                    TestItem;
+    u8                          ChNum;
+    u8                          GdmaIndex;
+    u8                          IsrCtrl:1;
+    u8                          GdmaOnOff:1;
+    u8                          Llpctrl:1;
+    u8                          Lli0:1;
+    u8                          Rsvd4to7:4;
+    u8                          GdmaIsrType;
+}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
+
+typedef struct _HAL_GDMA_CHNL_ {
+    u8 GdmaIndx;
+    u8 GdmaChnl;
+    u8 IrqNum;
+    u8 Reserved;
+}HAL_GDMA_CHNL, *PHAL_GDMA_CHNL;
+
+
+typedef struct _HAL_GDMA_OP_ {
+    VOID (*HalGdmaOnOff)(VOID *Data);
+    BOOL (*HalGdamChInit)(VOID *Data);
+    BOOL (*HalGdmaChSeting)(VOID *Data);
+    BOOL (*HalGdmaChBlockSeting)(VOID *Data);
+    VOID (*HalGdmaChDis)(VOID *Data);
+    VOID (*HalGdmaChEn)(VOID *Data);
+    VOID (*HalGdmaChIsrEnAndDis) (VOID *Data);
+    u8   (*HalGdmaChIsrClean)(VOID *Data);
+    VOID (*HalGdmaChCleanAutoSrc)(VOID *Data);
+    VOID (*HalGdmaChCleanAutoDst)(VOID *Data);
+}HAL_GDMA_OP, *PHAL_GDMA_OP;
+
+typedef struct _HAL_GDMA_OBJ_ {
+    HAL_GDMA_ADAPTER HalGdmaAdapter;
+    IRQ_HANDLE GdmaIrqHandle;
+    u8 Busy;      // is transfering
+} HAL_GDMA_OBJ, *PHAL_GDMA_OBJ;
+
+VOID HalGdmaOpInit(IN  VOID *Data);
+VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+
+extern HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum);
+extern VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum);
+extern PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption);
+extern VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl);
+extern BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj);
+extern VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj);
+extern VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len);
+
+extern const HAL_GDMA_OP _HalGdmaOp;
+extern const HAL_GDMA_CHNL GDMA_Chnl_Option[];
+extern const u16 HalGdmaChnlEn[6];
+
+#endif

component/soc/realtek/8195a/fwlib/hal_gpio.h

@@ -0,0 +1,236 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_GPIO_H_
+#define _HAL_GPIO_H_
+
+#define HAL_GPIO_PIN_INT_MODE       0x80
+
+typedef enum {
+    _PORT_A = 0,
+    _PORT_B = 1,
+    _PORT_C = 2,
+    _PORT_D = 3,
+    _PORT_E = 4,
+    _PORT_F = 5,
+    _PORT_G = 6,
+    _PORT_H = 7,
+    _PORT_I = 8,
+    _PORT_J = 9,
+    _PORT_K = 10,
+
+    _PORT_MAX
+} HAL_GPIO_PORT_NAME;
+
+typedef enum {
+    _PA_0  = (_PORT_A<<4|0),
+    _PA_1  = (_PORT_A<<4|1),
+    _PA_2  = (_PORT_A<<4|2),
+    _PA_3  = (_PORT_A<<4|3),
+    _PA_4  = (_PORT_A<<4|4),
+    _PA_5  = (_PORT_A<<4|5),
+    _PA_6  = (_PORT_A<<4|6),
+    _PA_7  = (_PORT_A<<4|7),
+
+    _PB_0  = (_PORT_B<<4|0),
+    _PB_1  = (_PORT_B<<4|1),
+    _PB_2  = (_PORT_B<<4|2),
+    _PB_3  = (_PORT_B<<4|3),
+    _PB_4  = (_PORT_B<<4|4),
+    _PB_5  = (_PORT_B<<4|5),
+    _PB_6  = (_PORT_B<<4|6),
+    _PB_7  = (_PORT_B<<4|7),
+
+    _PC_0  = (_PORT_C<<4|0),
+    _PC_1  = (_PORT_C<<4|1),
+    _PC_2  = (_PORT_C<<4|2),
+    _PC_3  = (_PORT_C<<4|3),
+    _PC_4  = (_PORT_C<<4|4),
+    _PC_5  = (_PORT_C<<4|5),
+    _PC_6  = (_PORT_C<<4|6),
+    _PC_7  = (_PORT_C<<4|7),
+    _PC_8  = (_PORT_C<<4|8),
+    _PC_9  = (_PORT_C<<4|9),
+
+    _PD_0  = (_PORT_D<<4|0),
+    _PD_1  = (_PORT_D<<4|1),
+    _PD_2  = (_PORT_D<<4|2),
+    _PD_3  = (_PORT_D<<4|3),
+    _PD_4  = (_PORT_D<<4|4),
+    _PD_5  = (_PORT_D<<4|5),
+    _PD_6  = (_PORT_D<<4|6),
+    _PD_7  = (_PORT_D<<4|7),
+    _PD_8  = (_PORT_D<<4|8),
+    _PD_9  = (_PORT_D<<4|9),
+  
+    _PE_0  = (_PORT_E<<4|0),
+    _PE_1  = (_PORT_E<<4|1),
+    _PE_2  = (_PORT_E<<4|2),
+    _PE_3  = (_PORT_E<<4|3),
+    _PE_4  = (_PORT_E<<4|4),
+    _PE_5  = (_PORT_E<<4|5),
+    _PE_6  = (_PORT_E<<4|6),
+    _PE_7  = (_PORT_E<<4|7),
+    _PE_8  = (_PORT_E<<4|8),
+    _PE_9  = (_PORT_E<<4|9),
+    _PE_A  = (_PORT_E<<4|10),
+  
+    _PF_0  = (_PORT_F<<4|0),
+    _PF_1  = (_PORT_F<<4|1),
+    _PF_2  = (_PORT_F<<4|2),
+    _PF_3  = (_PORT_F<<4|3),
+    _PF_4  = (_PORT_F<<4|4),
+    _PF_5  = (_PORT_F<<4|5),
+//    _PF_6  = (_PORT_F<<4|6),
+//    _PF_7  = (_PORT_F<<4|7),
+
+    _PG_0  = (_PORT_G<<4|0),
+    _PG_1  = (_PORT_G<<4|1),
+    _PG_2  = (_PORT_G<<4|2),
+    _PG_3  = (_PORT_G<<4|3),
+    _PG_4  = (_PORT_G<<4|4),
+    _PG_5  = (_PORT_G<<4|5),
+    _PG_6  = (_PORT_G<<4|6),
+    _PG_7  = (_PORT_G<<4|7),
+
+    _PH_0  = (_PORT_H<<4|0),
+    _PH_1  = (_PORT_H<<4|1),
+    _PH_2  = (_PORT_H<<4|2),
+    _PH_3  = (_PORT_H<<4|3),
+    _PH_4  = (_PORT_H<<4|4),
+    _PH_5  = (_PORT_H<<4|5),
+    _PH_6  = (_PORT_H<<4|6),
+    _PH_7  = (_PORT_H<<4|7),
+
+    _PI_0  = (_PORT_I<<4|0),
+    _PI_1  = (_PORT_I<<4|1),
+    _PI_2  = (_PORT_I<<4|2),
+    _PI_3  = (_PORT_I<<4|3),
+    _PI_4  = (_PORT_I<<4|4),
+    _PI_5  = (_PORT_I<<4|5),
+    _PI_6  = (_PORT_I<<4|6),
+    _PI_7  = (_PORT_I<<4|7),
+
+    _PJ_0  = (_PORT_J<<4|0),
+    _PJ_1  = (_PORT_J<<4|1),
+    _PJ_2  = (_PORT_J<<4|2),
+    _PJ_3  = (_PORT_J<<4|3),
+    _PJ_4  = (_PORT_J<<4|4),
+    _PJ_5  = (_PORT_J<<4|5),
+    _PJ_6  = (_PORT_J<<4|6),
+//    _PJ_7  = (_PORT_J<<4|7),
+
+    _PK_0  = (_PORT_K<<4|0),
+    _PK_1  = (_PORT_K<<4|1),
+    _PK_2  = (_PORT_K<<4|2),
+    _PK_3  = (_PORT_K<<4|3),
+    _PK_4  = (_PORT_K<<4|4),
+    _PK_5  = (_PORT_K<<4|5),
+    _PK_6  = (_PORT_K<<4|6),
+//    _PK_7  = (_PORT_K<<4|7),
+
+    // Not connected
+    _PIN_NC = (int)0xFFFFFFFF
+} HAL_PIN_NAME;
+
+typedef enum
+{
+  GPIO_PIN_LOW  = 0,
+  GPIO_PIN_HIGH = 1,
+  GPIO_PIN_ERR  = 2     // read Pin error
+} HAL_GPIO_PIN_STATE;
+
+typedef enum {
+    DIN_PULL_NONE   = 0,    //floating or high impedance ?
+    DIN_PULL_LOW    = 1,
+    DIN_PULL_HIGH   = 2,
+
+    DOUT_PUSH_PULL  = 3,
+    DOUT_OPEN_DRAIN = 4,
+
+    INT_LOW         = (5|HAL_GPIO_PIN_INT_MODE),    // Interrupt Low level trigger
+    INT_HIGH        = (6|HAL_GPIO_PIN_INT_MODE),    // Interrupt High level trigger
+    INT_FALLING     = (7|HAL_GPIO_PIN_INT_MODE),    // Interrupt Falling edge trigger
+    INT_RISING      = (8|HAL_GPIO_PIN_INT_MODE)     // Interrupt Rising edge trigger        
+} HAL_GPIO_PIN_MODE;
+
+enum {
+    GPIO_PORT_A = 0,
+    GPIO_PORT_B = 1,
+    GPIO_PORT_C = 2,
+    GPIO_PORT_D = 3
+};
+
+typedef enum {
+    hal_PullNone  = 0,
+    hal_PullUp    = 1,
+    hal_PullDown  = 2,
+    hal_OpenDrain = 3,
+    hal_PullDefault = hal_PullNone
+} HAL_PinMode;
+
+typedef struct _HAL_GPIO_PORT_ {
+    u32 out_data;       // to write the GPIO port
+    u32 in_data;        // to read the GPIO port
+    u32 dir;            // config each pin direction    
+}HAL_GPIO_PORT, *PHAL_GPIO_PORT;
+
+#define HAL_GPIO_PIN_NAME(port,pin)         (((port)<<5)|(pin))
+#define HAL_GPIO_GET_PORT_BY_NAME(x)        ((x>>5) & 0x03)
+#define HAL_GPIO_GET_PIN_BY_NAME(x)         (x & 0x1f)
+
+typedef struct _HAL_GPIO_PIN_ {
+    HAL_GPIO_PIN_MODE pin_mode;
+    u32 pin_name;    // Pin: [7:5]: port number, [4:0]: pin number
+}HAL_GPIO_PIN, *PHAL_GPIO_PIN;
+
+typedef struct _HAL_GPIO_OP_ {
+#if defined(__ICCARM__)
+    void* dummy;
+#endif
+}HAL_GPIO_OP, *PHAL_GPIO_OP;
+
+typedef void (*GPIO_IRQ_FUN)(VOID *Data, u32 Id);
+typedef void (*GPIO_USER_IRQ_FUN)(u32 Id);
+
+typedef struct _HAL_GPIO_ADAPTER_ {
+    IRQ_HANDLE IrqHandle;   // GPIO HAL IRQ Handle
+    GPIO_USER_IRQ_FUN UserIrqHandler;   // GPIO IRQ Handler
+    GPIO_IRQ_FUN PortA_IrqHandler[32]; // The interrupt handler triggered by Port A[x]
+    VOID *PortA_IrqData[32];
+    VOID (*EnterCritical)(void);
+    VOID (*ExitCritical)(void);
+    u32 Local_Gpio_Dir[3];  // to record direction setting: 0- IN, 1- Out
+    u8 Gpio_Func_En;    // Is GPIO HW function enabled ?
+    u8 Locked;
+}HAL_GPIO_ADAPTER, *PHAL_GPIO_ADAPTER;
+
+u32 
+HAL_GPIO_GetPinName(
+    u32 chip_pin
+);
+
+VOID 
+HAL_GPIO_PullCtrl(
+    u32 pin,
+    u32 mode    
+);
+
+VOID 
+HAL_GPIO_Init(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+VOID 
+HAL_GPIO_Irq_Init(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+#endif  // end of "#define _HAL_GPIO_H_"
+

component/soc/realtek/8195a/fwlib/hal_i2c.h

@@ -0,0 +1,565 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_I2C_H_     //#ifndef _HAL_I2C_H_
+#define _HAL_I2C_H_
+
+#include "rtl8195a_i2c.h"
+#include "hal_gdma.h"
+
+//================= I2C CONFIGURATION START ==================
+// I2C SAL User Configuration Flags
+
+// I2C SAL operation types
+#define I2C_POLL_OP_TYPE            1
+#define I2C_INTR_OP_TYPE            1
+#define I2C_DMA_OP_TYPE             1
+
+// I2C supports user register address
+#define I2C_USER_REG_ADDR           1       //I2C User specific register address by using 
+                                            //the first I2C data as the register 
+                                            //address
+                                            
+// I2C SAL used module. Please set the I2C module flag to 1 to enable the related 
+// I2C module functions.
+#define I2C0_USED                   1
+#define I2C1_USED                   1
+#define I2C2_USED                   1
+#define I2C3_USED                   1
+//================= I2C CONFIGURATION END  ===================
+
+
+//================= I2C HAL START  ==========================
+// I2C debug output
+#define I2C_PREFIX      "RTL8195A[i2c]: "
+#define I2C_PREFIX_LVL  "    [i2c_DBG]: "
+
+typedef enum _I2C_DBG_LVL_ {
+    HAL_I2C_LVL         =   0x01,
+    SAL_I2C_LVL         =   0x02,
+    VERI_I2C_LVL        =   0x03,
+}I2C_DBG_LVL,*PI2C_DBG_LVL;
+
+#ifdef CONFIG_DEBUG_LOG
+#ifdef CONFIG_DEBUG_LOG_I2C_HAL
+#define DBG_I2C_LOG_PERD    100
+
+    #define I2CDBGLVL   0xFF
+    #define DBG_8195A_I2C(...)  do{ \
+                                    _DbgDump("\r"I2C_PREFIX __VA_ARGS__);\
+                                }while(0)
+   
+    #define DBG_8195A_I2C_LVL(LVL,...)  do{\
+                                            if (LVL&I2CDBGLVL){\
+                                                _DbgDump("\r"I2C_PREFIX_LVL __VA_ARGS__);\
+                                            }\
+                                        }while(0)
+#else
+    #define DBG_I2C_LOG_PERD    100
+    #define DBG_8195A_I2C(...)
+    #define DBG_8195A_I2C_LVL(...)
+#endif
+#else
+    #define DBG_I2C_LOG_PERD    100
+    #define DBG_8195A_I2C(...)
+    #define DBG_8195A_I2C_LVL(...)
+#endif
+
+//======================================================
+// I2C HAL related enumeration
+// I2C Module Selection 
+typedef enum _I2C_MODULE_SEL_ {
+        I2C0_SEL    =   0x0,
+        I2C1_SEL    =   0x1,
+        I2C2_SEL    =   0x2,
+        I2C3_SEL    =   0x3,
+}I2C_MODULE_SEL,*PI2C_MODULE_SEL;
+
+// I2C HAL initial data structure 
+typedef struct _HAL_I2C_INIT_DAT_ {
+    u8                  I2CIdx;         //I2C index used
+    u8                  I2CEn;          //I2C module enable
+    u8                  I2CMaster;      //Master or Slave mode
+    u8                  I2CAddrMod;     //I2C addressing mode(7-bit, 10-bit)
+
+    u8                  I2CSpdMod;      //I2C  speed mode(Standard, Fast, High)
+    u8                  I2CSetup;       //I2C SDA setup time
+    u8                  I2CRXTL;        //I2C RX FIFO Threshold
+    u8                  I2CTXTL;        //I2C TX FIFO Threshold
+
+    u8                  I2CBusLd;       //I2C bus load (pf) for high speed mode
+    u8                  I2CReSTR;       //I2C restart support
+    u8                  I2CGC;          //I2C general support
+    u8                  I2CStartB;      //I2C start byte support
+
+    u8                  I2CSlvNoAck;    //I2C slave no ack support
+    u8                  I2CDMACtrl;     //I2C DMA feature support
+    u8                  I2CCmd;         //I2C Command
+    u8                  I2CDataLen;     //I2C Data Length
+
+    u8                  I2CSlvAckGC;    //I2C slave acks to General Call
+    u8                  I2CStop;        //I2C issues STOP bit or not
+    u16                 RSVD0;
+    
+    u8                  *I2CRWData;     //I2C Read/Write data pointer
+
+    u16                 I2CIntrMSK;     //I2C Interrupt Mask
+    u16                 I2CIntrClr;     //I2C Interrupt register to clear 
+
+    u16                 I2CAckAddr;     //I2C target address in I2C Master mode,
+                                        //ack address in I2C Slave mode    
+    u16                 I2CSdaHd;       //I2C SDA hold time
+
+    u32                 I2CClk;         //I2C bus clock (in kHz)
+
+    u8                  I2CTxDMARqLv;   //I2C TX DMA Empty Level
+    u8                  I2CRxDMARqLv;   //I2C RX DMA Full Level
+    u16                 RSVD1;          //Reserved
+}HAL_I2C_INIT_DAT,*PHAL_I2C_INIT_DAT;
+
+// I2C HAL Operations
+typedef struct _HAL_I2C_OP_ {
+    HAL_Status  (*HalI2CInit)       (VOID *Data);   //HAL I2C initialization
+    HAL_Status  (*HalI2CDeInit)     (VOID *Data);   //HAL I2C de-initialization
+    HAL_Status  (*HalI2CSend)       (VOID *Data);   //HAL I2C send
+    u8          (*HalI2CReceive)    (VOID *Data);   //HAL I2C receive
+    HAL_Status  (*HalI2CEnable)     (VOID *Data);   //HAL I2C enable module
+    HAL_Status  (*HalI2CIntrCtrl)   (VOID *Data);   //HAL I2C interrupt control
+    u32         (*HalI2CReadReg)    (VOID *Data, u8 I2CReg);//HAL I2C read register
+    HAL_Status  (*HalI2CWriteReg)   (VOID *Data, u8 I2CReg, u32 RegVal);//HAL I2C write register
+    HAL_Status  (*HalI2CSetCLK)     (VOID *Data);   //HAL I2C set bus clock
+    HAL_Status  (*HalI2CMassSend)   (VOID *Data);   //HAL I2C mass send
+    HAL_Status  (*HalI2CClrIntr)    (VOID *Data);   //HAL I2C clear interrupts
+    HAL_Status  (*HalI2CClrAllIntr) (VOID *Data);   //HAL I2C clear all interrupts
+    HAL_Status  (*HalI2CDMACtrl)    (VOID *Data);   //HAL I2C DMA control
+}HAL_I2C_OP, *PHAL_I2C_OP;
+//================= I2C HAL END   ===========================
+
+
+//================= I2C SAL START  ==========================
+//I2C SAL Macros
+
+//======================================================
+// I2C SAL related enumerations
+// I2C Extend Features
+typedef enum _I2C_EXD_SUPPORT_{
+    I2C_EXD_RESTART     =   0x1,            //BIT_0, RESTART bit
+    I2C_EXD_GENCALL     =   0x2,            //BIT_1, Master generates General Call. All "send" operations generate General Call addresss
+    I2C_EXD_STARTB      =   0x4,            //BIT_2, Using START BYTE, instead of START Bit
+    I2C_EXD_SLVNOACK    =   0x8,            //BIT_3, Slave no ack to master
+    I2C_EXD_BUS400PF    =   0x10,           //BIT_4, I2C bus loading is 400pf
+    I2C_EXD_SLVACKGC    =   0x20,           //BIT_5, Slave acks to a General Call
+    I2C_EXD_USER_REG    =   0x40,           //BIT_6, Using User Register Address
+    I2C_EXD_USER_TWOB   =   0x80,           //BIT_7, User Register Address is 2-byte
+    I2C_EXD_MTR_ADDR_RTY=   0x100,          //BIT_8, Master retries to send start condition and Slave address when the slave doesn't ack 
+                                            //         the address.
+    I2C_EXD_MTR_ADDR_UPD=   0x200,         //BIT_9, Master dynamically updates slave address
+    I2C_EXD_MTR_HOLD_BUS=   0x400,         //BIT_10, Master doesn't generate STOP when the FIFO is empty. This would make Master hold
+                                            //         the bus.
+}I2C_EXD_SUPPORT,*PI2C_EXD_SUPPORT;
+
+// I2C operation type
+typedef enum _I2C_OP_TYPE_ {
+    I2C_POLL_TYPE   =   0x0,
+    I2C_DMA_TYPE    =   0x1,
+    I2C_INTR_TYPE   =   0x2,
+}I2C_OP_TYPE, *PI2C_OP_TYPE;
+
+// I2C pinmux selection 
+typedef enum _I2C_PINMUX_ {
+    I2C_PIN_S0      =   0x0,
+    I2C_PIN_S1      =   0x1,
+    I2C_PIN_S2      =   0x2,
+    I2C_PIN_S3      =   0x3,    //Only valid for I2C0 and I2C3
+}I2C_PINMUX, *PI2C_PINMUX;
+
+// I2C module status 
+typedef enum _I2C_MODULE_STATUS_ {
+    I2C_DISABLE     =   0x0,
+    I2C_ENABLE      =   0x1,
+}I2C_MODULE_STATUS, *PI2C_MODULE_STATUS;
+
+// I2C device status 
+typedef enum _I2C_Device_STATUS_ {
+    I2C_STS_UNINITIAL   =   0x00,
+    I2C_STS_INITIALIZED =   0x01,
+    I2C_STS_IDLE        =   0x02,
+    
+    I2C_STS_TX_READY    =   0x03,    
+    I2C_STS_TX_ING      =   0x04,
+    
+    I2C_STS_RX_READY    =   0x05,
+    I2C_STS_RX_ING      =   0x06,
+
+    I2C_STS_ERROR       =   0x10,
+    I2C_STS_TIMEOUT     =   0x11, 
+}I2C_Device_STATUS, *PI2C_Device_STATUS;
+
+// I2C feature status 
+typedef enum _I2C_FEATURE_STATUS_{
+    I2C_FEATURE_DISABLED    =   0,
+    I2C_FEATURE_ENABLED     =   1,
+}I2C_FEATURE_STATUS,*PI2C_FEATURE_STATUS;
+
+// I2C device mode
+typedef enum _I2C_DEV_MODE_ {
+    I2C_SLAVE_MODE  =   0x0,
+    I2C_MASTER_MODE =   0x1,
+}I2C_DEV_MODE, *PI2C_DEV_MODE;
+
+// I2C Bus Transmit/Receive
+typedef enum _I2C_DIRECTION_ {
+    I2C_ONLY_TX     =   0x1,
+    I2C_ONLY_RX     =   0x2,
+    I2C_TXRX        =   0x3,
+}I2C_DIRECTION, *PI2C_DIRECTION;
+
+//I2C DMA module number
+typedef enum _I2C_DMA_MODULE_SEL_ {
+    I2C_DMA_MODULE_0    =   0x0,
+    I2C_DMA_MODULE_1    =   0x1
+}I2C_DMA_MODULE_SEL, *PI2C_DMA_MODULE_SEL;
+
+// I2C0 DMA peripheral number
+typedef enum _I2C0_DMA_PERI_NUM_ {
+    I2C0_DMA_TX_NUM =   0x8,
+    I2C0_DMA_RX_NUM =   0x9,
+}I2C0_DMA_PERI_NUM,*PI2C0_DMA_PERI_NUM;
+
+// I2C1 DMA peripheral number
+typedef enum _I2C1_DMA_PERI_NUM_ {
+    I2C1_DMA_TX_NUM =   0xA,
+    I2C1_DMA_RX_NUM =   0xB,
+}I2C1_DMA_PERI_NUM,*PI2C1_DMA_PERI_NUM;
+
+// I2C0 DMA module used
+typedef enum _I2C0_DMA_MODULE_ {
+    I2C0_DMA0   =   0x0,
+    I2C0_DMA1   =   0x1,
+}I2C0_DMA_MODULE,*PI2C0_DMA_MODULE;
+
+// I2C0 DMA module used
+typedef enum _I2C1_DMA_MODULE_ {
+    I2C1_DMA0   =   0x0,
+    I2C1_DMA1   =   0x1,
+}I2C1_DMA_MODULE,*PI2C1_DMA_MODULE;
+
+// I2C command type 
+typedef enum _I2C_COMMAND_TYPE_ {
+    I2C_WRITE_CMD   =   0x0,
+    I2C_READ_CMD    =   0x1,
+}I2C_COMMAND_TYPE,*PI2C_COMMAND_TYPE;
+
+// I2C STOP BIT 
+typedef enum _I2C_STOP_TYPE_ {
+    I2C_STOP_DIS    =   0x0,
+    I2C_STOP_EN     =   0x1,
+}I2C_STOP_TYPE, *PI2C_STOP_TYPE;
+
+// I2C error type 
+typedef enum _I2C_ERR_TYPE_ {
+    I2C_ERR_RX_UNDER    =   0x01,           //I2C RX FIFO Underflow
+    I2C_ERR_RX_OVER     =   0x02,           //I2C RX FIFO Overflow
+    I2C_ERR_TX_OVER     =   0x04,           //I2C TX FIFO Overflow
+    I2C_ERR_TX_ABRT     =   0x08,           //I2C TX terminated
+    I2C_ERR_SLV_TX_NACK =   0x10,           //I2C slave transmission terminated by master NACK, 
+                                            //but there are data in slave TX FIFO
+    I2C_ERR_USER_REG_TO =   0x20,
+
+    I2C_ERR_RX_CMD_TO   =   0x21,
+    I2C_ERR_RX_FF_TO    =   0x22,
+    I2C_ERR_TX_CMD_TO   =   0x23,
+    I2C_ERR_TX_FF_TO    =   0x24,
+
+    I2C_ERR_TX_ADD_TO   =   0x25,
+    I2C_ERR_RX_ADD_TO   =   0x26,
+}I2C_ERR_TYPE, *PI2C_ERR_TYPE;
+
+// I2C Time Out type
+typedef enum _I2C_TIMEOUT_TYPE_ {
+    I2C_TIMEOOUT_DISABLE    =   0x00,           
+    I2C_TIMEOOUT_ENDLESS    =   0xFFFFFFFF,
+}I2C_TIMEOUT_TYPE, *PI2C_TIMEOUT_TYPE;
+
+//======================================================
+// SAL I2C related data structures
+// I2C user callback adapter
+typedef struct _SAL_I2C_USERCB_ADPT_ {
+    VOID (*USERCB)      (VOID *Data);
+    u32  USERData;
+}SAL_I2C_USERCB_ADPT, *PSAL_I2C_USERCB_ADPT;
+
+// I2C user callback structure
+typedef struct _SAL_I2C_USER_CB_ {
+    PSAL_I2C_USERCB_ADPT    pTXCB;          //I2C Transmit Callback
+    PSAL_I2C_USERCB_ADPT    pTXCCB;         //I2C Transmit Complete Callback
+    PSAL_I2C_USERCB_ADPT    pRXCB;          //I2C Receive Callback
+    PSAL_I2C_USERCB_ADPT    pRXCCB;         //I2C Receive Complete Callback
+    PSAL_I2C_USERCB_ADPT    pRDREQCB;       //I2C Read Request Callback
+    PSAL_I2C_USERCB_ADPT    pERRCB;         //I2C Error Callback
+    PSAL_I2C_USERCB_ADPT    pDMATXCB;       //I2C DMA Transmit Callback
+    PSAL_I2C_USERCB_ADPT    pDMATXCCB;      //I2C DMA Transmit Complete Callback
+    PSAL_I2C_USERCB_ADPT    pDMARXCB;       //I2C DMA Receive Callback
+    PSAL_I2C_USERCB_ADPT    pDMARXCCB;      //I2C DMA Receive Complete Callback
+    PSAL_I2C_USERCB_ADPT    pGENCALLCB;     //I2C General Call Callback
+}SAL_I2C_USER_CB, *PSAL_I2C_USER_CB;
+
+// I2C Transmit Buffer
+typedef struct _SAL_I2C_TRANSFER_BUF_ {
+    u16     DataLen;                        //I2C Transmfer Length
+    u16     TargetAddr;                     //I2C Target Address. It's only valid in Master Mode.
+    u32     RegAddr;                        //I2C Register Address. It's only valid in Master Mode.
+    u32     RSVD;                           //
+    u8      *pDataBuf;                      //I2C Transfer Buffer Pointer
+}SAL_I2C_TRANSFER_BUF,*PSAL_I2C_TRANSFER_BUF;
+
+typedef struct _SAL_I2C_DMA_USER_DEF_ {
+    u8      TxDatSrcWdth;
+    u8      TxDatDstWdth;
+    u8      TxDatSrcBstSz;
+    u8      TxDatDstBstSz;
+    u8      TxChNo;
+    u8      RSVD0;
+    u16     RSVD1;
+    u8      RxDatSrcWdth;
+    u8      RxDatDstWdth;
+    u8      RxDatSrcBstSz;
+    u8      RxDatDstBstSz;
+    u8      RxChNo;
+    u8      RSVD2;
+    u16     RSVD3;
+}SAL_I2C_DMA_USER_DEF, *PSAL_I2C_DMA_USER_DEF;
+
+// RTK I2C OP
+typedef struct _RTK_I2C_OP_ {
+    HAL_Status (*Init)      (VOID *Data);
+    HAL_Status (*DeInit)    (VOID *Data);
+    HAL_Status (*Send)      (VOID *Data);
+    HAL_Status (*Receive)   (VOID *Data);
+    HAL_Status (*IoCtrl)    (VOID *Data);
+    HAL_Status (*PowerCtrl) (VOID *Data);    
+}RTK_I2C_OP, *PRTK_I2C_OP;
+
+// Software API Level I2C Handler 
+typedef struct _SAL_I2C_HND_ {
+    u8                      DevNum;             //I2C device number
+    u8                      PinMux;             //I2C pin mux seletion
+    u8                      OpType;             //I2C operation type selection
+    volatile u8             DevSts;             //I2C device status
+    
+    u8                      I2CMaster;          //I2C Master or Slave mode
+    u8                      I2CAddrMod;         //I2C 7-bit or 10-bit mode
+    u8                      I2CSpdMod;          //I2C SS/ FS/ HS speed mode
+    u8                      I2CAckAddr;         //I2C target address in Master 
+                                                //mode or ack address in Slave
+                                                //mode
+                                                
+    u16                     I2CClk;             //I2C bus clock
+    u8                      MasterRead;         //I2C Master Read Supported,
+                                                //An Address will be sent before
+                                                //read data back.
+                                                
+    u8                      I2CDmaSel;          //I2C DMA module select
+                                                //         0 for DMA0,
+                                                //         1 for DMA1
+    u8                      I2CTxDMARqLv;       //I2C TX DMA Empty Level
+    u8                      I2CRxDMARqLv;       //I2C RX DMA Full Level
+    u16                     RSVD0;              //Reserved
+
+    u32                     RSVD1;              //Reserved
+    
+    u32                     I2CExd;             //I2C extended options:
+                                                //bit 0: I2C RESTART supported,
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 1: I2C General Call supported
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 2: I2C START Byte supported
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 3: I2C Slave-No-Ack
+                                                //         supported
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 4: I2C bus loading,
+                                                //          0 for 100pf, 
+                                                //          1  for 400pf
+                                                //bit 5: I2C slave ack to General
+                                                //         Call
+                                                //bit 6: I2C User register address
+                                                //bit 7: I2C 2-Byte User register
+                                                //         address
+                                                //bit 8: I2C slave address no ack retry,
+                                                //        It's only for Master mode,
+                                                //        when slave doesn't ack the
+                                                //        address
+                                                //bit 31~bit 8: Reserved
+    u32                     ErrType;            //
+    u32                     TimeOut;            //I2C IO Timeout count,  in ms
+                                                                            
+    PHAL_I2C_INIT_DAT       pInitDat;           //Pointer to I2C initial data struct
+    PSAL_I2C_TRANSFER_BUF   pTXBuf;             //Pointer to I2C TX buffer
+    PSAL_I2C_TRANSFER_BUF   pRXBuf;             //Pointer to I2C RX buffer
+    PSAL_I2C_USER_CB        pUserCB;            //Pointer to I2C User Callback
+    PSAL_I2C_DMA_USER_DEF   pDMAConf;           //Pointer to I2C User Define DMA config
+}SAL_I2C_HND, *PSAL_I2C_HND;
+
+
+
+//======================================================
+// I2C SAL Function Prototypes
+
+// For checking I2C input index valid or not
+static inline HAL_Status
+RtkI2CIdxChk(
+    IN  u8  I2CIdx
+)
+{
+    if (I2CIdx > I2C3_SEL)
+        return HAL_ERR_UNKNOWN;
+        
+    return HAL_OK;
+}
+#if 0
+//For checking I2C operation type valid or not
+static inline HAL_Status
+RtkI2COpTypeChk(
+    IN  VOID *Data
+)
+{
+    PSAL_I2C_HND    pSalI2CHND = (PSAL_I2C_HND) Data;
+
+    if (pSalI2CHND->OpType == I2C_POLL_TYPE)
+        return HAL_ERR_UNKNOWN;
+
+    if (pSalI2CHND->OpType == I2C_DMA_TYPE)
+        return HAL_ERR_UNKNOWN;
+
+    if (pSalI2CHND->OpType == I2C_INTR_TYPE)
+        return HAL_ERR_UNKNOWN;
+
+    pSalI2CHND = pSalI2CHND;
+    
+    return HAL_OK;
+}
+#endif
+//For checking I2C DMA available or not
+static inline HAL_Status
+RtkI2CDMAChk(
+    IN  VOID *Data
+)
+{
+    PSAL_I2C_HND    pSalI2CHND = (PSAL_I2C_HND) Data;
+
+    if (pSalI2CHND->OpType == I2C_DMA_TYPE) {
+        if (pSalI2CHND->DevNum >= I2C2_SEL)
+            return HAL_ERR_UNKNOWN;
+    }
+    else {
+        return HAL_ERR_UNKNOWN;
+    }
+
+    return HAL_OK;
+}
+
+//For checking I2C DMA available or not
+static inline HAL_Status
+RtkI2CDMAInitChk(
+    IN  VOID *Data
+)
+{
+    PSAL_I2C_HND    pSalI2CHND = (PSAL_I2C_HND) Data;
+
+    if (pSalI2CHND->OpType != I2C_DMA_TYPE) {
+        return HAL_ERR_UNKNOWN;
+    }
+    else {
+        return HAL_OK;
+    }
+    
+}
+
+//======================================================
+//SAL I2C management function prototype
+_LONG_CALL_ HAL_Status RtkI2CLoadDefault(IN VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CInit(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CDeInit(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CSend(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CReceive(IN  VOID *Data);
+_LONG_CALL_ VOID RtkSalI2COpInit(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CSendUserAddr(IN  VOID *Data,IN  u8  MtrWr);
+_LONG_CALL_ HAL_Status RtkI2CIoCtrl(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CPowerCtrl(IN  VOID *Data);
+//================= I2C SAL END   ===========================
+
+
+//================= I2C SAL MANAGEMENT START  =================
+// I2C SAL management macros
+#define SAL_USER_CB_NUM     (sizeof(SAL_I2C_USER_CB) / sizeof(PSAL_I2C_USERCB_ADPT))
+
+//======================================================
+// I2C SAL management data structures
+// I2C SAL handle private 
+typedef struct _SAL_I2C_HND_PRIV_ {
+    VOID            **ppSalI2CHnd;              //Pointer to SAL_I2C_HND pointer
+    SAL_I2C_HND     SalI2CHndPriv;              //Private SAL_I2C_HND
+}SAL_I2C_HND_PRIV, *PSAL_I2C_HND_PRIV;
+
+//I2C SAL management adapter
+typedef struct _SAL_I2C_MNGT_ADPT_ {
+    PSAL_I2C_HND_PRIV       pSalHndPriv;                //Pointer to SAL_I2C_HND
+    PHAL_I2C_INIT_DAT       pHalInitDat;                //Pointer to HAL I2C initial data( HAL_I2C_INIT_DAT )
+    PHAL_I2C_OP             pHalOp;                     //Pointer to HAL I2C operation( HAL_I2C_OP )
+    VOID                    (*pHalOpInit)(VOID*);       //Pointer to HAL I2C initialize function
+    PIRQ_HANDLE             pIrqHnd;                    //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
+    PSAL_I2C_USER_CB        pUserCB;                    //Pointer to SAL user callbacks (SAL_I2C_USER_CB )
+    volatile u32            MstRDCmdCnt;                //Used for Master Read command count
+    volatile u32            InnerTimeOut;               //Used for SAL internal timeout count
+    VOID                    (*pSalIrqFunc)(VOID*);      //Used for SAL I2C interrupt function
+    
+    PSAL_I2C_DMA_USER_DEF   pDMAConf;                   //Pointer to I2C User Define DMA config
+    PHAL_GDMA_ADAPTER       pHalTxGdmaAdp;              //Pointer to HAL_GDMA_ADAPTER
+    PHAL_GDMA_ADAPTER       pHalRxGdmaAdp;              //Pointer to HAL_GDMA_ADAPTER
+    PHAL_GDMA_OP            pHalGdmaOp;                 //Pointer to HAL_GDMA_OP
+    VOID                    (*pHalGdmaOpInit)(VOID*);   //Pointer to HAL I2C initialize function
+    PIRQ_HANDLE             pIrqTxGdmaHnd;              //Pointer to IRQ handler for Tx GDMA
+    PIRQ_HANDLE             pIrqRxGdmaHnd;              //Pointer to IRQ handler for Rx GDMA
+    VOID                    (*pSalDMATxIrqFunc)(VOID*); //Used for SAL I2C interrupt function
+    VOID                    (*pSalDMARxIrqFunc)(VOID*); //Used for SAL I2C interrupt function
+    u32                     RSVD;                       //Reserved
+}SAL_I2C_MNGT_ADPT, *PSAL_I2C_MNGT_ADPT;
+
+//======================================================
+//SAL I2C management function prototype
+PSAL_I2C_MNGT_ADPT RtkI2CGetMngtAdpt(IN u8 I2CIdx);
+HAL_Status RtkI2CFreeMngtAdpt(IN  PSAL_I2C_MNGT_ADPT  pSalI2CMngtAdpt);
+PSAL_I2C_HND RtkI2CGetSalHnd(IN  u8  I2CIdx);
+HAL_Status RtkI2CFreeSalHnd(IN  PSAL_I2C_HND    pSalI2CHND);
+u32 RtkSalI2CSts(IN  VOID *Data);
+
+extern _LONG_CALL_ VOID I2CISRHandle(IN  VOID *Data);
+extern _LONG_CALL_ VOID I2CTXGDMAISRHandle(IN  VOID *Data);
+extern _LONG_CALL_ VOID I2CRXGDMAISRHandle(IN  VOID *Data);
+extern HAL_Status I2CIsTimeout (IN  u32 StartCount, IN  u32 TimeoutCnt);
+extern HAL_TIMER_OP        HalTimerOp;
+//======================================================
+// Function Prototypes
+_LONG_CALL_ VOID HalI2COpInit(IN VOID *Data);
+//================= I2C SAL MANAGEMENT END   ==================
+
+//================= Rtl8195a I2C V02 function prototype  ============
+_LONG_CALL_ VOID HalI2COpInitV02(IN  VOID *Data);
+_LONG_CALL_ VOID I2CISRHandleV02(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CSendV02(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CReceiveV02(IN  VOID *Data);
+_LONG_CALL_ VOID RtkSalI2COpInitV02(IN  VOID *Data);
+//================= Rtl8195a I2C V02 function prototype  END==========
+
+#endif                  //#ifndef _HAL_I2C_H_

component/soc/realtek/8195a/fwlib/hal_i2s.h

@@ -0,0 +1,333 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_I2S_H_
+#define _HAL_I2S_H_
+
+#include "rtl8195a_i2s.h"
+
+/* User Define Flags */
+
+#define I2S_MAX_ID                  1   // valid I2S index 0 ~ I2S_MAX_ID
+
+/**********************************************************************/
+/* I2S HAL initial data structure */
+typedef struct _HAL_I2S_INIT_DAT_ {
+    u8                  I2SIdx;         /*I2S index used*/
+    u8                  I2SEn;          /*I2S module enable tx/rx/tx+rx*/
+    u8                  I2SMaster;      /*I2S Master or Slave mode*/
+    u8                  I2SWordLen;     /*I2S Word length 16 or 24bits*/
+
+    u8                  I2SChNum;       /*I2S Channel number mono or stereo*/
+    u8                  I2SPageNum;     /*I2S Page Number 2~4*/
+    u16                 I2SPageSize;    /*I2S page Size 1~4096 word*/
+
+    u8                  *I2STxData;     /*I2S Tx data pointer*/
+
+    u8                  *I2SRxData;     /*I2S Rx data pointer*/
+
+    u32                 I2STxIntrMSK;   /*I2S Tx Interrupt Mask*/
+    u32                 I2STxIntrClr;   /*I2S Tx Interrupt register to clear */
+
+    u32                 I2SRxIntrMSK;   /*I2S Rx Interrupt Mask*/
+    u32                 I2SRxIntrClr;   /*I2S Rx Interrupt register to clear*/
+
+	u16                 I2STxIdx;       /*I2S TX page index */
+	u16                 I2SRxIdx;       /*I2S RX page index */
+
+	u16                 I2SHWTxIdx;       /*I2S HW TX page index */
+	u16                 I2SHWRxIdx;       /*I2S HW RX page index */
+
+	
+    u16                 I2SRate;        /*I2S sample rate*/
+    u8                  I2STRxAct;      /*I2S tx rx act*/	
+}HAL_I2S_INIT_DAT, *PHAL_I2S_INIT_DAT;
+
+/**********************************************************************/
+/* I2S Data Structures */
+/* I2S Module Selection */
+typedef enum _I2S_MODULE_SEL_ {
+        I2S0_SEL    =   0x0,
+        I2S1_SEL    =   0x1,
+}I2S_MODULE_SEL,*PI2S_MODULE_SEL;
+/*
+typedef struct _HAL_I2S_ADAPTER_ {
+    u32                       Enable:1;
+    I2S_CTL_REG               I2sCtl;
+    I2S_SETTING_REG           I2sSetting;
+    u32                       abc;
+    u8                        I2sIndex;
+}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
+*/
+/* I2S HAL Operations */
+typedef struct _HAL_I2S_OP_ {
+    RTK_STATUS  (*HalI2SInit)       (VOID *Data);
+    RTK_STATUS  (*HalI2SDeInit)     (VOID *Data);
+    RTK_STATUS  (*HalI2STx)       (VOID *Data, u8 *pBuff);
+    RTK_STATUS  (*HalI2SRx)       (VOID *Data, u8 *pBuff);
+    RTK_STATUS  (*HalI2SEnable)     (VOID *Data);
+    RTK_STATUS  (*HalI2SIntrCtrl)   (VOID *Data);
+    u32         (*HalI2SReadReg)    (VOID *Data, u8 I2SReg);
+    RTK_STATUS  (*HalI2SSetRate)    (VOID *Data);
+    RTK_STATUS  (*HalI2SSetWordLen) (VOID *Data);
+    RTK_STATUS  (*HalI2SSetChNum)   (VOID *Data);
+    RTK_STATUS  (*HalI2SSetPageNum) (VOID *Data);
+    RTK_STATUS  (*HalI2SSetPageSize) (VOID *Data);
+
+    RTK_STATUS  (*HalI2SClrIntr)    (VOID *Data);
+    RTK_STATUS  (*HalI2SClrAllIntr) (VOID *Data);
+    RTK_STATUS  (*HalI2SDMACtrl)    (VOID *Data); 
+/*
+    VOID (*HalI2sOnOff)(VOID *Data);
+    BOOL (*HalI2sInit)(VOID *Data);
+    BOOL (*HalI2sSetting)(VOID *Data);
+    BOOL (*HalI2sEn)(VOID *Data);
+    BOOL (*HalI2sIsrEnAndDis) (VOID *Data);
+    BOOL (*HalI2sDumpReg)(VOID *Data);
+    BOOL (*HalI2s)(VOID *Data);
+*/
+}HAL_I2S_OP, *PHAL_I2S_OP;
+
+
+/**********************************************************************/
+
+/* I2S Pinmux Selection */
+#if 0
+typedef enum _I2S0_PINMUX_ {
+    I2S0_TO_S0      =   0x0,
+    I2S0_TO_S1      =   0x1,
+    I2S0_TO_S2      =   0x2,
+}I2S0_PINMUX, *PI2S0_PINMUX;
+
+typedef enum _I2S1_PINMUX_ {
+    I2S1_TO_S0      =   0x0,
+    I2S1_TO_S1      =   0x1,
+}I2S1_PINMUX, *PI2S1_PINMUX;
+#endif
+
+typedef enum _I2S_PINMUX_ {
+    I2S_S0      =   0,
+    I2S_S1      =   1,
+    I2S_S2      =   2,
+    I2S_S3      =   3
+}I2S_PINMUX, *PI2S_PINMUX;
+
+
+/* I2S Module Status */
+typedef enum _I2S_MODULE_STATUS_ {
+    I2S_DISABLE     =   0x0,
+    I2S_ENABLE      =   0x1,
+}I2S_MODULE_STATUS, *PI2S_MODULE_STATUS;
+
+
+/* I2S Device Status */
+typedef enum _I2S_Device_STATUS_ {
+    I2S_STS_UNINITIAL   =   0x00,
+    I2S_STS_INITIALIZED =   0x01,
+    I2S_STS_IDLE        =   0x02,
+    
+    I2S_STS_TX_READY    =   0x03,    
+    I2S_STS_TX_ING      =   0x04,
+    
+    I2S_STS_RX_READY    =   0x05,
+    I2S_STS_RX_ING      =   0x06,
+
+    I2S_STS_TRX_READY   =   0x07,    
+    I2S_STS_TRX_ING     =   0x08,
+    
+    I2S_STS_ERROR       =   0x09,
+}I2S_Device_STATUS, *PI2S_Device_STATUS;
+
+
+/* I2S Feature Status */
+typedef enum _I2S_FEATURE_STATUS_{
+    I2S_FEATURE_DISABLED    =   0,
+    I2S_FEATURE_ENABLED     =   1,
+}I2S_FEATURE_STATUS,*PI2S_FEATURE_STATUS;
+
+/* I2S Device Mode */
+typedef enum _I2S_DEV_MODE_ {
+	I2S_MASTER_MODE =   0x0,
+    I2S_SLAVE_MODE  =   0x1
+}I2S_DEV_MODE, *PI2S_DEV_MODE;
+
+/* I2S Word Length */
+typedef enum _I2S_WORD_LEN_ {
+	I2S_WL_16 = 0x0,
+    I2S_WL_24 = 0x1,    
+}I2S_WORD_LEN, *PI2S_WORD_LEN;
+
+/* I2S Bus Transmit/Receive */
+typedef enum _I2S_DIRECTION_ {
+    I2S_ONLY_RX     =   0x0,
+    I2S_ONLY_TX     =   0x1,
+    I2S_TXRX        =   0x2
+}I2S_DIRECTION, *PI2S_DIRECTION;
+
+/* I2S Channel number */
+typedef enum _I2S_CH_NUM_ {
+    I2S_CH_STEREO   =   0x0,
+    I2S_CH_RSVD     =   0x1,
+    I2S_CH_MONO     =   0x2
+}I2S_CH_NUM, *PI2S_CH_NUM;
+
+/* I2S Page number */
+typedef enum _I2S_PAGE_NUM_ {
+    I2S_1PAGE       =   0x0,
+    I2S_2PAGE       =   0x1,
+    I2S_3PAGE       =   0x2,
+    I2S_4PAGE       =   0x3
+}I2S_PAGE_NUM, *PI2S_PAGE_NUM;
+
+/* I2S Sample rate*/
+typedef enum _I2S_SAMPLE_RATE_ {
+    I2S_SR_8KHZ     =   0x00,	// /12
+    I2S_SR_16KHZ    =   0x01,	// /6
+    I2S_SR_24KHZ    =   0x02,	// /4
+	I2S_SR_32KHZ	= 	0x03,	// /3
+    I2S_SR_48KHZ    =   0x05,	// /2
+	I2S_SR_96KHZ	=	0x06,	// x1, base 96kHz
+	I2S_SR_7p35KHZ	= 	0x10,
+	I2S_SR_11p02KHZ	= 	0x11,
+	I2S_SR_22p05KHZ	= 	0x12,
+	I2S_SR_29p4KHZ	= 	0x13,
+	I2S_SR_44p1KHZ	= 	0x15,	
+	I2S_SR_88p2KHZ	= 	0x16	// x1, base 88200Hz
+}I2S_SAMPLE_RATE, *PI2S_SAMPLE_RATE;
+
+/* I2S TX interrupt mask/status */
+typedef enum _I2S_TX_IMR_ {
+    I2S_TX_INT_PAGE0_OK = (1<<0),
+    I2S_TX_INT_PAGE1_OK = (1<<1),
+    I2S_TX_INT_PAGE2_OK = (1<<2),
+    I2S_TX_INT_PAGE3_OK = (1<<3),
+    I2S_TX_INT_FULL     = (1<<4),
+    I2S_TX_INT_EMPTY    = (1<<5)    
+} I2S_TX_IMR, *PI2S_TX_IMR;
+
+/* I2S RX interrupt mask/status */
+typedef enum _I2S_RX_IMR_ {
+    I2S_RX_INT_PAGE0_OK = (1<<0),
+    I2S_RX_INT_PAGE1_OK = (1<<1),
+    I2S_RX_INT_PAGE2_OK = (1<<2),
+    I2S_RX_INT_PAGE3_OK = (1<<3),
+    I2S_RX_INT_EMPTY    = (1<<4),
+    I2S_RX_INT_FULL     = (1<<5)    
+} I2S_RX_IMR, *PI2S_RX_IMR;
+
+/* I2S User Callbacks */
+typedef struct _SAL_I2S_USER_CB_{
+    VOID (*TXCB)        (VOID *Data);
+    VOID (*TXCCB)       (VOID *Data);
+    VOID (*RXCB)        (VOID *Data);
+    VOID (*RXCCB)       (VOID *Data);
+    VOID (*RDREQCB)     (VOID *Data);
+    VOID (*ERRCB)       (VOID *Data);
+    VOID (*GENCALLCB)   (VOID *Data);
+}SAL_I2S_USER_CB,*PSAL_I2S_USER_CB;
+
+typedef struct _I2S_USER_CB_{
+    VOID (*TxCCB)(uint32_t id, char *pbuf);
+    u32 TxCBId;
+    VOID (*RxCCB)(uint32_t id, char *pbuf);
+    u32 RxCBId;
+}I2S_USER_CB,*PI2S_USER_CB;
+
+/* Software API Level I2S Handler */
+typedef struct _HAL_I2S_ADAPTER_{
+    u8                      DevNum;             //I2S device number
+    u8                      PinMux;             //I2S pin mux seletion
+    u8                      RSVD0;              //Reserved
+    volatile u8             DevSts;             //I2S device status
+    
+    u32                     RSVD2;              //Reserved
+    u32                     I2SExd;             //I2S extended options:
+                                                //bit 0: I2C RESTART supported,
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 1: I2C General Call supported
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 2: I2C START Byte supported
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 3: I2C Slave-No-Ack
+                                                //         supported
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 4: I2C bus loading,
+                                                //          0 for 100pf, 
+                                                //          1  for 400pf
+                                                //bit 5: I2C slave ack to General
+                                                //         Call
+                                                //bit 6: I2C User register address
+                                                //bit 7: I2C 2-Byte User register
+                                                //         address
+                                                //bit 31~bit 8: Reserved
+    u32                     ErrType;         //
+    u32                     TimeOut;            //I2S IO Timeout count
+                                                                            
+    PHAL_I2S_INIT_DAT       pInitDat;           //Pointer to I2S initial data struct
+    I2S_USER_CB             UserCB;            //Pointer to I2S User Callback
+    IRQ_HANDLE              IrqHandle;          // Irq Handler
+
+    u32* TxPageList[4];       // The Tx DAM buffer: pointer of each page
+    u32* RxPageList[4];       // The Tx DAM buffer: pointer of each page
+}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
+
+typedef struct _HAL_I2S_DEF_SETTING_{
+    u8 I2SMaster;           // Master or Slave mode
+    u8 DevSts;             //I2S device status
+    u8 I2SChNum;           //I2S Channel number mono or stereo
+    u8 I2SPageNum;         //I2S Page number 2~4
+    u8  I2STRxAct;          //I2S tx rx act, tx only or rx only or tx+rx
+    u8  I2SWordLen;         //I2S Word length 16bit or 24bit
+    u16 I2SPageSize;        //I2S Page size 1~4096 word
+                                                
+    u16 I2SRate;            //I2S sample rate 8k ~ 96khz
+    
+    u32 I2STxIntrMSK;   /*I2S Tx Interrupt Mask*/
+    u32 I2SRxIntrMSK;   /*I2S Rx Interrupt Mask*/
+}HAL_I2S_DEF_SETTING, *PHAL_I2S_DEF_SETTING;
+
+
+
+/**********************************************************************/
+HAL_Status
+RtkI2SLoadDefault(IN  VOID *Adapter, IN  VOID *Setting);
+
+HAL_Status
+RtkI2SInit(IN  VOID *Data);
+
+HAL_Status
+RtkI2SDeInit(IN  VOID *Data);
+
+HAL_Status
+RtkI2SEnable(IN  VOID *Data);
+
+HAL_Status
+RtkI2SDisable(IN  VOID *Data);
+
+
+/**********************************************************************/
+
+
+VOID I2S0ISRHandle(VOID *Data);
+VOID I2S1ISRHandle(VOID *Data);
+
+
+/**********************************************************************/
+
+VOID HalI2SOpInit(
+    IN  VOID *Data
+);
+
+
+#endif
+

component/soc/realtek/8195a/fwlib/hal_irqn.h

@@ -0,0 +1,111 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_IRQN_H_
+#define _HAL_IRQN_H_
+
+#define PERIPHERAL_IRQ_BASE_NUM     64
+
+typedef enum _IRQn_Type_ {
+#if 0
+/******  Cortex-M3 Processor Exceptions Numbers ********/  
+    NON_MASKABLE_INT_IRQ            = -14,
+    HARD_FAULT_IRQ                  = -13,
+    MEM_MANAGE_FAULT_IRQ            = -12,
+    BUS_FAULT_IRQ                   = -11,
+    USAGE_FAULT_IRQ                 = -10,
+    SVCALL_IRQ                      = -5,
+    DEBUG_MONITOR_IRQ               = -4,
+    PENDSVC_IRQ                     = -2,
+    SYSTICK_IRQ                     = -1,
+#else    
+/******  Cortex-M3 Processor Exceptions Numbers ********/  
+    NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                         */
+    HardFault_IRQn                  = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
+    MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
+    BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
+    UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
+    SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
+    DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
+    PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
+    SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
+#endif
+/******  RTL8195A Specific Interrupt Numbers ************/
+    SYSTEM_ON_IRQ                   =  0,
+    WDG_IRQ                         =  1,
+    TIMER0_IRQ                      =  2,
+    TIMER1_IRQ                      =  3,
+    I2C3_IRQ                        =  4,
+    TIMER2_7_IRQ                    =  5,
+    SPI0_IRQ                        =  6,
+    GPIO_IRQ                        =  7,
+    UART0_IRQ                       =  8,
+    SPI_FLASH_IRQ                   =  9,
+    USB_OTG_IRQ                     =  10,
+    SDIO_HOST_IRQ                   =  11,
+    SDIO_DEVICE_IRQ                 =  12,
+    I2S0_PCM0_IRQ                   =  13,
+    I2S1_PCM1_IRQ                   =  14,
+    WL_DMA_IRQ                      =  15,
+    WL_PROTOCOL_IRQ                 =  16,
+    CRYPTO_IRQ                      =  17,
+    GMAC_IRQ						=  18,
+    PERIPHERAL_IRQ                  =  19,
+    GDMA0_CHANNEL0_IRQ              =  20,
+    GDMA0_CHANNEL1_IRQ              =  21,
+    GDMA0_CHANNEL2_IRQ              =  22,
+    GDMA0_CHANNEL3_IRQ              =  23,
+    GDMA0_CHANNEL4_IRQ              =  24,
+    GDMA0_CHANNEL5_IRQ              =  25,
+    GDMA1_CHANNEL0_IRQ              =  26,
+    GDMA1_CHANNEL1_IRQ              =  27,
+    GDMA1_CHANNEL2_IRQ              =  28,
+    GDMA1_CHANNEL3_IRQ              =  29,
+    GDMA1_CHANNEL4_IRQ              =  30,
+    GDMA1_CHANNEL5_IRQ              =  31,
+
+/******  RTL8195A Peripheral Interrupt Numbers ************/
+    I2C0_IRQ                        =  64,// 0 + 64,
+    I2C1_IRQ                        =  65,// 1 + 64,
+    I2C2_IRQ                        =  66,// 2 + 64,
+    SPI1_IRQ                        =  72,// 8 + 64,
+    SPI2_IRQ                        =  73,// 9 + 64,
+    UART1_IRQ                       =  80,// 16 + 64,
+    UART2_IRQ                       =  81,// 17 + 64,
+    UART_LOG_IRQ                    =  88,// 24 + 64,
+    ADC_IRQ                         =  89,// 25 + 64,
+    DAC0_IRQ                        =  91,// 27 + 64,
+    DAC1_IRQ                        =  92,// 28 + 64,
+    //RXI300_IRQ                      =  93// 29 + 64
+    LP_EXTENSION_IRQ                =  93,// 29+64
+    
+    RXI300_IRQ                      =  96,// 0+32 + 64
+    NFC_IRQ                         =  97// 1+32+64
+} IRQn_Type, *PIRQn_Type;
+
+
+typedef VOID (*HAL_VECTOR_FUN) (VOID);
+
+typedef enum _VECTOR_TABLE_TYPE_{
+    DEDECATED_VECTRO_TABLE,
+    PERIPHERAL_VECTOR_TABLE
+}VECTOR_TABLE_TYPE, *PVECTOR_TABLE_TYPE;
+
+
+typedef u32 (*IRQ_FUN)(VOID *Data);
+
+typedef struct _IRQ_HANDLE_ {
+    IRQ_FUN     IrqFun;
+    IRQn_Type   IrqNum;
+    u32         Data;
+    u32         Priority;
+}IRQ_HANDLE, *PIRQ_HANDLE;
+
+
+#endif //_HAL_IRQN_H_

component/soc/realtek/8195a/fwlib/hal_mii.h

@@ -0,0 +1,118 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_MII_H_
+#define _HAL_MII_H_
+
+#include "rtl8195a_mii.h"
+
+
+/**
+ * LOG Configurations
+ */
+
+// #define NOLOG
+
+#define LOG_TAG           "NoTag"
+#define LOG_INFO_HEADER   "I"
+#define LOG_DEBUG_HEADER  "D"
+#define LOG_ERROR_HEADER  "E"
+#define LOG_TEST_HEADER   "T"
+
+#define IDENT_TWO_SPACE    "  "
+#define IDENT_FOUR_SPACE   "    "
+
+#define LOG_INFO(...)  do {\
+            DiagPrintf("\r"LOG_INFO_HEADER"/"LOG_TAG": " __VA_ARGS__);\
+}while(0)
+
+#define LOG_DEBUG(...)  do {\
+            DiagPrintf("\r"LOG_DEBUG_HEADER"/"LOG_TAG": " __VA_ARGS__);\
+}while(0)
+
+#define LOG_ERROR(...)  do {\
+            DiagPrintf("\r"LOG_ERROR_HEADER"/"LOG_TAG": " __VA_ARGS__);\
+}while(0)
+
+#ifdef NOLOG
+    #define LOGI
+    #define LOGD
+    #define LOGE
+    #define LOGI2
+    #define LOGD2
+    #define LOGE2
+    #define LOGI4
+    #define LOGD4
+    #define LOGE4
+#else
+    #define LOGI  LOG_INFO
+    #define LOGD  LOG_DEBUG
+    #define LOGE  LOG_ERROR
+    #define LOGI2(...) LOG_INFO(IDENT_TWO_SPACE __VA_ARGS__)
+    #define LOGD2(...) LOG_DEBUG(IDENT_TWO_SPACE __VA_ARGS__)
+    #define LOGE2(...) LOG_ERROR(IDENT_TWO_SPACE __VA_ARGS__)
+    #define LOGI4(...) LOG_INFO(IDENT_FOUR_SPACE __VA_ARGS__)
+    #define LOGD4(...) LOG_DEBUG(IDENT_FOUR_SPACE __VA_ARGS__)
+    #define LOGE4(...) LOG_ERROR(IDENT_FOUR_SPACE __VA_ARGS__)
+#endif
+
+#define ANSI_COLOR_GREEN   "\x1b[32m"
+#define ANSI_COLOR_CYAN    "\x1b[36m"
+#define ANSI_COLOR_YELLOW  "\x1b[33m"
+#define ANSI_COLOR_MAGENTA "\x1b[35m"
+#define ANSI_COLOR_RED     "\x1b[31m"
+#define ANSI_COLOR_BLUE    "\x1b[34m"
+#define ANSI_COLOR_RESET   "\x1b[0m"
+
+#define DBG_ENTRANCE LOGI(ANSI_COLOR_GREEN "=> %s() <%s>\n" ANSI_COLOR_RESET, \
+        __func__, __FILE__)
+
+
+// GMAC MII Configurations
+#ifdef LOG_TAG
+#undef LOG_TAG
+#define LOG_TAG  "MII"
+#endif
+
+
+typedef struct _HAL_MII_ADAPTER_ {
+    u32 InterruptMask;
+    PPHY_MODE_INFO pPhyModeInfo;
+}HAL_MII_ADAPTER, *PHAL_MII_ADAPTER;
+
+typedef struct _HAL_MII_OP_ {
+    BOOL (*HalMiiGmacInit)(VOID *Data);
+    BOOL (*HalMiiInit)(VOID *Data);
+    BOOL (*HalMiiGmacReset)(VOID *Data);
+    BOOL (*HalMiiGmacEnablePhyMode)(VOID *Data);
+    u32  (*HalMiiGmacXmit)(VOID *Data);
+    VOID (*HalMiiGmacCleanTxRing)(VOID *Data);
+    VOID (*HalMiiGmacFillTxInfo)(VOID *Data);
+    VOID (*HalMiiGmacFillRxInfo)(VOID *Data);
+    VOID (*HalMiiGmacTx)(VOID *Data);
+    VOID (*HalMiiGmacRx)(VOID *Data);
+    VOID (*HalMiiGmacSetDefaultEthIoCmd)(VOID *Data);
+    VOID (*HalMiiGmacInitIrq)(VOID *Data);
+    u32  (*HalMiiGmacGetInterruptStatus)(VOID);
+    VOID (*HalMiiGmacClearInterruptStatus)(u32 IsrStatus);
+}HAL_MII_OP, *PHAL_MII_OP;
+
+VOID HalMiiOpInit(IN VOID *Data);
+
+typedef struct _MII_ADAPTER_ {
+    PHAL_MII_OP      pHalMiiOp;
+    PHAL_MII_ADAPTER pHalMiiAdapter;
+    PTX_INFO         pTx_Info;
+    PRX_INFO         pRx_Info;
+    VOID*            TxBuffer;
+    VOID*            RxBuffer;
+}MII_ADAPTER, *PMII_ADAPTER;
+
+#endif
+

component/soc/realtek/8195a/fwlib/hal_misc.h

@@ -0,0 +1,30 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _MISC_H_
+#define _MISC_H_
+
+#include <basic_types.h>
+
+#ifdef CONFIG_TIMER_MODULE
+extern _LONG_CALL_ u32 HalDelayUs(u32 us);
+#endif
+
+extern _LONG_CALL_ u32 HalGetCpuClk(VOID);
+extern _LONG_CALL_ u8 HalGetRomInfo(VOID);
+
+extern _LONG_CALL_ void *_memset( void *s, int c, SIZE_T n );
+extern _LONG_CALL_ void *_memcpy( void *s1, const void *s2, SIZE_T n );
+extern _LONG_CALL_ int _memcmp( const void *av, const void *bv, SIZE_T len );
+
+extern _LONG_CALL_ SIZE_T _strlen(const char *s);
+extern _LONG_CALL_ int _strcmp(const char *cs, const char *ct);
+
+
+#endif  //_MISC_H_

component/soc/realtek/8195a/fwlib/hal_nfc.h

@@ -0,0 +1,22 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_NFC_H_
+#define _HAL_NFC_H_
+
+#include "rtl8195a_nfc.h"
+
+
+VOID HalNFCOpInit(
+    IN  VOID *Data
+);
+
+
+#endif
+

component/soc/realtek/8195a/fwlib/hal_pcm.h

@@ -0,0 +1,104 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_PCM_H_
+#define _HAL_PCM_H_
+
+#include "rtl8195a_pcm.h"
+/*
+typedef struct _GDMA_CH_LLI_ELE_ {
+    u32                   Sarx;
+    u32                   Darx;
+    u32                   Llpx;
+    u32                   CtlxLow;
+    u32                   CtlxUp;
+    u32                   Temp;
+}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
+#if 1
+#if 0
+typedef struct _GDMA_CH_LLI_ {
+    PGDMA_CH_LLI_ELE      pLliEle;
+    PGDMA_CH_LLI          pNextLli;
+}GDMA_CH_LLI, *PGDMA_CH_LLI;
+
+typedef struct _BLOCK_SIZE_LIST_ {
+    u32                  BlockSize;
+    PBLOCK_SIZE_LIST     pNextBlockSiz;
+}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
+#else
+struct GDMA_CH_LLI {
+    PGDMA_CH_LLI_ELE                pLliEle;
+    struct GDMA_CH_LLI             *pNextLli;
+};
+
+struct BLOCK_SIZE_LIST {
+    u32                             BlockSize;
+    struct BLOCK_SIZE_LIST          *pNextBlockSiz;
+};
+
+#endif
+
+#endif
+typedef struct _HAL_GDMA_ADAPTER_ {
+    u32                   ChSar;
+    u32                   ChDar;
+    GDMA_CHANNEL_NUM      ChEn;
+    GDMA_CTL_REG          GdmaCtl;
+    GDMA_CFG_REG          GdmaCfg;
+    u32                   PacketLen;
+    u32                   BlockLen;
+    u32                   MuliBlockCunt;
+    u32                   MaxMuliBlock;
+    struct GDMA_CH_LLI          *pLlix;
+    struct BLOCK_SIZE_LIST      *pBlockSizeList;
+
+    PGDMA_CH_LLI_ELE            pLli;
+    u32                         NextPlli;
+    u8                    TestItem;
+    u8                          ChNum;
+    u8                          GdmaIndex;
+    u8                          IsrCtrl:1;
+    u8                          GdmaOnOff:1;
+    u8                          Llpctrl:1;
+    u8                          Lli0:1;
+    u8                          Rsvd4to7:4;
+    u8                          GdmaIsrType;
+}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
+
+*/
+
+typedef struct _HAL_PCM_ADAPTER_ {
+    u32                       Enable:1;
+    PCM_CTL_REG               PcmCtl;
+    PCM_CHCNR03_REG           PcmChCNR03;
+    PCM_TSR03_REG             PcmTSR03;
+    PCM_BSIZE03_REG           PcmBSize03;
+    u32                       abc;
+    u8                        PcmIndex;
+    u8                        PcmCh;
+}HAL_PCM_ADAPTER, *PHAL_PCM_ADAPTER;
+
+
+typedef struct _HAL_PCM_OP_ {
+    VOID (*HalPcmOnOff)(VOID *Data);
+    BOOL (*HalPcmInit)(VOID *Data);
+    BOOL (*HalPcmSetting)(VOID *Data);
+    BOOL (*HalPcmEn)(VOID *Data);
+    BOOL (*HalPcmIsrEnAndDis) (VOID *Data);
+    BOOL (*HalPcmDumpReg)(VOID *Data);
+    BOOL (*HalPcm)(VOID *Data);
+}HAL_PCM_OP, *PHAL_PCM_OP;
+
+
+VOID HalPcmOpInit(
+    IN  VOID *Data
+);
+
+
+#endif

component/soc/realtek/8195a/fwlib/hal_peri_on.h

@@ -0,0 +1,451 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_PERI_ON_H_
+#define _HAL_PERI_ON_H_
+
+#define MASK_ALLON                          0xFFFFFFFF
+
+#define HAL_PERI_ON_READ32(addr)            HAL_READ32(PERI_ON_BASE, addr)
+#define HAL_PERI_ON_WRITE32(addr, value)    HAL_WRITE32(PERI_ON_BASE, addr, value)
+#define HAL_PERI_ON_READ16(addr)            HAL_READ16(PERI_ON_BASE, addr)
+#define HAL_PERI_ON_WRITE16(addr, value)    HAL_WRITE16(PERI_ON_BASE, addr, value)
+#define HAL_PERI_ON_READ8(addr)             HAL_READ8(PERI_ON_BASE, addr)
+#define HAL_PERI_ON_WRITE8(addr, value)     HAL_WRITE8(PERI_ON_BASE, addr, value)
+#define HAL_PERL_ON_FUNC_CTRL(addr,value,ctrl)  \
+        HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~value))|((MASK_ALLON - ctrl + 1) & value)))
+#define HAL_PERL_ON_PIN_SEL(addr,mask,value)  \
+        HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~mask)) | value))
+
+//40 REG_SYS_REGU_CTRL0
+#define LDO25M_CTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_SYS_REGU_CTRL0, BIT_SYS_REGU_LDO25M_EN, ctrl)
+
+//A0 SYS_DEBUG_CTRL
+#define DEBUG_PIN_CTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_SYS_DEBUG_CTRL, BIT_SYS_DBG_PIN_EN, ctrl)
+
+//A4 SYS_PINMUX_CTRL
+#define SIC_PIN_CTRL(ctrl)      HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_SIC_PIN_EN, ctrl)
+#define EEPROM_PIN_CTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_EEPROM_PIN_EN, ctrl)
+
+
+//210 SOV_FUNC_EN
+#define LXBUS_FCTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LXBUS_EN, ctrl)
+#define FLASH_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SPI_FLASH_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_FLASH_EN, ctrl);}
+
+#define MEM_CTRL_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SDR_SDRAM_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_MEM_CTRL_EN, ctrl);}
+
+#define LOC_UART_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(LOG_UART_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LOG_UART_EN, ctrl);}
+
+#define GDMA0_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(GDMA0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA0_EN, ctrl);}
+
+#define GDMA1_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(GDMA1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA1_EN, ctrl);}
+
+#define GTIMER_FCTRL(ctrl)      { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(TIMER_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GTIMER_EN, ctrl);}
+
+#define SECURITY_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(CRYPTO_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_SECURITY_ENGINE_EN, ctrl);}
+
+//214 SOC_HCI_COM_FUNC_EN
+#define SDIOD_ON_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN, ctrl);}
+
+#define SDIOD_OFF_FCTRL(ctrl)   { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN, ctrl);}
+
+#define SDIOH_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SDIO_HOST_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN, ctrl);}
+
+#define SDIO_ON_RST_MASK(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_RST_MUX, ctrl)
+#define OTG_FCTRL(ctrl)         { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(USB_OTG_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_EN, ctrl);}
+
+#define OTG_RST_MASK(ctrl)      HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_RST_MUX, ctrl)
+#define MII_FCTRL(ctrl)         { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(MII_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_MII_EN, ctrl);}
+
+#define MII_MUX_SEL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SM_SEL, ctrl)
+#define WL_MACON_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(WIFI_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_WL_MACON_EN, ctrl);}
+
+//218 SOC_PERI_FUNC0_EN
+#define UART0_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(UART0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART0_EN, ctrl);}
+
+#define UART1_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(UART1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART1_EN, ctrl);}
+
+#define UART2_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(UART2_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART2_EN, ctrl);}
+
+#define SPI0_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SPI0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI0_EN, ctrl);}
+
+#define SPI1_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SPI1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI1_EN, ctrl);}
+
+#define SPI2_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SPI2_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI2_EN, ctrl);}
+
+#define I2C0_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(I2C0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C0_EN, ctrl);}
+
+#define I2C1_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(I2C1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C1_EN, ctrl);}
+
+#define I2C2_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(I2C2_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C2_EN, ctrl);}
+
+#define I2C3_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(I2C3_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C3_EN, ctrl);}
+
+#define I2S0_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(I2S0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S0_EN, ctrl);}
+
+#define I2S1_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(I2S1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S1_EN, ctrl);}
+
+#define PCM0_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(PCM0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM0_EN, ctrl);}
+
+#define PCM1_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(PCM1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM1_EN, ctrl);}
+
+//21C SOC_PERI_FUNC1_EN
+#define ADC0_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(ADC_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_ADC0_EN, ctrl);}
+
+#define DAC0_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(DAC_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC0_EN, ctrl);}
+
+#define DAC1_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(DAC_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC1_EN, ctrl);}
+
+#define GPIO_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(GPIO_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_GPIO_EN, ctrl);}
+
+//220 SOC_PERI_BD_FUNC0_EN
+#define UART0_BD_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(UART0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART0_BD_EN, ctrl);}
+
+#define UART1_BD_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(UART1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART1_BD_EN, ctrl);}
+
+#define UART2_BD_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(UART2_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART2_BD_EN, ctrl);}
+
+//230 PESOC_CLK_CTRL
+#define ACTCK_CPU_CCTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_CKE_PLFM, ctrl)
+#define ACTCK_TRACE_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TRACE_EN, ctrl)
+#define SLPCK_TRACE_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TRACE_EN, ctrl)
+#define ACTCK_VENDOR_CCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_VENDOR_REG_EN, ctrl)
+#define SLPCK_VENDOR_CCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_VENDOR_REG_EN, ctrl)
+#define ACTCK_FLASH_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_FLASH_EN, ctrl)
+#define SLPCK_FLASH_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_FLASH_EN, ctrl)
+#define ACTCK_SDR_CCTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_SDR_EN, ctrl)
+#define SLPCK_SDR_CCTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_SDR_EN, ctrl)
+#define ACTCK_LOG_UART_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_LOG_UART_EN, ctrl)
+#define SLPCK_LOG_UART_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_LOG_UART_EN, ctrl)
+#define ACTCK_TIMER_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TIMER_EN, ctrl)
+#define SLPCK_TIMER_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TIMER_EN, ctrl)
+#define ACTCK_GDMA0_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA0_EN, ctrl)
+#define SLPCK_GDMA0_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA0_EN, ctrl)
+#define ACTCK_GDMA1_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA1_EN, ctrl)
+#define SLPCK_GDMA1_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA1_EN, ctrl)
+#define ACTCK_GPIO_CCTRL(ctrl)      HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GPIO_EN, ctrl)
+#define SLPCK_GPIO_CCTRL(ctrl)      HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GPIO_EN, ctrl)
+#define ACTCK_BTCMD_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_BTCMD_EN, ctrl)
+#define SLPCK_BTCMD_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_BTCMD_EN, ctrl)
+
+//234 PESOC_PERI_CLK_CTRL0
+#define ACTCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART0_EN, ctrl)
+#define SLPCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART0_EN, ctrl)
+#define ACTCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART1_EN, ctrl)
+#define SLPCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART1_EN, ctrl)
+#define ACTCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART2_EN, ctrl)
+#define SLPCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART2_EN, ctrl)
+#define ACTCK_SPI0_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI0_EN, ctrl)
+#define SLPCK_SPI0_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI0_EN, ctrl)
+#define ACTCK_SPI1_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI1_EN, ctrl)
+#define SLPCK_SPI1_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI1_EN, ctrl)
+#define ACTCK_SPI2_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI2_EN, ctrl)
+#define SLPCK_SPI2_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI2_EN, ctrl)
+
+//238 PESOC_PERI_CLK_CTRL1
+#define ACTCK_I2C0_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C0_EN, ctrl)
+#define SLPCK_I2C0_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C0_EN, ctrl)
+#define ACTCK_I2C1_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C1_EN, ctrl)
+#define SLPCK_I2C1_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C1_EN, ctrl)
+#define ACTCK_I2C2_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C2_EN, ctrl)
+#define SLPCK_I2C2_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C2_EN, ctrl)
+#define ACTCK_I2C3_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C3_EN, ctrl)
+#define SLPCK_I2C3_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C3_EN, ctrl)
+#define ACTCK_I2S_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2S_EN, ctrl)
+#define SLPCK_I2S_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2S_EN, ctrl)
+#define ACTCK_PCM_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_PCM_EN, ctrl)
+#define SLPCK_PCM_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_PCM_EN, ctrl)
+#define ACTCK_ADC_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_ADC_EN, ctrl)
+#define SLPCK_ADC_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_ADC_EN, ctrl)
+#define ACTCK_DAC_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_DAC_EN, ctrl)
+#define SLPCK_DAC_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_DAC_EN, ctrl)
+
+//240 PESOC_HCI_CLK_CTRL0
+#define ACTCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_DEV_EN, ctrl)
+#define SLPCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_DEV_EN, ctrl)
+#define ACTCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_HST_EN, ctrl)
+#define SLPCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_HST_EN, ctrl)
+#define ACTCK_OTG_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_OTG_EN, ctrl)
+#define SLPCK_OTG_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_OTG_EN, ctrl)
+#define ACTCK_MII_MPHY_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_MII_MPHY_EN, ctrl)
+#define SLPCK_MII_MPHY_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_MII_MPHY_EN, ctrl)
+
+//244 PESOC_COM_CLK_CTRL1
+#define ACTCK_WL_CCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_WL_EN, ctrl)
+#define SLPCK_WL_CCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_WL_EN, ctrl)
+#define ACTCK_SEC_ENG_CCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_SECURITY_ENG_EN, ctrl)
+#define SLPCK_SEC_ENG_CCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_SECURITY_ENG_EN, ctrl)
+#define ACTCK_NFC_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_NFC_EN, ctrl)
+#define SLPCK_NFC_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_NFC_EN, ctrl)
+#define NFC_CAL_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_NFC_CAL_EN, ctrl)
+
+//250 REG_PERI_CLK_SEL
+#define TRACE_CLK_SEL(num)      HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_TRACE_CK_SEL << BIT_SHIFT_PESOC_TRACE_CK_SEL), BIT_PESOC_TRACE_CK_SEL(num))
+#define FLASH_CLK_SEL(num)      HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_FLASH_CK_SEL << BIT_SHIFT_PESOC_FLASH_CK_SEL), BIT_PESOC_FLASH_CK_SEL(num))
+#define SDR_CLK_SEL(num)        HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_SDR_CK_SEL << BIT_SHIFT_PESOC_SDR_CK_SEL), BIT_PESOC_SDR_CK_SEL(num))
+#define I2C_SCLK_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_PERI_SCLK_SEL << BIT_SHIFT_PESOC_PERI_SCLK_SEL), BIT_PESOC_PERI_SCLK_SEL(num))
+
+//270 REG_OSC32K_CTRL
+#define OSC32K_CKGEN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_OSC32K_CTRL, BIT_32K_POW_CKGEN_EN, ctrl)
+
+//280 REG_UART_MUX_CTRL
+#define UART0_PIN_CTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART0_PIN_EN, ctrl)
+#define UART0_PIN_SEL(num)      HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART0_PIN_SEL << BIT_SHIFT_UART0_PIN_SEL), BIT_UART0_PIN_SEL(num))
+#define UART1_PIN_CTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART1_PIN_EN, ctrl)
+#define UART1_PIN_SEL(num)      HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART1_PIN_SEL << BIT_SHIFT_UART1_PIN_SEL), BIT_UART1_PIN_SEL(num))
+#define UART2_PIN_CTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART2_PIN_EN, ctrl)
+#define UART2_PIN_SEL(num)      HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART2_PIN_SEL << BIT_SHIFT_UART2_PIN_SEL), BIT_UART2_PIN_SEL(num))
+
+//284 REG_SPI_MUX_CTRL
+#define SPI0_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_PIN_EN, ctrl)
+#define SPI0_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI0_PIN_SEL << BIT_SHIFT_SPI0_PIN_SEL), BIT_SPI0_PIN_SEL(num))
+#define SPI1_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI1_PIN_EN, ctrl)
+#define SPI1_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI1_PIN_SEL << BIT_SHIFT_SPI1_PIN_SEL), BIT_SPI1_PIN_SEL(num))
+#define SPI2_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI2_PIN_EN, ctrl)
+#define SPI2_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI2_PIN_SEL << BIT_SHIFT_SPI2_PIN_SEL), BIT_SPI2_PIN_SEL(num))
+#define SPI0_MULTI_CS_CTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_MULTI_CS_EN, ctrl)
+
+//288 REG_I2C_MUX_CTRL
+#define I2C0_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C0_PIN_EN, ctrl)
+#define I2C0_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C0_PIN_SEL << BIT_SHIFT_I2C0_PIN_SEL), BIT_I2C0_PIN_SEL(num))
+#define I2C1_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C1_PIN_EN, ctrl)
+#define I2C1_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C1_PIN_SEL << BIT_SHIFT_I2C1_PIN_SEL), BIT_I2C1_PIN_SEL(num))
+#define I2C2_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C2_PIN_EN, ctrl)
+#define I2C2_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C2_PIN_SEL << BIT_SHIFT_I2C2_PIN_SEL), BIT_I2C2_PIN_SEL(num))
+#define I2C3_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C3_PIN_EN, ctrl)
+#define I2C3_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C3_PIN_SEL << BIT_SHIFT_I2C3_PIN_SEL), BIT_I2C3_PIN_SEL(num))
+
+//28C REG_I2S_MUX_CTRL
+#define I2S0_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_PIN_EN, ctrl)
+#define I2S0_MCK_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_MCK_EN, ctrl)
+#define I2S0_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S0_PIN_SEL << BIT_SHIFT_I2S0_PIN_SEL), BIT_I2S0_PIN_SEL(num))
+#define I2S1_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_PIN_EN, ctrl)
+#define I2S1_MCK_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_MCK_EN, ctrl)
+#define I2S1_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S1_PIN_SEL << BIT_SHIFT_I2S1_PIN_SEL), BIT_I2S1_PIN_SEL(num))
+#define PCM0_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM0_PIN_EN, ctrl)
+#define PCM0_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM0_PIN_SEL << BIT_SHIFT_PCM0_PIN_SEL), BIT_PCM0_PIN_SEL(num))
+#define PCM1_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM1_PIN_EN, ctrl)
+#define PCM1_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM1_PIN_SEL << BIT_SHIFT_PCM1_PIN_SEL), BIT_PCM1_PIN_SEL(num))
+
+//2A0 HCI_PINMUX_CTRL
+#define SDIOD_PIN_FCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN, ctrl)
+#define SDIOH_PIN_FCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN, ctrl)
+#define MII_PIN_FCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN, ctrl)
+
+//2A4 WL_PINMUX_CTRL
+#define LED_PIN_FCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_LED_PIN_EN, ctrl)
+#define LED_PIN_SEL(num)        HAL_PERL_ON_PIN_SEL(REG_WL_PINMUX_CTRL, (BIT_MASK_WL_LED_PIN_SEL << BIT_SHIFT_WL_LED_PIN_SEL), BIT_WL_LED_PIN_SEL(num))
+#define ANT0_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT0_PIN_EN, ctrl)
+#define ANT1_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT1_PIN_EN, ctrl)
+#define BTCOEX_PIN_FCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCOEX_PIN_EN, ctrl)
+#define BTCMD_PIN_FCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCMD_PIN_EN, ctrl)
+#define NFC_PIN_FCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_NFC_PIN_EN, ctrl)
+
+//2AC PWM_PINMUX_CTRL
+#define PWM0_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM0_PIN_EN, ctrl)
+#define PWM0_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM0_PIN_SEL << BIT_SHIFT_PWM0_PIN_SEL), BIT_PWM0_PIN_SEL(num))
+#define PWM1_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM1_PIN_EN, ctrl)
+#define PWM1_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM1_PIN_SEL << BIT_SHIFT_PWM1_PIN_SEL), BIT_PWM1_PIN_SEL(num))
+#define PWM2_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM2_PIN_EN, ctrl)
+#define PWM2_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM2_PIN_SEL << BIT_SHIFT_PWM2_PIN_SEL), BIT_PWM2_PIN_SEL(num))
+#define PWM3_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM3_PIN_EN, ctrl)
+#define PWM3_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM3_PIN_SEL << BIT_SHIFT_PWM3_PIN_SEL), BIT_PWM3_PIN_SEL(num))
+#define ETE0_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE0_PIN_EN, ctrl)
+#define ETE0_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE0_PIN_SEL << BIT_SHIFT_ETE0_PIN_SEL), BIT_ETE0_PIN_SEL(num))
+#define ETE1_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE1_PIN_EN, ctrl)
+#define ETE1_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE1_PIN_SEL << BIT_SHIFT_ETE1_PIN_SEL), BIT_ETE1_PIN_SEL(num))
+#define ETE2_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE2_PIN_EN, ctrl)
+#define ETE2_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE2_PIN_SEL << BIT_SHIFT_ETE2_PIN_SEL), BIT_ETE2_PIN_SEL(num))
+#define ETE3_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE3_PIN_EN, ctrl)
+#define ETE3_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE3_PIN_SEL << BIT_SHIFT_ETE3_PIN_SEL), BIT_ETE3_PIN_SEL(num))
+
+//2C0 CPU_PERIPHERAL_CTRL
+#define SPI_FLASH_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SPI_FLSH_PIN_EN, ctrl)
+#define SPI_FLASH_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_CPU_PERIPHERAL_CTRL, (BIT_MASK_SPI_FLSH_PIN_SEL << BIT_SHIFT_SPI_FLSH_PIN_SEL), BIT_SPI_FLSH_PIN_SEL(num))
+#define SDR_PIN_FCTRL(ctrl)          HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SDR_PIN_EN, ctrl)
+#define TRACE_PIN_FCTRL(ctrl)        HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_TRACE_PIN_EN, ctrl)
+#define LOG_UART_PIN_FCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_PIN_EN, ctrl)
+#define LOG_UART_IR_FCTRL(ctrl)      HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_IR_EN, ctrl)
+
+//300 REG_PESOC_MEM_CTRL
+#define SDR_DDL_FCTRL(ctrl)      HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_SDR_DDL_CTRL << BIT_SHIFT_PESOC_SDR_DDL_CTRL), BIT_PESOC_SDR_DDL_CTRL(ctrl))
+#define FLASH_DDL_FCTRL(ctrl)    HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_FLASH_DDL_CTRL << BIT_SHIFT_PESOC_FLASH_DDL_CTRL), BIT_PESOC_FLASH_DDL_CTRL(ctrl))
+
+//304 REG_PESOC_SOC_CTRL
+#define SRAM_MUX_CFG(num)        HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_SRAM_MUX_CFG << BIT_SHIFT_PESOC_SRAM_MUX_CFG), BIT_PESOC_SRAM_MUX_CFG(num))
+#define LX_WL_SWAP_CTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_WL_SWAP_SEL, ctrl)
+#define LX_MST_SWAP_CTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_MST_SWAP_SEL, ctrl)
+#define LX_SLV_SWAP_CTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_SLV_SWAP_SEL, ctrl)
+#define MII_LX_WRAPPER_FCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_WRAPPER_EN, ctrl)
+#define MII_LX_MST_SWAP_CTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_MST_SWAP_SEL, ctrl)
+#define MII_LX_SLV_SWAP_CTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_SLV_SWAP_SEL, ctrl)
+#define GDMA_CFG(num)            HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_GDMA_CFG << BIT_SHIFT_PESOC_GDMA_CFG), BIT_PESOC_GDMA_CFG(num))
+
+//308 PESOC_PERI_CTRL
+#define SPI_RN_FCTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CTRL, BIT_SOC_FUNC_SPI_RN, ctrl)
+
+//320 GPIO_SHTDN_CTRL
+#define GPIO_GPA_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPA_SHTDN_N, ctrl)
+#define GPIO_GPB_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPB_SHTDN_N, ctrl)
+#define GPIO_GPC_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPC_SHTDN_N, ctrl)
+#define GPIO_GPD_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPD_SHTDN_N, ctrl)
+#define GPIO_GPE_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPE_SHTDN_N, ctrl)
+#define GPIO_GPF_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPF_SHTDN_N, ctrl)
+#define GPIO_GPG_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPG_SHTDN_N, ctrl)
+#define GPIO_GPH_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPH_SHTDN_N, ctrl)
+#define GPIO_GPI_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPI_SHTDN_N, ctrl)
+#define GPIO_GPJ_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPJ_SHTDN_N, ctrl)
+#define GPIO_GPK_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPK_SHTDN_N, ctrl)
+
+//374
+#define EGTIM_FCTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_PERI_EGTIM_CTRL, BIT_PERI_EGTIM_EN, ctrl)
+#define EGTIM_RSIG_SEL(num)     HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_REF_SIG_SEL << BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL), BIT_PERI_EGTIM_REF_SIG_SEL(num))
+#define EGTIME_PIN_G0_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP0_OPT_SEL(num))
+#define EGTIME_PIN_G1_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP1_OPT_SEL(num))
+#define EGTIME_PIN_G2_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP2_OPT_SEL(num))
+
+
+#endif //_HAL_PERI_ON_H_
+

component/soc/realtek/8195a/fwlib/hal_pinmux.h

@@ -0,0 +1,60 @@
+#ifndef _HAL_PINMUX_
+#define _HAL_PINMUX_
+
+
+//Function Index
+#define UART0       0
+#define UART1       1
+#define UART2       2
+#define SPI0        8
+#define SPI1        9
+#define SPI2        10
+#define SPI0_MCS    15
+#define I2C0        16
+#define I2C1        17
+#define I2C2        18
+#define I2C3        19
+#define I2S0        24
+#define I2S1        25
+#define PCM0        28
+#define PCM1        29
+#define SDIOD       64
+#define SDIOH       65
+#define MII         88
+#define WL_LED      96
+#define WL_ANT0     104
+#define WL_ANT1     105
+#define WL_BTCOEX   108
+#define WL_BTCMD    109
+#define NFC         112
+#define PWM0        160
+#define PWM1        161
+#define PWM2        162
+#define PWM3        163
+#define ETE0        164
+#define ETE1        165
+#define ETE2        166
+#define ETE3        167
+#define EGTIM       168
+#define SPI_FLASH   196
+#define SDR         200
+#define JTAG        216
+#define TRACE       217
+#define LOG_UART    220
+#define LOG_UART_IR 221
+#define SIC         224
+#define EEPROM      225
+#define DEBUG       226
+
+//Location Index(Pin Mux Selection)
+#define S0          0
+#define S1          1
+#define S2          2
+#define S3          3
+
+_LONG_CALL_ u8 
+HalPinCtrlRtl8195A(
+    IN u32  Function, 
+    IN u32  PinLocation, 
+    IN BOOL   Operation);
+#endif   //_HAL_PINMUX_

component/soc/realtek/8195a/fwlib/hal_platform.h

@@ -0,0 +1,102 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _HAL_PLATFORM_
+#define _HAL_PLATFORM_
+
+#define ROMVERSION 0x03
+#define ROMINFORMATION (ROMVERSION)
+
+#define SYSTEM_CLK                  PLATFORM_CLOCK
+
+#define SDR_SDRAM_BASE              0x30000000
+#define SYSTEM_CTRL_BASE            0x40000000
+#define PERI_ON_BASE                0x40000000
+#define VENDOR_REG_BASE             0x40002800
+#define SPI_FLASH_BASE              0x98000000
+#define SDR_CTRL_BASE               0x40005000
+
+#define PERIPHERAL_IRQ_STATUS       0x04
+#define PERIPHERAL_IRQ_MODE         0x08
+#define PERIPHERAL_IRQ_EN           0x0C
+#define LP_PERI_EXT_IRQ_STATUS      0x24
+#define LP_PERI_EXT_IRQ_MODE        0x28
+#define LP_PERI_EXT_IRQ_EN          0x2C
+
+#define PERIPHERAL_IRQ_ALL_LEVEL    0
+
+#define TIMER_CLK                   32*1000
+
+//3 Peripheral IP Base Address
+#define GPIO_REG_BASE               0x40001000
+#define TIMER_REG_BASE              0x40002000
+#define NFC_INTERFACE_BASE          0x40002400
+#define LOG_UART_REG_BASE           0x40003000
+#define I2C2_REG_BASE               0x40003400
+#define I2C3_REG_BASE               0x40003800
+#define SPI_FLASH_CTRL_BASE         0x40006000
+#define ADC_REG_BASE                0x40010000
+#define DAC_REG_BASE                0x40011000
+#define UART0_REG_BASE              0x40040000
+#define UART1_REG_BASE              0x40040400
+#define UART2_REG_BASE              0x40040800
+#define SPI0_REG_BASE               0x40042000
+#define SPI1_REG_BASE               0x40042400
+#define SPI2_REG_BASE               0x40042800
+#define I2C0_REG_BASE               0x40044000
+#define I2C1_REG_BASE               0x40044400
+#define SDIO_DEVICE_REG_BASE        0x40050000
+#define MII_REG_BASE                0x40050000
+#define SDIO_HOST_REG_BASE          0x40058000
+#define GDMA0_REG_BASE              0x40060000
+#define GDMA1_REG_BASE              0x40061000
+#define I2S0_REG_BASE               0x40062000
+#define I2S1_REG_BASE               0x40063000
+#define PCM0_REG_BASE               0x40064000
+#define PCM1_REG_BASE               0x40065000
+#define CRYPTO_REG_BASE             0x40070000
+#define WIFI_REG_BASE               0x40080000
+#define USB_OTG_REG_BASE            0x400C0000
+
+#define GDMA1_REG_OFF               0x1000
+#define I2S1_REG_OFF                0x1000
+#define PCM1_REG_OFF                0x1000
+#define SSI_REG_OFF                 0x400
+#define RUART_REG_OFF               0x400
+
+#define CPU_CLK_TYPE_NO             6
+
+enum _BOOT_TYPE_ {
+    BOOT_FROM_FLASH = 0,
+    BOOT_FROM_SDIO  = 1,        
+    BOOT_FROM_USB   = 2,
+    BOOT_FROM_RSVD  = 3,    
+};
+
+enum _EFUSE_CPU_CLK_ {
+    #if 1
+    CLK_200M   = 0,
+    CLK_100M   = 1,
+    CLK_50M    = 2,
+    CLK_25M    = 3,
+    CLK_12_5M  = 4,    
+    CLK_4M     = 5,
+    #else
+    CLK_25M    = 0,
+    CLK_200M   = 1,
+    CLK_100M   = 2,        
+    CLK_50M    = 3,
+    CLK_12_5M  = 4,    
+    CLK_4M     = 5,    
+    #endif
+};
+
+
+#endif //_HAL_PLATFORM_

component/soc/realtek/8195a/fwlib/hal_pwm.h

@@ -0,0 +1,57 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_PWM_H_
+#define _HAL_PWM_H_
+
+#define MAX_PWM_CTRL_PIN        4
+// the minimum tick time for G-timer is 61 us (clock source = 32768Hz, reload value=1 and reload takes extra 1T)
+#define GTIMER_TICK_US            31   // micro-second, 1000000/32768 ~= 30.5
+#define MIN_GTIMER_TIMEOUT    61  // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
+#define PWM_GTIMER_TICK_TIME    61  // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
+
+typedef struct _HAL_PWM_ADAPTER_ {
+    u8 pwm_id;      // the PWM ID, 0~3
+    u8 sel;         // PWM Pin selection, 0~3
+    u8 gtimer_id;   // using G-Timer ID, there are 7 G-timer, but we prefer to use timer 3~6
+    u8 enable;      // is enabled
+//    u32 timer_value;    // the G-Timer auto-reload value, source clock is 32768Hz, reload will takes extra 1 tick. To set the time of a tick of PWM
+    u32 tick_time;  // the tick time for the G-timer
+    u32 period;    // the period of a PWM control cycle, in PWM tick
+    u32 pulsewidth;    // the pulse width in a period of a PWM control cycle, in PWM tick. To control the ratio
+//    float duty_ratio;   // the dyty ratio = pulswidth/period
+}HAL_PWM_ADAPTER, *PHAL_PWM_ADAPTER;
+
+
+extern HAL_Status 
+HAL_Pwm_Init(
+    u32 pwm_id,
+    u32 sel
+);
+
+extern void 
+HAL_Pwm_Enable(
+    u32 pwm_id
+);
+
+extern void 
+HAL_Pwm_Disable(
+    u32 pwm_id
+);
+
+extern void
+HAL_Pwm_SetDuty(
+    u32 pwm_id,
+    u32 period,
+    u32 pulse_width
+);
+
+
+#endif
+

component/soc/realtek/8195a/fwlib/hal_sdio.h

@@ -0,0 +1,241 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_SDIO_H_
+#define _HAL_SDIO_H_
+
+#include "rtl8195a_sdio.h"
+
+#if !SDIO_BOOT_DRIVER
+#include "mailbox.h"
+#endif
+
+#if SDIO_BOOT_DRIVER
+typedef struct _HAL_SDIO_ADAPTER_ {
+	u8				*pTXBDAddr;			/* The TX_BD start address */
+	PSDIO_TX_BD		pTXBDAddrAligned;	/* The TX_BD start address, it must be 4-bytes aligned */
+	PSDIO_TX_BD_HANDLE	pTXBDHdl;		/* point to the allocated memory for TX_BD Handle array */
+	u16				TXBDWPtr;		    /* The SDIO TX(Host->Device) BD local write index, different with HW maintained write Index. */
+	u16				TXBDRPtr;		    /* The SDIO TX(Host->Device) BD read index */
+	u16				TXBDRPtrReg;		/* The SDIO TX(Host->Device) BD read index has been write to HW register */
+    u16             reserve1;
+    
+	u8				*pRXBDAddr;			/* The RX_BD start address */
+	PSDIO_RX_BD		pRXBDAddrAligned;	/* The RX_BD start address, it must be 8-bytes aligned */
+	PSDIO_RX_BD_HANDLE	pRXBDHdl;		/* point to the allocated memory for RX_BD Handle array */
+	u16				RXBDWPtr;		    /* The SDIO RX(Device->Host) BD write index */
+	u16				RXBDRPtr;		    /* The SDIO RX(Device->Host) BD local read index, different with HW maintained Read Index. */
+	u16				IntMask;			/* The Interrupt Mask */
+	u16				IntStatus;			/* The Interrupt Status */
+	u32				Events;				/* The Event to the SDIO Task */
+
+	u32				EventSema;			/* Semaphore for SDIO events, use to wakeup the SDIO task */	
+    u8              CCPWM;              /* the value write to register CCPWM, which will sync to Host HCPWM */
+    u8              reserve2;
+    u16             CCPWM2;             /* the value write to register CCPWM2, which will sync to Host HCPWM2 */
+    
+	s8              (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize);	/* to hook the WLan driver TX callback function to handle a Packet TX */
+	VOID			*pTxCb_Adapter;		/* a pointer will be used to call the TX Callback function, 
+											which is from the TX CallBack function register */
+	s8			(*pTxCallback_Backup)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize);	// Use to back up the registered TX Callback function, for MP/Normal mode switch
+	VOID			*pTxCb_Adapter_Backup;	// Backup the pTxCb_Adapter, for MP/Normal mode switch
+	_LIST			FreeTxPktList;		/* The list to queue free Tx packets handler */
+	_LIST			RxPktList;			/* The list to queue RX packets */
+	_LIST			FreeRxPktList;		/* The list to queue free Rx packets handler */
+	SDIO_TX_PACKET	*pTxPktHandler;		/* to store allocated TX Packet handler memory address */
+	SDIO_RX_PACKET	*pRxPktHandler;		/* to store allocated RX Packet handler memory address */
+	u32				RxInQCnt;			/* The packet count for Rx In Queue */
+	u32				MemAllocCnt;		// Memory allocated count, for debug only
+	u32				MAllocFailedCnt;	// MemAlloc Failed count, for debugging
+	
+//	VOID			*pHalOp;			/* point to HAL operation function table */
+} HAL_SDIO_ADAPTER, *PHAL_SDIO_ADAPTER;
+
+extern BOOL SDIO_Device_Init_Rom(
+	IN PHAL_SDIO_ADAPTER pSDIODev
+);
+extern VOID SDIO_Device_DeInit_Rom(
+	IN PHAL_SDIO_ADAPTER pSDIODev
+);
+extern VOID SDIO_Send_C2H_IOMsg_Rom(
+	IN PHAL_SDIO_ADAPTER pSDIODev, 
+	IN u32 *C2HMsg
+);
+extern u8 SDIO_Send_C2H_PktMsg_Rom(
+	IN PHAL_SDIO_ADAPTER pSDIODev, 
+	IN u8 *C2HMsg, 
+	IN u16 MsgLen
+);
+extern VOID SDIO_Register_Tx_Callback_Rom(
+	IN PHAL_SDIO_ADAPTER pSDIODev,
+	IN s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize),
+	IN VOID *pAdapter	
+);
+extern s8 SDIO_Rx_Callback_Rom(
+	IN PHAL_SDIO_ADAPTER pSDIODev,
+	IN VOID *pData,
+	IN u16 Offset,
+	IN u16 Length,
+	IN u8 CmdType
+);
+
+#else   // else of "#if SDIO_BOOT_DRIVER"
+typedef struct _HAL_SDIO_ADAPTER_ {
+//	u8				*pTxBuff;			/* point to the SDIO TX Buffer */
+//	u8				*pTxBuffAligned;	/* point to the SDIO TX Buffer with 4-bytes aligned */
+//	u32				TXFifoRPtr;		    /* The SDIO TX(Host->Device) FIFO buffer read pointer */
+
+	u8				*pTXBDAddr;			/* The TX_BD start address */
+	PSDIO_TX_BD		pTXBDAddrAligned;	/* The TX_BD start address, it must be 4-bytes aligned */
+	PSDIO_TX_BD_HANDLE	pTXBDHdl;		/* point to the allocated memory for TX_BD Handle array */
+	u16				TXBDWPtr;		    /* The SDIO TX(Host->Device) BD local write index, different with HW maintained write Index. */
+	u16				TXBDRPtr;		    /* The SDIO TX(Host->Device) BD read index */
+	u16				TXBDRPtrReg;		/* The SDIO TX(Host->Device) BD read index has been write to HW register */
+    
+	u8				*pRXBDAddr;			/* The RX_BD start address */
+	PSDIO_RX_BD		pRXBDAddrAligned;	/* The RX_BD start address, it must be 8-bytes aligned */
+	PSDIO_RX_BD_HANDLE	pRXBDHdl;		/* point to the allocated memory for RX_BD Handle array */
+	u16				RXBDWPtr;		    /* The SDIO RX(Device->Host) BD write index */
+	u16				RXBDRPtr;		    /* The SDIO RX(Device->Host) BD local read index, different with HW maintained Read Index. */
+	u16				IntMask;			/* The Interrupt Mask */
+	u16				IntStatus;			/* The Interrupt Status */
+	u32				Events;				/* The Event to the SDIO Task */
+
+#if !TASK_SCHEDULER_DISABLED
+	_Sema			TxSema;             /* Semaphore for SDIO TX, use to wakeup the SDIO TX task */	
+    _Sema           RxSema;             /* Semaphore for SDIO RX, use to wakeup the SDIO RX task */    
+#else
+	u32				EventSema;			/* Semaphore for SDIO events, use to wakeup the SDIO task */	
+#endif
+	s8              (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize);	/* to hook the WLan driver TX callback function to handle a Packet TX */
+	VOID			*pTxCb_Adapter;		/* a pointer will be used to call the TX Callback function, 
+											which is from the TX CallBack function register */
+	s8			(*pTxCallback_Backup)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize);	// Use to back up the registered TX Callback function, for MP/Normal mode switch
+	VOID			*pTxCb_Adapter_Backup;	// Backup the pTxCb_Adapter, for MP/Normal mode switch
+	_LIST			FreeTxPktList;		/* The list to queue free Tx packets handler */
+	_LIST			RxPktList;			/* The list to queue RX packets */
+	_LIST			FreeRxPktList;		/* The list to queue free Rx packets handler */
+//	_LIST			RecyclePktList;		/* The list to queue packets handler to be recycled */
+	SDIO_TX_PACKET	*pTxPktHandler;		/* to store allocated TX Packet handler memory address */
+	SDIO_RX_PACKET	*pRxPktHandler;		/* to store allocated RX Packet handler memory address */
+	_Mutex			RxMutex;			/* The Mutex to protect RxPktList */
+	u32				RxInQCnt;			/* The packet count for Rx In Queue */
+#if SDIO_DEBUG
+	_Mutex			StatisticMutex;		/* The Mutex to protect Statistic data */
+	u32				MemAllocCnt;		// Memory allocated count, for debug only
+	u32				MAllocFailedCnt;	// MemAlloc Failed count, for debugging
+#endif	
+	VOID			*pHalOp;			/* point to HAL operation function table */
+	RTL_MAILBOX		*pMBox;				/* the Mail box for other driver module can send message to SDIO driver */
+
+#ifdef PLATFORM_FREERTOS
+	xTaskHandle		xSDIOTxTaskHandle;	/* The handle of the SDIO Task for TX, can be used to delte the task */
+    xTaskHandle     xSDIORxTaskHandle;  /* The handle of the SDIO Task speical for RX, can be used to delte the task */
+#endif
+
+#if SDIO_MP_MODE
+#if !TASK_SCHEDULER_DISABLED
+	u32				MP_Events;				/* The Event to the SDIO Task */
+	_Sema			MP_EventSema;		/* Semaphore for SDIO events, use to wakeup the SDIO task */	
+    RTL_MAILBOX     *pMP_MBox;  /* the Mail box for communication with other driver module */
+#ifdef PLATFORM_FREERTOS
+    xTaskHandle     MP_TaskHandle;      /* The handle of the MP loopback Task, can be used to delte the task */
+#endif  // end of "#ifdef PLATFORM_FREERTOS"
+#endif  // end of "#if !TASK_SCHEDULER_DISABLED"
+	// for MP mode
+    RTL_TIMER       *pPeriodTimer;      /* a timer to calculate throughput periodically */
+	u8				MP_ModeEn;			/* is in MP mode */
+	u8				MP_LoopBackEn;		/* is loop-back enabled */
+	u8				MP_ContinueTx;		/* is continue TX test enabled */
+	u8				MP_ContinueRx;		/* is continue RX test enabled */
+	u8				MP_ContinueRxMode;  /* continue RX test mode: static RX Buf, Dyna-Allocate RX Buf, Pre-Allocate RX Buf */
+	u8				MP_CRxInfinite;		/* is non-stop SDIO RX, no packet count limit */
+    u16				MP_CRxSize;		    /* SDIO RX test packet size */
+    u8              *pMP_CRxBuf;        // the buffer for continye RX test
+    u32             MP_CRxPktCnt;       /* SDIO RX test packet count */
+    u32             MP_CRxPktPendingCnt;       /* SDIO RX test packet pening count */
+	u32				MP_TxPktCnt;		/* SDIO TX packet count */
+	u32				MP_RxPktCnt;		/* SDIO RX packet count */
+	u32				MP_TxByteCnt;		/* SDIO TX Byte count */
+	u32				MP_RxByteCnt;		/* SDIO RX Byte count */
+	u32				MP_TxDropCnt;		/* SDIO TX Drop packet count */
+	u32				MP_RxDropCnt;		/* SDIO RX Drop packet count */
+
+	u32				MP_TxPktCntInPeriod;    /* SDIO TX packet count in a period */
+	u32				MP_RxPktCntInPeriod;	/* SDIO RX packet count in a period */
+	u32				MP_TxByteCntInPeriod;	/* SDIO TX Byte count in a period */
+	u32				MP_RxByteCntInPeriod;	/* SDIO RX Byte count in a period */
+
+	u32				MP_TxAvgTPWin[SDIO_AVG_TP_WIN_SIZE];        /* a window of SDIO TX byte count history, for average throughput calculation */
+	u32				MP_RxAvgTPWin[SDIO_AVG_TP_WIN_SIZE];        /* a window of SDIO RX byte count history, for average throughput calculation */
+	u32				MP_TxAvgTPWinSum;        /* The sum of all byte-count in the window */
+	u32				MP_RxAvgTPWinSum;        /* The sum of all byte-count in the window */
+    u8              OldestTxAvgWinIdx;      /* the index of the oldest TX byte count log */
+    u8              TxAvgWinCnt;            /* the number of log in the Window */
+    u8              OldestRxAvgWinIdx;      /* the index of the oldest RX byte count log */
+    u8              RxAvgWinCnt;            /* the number of log in the Window */
+
+	_LIST			MP_RxPktList;		/* The list to queue RX packets, for MP loopback test */
+#endif	// end of '#if SDIO_MP_MODE'
+} HAL_SDIO_ADAPTER, *PHAL_SDIO_ADAPTER;
+#endif  // end of "#else of "#if SDIO_BOOT_DRIVER""
+
+
+typedef struct _HAL_SDIO_OP_ {
+	BOOL (*HalSdioDevInit)(PHAL_SDIO_ADAPTER pSDIODev);	
+	VOID (*HalSdioDevDeInit)(PHAL_SDIO_ADAPTER pSDIODev);
+	VOID (*HalSdioSendC2HIOMsg)(PHAL_SDIO_ADAPTER pSDIODev, u32 *C2HMsg);
+	u8   (*HalSdioSendC2HPktMsg)(PHAL_SDIO_ADAPTER pSDIODev, u8 *C2HMsg, u16 MsgLen);
+	VOID (*HalSdioRegTxCallback)(PHAL_SDIO_ADAPTER pSDIODev,s8 (*CallbackFun)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize), VOID *pAdapter);
+	s8   (*HalSdioRxCallback)(PHAL_SDIO_ADAPTER pSDIODev, VOID *pData, u16 Offset, u16 PktSize, u8 CmdType);
+#if SDIO_MP_MODE
+	VOID (*HalSdioDevMPApp)(PHAL_SDIO_ADAPTER pSDIODev, u16 argc, u8  *argv[]);
+#endif
+}HAL_SDIO_OP, *PHAL_SDIO_OP;
+
+
+extern BOOL SDIO_Device_Init(
+	IN PHAL_SDIO_ADAPTER pSDIODev
+);
+extern VOID SDIO_Device_DeInit(
+	IN PHAL_SDIO_ADAPTER pSDIODev
+);
+extern VOID SDIO_Send_C2H_IOMsg(
+	IN PHAL_SDIO_ADAPTER pSDIODev, 
+	IN u32 *C2HMsg
+);
+extern u8 SDIO_Send_C2H_PktMsg(
+	IN PHAL_SDIO_ADAPTER pSDIODev, 
+	IN u8 *C2HMsg, 
+	IN u16 MsgLen
+);
+extern VOID SDIO_Register_Tx_Callback(
+	IN PHAL_SDIO_ADAPTER pSDIODev,
+	IN s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize),
+	IN VOID *pAdapter	
+);
+extern s8 SDIO_Rx_Callback(
+	IN PHAL_SDIO_ADAPTER pSDIODev,
+	IN VOID *pData,
+	IN u16 Offset,
+	IN u16 Length,
+	IN u8 CmdType
+);
+#if SDIO_MP_MODE
+extern VOID SDIO_DeviceMPApp(
+	IN PHAL_SDIO_ADAPTER pSDIODev,
+	IN u16 argc, 
+    IN u8  *argv[]
+);
+#endif
+
+extern PHAL_SDIO_ADAPTER pgSDIODev;
+extern VOID HalSdioInit(VOID);
+extern VOID HalSdioDeInit(VOID);
+#endif	// #ifndef _HAL_SDIO_H_

component/soc/realtek/8195a/fwlib/hal_sdr_controller.h

@@ -0,0 +1,188 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_SDR_CONTROLLER_H_
+#define _HAL_SDR_CONTROLLER_H_
+
+typedef enum _DRAM_TYPE_ {
+  DRAM_DDR_1 = 1,
+  DRAM_DDR_2 = 2,
+  DRAM_DDR_3 = 3,
+  DRAM_DDR_4 = 4,
+  DRAM_SDR   = 8 
+}DRAM_TYPE;
+
+typedef enum _DRAM_COLADDR_WTH_ {
+  DRAM_COLADDR_8B   = 0,
+  DRAM_COLADDR_9B   = 1,
+  DRAM_COLADDR_10B  = 2,
+  DRAM_COLADDR_11B  = 3,
+  DRAM_COLADDR_12B  = 4,
+  DRAM_COLADDR_13B  = 5,
+  DRAM_COLADDR_14B  = 6,
+  DRAM_COLADDR_15B  = 7,
+  DRAM_COLADDR_16B  = 8 
+}DRAM_COLADDR_WTH;
+
+typedef enum _DRAM_BANK_SIZE_ {
+  DRAM_BANK_2       = 0,
+  DRAM_BANK_4       = 1,
+  DRAM_BANK_8       = 2 
+}DRAM_BANK_SIZE;
+
+typedef enum _DRAM_DQ_WIDTH_ {
+  DRAM_DQ_16        = 0,
+  DRAM_DQ_32        = 1, 
+  DRAM_HALF_DQ32    = 2 
+}DRAM_DQ_WIDTH;
+
+typedef enum _MODE0_BST_LEN_ {
+  BST_LEN_4   = 0,
+  BST_LEN_FLY = 1,
+  BST_LEN_8   = 2 
+}MODE0_BST_LEN;
+
+typedef enum _MODE0_BST_TYPE_ {
+  SENQUENTIAL = 0,
+  INTERLEAVE  = 1 
+}MODE0_BST_TYPE;   
+
+typedef enum _DFI_RATIO_TYPE_ {
+  DFI_RATIO_1 = 0,  // DFI= 1:1, or SDR
+  DFI_RATIO_2 = 1, 
+  DFI_RATIO_4 = 2  
+}DFI_RATIO_TYPE;   
+
+typedef struct _DRAM_INFO_ {
+  DRAM_TYPE         DeviceType;   
+  DRAM_COLADDR_WTH  ColAddrWth;   
+  DRAM_BANK_SIZE    Bank;   
+  DRAM_DQ_WIDTH     DqWidth;
+}DRAM_INFO;
+
+typedef struct _DRAM_MODE_REG_INFO_ {
+  MODE0_BST_LEN     BstLen;
+  MODE0_BST_TYPE    BstType;
+  //enum mode0_cas         rd_cas;
+  u32 Mode0Cas;
+  u32 Mode0Wr;
+  u32 Mode1DllEnN;
+  u32 Mode1AllLat;
+  u32 Mode2Cwl;
+}DRAM_MODE_REG_INFO;
+
+typedef struct _DRAM_TIMING_INFO_ {
+  u32  TrfcPs;
+  u32  TrefiPs;
+  u32  WrMaxTck;
+  u32  TrcdPs; 
+  u32  TrpPs;
+  u32  TrasPs;
+  u32  TrrdTck;
+  u32  TwrPs;
+  u32  TwtrTck; 
+  //u32  TrtpPs;
+  u32  TmrdTck;
+  u32  TrtpTck;
+  u32  TccdTck;
+  u32  TrcPs;
+}DRAM_TIMING_INFO;
+
+
+typedef struct _DRAM_DEVICE_INFO_ {
+  DRAM_INFO          *Dev;
+  DRAM_MODE_REG_INFO *ModeReg;
+  DRAM_TIMING_INFO   *Timing;
+  u32                DdrPeriodPs;
+  DFI_RATIO_TYPE     *DfiRate; 
+}DRAM_DEVICE_INFO;
+
+
+//======================================================
+//DRAM Info
+#ifdef CONFIG_FPGA
+    #define DRAM_INFO_TYPE          DRAM_SDR
+    #define DRAM_INFO_COL_ADDR_WTH  DRAM_COLADDR_9B
+    #define DRAM_INFO_BANK_SZ       DRAM_BANK_4
+    #define DRAM_INFO_DQ_WTH        DRAM_DQ_16
+#else
+    #define DRAM_INFO_TYPE          DRAM_SDR
+    #define DRAM_INFO_COL_ADDR_WTH  DRAM_COLADDR_8B
+    #define DRAM_INFO_BANK_SZ       DRAM_BANK_2
+    #define DRAM_INFO_DQ_WTH        DRAM_DQ_16
+#endif
+
+//======================================================
+//DRAM Timing 
+#ifdef CONFIG_SDR_100MHZ
+#define DRAM_TIMING_TCK         10000       //ps
+#endif
+#ifdef CONFIG_SDR_50MHZ
+#define DRAM_TIMING_TCK         20000       //ps
+#endif
+#ifdef CONFIG_SDR_25MHZ
+#define DRAM_TIMING_TCK         40000       //ps
+#endif
+#ifdef CONFIG_SDR_12_5MHZ
+#define DRAM_TIMING_TCK         80000       //ps
+#endif
+
+#if 1
+#define DRAM_TIMING_TREF        64000       //us
+#define DRAM_ROW_NUM            8192        //depends on row bit number
+
+#define DRAM_TIMING_TRFC        60000       //ps
+#define DRAM_TIMING_TREFI       ((u32)((DRAM_TIMING_TREF*1000)/DRAM_ROW_NUM)*1000)  //ps
+#define DRAM_TIMING_TWRMAXTCK   2           //tck
+#define DRAM_TIMING_TRCD        15000       //ps
+#define DRAM_TIMING_TRP         15000       //ps
+#define DRAM_TIMING_TRAS        42000       //ps
+#define DRAM_TIMING_TRRD        2           //tck
+#define DRAM_TIMING_TWR         ((u32)(DRAM_TIMING_TCK*2))
+#define DRAM_TIMING_TWTR        0           //tck
+#define DRAM_TIMING_TMRD        2           //tck
+#define DRAM_TIMING_TRTP        0           //tck
+#define DRAM_TIMING_TCCD        1           //tck
+#define DRAM_TIMING_TRC         60000       //ps    
+#else
+
+#define DRAM_TIMING_TREF        66000       //us
+#define DRAM_ROW_NUM            8192        //depends on row bit number
+
+#define DRAM_TIMING_TRFC        66000       //ps
+#define DRAM_TIMING_TREFI       63999800
+#define DRAM_TIMING_TWRMAXTCK   2           //tck
+#define DRAM_TIMING_TRCD        15000       //ps
+#define DRAM_TIMING_TRP         15000       //ps
+#define DRAM_TIMING_TRAS        37000       //ps
+#define DRAM_TIMING_TRRD        2           //tck
+#define DRAM_TIMING_TWR         7000
+#define DRAM_TIMING_TWTR        0           //tck
+#define DRAM_TIMING_TMRD        2           //tck
+#define DRAM_TIMING_TRTP        0           //tck
+#define DRAM_TIMING_TCCD        1           //tck
+#define DRAM_TIMING_TRC         60000       //ps
+#endif
+
+#define HAL_SDR_WRITE32(addr, value32)  HAL_WRITE32(SDR_CTRL_BASE, addr, value32)
+#define HAL_SDR_WRITE16(addr, value16)  HAL_WRITE16(SDR_CTRL_BASE, addr, value16)
+#define HAL_SDR_WRITE8(addr, value8)    HAL_WRITE8(SDR_CTRL_BASE, addr, value8)
+#define HAL_SDR_READ32(addr)            HAL_READ32(SDR_CTRL_BASE, addr)
+#define HAL_SDR_READ16(addr)            HAL_READ16(SDR_CTRL_BASE, addr)
+#define HAL_SDR_READ8(addr)             HAL_READ8(SDR_CTRL_BASE, addr)
+
+#define HAL_SDRAM_WRITE32(addr, value32)  HAL_WRITE32(SDR_SDRAM_BASE, addr, value32)
+#define HAL_SDRAM_WRITE16(addr, value16)  HAL_WRITE16(SDR_SDRAM_BASE, addr, value16)
+#define HAL_SDRAM_WRITE8(addr, value8)    HAL_WRITE8(SDR_SDRAM_BASE, addr, value8)
+#define HAL_SDRAM_READ32(addr)            HAL_READ32(SDR_SDRAM_BASE, addr)
+#define HAL_SDRAM_READ16(addr)            HAL_READ16(SDR_SDRAM_BASE, addr)
+#define HAL_SDRAM_READ8(addr)             HAL_READ8(SDR_SDRAM_BASE, addr)
+
+
+#endif  // end of "#ifndef _HAL_SDR_CONTROLLER_H_"

component/soc/realtek/8195a/fwlib/hal_soc_ps_monitor.h

@@ -0,0 +1,254 @@
+#ifndef _HAL_SOCPWR_
+#define _HAL_SOCPWR_
+
+
+
+#define MAX_BACKUP_SIZE 129
+#define MAXFUNC     10
+#define FSTREG      0xFF
+
+#define REG_VDR_ANACK_CAL_CTRL 0xA0
+
+//SLP
+#define     SLP_STIMER    BIT0
+#define     SLP_GTIMER    BIT1
+#define     SLP_GPIO      BIT2
+#define     SLP_WL        BIT3
+#define     SLP_NFC       BIT4
+#define     SLP_SDIO      BIT5
+#define     SLP_USB       BIT6
+#define     SLP_TIMER33   BIT7
+
+//DSTBY
+#define     DSTBY_STIMER  BIT0
+#define     DSTBY_NFC     BIT1
+#define     DSTBY_TIMER33 BIT2
+#define     DSTBY_GPIO    BIT3
+
+//DS wake event
+#define DS_TIMER33 BIT0
+#define DS_GPIO    BIT1
+
+enum power_state_idx{
+    ACT    = 0,
+    WFE    = 1,
+    WFI    = 2,
+    SNOOZE = 3,
+    SLPCG  = 4,
+    SLPPG  = 5,
+    DSTBY  = 6,
+    DSLP   = 7,
+    INACT  = 8,
+    MAXSTATE = 9
+};
+
+enum clk_idx{
+    ANACK = 0,
+    A33CK = 1,
+};
+
+
+typedef struct _power_state_{
+    u8  FuncIdx;
+    u8  PowerState;
+    u32 ReqDuration;
+    u32 RegCount;
+    u32 RemainDuration;
+}POWER_STATE, *pPOWER_STATE;
+
+typedef struct _reg_power_state_{
+    u8  FuncIdx;
+    u8  PwrState;
+    u32 ReqDuration;
+    //u8 StateIdx;
+}REG_POWER_STATE, *pPREG_POWER_STATE;
+
+typedef struct _power_mgn_{
+    u8          ActFuncCount;
+    POWER_STATE PwrState[MAXFUNC];
+    u8          CurrentState;
+    u32         MSPbackup[MAX_BACKUP_SIZE];
+    u32         CPURegbackup[25];
+    u32         CPUPSP;
+    u32         WakeEventFlag;
+    BOOL        SleepFlag;
+    //u32         CPUReg[13];
+    //u32         MSBackUp[128];
+}Power_Mgn, *pPower_Mgn;
+
+typedef struct _SYS_ADAPTER_ {
+    u8      function;
+}SYS_ADAPTER, *PSYS_ADAPTER;
+
+extern Power_Mgn PwrAdapter;
+
+u8 ChangeSoCPwrState(
+    IN  u8  RequestState,
+    IN  u32 ReqCount
+);
+
+VOID PrintCPU(VOID);
+void WakeFromSLPPG(void);
+VOID SOCPSTestApp(VOID *Data);
+
+
+__inline static VOID 
+CPURegBackUp(
+    VOID
+)
+{
+#if defined (__ICCARM__)
+    // TODO: IAR has different way using assembly
+#elif defined (__GNUC__)
+	//backup cpu reg
+    #if 0
+    asm volatile
+    (
+        "PUSH {PSR, PC, LR, R12,R3,R2,R1,R0}\n"
+    );
+    #endif
+    #if 0
+    asm volatile
+    (
+        "PUSH {r0,r1,r2,r3,r4}\n"
+    );
+    #endif
+    
+    asm volatile
+    (
+
+        "MOV %0, r0\n"
+        :"=r"(PwrAdapter.CPURegbackup[0])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r1\n"
+        :"=r"(PwrAdapter.CPURegbackup[1])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r2\n"
+        :"=r"(PwrAdapter.CPURegbackup[2])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r3\n"
+        :"=r"(PwrAdapter.CPURegbackup[3])
+        ::"memory"
+    );
+    
+    asm volatile
+    (
+        "MOV %0, r4\n"
+        :"=r"(PwrAdapter.CPURegbackup[4])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r5\n"
+        :"=r"(PwrAdapter.CPURegbackup[5])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r6\n"
+        :"=r"(PwrAdapter.CPURegbackup[6])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r7\n"
+        :"=r"(PwrAdapter.CPURegbackup[7])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r8\n"
+        :"=r"(PwrAdapter.CPURegbackup[8])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r9\n"
+        :"=r"(PwrAdapter.CPURegbackup[9])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r10\n"
+        :"=r"(PwrAdapter.CPURegbackup[10])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r11\n"
+        :"=r"(PwrAdapter.CPURegbackup[11])
+        ::"memory"
+    );
+    asm volatile
+    (
+        "MOV %0, r12\n"
+        :"=r"(PwrAdapter.CPURegbackup[12])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r13\n"
+        :"=r"(PwrAdapter.CPURegbackup[13])
+        ::"memory"
+    );
+    asm volatile
+    (
+        //"MOV %0, r14\n"
+        "LDR %0, =SLPPG_WAKEUP_POINT\n"
+        "ADD %0, #1\n"
+        :"=r"(PwrAdapter.CPURegbackup[14])
+        ::"memory"
+    );
+    asm volatile
+    (
+        "LDR %0, =SLPPG_WAKEUP_POINT\n"
+        "ADD %0, #1\n"
+        :"=r"(PwrAdapter.CPURegbackup[15])
+        ::"memory"
+    );
+    asm volatile
+    (
+        "MRS %0, PSR\n"
+        :"=r"(PwrAdapter.CPURegbackup[16])
+        ::"memory"
+    );
+
+#if 1
+    asm volatile
+    (
+        "mov %0, r13\n"
+        "MOV %1, PC\n" 
+        "MRS %2, CONTROL\n"
+        "MRS %3, PSP\n" 
+        "MRS %4, MSP\n" 
+        :"=r"(PwrAdapter.CPURegbackup[24]),"=r"(PwrAdapter.CPURegbackup[23]),"=r"(PwrAdapter.CPURegbackup[22]),"=r"(PwrAdapter.CPURegbackup[21]),"=r"(PwrAdapter.CPURegbackup[20])
+        ::"memory"
+    );
+#endif
+    #ifdef CONFIG_SOC_PS_VERIFY
+    PrintCPU();
+    #endif  //#ifdef CONFIG_SOC_PS_VERIFY
+#endif //#elif defined (__GNUC__)
+}
+
+#endif  //_HAL_SOCPWR_

component/soc/realtek/8195a/fwlib/hal_spi_flash.h

@@ -0,0 +1,235 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _HAL_SPIFLASH__
+#define _HAL_SPIFLASH__
+//======================================================
+// Header files
+#include "rtl8195a_spi_flash.h"
+
+#define SPIC_CALIBRATION_IN_NVM         1   // if store the SPIC calibration data in the NVM
+#ifndef CONFIG_IMAGE_SEPARATE       // Store SPIC Calibration only for seprated image
+#undef SPIC_CALIBRATION_IN_NVM
+#define SPIC_CALIBRATION_IN_NVM         0
+#endif
+
+//======================================================
+// Definition
+#define HAL_SPI_WRITE32(addr, value32)  HAL_WRITE32(SPI_FLASH_CTRL_BASE, addr, value32)
+#define HAL_SPI_WRITE16(addr, value16)  HAL_WRITE16(SPI_FLASH_CTRL_BASE, addr, value16)
+#define HAL_SPI_WRITE8(addr, value8)    HAL_WRITE8(SPI_FLASH_CTRL_BASE, addr, value8)
+#define HAL_SPI_READ32(addr)            HAL_READ32(SPI_FLASH_CTRL_BASE, addr)
+#define HAL_SPI_READ16(addr)            HAL_READ16(SPI_FLASH_CTRL_BASE, addr)
+#define HAL_SPI_READ8(addr)             HAL_READ8(SPI_FLASH_CTRL_BASE, addr)
+
+typedef struct _SPIC_INIT_PARA_ {
+    u8  BaudRate;
+    u8  RdDummyCyle;
+    u8  DelayLine;
+    union {
+        u8  Rsvd;
+        u8  Valid;
+    };
+}SPIC_INIT_PARA, *PSPIC_INIT_PARA;
+
+
+enum _SPIC_BIT_MODE_ {
+    SpicOneBitMode = 0,
+    SpicDualBitMode = 1,
+    SpicQuadBitMode = 2,
+};
+
+//======================================================
+// Flash type used 
+#define FLASH_MXIC_MX25L4006E   1
+#define FLASH_MXIC_MX25L8073E   0
+
+// The below parts are based on the flash characteristics
+//====== Flash Command Definition  ======
+#if FLASH_MXIC_MX25L4006E
+    #define FLASH_CMD_WREN      0x06            //write enable
+    #define FLASH_CMD_WRDI      0x04            //write disable
+    #define FLASH_CMD_WRSR      0x01            //write status register
+    #define FLASH_CMD_RDID      0x9F            //read idenfication
+    #define FLASH_CMD_RDSR      0x05            //read status register
+    #define FLASH_CMD_READ      0x03            //read data
+    #define FLASH_CMD_FREAD     0x0B            //fast read data
+    #define FLASH_CMD_RDSFDP    0x5A            //Read SFDP
+    #define FLASH_CMD_RES       0xAB            //Read Electronic ID
+    #define FLASH_CMD_REMS      0x90            //Read Electronic Manufacturer & Device ID
+    #define FLASH_CMD_DREAD     0x3B            //Double Output Mode command
+    #define FLASH_CMD_SE        0x20            //Sector Erase
+    #define FLASH_CMD_BE        0xD8            //Block Erase(or 0x52)
+    #define FLASH_CMD_CE        0x60            //Chip Erase(or 0xC7)
+    #define FLASH_CMD_PP        0x02            //Page Program
+    #define FLASH_CMD_DP        0xB9            //Deep Power Down
+    #define FLASH_CMD_RDP       0xAB            //Release from Deep Power-Down
+#elif  FLASH_MXIC_MX25L8073E
+    #define FLASH_CMD_WREN      0x06            //write enable
+    #define FLASH_CMD_WRDI      0x04            //write disable
+    #define FLASH_CMD_WRSR      0x01            //write status register
+    #define FLASH_CMD_RDID      0x9F            //read idenfication
+    #define FLASH_CMD_RDSR      0x05            //read status register
+    #define FLASH_CMD_READ      0x03            //read data
+    #define FLASH_CMD_FREAD     0x0B            //fast read data
+    #define FLASH_CMD_RDSFDP    0x5A            //Read SFDP
+    #define FLASH_CMD_RES       0xAB            //Read Electronic ID
+    #define FLASH_CMD_REMS      0x90            //Read Electronic Manufacturer & Device ID
+    #define FLASH_CMD_DREAD     0x3B            //Double Output Mode command
+    #define FLASH_CMD_SE        0x20            //Sector Erase
+    #define FLASH_CMD_BE        0x52            //Block Erase
+    #define FLASH_CMD_CE        0x60            //Chip Erase(or 0xC7)
+    #define FLASH_CMD_PP        0x02            //Page Program
+    #define FLASH_CMD_DP        0xB9            //Deep Power Down
+    #define FLASH_CMD_RDP       0xAB            //Release from Deep Power-Down
+    #define FLASH_CMD_2READ     0xBB            // 2 x I/O read  command
+    #define FLASH_CMD_4READ     0xEB            // 4 x I/O read  command
+    #define FLASH_CMD_QREAD     0x6B            // 1I / 4O read command
+    #define FLASH_CMD_4PP       0x38            //quad page program
+    #define FLASH_CMD_FF        0xFF            //Release Read Enhanced
+    #define FLASH_CMD_REMS2     0xEF            // read ID for 2x I/O mode
+    #define FLASH_CMD_REMS4     0xDF            // read ID for 4x I/O mode
+    #define FLASH_CMD_ENSO      0xB1            // enter secured OTP
+    #define FLASH_CMD_EXSO      0xC1            // exit secured OTP
+    #define FLASH_CMD_RDSCUR    0x2B            // read security register
+    #define FLASH_CMD_WRSCUR    0x2F            // write security register
+#else
+    #define FLASH_CMD_WREN      0x06            //write enable
+    #define FLASH_CMD_WRDI      0x04            //write disable
+    #define FLASH_CMD_WRSR      0x01            //write status register
+    #define FLASH_CMD_RDID      0x9F            //read idenfication
+    #define FLASH_CMD_RDSR      0x05            //read status register
+    #define FLASH_CMD_READ      0x03            //read data
+    #define FLASH_CMD_FREAD     0x0B            //fast read data
+    #define FLASH_CMD_RDSFDP    0x5A            //Read SFDP
+    #define FLASH_CMD_RES       0xAB            //Read Electronic ID
+    #define FLASH_CMD_REMS      0x90            //Read Electronic Manufacturer & Device ID
+    #define FLASH_CMD_DREAD     0x3B            //Double Output Mode command
+    #define FLASH_CMD_SE        0x20            //Sector Erase
+    #define FLASH_CMD_BE        0x52            //Block Erase
+    #define FLASH_CMD_CE        0x60            //Chip Erase(or 0xC7)
+    #define FLASH_CMD_PP        0x02            //Page Program
+    #define FLASH_CMD_DP        0xB9            //Deep Power Down
+    #define FLASH_CMD_RDP       0xAB            //Release from Deep Power-Down
+    #define FLASH_CMD_2READ     0xBB            // 2 x I/O read  command
+    #define FLASH_CMD_4READ     0xEB            // 4 x I/O read  command
+    #define FLASH_CMD_QREAD     0x6B            // 1I / 4O read command
+    #define FLASH_CMD_4PP       0x38            //quad page program
+    #define FLASH_CMD_FF        0xFF            //Release Read Enhanced
+    #define FLASH_CMD_REMS2     0xEF            // read ID for 2x I/O mode
+    #define FLASH_CMD_REMS4     0xDF            // read ID for 4x I/O mode
+    #define FLASH_CMD_ENSO      0xB1            // enter secured OTP
+    #define FLASH_CMD_EXSO      0xC1            // exit secured OTP
+    #define FLASH_CMD_RDSCUR    0x2B            // read security register
+    #define FLASH_CMD_WRSCUR    0x2F            // write security register
+#endif //#if FLASH_MXIC_MX25L4006E
+// ============================
+
+// =====  Flash Parameter Definition  =====
+#if FLASH_MXIC_MX25L4006E
+    #define FLASH_RD_2IO_EN         0
+    #define FLASH_RD_2O_EN          1
+    #define FLASH_RD_4IO_EN         0
+    #define FLASH_RD_4O_EN          0
+    #define FLASH_WR_2IO_EN         0
+    #define FLASH_WR_2O_EN          0
+    #define FLASH_WR_4IO_EN         0
+    #define FLASH_WR_4O_EN          0    
+    
+    #define FLASH_DM_CYCLE_2O   0x08
+    #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_I)
+    #define FLASH_VLD_QUAD_CMDS (0)
+    
+#elif  FLASH_MXIC_MX25L8073E //This flash model is just for prototype, if you want to use it, 
+                             //the code MUST be rechecked according to the flash spec.
+    #define FLASH_RD_2IO_EN         1
+    #define FLASH_RD_2O_EN          0
+    #define FLASH_RD_4IO_EN         1
+    #define FLASH_RD_4O_EN          0
+    #define FLASH_WR_2IO_EN         1
+    #define FLASH_WR_2O_EN          0
+    #define FLASH_WR_4IO_EN         1
+    #define FLASH_WR_4O_EN          0                             
+    
+    #define FLASH_DM_CYCLE_2O  0x08
+    #define FLASH_DM_CYCLE_2IO 0x04
+    #define FLASH_DM_CYCLE_4O  0x08
+    #define FLASH_DM_CYCLE_4IO 0x04
+    
+    #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
+    #define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
+#else
+    #define FLASH_RD_2IO_EN         1
+    #define FLASH_RD_2O_EN          0
+    #define FLASH_RD_4IO_EN         1
+    #define FLASH_RD_4O_EN          0
+    #define FLASH_WR_2IO_EN         1
+    #define FLASH_WR_2O_EN          0
+    #define FLASH_WR_4IO_EN         1
+    #define FLASH_WR_4O_EN          0
+    
+    #define FLASH_DM_CYCLE_2O  0x08
+    #define FLASH_DM_CYCLE_2IO 0x04
+    #define FLASH_DM_CYCLE_4O  0x08
+    #define FLASH_DM_CYCLE_4IO 0x04
+    
+    #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)  
+    #define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
+#endif
+#if 0
+//======================================================
+// Function prototype
+BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
+
+_LONG_CALL_
+extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara); 
+
+// spi-flash controller initialization
+_LONG_CALL_
+extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode);
+
+// wait sr[0] = 0, wait transmission done
+_LONG_CALL_
+extern VOID SpicWaitBusyDoneRtl8195A(VOID);
+
+// wait spi-flash status register[0] = 0
+//_LONG_CALL_
+//extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara);
+#endif
+
+//======================================================
+// ROM Function prototype
+_LONG_CALL_ VOID SpiFlashAppV02(IN  VOID *Data);
+_LONG_CALL_ VOID SpicInitRtl8195AV02(IN  u8 InitBaudRate,IN  u8 SpicBitMode);
+
+_LONG_CALL_ VOID SpicEraseFlashRtl8195AV02();
+
+_LONG_CALL_ VOID SpicLoadInitParaFromClockRtl8195AV02(IN  u8 CpuClkMode,IN  u8 BaudRate,IN  PSPIC_INIT_PARA pSpicInitPara);
+
+
+VOID SpicBlockEraseFlashRtl8195A(IN u32 Address);
+VOID SpicSectorEraseFlashRtl8195A(IN u32 Address);
+VOID SpicWriteProtectFlashRtl8195A(IN u32 Protect);
+VOID SpicWaitWipDoneRefinedRtl8195A(IN  SPIC_INIT_PARA SpicInitPara);
+VOID SpicRxCmdRefinedRtl8195A(IN  u8 cmd,IN  SPIC_INIT_PARA SpicInitPara);
+u8 SpicGetFlashStatusRefinedRtl8195A(IN  SPIC_INIT_PARA SpicInitPara);
+VOID SpicInitRefinedRtl8195A(IN  u8 InitBaudRate,IN  u8 SpicBitMode);
+u32 SpicWaitWipRtl8195A(VOID);
+u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk);
+VOID SpicDisableRtl8195A(VOID);
+VOID SpicDeepPowerDownFlashRtl8195A(VOID);
+
+#if SPIC_CALIBRATION_IN_NVM
+VOID SpicNVMCalLoad(u8 BitMode, u8 CpuClk);
+VOID SpicNVMCalLoadAll(void);
+VOID SpicNVMCalStore(u8 BitMode, u8 CpuClk);
+#endif  // #if SPIC_CALIBRATION_IN_NVM
+
+#endif //_HAL_SPIFLASH__

component/soc/realtek/8195a/fwlib/hal_ssi.h

@@ -0,0 +1,303 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_SSI_H_
+#define _HAL_SSI_H_
+
+#include "rtl8195a_ssi.h"
+
+/**
+ * LOG Configurations
+ */
+
+extern u32 SSI_DBG_CONFIG;
+extern uint8_t SPI0_IS_AS_SLAVE;
+
+
+#define SSI_DBG_ENTRANCE(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENTRANCE)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE ANSI_COLOR_GREEN __VA_ARGS__ ANSI_COLOR_RESET); \
+}while(0)
+
+#define SSI_DBG_INIT(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INIT_V(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_V)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INIT_VV(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_VV)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_PINMUX(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_PINMUX)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_ENDIS(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENDIS)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INT(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INT_V(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_V)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INT_HNDLR(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_HNDLR)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INT_READ(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_READ)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INT_WRITE(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_WRITE)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_STATUS(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_STATUS)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_FIFO(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_FIFO)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_READ(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_READ)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_WRITE(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_WRITE)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_SLV_CTRL(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_SLV_CTRL)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+typedef enum _SSI_DBG_TYPE_LIST_ {
+    DBG_TYPE_ENTRANCE  = 1 << 0,
+    DBG_TYPE_INIT      = 1 << 1,
+    DBG_TYPE_INIT_V    = 1 << 2,
+    DBG_TYPE_INIT_VV   = 1 << 3,
+    DBG_TYPE_PINMUX    = 1 << 4,
+    DBG_TYPE_ENDIS     = 1 << 5,
+    DBG_TYPE_INT       = 1 << 6,
+    DBG_TYPE_INT_V     = 1 << 7,
+    DBG_TYPE_INT_HNDLR = 1 << 8,
+    DBG_TYPE_INT_READ  = 1 << 9,
+    DBG_TYPE_INT_WRITE = 1 << 10,
+    DBG_TYPE_STATUS    = 1 << 11,
+    DBG_TYPE_FIFO      = 1 << 12,
+    DBG_TYPE_READ      = 1 << 13,
+    DBG_TYPE_WRITE     = 1 << 14,
+    DBG_TYPE_SLV_CTRL  = 1 << 15
+} SSI_DBG_TYPE_LIST, *PSSI_DBG_TYPE_LIST;
+
+ typedef struct _SSI_DMA_CONFIG_ {
+    VOID *pHalGdmaOp;
+    VOID *pTxHalGdmaAdapter;
+    VOID *pRxHalGdmaAdapter;
+    u8    RxDmaBurstSize;
+    u8    TxDmaBurstSize;
+    u8    RxDmaEnable;
+    u8    TxDmaEnable;
+    IRQ_HANDLE RxGdmaIrqHandle;
+    IRQ_HANDLE TxGdmaIrqHandle;
+}SSI_DMA_CONFIG, *PSSI_DMA_CONFIG;
+
+/**
+ * DesignWare SSI Configurations
+ */
+typedef struct _HAL_SSI_ADAPTOR_ {
+    SSI_DMA_CONFIG DmaConfig;
+    IRQ_HANDLE IrqHandle;
+    //
+    VOID (*RxCompCallback)(VOID *Para);
+    VOID *RxCompCbPara;
+    VOID *RxData;
+    VOID (*TxCompCallback)(VOID *Para);
+    VOID *TxCompCbPara;
+    VOID *TxData;
+    u32  DmaRxDataLevel;
+    u32  DmaTxDataLevel;
+    u32  InterruptPriority;
+    u32  RxLength;
+    u32  RxLengthRemainder;
+    u32  RxThresholdLevel;
+    u32  TxLength;
+    u32  TxThresholdLevel;
+    u32  SlaveSelectEnable;
+    //
+    u16  ClockDivider;
+    u16  DataFrameNumber;
+    //
+    u8   ControlFrameSize;
+    u8   DataFrameFormat;
+    u8   DataFrameSize;
+    u8   DmaControl;
+    u8   Index;
+    u8   InterruptMask;
+    u8   MicrowireDirection;
+    u8   MicrowireHandshaking;
+    u8   MicrowireTransferMode;
+    u8   PinmuxSelect;
+    u8   Role;
+    u8   SclkPhase;
+    u8   SclkPolarity;
+    u8   SlaveOutputEnable;
+    u8   TransferMode;
+    u8   TransferMechanism;
+
+    // Extend
+    u32 Reserved1;
+    u8 DefaultRxThresholdLevel;
+}HAL_SSI_ADAPTOR, *PHAL_SSI_ADAPTOR;
+
+typedef struct _HAL_SSI_OP_{
+    HAL_Status (*HalSsiPinmuxEnable)(VOID *Adaptor);
+    HAL_Status (*HalSsiPinmuxDisable)(VOID *Adaptor);
+    HAL_Status (*HalSsiEnable)(VOID *Adaptor);
+    HAL_Status (*HalSsiDisable)(VOID *Adaptor);
+    HAL_Status (*HalSsiInit)(VOID *Adaptor);
+    HAL_Status (*HalSsiSetSclkPolarity)(VOID *Adaptor);
+    HAL_Status (*HalSsiSetSclkPhase)(VOID *Adaptor);
+    HAL_Status (*HalSsiWrite)(VOID *Adaptor, u32 value);
+    HAL_Status (*HalSsiLoadSetting)(VOID *Adaptor, VOID *Setting);
+    HAL_Status (*HalSsiSetInterruptMask)(VOID *Adaptor);
+    HAL_Status (*HalSsiSetDeviceRole)(VOID *Adaptor, u32 Role);
+    HAL_Status (*HalSsiInterruptEnable)(VOID *Adaptor);
+    HAL_Status (*HalSsiInterruptDisable)(VOID *Adaptor);
+    HAL_Status (*HalSsiReadInterrupt)(VOID *Adaptor, VOID *RxData, u32 Length);
+    HAL_Status (*HalSsiSetRxFifoThresholdLevel)(VOID *Adaptor);
+    HAL_Status (*HalSsiSetTxFifoThresholdLevel)(VOID *Adaptor);
+    HAL_Status (*HalSsiWriteInterrupt)(VOID *Adaptor, u8 *TxData, u32 Length);
+    HAL_Status (*HalSsiSetSlaveEnableRegister)(VOID *Adaptor, u32 SlaveIndex);
+    u32  (*HalSsiBusy)(VOID *Adaptor);
+    u32  (*HalSsiReadable)(VOID *Adaptor);
+    u32  (*HalSsiWriteable)(VOID *Adaptor);
+    u32  (*HalSsiGetInterruptMask)(VOID *Adaptor);
+    u32  (*HalSsiGetRxFifoLevel)(VOID *Adaptor);
+    u32  (*HalSsiGetTxFifoLevel)(VOID *Adaptor);
+    u32  (*HalSsiGetStatus)(VOID *Adaptor);
+    u32  (*HalSsiGetInterruptStatus)(VOID *Adaptor);
+    u32  (*HalSsiRead)(VOID *Adaptor);
+    u32  (*HalSsiGetRawInterruptStatus)(VOID *Adaptor);
+    u32  (*HalSsiGetSlaveEnableRegister)(VOID *Adaptor);
+}HAL_SSI_OP, *PHAL_SSI_OP;
+
+typedef struct _DW_SSI_DEFAULT_SETTING_ {
+    VOID (*RxCompCallback)(VOID *Para);
+    VOID *RxCompCbPara;
+    VOID *RxData;
+    VOID (*TxCompCallback)(VOID *Para);
+    VOID *TxCompCbPara;
+    VOID *TxData;
+    u32  DmaRxDataLevel;
+    u32  DmaTxDataLevel;
+    u32  InterruptPriority;
+    u32  RxLength;
+    u32  RxLengthRemainder;
+    u32  RxThresholdLevel;
+    u32  TxLength;
+    u32  TxThresholdLevel;
+    u32  SlaveSelectEnable;
+    //
+    u16  ClockDivider;
+    u16  DataFrameNumber;
+    //
+    u8   ControlFrameSize;
+    u8   DataFrameFormat;
+    u8   DataFrameSize;
+    u8   DmaControl;
+    //u8   Index;
+    u8   InterruptMask;
+    u8   MicrowireDirection;
+    u8   MicrowireHandshaking;
+    u8   MicrowireTransferMode;
+    //u8   PinmuxSelect;
+    //u8   Role;
+    u8   SclkPhase;
+    u8   SclkPolarity;
+    u8   SlaveOutputEnable;
+    u8   TransferMode;
+    u8   TransferMechanism;
+} DW_SSI_DEFAULT_SETTING, *PDW_SSI_DEFAULT_SETTING;
+
+
+struct spi_s {
+    HAL_SSI_ADAPTOR spi_adp;
+    HAL_SSI_OP      spi_op;
+    u32 irq_handler;
+    u32 irq_id;
+    u32 dma_en;
+    u32 state;
+    u8 sclk;
+#ifdef CONFIG_GDMA_EN    
+    HAL_GDMA_ADAPTER spi_gdma_adp_tx;
+    HAL_GDMA_ADAPTER spi_gdma_adp_rx;
+#endif    
+};
+
+VOID HalSsiOpInit(VOID *Adaptor);
+static __inline__ VOID HalSsiSetSclk(
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter,
+    IN u32 ClkRate)
+{
+    HalSsiSetSclkRtl8195a((VOID*)pHalSsiAdapter, ClkRate);
+}
+
+#ifdef CONFIG_GDMA_EN    
+HAL_Status HalSsiTxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
+VOID HalSsiTxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
+HAL_Status HalSsiRxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
+VOID HalSsiRxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
+
+static __inline__ VOID
+HalSsiDmaInit(
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    HalSsiDmaInitRtl8195a((void *)pHalSsiAdapter);
+}
+
+static __inline__ HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length)
+{
+    return (HalSsiDmaSendRtl8195a(Adapter, pTxData, Length));
+}
+
+static __inline__ HAL_Status HalSsiDmaRecv(VOID *Adapter, u8  *pRxData, u32 Length)
+{
+    return (HalSsiDmaRecvRtl8195a(Adapter, pRxData, Length));
+}
+    
+
+#endif  // end of "#ifdef CONFIG_GDMA_EN"
+
+#endif
+

component/soc/realtek/8195a/fwlib/hal_timer.h

@@ -0,0 +1,57 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_TIMER_H_
+#define _HAL_TIMER_H_
+#include "basic_types.h"
+#include "hal_platform.h"
+#include "rtl8195a_timer.h"
+
+#define TIMER_TICK_US_X4        (4*1000000/32000)
+
+typedef enum _TIMER_MODE_ {
+    FREE_RUN_MODE = 0,
+    USER_DEFINED = 1
+}TIMER_MODE, *PTIMER_MODE;
+
+
+typedef struct _TIMER_ADAPTER_ {
+
+    u32         TimerLoadValueUs;
+    u32         TimerIrqPriority;
+    TIMER_MODE  TimerMode;
+    IRQ_HANDLE  IrqHandle;
+    u8          TimerId;    
+    u8          IrqDis;
+
+}TIMER_ADAPTER, *PTIMER_ADAPTER;
+
+
+typedef struct _HAL_TIMER_OP_ {
+    u32  (*HalGetTimerId)(u32 *TimerId);
+    BOOL (*HalTimerInit)(VOID *Data);
+    u32  (*HalTimerReadCount)(u32 TimerId);
+    VOID (*HalTimerIrqClear)(u32 TimerId);
+    VOID (*HalTimerDis)(u32 TimerId);
+    VOID (*HalTimerEn)(u32 TimerId);
+    VOID (*HalTimerDumpReg)(u32 TimerId);
+}HAL_TIMER_OP, *PHAL_TIMER_OP;
+
+VOID HalTimerOpInit_Patch(
+    IN  VOID *Data
+);
+
+
+//======================================================
+// ROM Function prototype
+_LONG_CALL_ VOID HalTimerOpInitV02(IN  VOID *Data);
+
+#define HalTimerOpInit      HalTimerOpInit_Patch
+
+#endif

component/soc/realtek/8195a/fwlib/hal_uart.h

@@ -0,0 +1,145 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_UART_H_
+#define _HAL_UART_H_
+
+#include "rtl8195a_uart.h"
+
+/**
+ * RUART Configurations
+ */
+#define UART_WAIT_FOREVER       0xffffffff
+
+typedef struct _UART_DMA_CONFIG_ {
+    u8 TxDmaEnable;
+    u8 RxDmaEnable;
+    u8 TxDmaBurstSize;
+    u8 RxDmaBurstSize;
+    VOID *pHalGdmaOp;
+    VOID *pTxHalGdmaAdapter;
+    VOID *pRxHalGdmaAdapter;
+    IRQ_HANDLE TxGdmaIrqHandle;
+    IRQ_HANDLE RxGdmaIrqHandle;
+}UART_DMA_CONFIG, *PUART_DMA_CONFIG;
+
+typedef struct _HAL_RUART_ADAPTER_ {
+    u32 BaudRate;
+    u32 FlowControl;
+    u32 FifoControl;
+    u32 Interrupts;
+    u32 TxCount;     // how many byte to TX
+    u32 RxCount;     // how many bytes to RX
+    u8 *pTxBuf;
+    u8 *pRxBuf;
+    HAL_UART_State State;       // UART state
+    u8 Status;      // Transfer Status
+    u8 Locked;      // is UART locked for operation
+    u8 UartIndex;
+    u8 WordLen;     // word length select: 0 -> 7 bits, 1 -> 8 bits
+    u8 StopBit;     // word length select: 0 -> no stop bit, 1 -> 1 stop bit
+    u8 Parity;      // parity check enable
+    u8 ParityType;  // parity check type
+    u8 StickParity;
+    u8 ModemStatus; // the modem status
+    u8 DmaEnable;
+    u8 TestCaseNumber;
+    u8 PinmuxSelect;
+    BOOL PullMode;
+    IRQ_HANDLE IrqHandle;
+    PUART_DMA_CONFIG DmaConfig;
+    VOID (*ModemStatusInd)(VOID *pAdapter);    // modem status indication interrupt handler
+    VOID (*TxTDCallback)(VOID *pAdapter);      // User Tx Done callback function
+    VOID (*RxDRCallback)(VOID *pAdapter);      // User Rx Data ready callback function
+    VOID (*TxCompCallback)(VOID *para);    // User Tx complete callback function
+    VOID (*RxCompCallback)(VOID *para);    // User Rx complete callback function
+    VOID *TxTDCbPara;   // the pointer agrument for TxTDCallback
+    VOID *RxDRCbPara;   // the pointer agrument for RxDRCallback
+    VOID *TxCompCbPara; // the pointer argument for TxCompCbPara
+    VOID *RxCompCbPara; // the pointer argument for RxCompCallback
+    VOID (*EnterCritical)(void);
+    VOID (*ExitCritical)(void);
+}HAL_RUART_ADAPTER, *PHAL_RUART_ADAPTER;
+
+typedef struct _HAL_RUART_OP_ {
+    VOID (*HalRuartAdapterLoadDef)(VOID *pAdp, u8 UartIdx);    // Load UART adapter default setting
+    VOID (*HalRuartTxGdmaLoadDef)(VOID *pAdp, VOID *pCfg);     // Load TX GDMA default setting
+    VOID (*HalRuartRxGdmaLoadDef)(VOID *pAdp, VOID *pCfg);     // Load RX GDMA default setting
+    HAL_Status (*HalRuartResetRxFifo)(VOID *Data);
+    HAL_Status (*HalRuartInit)(VOID *Data);
+    VOID (*HalRuartDeInit)(VOID *Data);
+    HAL_Status (*HalRuartPutC)(VOID *Data, u8 TxData);
+    u32  (*HalRuartSend)(VOID *Data, u8 *pTxData, u32 Length, u32 Timeout);
+    HAL_Status  (*HalRuartIntSend)(VOID *Data, u8 *pTxData, u32 Length);
+    HAL_Status  (*HalRuartDmaSend)(VOID *Data, u8 *pTxData, u32 Length);
+    HAL_Status  (*HalRuartStopSend)(VOID *Data);
+    HAL_Status (*HalRuartGetC)(VOID *Data, u8 *pRxByte);
+    u32  (*HalRuartRecv)(VOID *Data, u8  *pRxData, u32 Length, u32 Timeout);
+    HAL_Status  (*HalRuartIntRecv)(VOID *Data, u8  *pRxData, u32 Length);
+    HAL_Status  (*HalRuartDmaRecv)(VOID *Data, u8  *pRxData, u32 Length);
+    HAL_Status  (*HalRuartStopRecv)(VOID *Data);
+    u8   (*HalRuartGetIMR)(VOID *Data);
+    VOID (*HalRuartSetIMR)(VOID *Data);
+    u32  (*HalRuartGetDebugValue)(VOID *Data, u32 DbgSel);
+    VOID (*HalRuartDmaInit)(VOID *Data);
+    VOID (*HalRuartRTSCtrl)(VOID *Data, BOOLEAN RtsCtrl);
+    VOID (*HalRuartRegIrq)(VOID *Data);
+    VOID (*HalRuartIntEnable)(VOID *Data);
+    VOID (*HalRuartIntDisable)(VOID *Data);
+}HAL_RUART_OP, *PHAL_RUART_OP;
+
+typedef struct _RUART_DATA_ {
+    PHAL_RUART_ADAPTER pHalRuartAdapter;
+    BOOL PullMode;
+    u8   BinaryData;
+    u8   SendBuffer;
+    u8   RecvBuffer;
+}RUART_DATA, *PRUART_DATA;
+
+typedef struct _RUART_ADAPTER_ {
+    PHAL_RUART_OP      pHalRuartOp;
+    PHAL_RUART_ADAPTER pHalRuartAdapter;
+    PUART_DMA_CONFIG   pHalRuartDmaCfg;
+}RUART_ADAPTER, *PRUART_ADAPTER;
+
+extern VOID
+HalRuartOpInit(
+        IN VOID *Data
+);
+
+extern HAL_Status
+HalRuartTxGdmaInit(
+    PHAL_RUART_OP pHalRuartOp,
+    PHAL_RUART_ADAPTER pHalRuartAdapter,
+    PUART_DMA_CONFIG pUartGdmaConfig
+);
+
+extern VOID
+HalRuartTxGdmaDeInit(
+    PUART_DMA_CONFIG pUartGdmaConfig
+);
+
+extern HAL_Status
+HalRuartRxGdmaInit(
+    PHAL_RUART_OP pHalRuartOp,
+    PHAL_RUART_ADAPTER pHalRuartAdapter,
+    PUART_DMA_CONFIG pUartGdmaConfig
+);
+
+extern VOID
+HalRuartRxGdmaDeInit(
+    PUART_DMA_CONFIG pUartGdmaConfig
+);
+
+extern const HAL_RUART_OP _HalRuartOp;
+extern HAL_Status RuartLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
+extern VOID RuartUnLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
+
+#endif
+

component/soc/realtek/8195a/fwlib/hal_util.h

@@ -0,0 +1,252 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+#ifndef _HAL_UTIL_H_
+#define _HAL_UTIL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Simple doubly linked list implementation.
+ *
+ * Some of the internal functions ("__xxx") are useful when
+ * manipulating whole lists rather than single entries, as
+ * sometimes we already know the next/prev entries and we can
+ * generate better code by using them directly rather than
+ * using the generic single-entry routines.
+ */
+struct LIST_HEADER {
+	struct LIST_HEADER *Next, *Prev;
+};
+
+typedef struct  LIST_HEADER     _LIST;
+
+//#define RTL_LIST_HEAD_INIT(name) { &(name), &(name) }
+
+#define RTL_INIT_LIST_HEAD(ptr) do { \
+	(ptr)->Next = (ptr); (ptr)->Prev = (ptr); \
+} while (0)
+
+
+/*
+ * Insert a new entry between two known consecutive entries. 
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+ static __inline__ VOID 
+ __List_Add(
+    IN  struct LIST_HEADER * New,
+    IN  struct LIST_HEADER * Prev,
+    IN  struct LIST_HEADER * Next
+)
+{
+	Next->Prev = New;
+	New->Next = Next;
+	New->Prev = Prev;
+	Prev->Next = New;
+}
+
+/*
+ * Delete a list entry by making the prev/next entries
+ * point to each other.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+ static __inline__ VOID
+ __List_Del(
+    IN  struct LIST_HEADER * Prev,
+    IN  struct LIST_HEADER * Next
+ )
+{
+	Next->Prev = Prev;
+	Prev->Next = Next;
+}
+
+/**
+ * ListDel - deletes entry from list.
+ * @entry: the element to delete from the list.
+ * Note: list_empty on entry does not return true after this, the entry is in an undefined state.
+ */
+static __inline__ VOID 
+ListDel(
+    IN  struct LIST_HEADER *Entry
+)
+{
+	__List_Del(Entry->Prev, Entry->Next);
+}
+
+/**
+ * ListDelInit - deletes entry from list and reinitialize it.
+ * @entry: the element to delete from the list.
+ */
+static  __inline__ VOID
+ListDelInit(
+    IN  struct LIST_HEADER *Entry
+)
+{
+	__List_Del(Entry->Prev, Entry->Next);
+	RTL_INIT_LIST_HEAD(Entry);
+
+}
+
+/**
+ * ListEmpty - tests whether a list is empty
+ * @head: the list to test.
+ */
+static __inline__ u32 
+ListEmpty(
+    IN  struct LIST_HEADER *Head
+)
+{
+	return Head->Next == Head;
+}
+
+/**
+ * ListSplice - join two lists
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static __inline__ VOID 
+ListSplice(
+    IN  struct LIST_HEADER *List,
+    IN  struct LIST_HEADER *Head
+)
+{
+	struct LIST_HEADER *First = List->Next;
+
+	if (First != List) {
+		struct LIST_HEADER *Last = List->Prev;
+		struct LIST_HEADER *At = Head->Next;
+
+		First->Prev = Head;
+		Head->Next = First;
+
+		Last->Next = At;
+		At->Prev = Last;
+	}
+}
+
+static __inline__ VOID 
+ListAdd(
+    IN  struct LIST_HEADER *New, 
+    IN  struct LIST_HEADER *head
+)
+{
+	__List_Add(New, head, head->Next);
+}
+
+
+static __inline__ VOID 
+ListAddTail(
+    IN  struct LIST_HEADER *New, 
+    IN  struct LIST_HEADER *head
+)
+{
+	__List_Add(New, head->Prev, head);
+}
+
+static __inline VOID 
+RtlInitListhead(
+    IN  _LIST *list
+)
+{
+    RTL_INIT_LIST_HEAD(list);
+}
+
+
+/*
+For the following list_xxx operations, 
+caller must guarantee the atomic context.
+Otherwise, there will be racing condition.
+*/
+static __inline u32	
+RtlIsListEmpty(
+    IN  _LIST *phead
+)
+{
+
+	if (ListEmpty(phead))
+		return _TRUE;
+	else
+		return _FALSE;
+	
+}
+
+static __inline VOID 
+RtlListInsertHead(
+    IN  _LIST *plist,
+    IN  _LIST *phead
+)
+{
+	ListAdd(plist, phead);
+}
+
+static __inline VOID 
+RtlListInsertTail(
+    IN  _LIST *plist,
+    IN  _LIST *phead
+)
+{
+	ListAddTail(plist, phead);	
+}
+
+
+static __inline _LIST
+*RtlListGetNext(
+    IN  _LIST *plist
+)
+{
+	return plist->Next;
+}
+
+static __inline VOID 
+RtlListDelete(
+    IN _LIST *plist
+)
+{
+	ListDelInit(plist);
+}
+
+#define RTL_LIST_CONTAINOR(ptr, type, member) \
+        ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
+        
+#ifndef CONTAINER_OF
+#define CONTAINER_OF(ptr, type, member) \
+        ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
+#endif
+
+#define list_entry(ptr, type, member) \
+ 		CONTAINER_OF(ptr, type, member)
+
+#define list_first_entry(ptr, type, member) \
+        list_entry((ptr)->Next, type, member) 		
+
+#define list_next_entry(pos, member, type) \
+        list_entry((pos)->member.Next, type, member)
+
+#define list_for_each_entry(pos, head, member, type) \
+        for (pos = list_first_entry(head, type, member); \
+             &pos->member != (head); \
+             pos = list_next_entry(pos, member, type))
+#define list_for_each(pos, head) \
+        for (pos = (head)->Next; pos != (head); pos = pos->Next)
+
+
+#ifndef BIT
+	#define BIT(x)	( 1 << (x))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_HAL_UTIL_H_

component/soc/realtek/8195a/fwlib/hal_vector_table.h

@@ -0,0 +1,53 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _HAL_VECTOR_TABLE_H_
+#define _HAL_VECTOR_TABLE_H_
+
+
+
+
+extern _LONG_CALL_ VOID
+VectorTableInitRtl8195A(
+    IN  u32 StackP
+);
+
+extern _LONG_CALL_ VOID
+VectorTableInitForOSRtl8195A(
+    IN  VOID *PortSVC,
+    IN  VOID *PortPendSVH,
+    IN  VOID *PortSysTick    
+);
+
+extern _LONG_CALL_ BOOL
+VectorIrqRegisterRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+);
+
+extern _LONG_CALL_ BOOL
+VectorIrqUnRegisterRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+);
+
+
+extern _LONG_CALL_ VOID
+VectorIrqEnRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+);
+
+extern _LONG_CALL_ VOID
+VectorIrqDisRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+);
+
+ 
+extern _LONG_CALL_ VOID
+HalPeripheralIntrHandle(VOID);
+#endif //_HAL_VECTOR_TABLE_H_

component/soc/realtek/8195a/fwlib/ram_lib/wlan/realtek/wlan_ram_map/rom/rom_wlan_ram_map.h

@@ -0,0 +1,9 @@
+#ifndef ROM_WLAN_RAM_MAP_H
+#define ROM_WLAN_RAM_MAP_H
+
+struct _rom_wlan_ram_map {
+	unsigned char * (*rtw_malloc)(unsigned int sz);
+	void (*rtw_mfree)(unsigned char *pbuf, unsigned int sz);
+};
+
+#endif	/* ROM_WLAN_RAM_MAP_H */

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h

@@ -0,0 +1,155 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+#ifndef _HAL_8195A_H_
+#define _HAL_8195A_H_
+
+#include "platform_autoconf.h"
+#include "basic_types.h"
+#include "section_config.h"
+#include "rtl8195a_sys_on.h"
+#include "rtl8195a_peri_on.h"
+#include "hal_platform.h"
+#include "hal_pinmux.h"
+#include "hal_api.h"
+#include "hal_peri_on.h"
+#include "hal_misc.h"
+#include "hal_irqn.h"
+#include "hal_vector_table.h"
+#include "hal_diag.h"
+#include "hal_spi_flash.h"
+#include "hal_timer.h"
+#include "hal_util.h"
+#include "hal_efuse.h"
+#include "hal_soc_ps_monitor.h"
+#include "diag.h"
+#include "hal_common.h"
+/* ----------------------------------------------------------------------------
+   -- Cortex M3 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM3_REV                      0x0200    /**< Core revision r0p0 */
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         1         /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm3.h"
+
+#ifdef CONFIG_TIMER_EN
+#include "hal_timer.h"
+#endif
+
+#ifdef CONFIG_GDMA_EN
+#include "hal_gdma.h"
+#include "rtl8195a_gdma.h"
+#endif
+
+#ifdef CONFIG_GPIO_EN
+#include "hal_gpio.h"
+#include "rtl8195a_gpio.h"
+#endif
+
+#ifdef CONFIG_SPI_COM_EN
+#include "hal_ssi.h"
+#include "rtl8195a_ssi.h"
+#endif
+
+#ifdef CONFIG_UART_EN
+#include "hal_uart.h"
+#include "rtl8195a_uart.h"
+#endif
+
+#ifdef CONFIG_I2C_EN
+#include "hal_i2c.h"
+#include "rtl8195a_i2c.h"
+#endif
+
+#ifdef CONFIG_PCM_EN
+#include "hal_pcm.h"
+#include "rtl8195a_pcm.h"
+#endif
+
+#ifdef CONFIG_PWM_EN
+#include "hal_pwm.h"
+#include "rtl8195a_pwm.h"
+#endif
+
+#ifdef CONFIG_I2S_EN
+#include "hal_i2s.h"
+#include "rtl8195a_i2s.h"
+#endif
+
+#ifdef CONFIG_DAC_EN
+#include "hal_dac.h"
+#include "rtl8195a_dac.h"
+#endif
+
+#ifdef CONFIG_ADC_EN
+#include "hal_adc.h"
+#include "rtl8195a_adc.h"
+#endif
+
+#ifdef CONFIG_SDR_EN
+#endif
+
+#ifdef CONFIG_SPIC_EN
+#endif
+
+#ifdef CONFIG_SDIO_DEVICE_EN
+#include "hal_sdio.h"
+#endif
+
+#ifdef CONFIG_NFC_EN
+#include "hal_nfc.h"
+#include "rtl8195a_nfc.h"
+#endif
+
+#if CONFIG_WDG
+#include "rtl8195a_wdt.h"
+#endif
+
+#ifdef CONFIG_USB_EN
+#include "hal_usb.h"
+#include "rtl8195a_usb.h"
+#endif
+
+
+// firmware information, located at the header of Image2
+#define FW_VERSION          (0x0100)
+#define FW_SUBVERSION       (0x0001)
+#define FW_CHIP_ID          (0x8195)
+#define FW_CHIP_VER         (0x01)
+#define FW_BUS_TYPE         (0x01)          // the iNIC firmware type: USB/SDIO
+#define FW_INFO_RSV1        (0x00)          // the firmware information reserved
+#define FW_INFO_RSV2        (0x00)          // the firmware information reserved
+#define FW_INFO_RSV3        (0x00)          // the firmware information reserved
+#define FW_INFO_RSV4        (0x00)          // the firmware information reserved
+
+#define FLASH_RESERVED_DATA_BASE		0x8000  // reserve 32K for Image1
+#define FLASH_SYSTEM_DATA_ADDR			0x9000  // reserve 32K+4K for Image1 + Reserved data
+// Flash Map for Calibration data
+#define FLASH_CAL_DATA_BASE				0xA000
+#define FLASH_CAL_DATA_ADDR(_offset)	(FLASH_CAL_DATA_BASE + _offset)
+#define FLASH_CAL_DATA_SIZE				0x1000
+#define FLASH_SECTOR_SIZE				0x1000
+// SPIC Calibration Data
+#define FLASH_SPIC_PARA_OFFSET          0x80
+#define FLASH_SPIC_PARA_BASE            (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET)
+// SDRC Calibration Data
+#define FLASH_SDRC_PARA_OFFSET          0x180
+#define FLASH_SDRC_PARA_BASE            (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET)
+// ADC Calibration Data
+#define FLASH_ADC_PARA_OFFSET           0x200
+#define FLASH_ADC_PARA_BASE             (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET)
+
+#endif //_HAL_8195A_H_

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_adc.h

@@ -0,0 +1,350 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL8195A_ADC_H_
+#define _RTL8195A_ADC_H_
+
+
+//================ Register Bit Field ==========================
+//2 REG_ADC_FIFO_READ
+
+#define BIT_SHIFT_ADC_FIFO_RO 0
+#define BIT_MASK_ADC_FIFO_RO 0xffffffffL
+#define BIT_ADC_FIFO_RO(x)                    	(((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
+#define BIT_CTRL_ADC_FIFO_RO(x)               	(((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
+#define BIT_GET_ADC_FIFO_RO(x)                	(((x) >> BIT_SHIFT_ADC_FIFO_RO) & BIT_MASK_ADC_FIFO_RO)
+
+
+//2 REG_ADC_CONTROL
+
+#define BIT_SHIFT_ADC_DBG_SEL 24
+#define BIT_MASK_ADC_DBG_SEL 0x7
+#define BIT_ADC_DBG_SEL(x)                    	(((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
+#define BIT_CTRL_ADC_DBG_SEL(x)               	(((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
+#define BIT_GET_ADC_DBG_SEL(x)                	(((x) >> BIT_SHIFT_ADC_DBG_SEL) & BIT_MASK_ADC_DBG_SEL)
+
+
+#define BIT_SHIFT_ADC_THRESHOLD 16
+#define BIT_MASK_ADC_THRESHOLD 0x3f
+#define BIT_ADC_THRESHOLD(x)                  	(((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
+#define BIT_CTRL_ADC_THRESHOLD(x)             	(((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
+#define BIT_GET_ADC_THRESHOLD(x)              	(((x) >> BIT_SHIFT_ADC_THRESHOLD) & BIT_MASK_ADC_THRESHOLD)
+
+
+#define BIT_SHIFT_ADC_BURST_SIZE 8
+#define BIT_MASK_ADC_BURST_SIZE 0x1f
+#define BIT_ADC_BURST_SIZE(x)                 	(((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
+#define BIT_CTRL_ADC_BURST_SIZE(x)            	(((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
+#define BIT_GET_ADC_BURST_SIZE(x)             	(((x) >> BIT_SHIFT_ADC_BURST_SIZE) & BIT_MASK_ADC_BURST_SIZE)
+
+#define BIT_ADC_ENDIAN                        	BIT(3)
+#define BIT_SHIFT_ADC_ENDIAN                  	3
+#define BIT_MASK_ADC_ENDIAN                   	0x1
+#define BIT_CTRL_ADC_ENDIAN(x)                	(((x) & BIT_MASK_ADC_ENDIAN) << BIT_SHIFT_ADC_ENDIAN)
+
+#define BIT_ADC_OVERWRITE                     	BIT(2)
+#define BIT_SHIFT_ADC_OVERWRITE               	2
+#define BIT_MASK_ADC_OVERWRITE                	0x1
+#define BIT_CTRL_ADC_OVERWRITE(x)             	(((x) & BIT_MASK_ADC_OVERWRITE) << BIT_SHIFT_ADC_OVERWRITE)
+
+#define BIT_ADC_ONESHOT                       	BIT(1)
+#define BIT_SHIFT_ADC_ONESHOT                 	1
+#define BIT_MASK_ADC_ONESHOT                  	0x1
+#define BIT_CTRL_ADC_ONESHOT(x)               	(((x) & BIT_MASK_ADC_ONESHOT) << BIT_SHIFT_ADC_ONESHOT)
+
+#define BIT_ADC_COMP_ONLY                     	BIT(0)
+#define BIT_SHIFT_ADC_COMP_ONLY               	0
+#define BIT_MASK_ADC_COMP_ONLY                	0x1
+#define BIT_CTRL_ADC_COMP_ONLY(x)             	(((x) & BIT_MASK_ADC_COMP_ONLY) << BIT_SHIFT_ADC_COMP_ONLY)
+
+
+//2 REG_ADC_INTR_EN
+#define BIT_ADC_AWAKE_CPU_EN                  	BIT(7)
+#define BIT_SHIFT_ADC_AWAKE_CPU_EN            	7
+#define BIT_MASK_ADC_AWAKE_CPU_EN             	0x1
+#define BIT_CTRL_ADC_AWAKE_CPU_EN(x)          	(((x) & BIT_MASK_ADC_AWAKE_CPU_EN) << BIT_SHIFT_ADC_AWAKE_CPU_EN)
+
+#define BIT_ADC_FIFO_RD_ERROR_EN              	BIT(6)
+#define BIT_SHIFT_ADC_FIFO_RD_ERROR_EN        	6
+#define BIT_MASK_ADC_FIFO_RD_ERROR_EN         	0x1
+#define BIT_CTRL_ADC_FIFO_RD_ERROR_EN(x)      	(((x) & BIT_MASK_ADC_FIFO_RD_ERROR_EN) << BIT_SHIFT_ADC_FIFO_RD_ERROR_EN)
+
+#define BIT_ADC_FIFO_RD_REQ_EN                	BIT(5)
+#define BIT_SHIFT_ADC_FIFO_RD_REQ_EN          	5
+#define BIT_MASK_ADC_FIFO_RD_REQ_EN           	0x1
+#define BIT_CTRL_ADC_FIFO_RD_REQ_EN(x)        	(((x) & BIT_MASK_ADC_FIFO_RD_REQ_EN) << BIT_SHIFT_ADC_FIFO_RD_REQ_EN)
+
+#define BIT_ADC_FIFO_FULL_EN                  	BIT(4)
+#define BIT_SHIFT_ADC_FIFO_FULL_EN            	4
+#define BIT_MASK_ADC_FIFO_FULL_EN             	0x1
+#define BIT_CTRL_ADC_FIFO_FULL_EN(x)          	(((x) & BIT_MASK_ADC_FIFO_FULL_EN) << BIT_SHIFT_ADC_FIFO_FULL_EN)
+
+#define BIT_ADC_COMP_3_EN                     	BIT(3)
+#define BIT_SHIFT_ADC_COMP_3_EN               	3
+#define BIT_MASK_ADC_COMP_3_EN                	0x1
+#define BIT_CTRL_ADC_COMP_3_EN(x)             	(((x) & BIT_MASK_ADC_COMP_3_EN) << BIT_SHIFT_ADC_COMP_3_EN)
+
+#define BIT_ADC_COMP_2_EN                     	BIT(2)
+#define BIT_SHIFT_ADC_COMP_2_EN               	2
+#define BIT_MASK_ADC_COMP_2_EN                	0x1
+#define BIT_CTRL_ADC_COMP_2_EN(x)             	(((x) & BIT_MASK_ADC_COMP_2_EN) << BIT_SHIFT_ADC_COMP_2_EN)
+
+#define BIT_ADC_COMP_1_EN                     	BIT(1)
+#define BIT_SHIFT_ADC_COMP_1_EN               	1
+#define BIT_MASK_ADC_COMP_1_EN                	0x1
+#define BIT_CTRL_ADC_COMP_1_EN(x)             	(((x) & BIT_MASK_ADC_COMP_1_EN) << BIT_SHIFT_ADC_COMP_1_EN)
+
+#define BIT_ADC_COMP_0_EN                     	BIT(0)
+#define BIT_SHIFT_ADC_COMP_0_EN               	0
+#define BIT_MASK_ADC_COMP_0_EN                	0x1
+#define BIT_CTRL_ADC_COMP_0_EN(x)             	(((x) & BIT_MASK_ADC_COMP_0_EN) << BIT_SHIFT_ADC_COMP_0_EN)
+
+
+//2 REG_ADC_INTR_STS
+#define BIT_ADC_FIFO_THRESHOLD                	BIT(7)
+#define BIT_SHIFT_ADC_FIFO_THRESHOLD          	7
+#define BIT_MASK_ADC_FIFO_THRESHOLD           	0x1
+#define BIT_CTRL_ADC_FIFO_THRESHOLD(x)        	(((x) & BIT_MASK_ADC_FIFO_THRESHOLD) << BIT_SHIFT_ADC_FIFO_THRESHOLD)
+
+#define BIT_ADC_FIFO_RD_ERROR_ST              	BIT(6)
+#define BIT_SHIFT_ADC_FIFO_RD_ERROR_ST        	6
+#define BIT_MASK_ADC_FIFO_RD_ERROR_ST         	0x1
+#define BIT_CTRL_ADC_FIFO_RD_ERROR_ST(x)      	(((x) & BIT_MASK_ADC_FIFO_RD_ERROR_ST) << BIT_SHIFT_ADC_FIFO_RD_ERROR_ST)
+
+#define BIT_ADC_FIFO_RD_REQ_ST                	BIT(5)
+#define BIT_SHIFT_ADC_FIFO_RD_REQ_ST          	5
+#define BIT_MASK_ADC_FIFO_RD_REQ_ST           	0x1
+#define BIT_CTRL_ADC_FIFO_RD_REQ_ST(x)        	(((x) & BIT_MASK_ADC_FIFO_RD_REQ_ST) << BIT_SHIFT_ADC_FIFO_RD_REQ_ST)
+
+#define BIT_ADC_FIFO_FULL_ST                  	BIT(4)
+#define BIT_SHIFT_ADC_FIFO_FULL_ST            	4
+#define BIT_MASK_ADC_FIFO_FULL_ST             	0x1
+#define BIT_CTRL_ADC_FIFO_FULL_ST(x)          	(((x) & BIT_MASK_ADC_FIFO_FULL_ST) << BIT_SHIFT_ADC_FIFO_FULL_ST)
+
+#define BIT_ADC_COMP_3_ST                     	BIT(3)
+#define BIT_SHIFT_ADC_COMP_3_ST               	3
+#define BIT_MASK_ADC_COMP_3_ST                	0x1
+#define BIT_CTRL_ADC_COMP_3_ST(x)             	(((x) & BIT_MASK_ADC_COMP_3_ST) << BIT_SHIFT_ADC_COMP_3_ST)
+
+#define BIT_ADC_COMP_2_ST                     	BIT(2)
+#define BIT_SHIFT_ADC_COMP_2_ST               	2
+#define BIT_MASK_ADC_COMP_2_ST                	0x1
+#define BIT_CTRL_ADC_COMP_2_ST(x)             	(((x) & BIT_MASK_ADC_COMP_2_ST) << BIT_SHIFT_ADC_COMP_2_ST)
+
+#define BIT_ADC_COMP_1_ST                     	BIT(1)
+#define BIT_SHIFT_ADC_COMP_1_ST               	1
+#define BIT_MASK_ADC_COMP_1_ST                	0x1
+#define BIT_CTRL_ADC_COMP_1_ST(x)             	(((x) & BIT_MASK_ADC_COMP_1_ST) << BIT_SHIFT_ADC_COMP_1_ST)
+
+#define BIT_ADC_COMP_0_ST                     	BIT(0)
+#define BIT_SHIFT_ADC_COMP_0_ST               	0
+#define BIT_MASK_ADC_COMP_0_ST                	0x1
+#define BIT_CTRL_ADC_COMP_0_ST(x)             	(((x) & BIT_MASK_ADC_COMP_0_ST) << BIT_SHIFT_ADC_COMP_0_ST)
+
+
+//2 REG_ADC_COMP_VALUE_L
+
+#define BIT_SHIFT_ADC_COMP_TH_1 16
+#define BIT_MASK_ADC_COMP_TH_1 0xffff
+#define BIT_ADC_COMP_TH_1(x)                  	(((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
+#define BIT_CTRL_ADC_COMP_TH_1(x)             	(((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
+#define BIT_GET_ADC_COMP_TH_1(x)              	(((x) >> BIT_SHIFT_ADC_COMP_TH_1) & BIT_MASK_ADC_COMP_TH_1)
+
+
+#define BIT_SHIFT_ADC_COMP_TH_0 0
+#define BIT_MASK_ADC_COMP_TH_0 0xffff
+#define BIT_ADC_COMP_TH_0(x)                  	(((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
+#define BIT_CTRL_ADC_COMP_TH_0(x)             	(((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
+#define BIT_GET_ADC_COMP_TH_0(x)              	(((x) >> BIT_SHIFT_ADC_COMP_TH_0) & BIT_MASK_ADC_COMP_TH_0)
+
+
+//2 REG_ADC_COMP_VALUE_H
+
+#define BIT_SHIFT_ADC_COMP_TH_3 16
+#define BIT_MASK_ADC_COMP_TH_3 0xffff
+#define BIT_ADC_COMP_TH_3(x)                  	(((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
+#define BIT_CTRL_ADC_COMP_TH_3(x)             	(((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
+#define BIT_GET_ADC_COMP_TH_3(x)              	(((x) >> BIT_SHIFT_ADC_COMP_TH_3) & BIT_MASK_ADC_COMP_TH_3)
+
+
+#define BIT_SHIFT_ADC_COMP_TH_2 0
+#define BIT_MASK_ADC_COMP_TH_2 0xffff
+#define BIT_ADC_COMP_TH_2(x)                  	(((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
+#define BIT_CTRL_ADC_COMP_TH_2(x)             	(((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
+#define BIT_GET_ADC_COMP_TH_2(x)              	(((x) >> BIT_SHIFT_ADC_COMP_TH_2) & BIT_MASK_ADC_COMP_TH_2)
+
+
+//2 REG_ADC_COMP_SET
+
+#define BIT_SHIFT_ADC_GREATER_THAN 0
+#define BIT_MASK_ADC_GREATER_THAN 0xf
+#define BIT_ADC_GREATER_THAN(x)               	(((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
+#define BIT_CTRL_ADC_GREATER_THAN(x)          	(((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
+#define BIT_GET_ADC_GREATER_THAN(x)           	(((x) >> BIT_SHIFT_ADC_GREATER_THAN) & BIT_MASK_ADC_GREATER_THAN)
+
+
+//2 REG_ADC_POWER
+
+#define BIT_SHIFT_ADC_PWR_CUT_CNTR 16
+#define BIT_MASK_ADC_PWR_CUT_CNTR 0xff
+#define BIT_ADC_PWR_CUT_CNTR(x)               	(((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
+#define BIT_CTRL_ADC_PWR_CUT_CNTR(x)          	(((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
+#define BIT_GET_ADC_PWR_CUT_CNTR(x)           	(((x) >> BIT_SHIFT_ADC_PWR_CUT_CNTR) & BIT_MASK_ADC_PWR_CUT_CNTR)
+
+#define BIT_ADC_FIFO_ON_ST                    	BIT(11)
+#define BIT_SHIFT_ADC_FIFO_ON_ST              	11
+#define BIT_MASK_ADC_FIFO_ON_ST               	0x1
+#define BIT_CTRL_ADC_FIFO_ON_ST(x)            	(((x) & BIT_MASK_ADC_FIFO_ON_ST) << BIT_SHIFT_ADC_FIFO_ON_ST)
+
+#define BIT_ADC_ISO_ON_ST                     	BIT(10)
+#define BIT_SHIFT_ADC_ISO_ON_ST               	10
+#define BIT_MASK_ADC_ISO_ON_ST                	0x1
+#define BIT_CTRL_ADC_ISO_ON_ST(x)             	(((x) & BIT_MASK_ADC_ISO_ON_ST) << BIT_SHIFT_ADC_ISO_ON_ST)
+
+#define BIT_ADC_PWR33_ON_ST                   	BIT(9)
+#define BIT_SHIFT_ADC_PWR33_ON_ST             	9
+#define BIT_MASK_ADC_PWR33_ON_ST              	0x1
+#define BIT_CTRL_ADC_PWR33_ON_ST(x)           	(((x) & BIT_MASK_ADC_PWR33_ON_ST) << BIT_SHIFT_ADC_PWR33_ON_ST)
+
+#define BIT_ADC_PWR12_ON_ST                   	BIT(8)
+#define BIT_SHIFT_ADC_PWR12_ON_ST             	8
+#define BIT_MASK_ADC_PWR12_ON_ST              	0x1
+#define BIT_CTRL_ADC_PWR12_ON_ST(x)           	(((x) & BIT_MASK_ADC_PWR12_ON_ST) << BIT_SHIFT_ADC_PWR12_ON_ST)
+
+#define BIT_ADC_ISO_MANUAL                    	BIT(3)
+#define BIT_SHIFT_ADC_ISO_MANUAL              	3
+#define BIT_MASK_ADC_ISO_MANUAL               	0x1
+#define BIT_CTRL_ADC_ISO_MANUAL(x)            	(((x) & BIT_MASK_ADC_ISO_MANUAL) << BIT_SHIFT_ADC_ISO_MANUAL)
+
+#define BIT_ADC_PWR33_MANUAL                  	BIT(2)
+#define BIT_SHIFT_ADC_PWR33_MANUAL            	2
+#define BIT_MASK_ADC_PWR33_MANUAL             	0x1
+#define BIT_CTRL_ADC_PWR33_MANUAL(x)          	(((x) & BIT_MASK_ADC_PWR33_MANUAL) << BIT_SHIFT_ADC_PWR33_MANUAL)
+
+#define BIT_ADC_PWR12_MANUAL                  	BIT(1)
+#define BIT_SHIFT_ADC_PWR12_MANUAL            	1
+#define BIT_MASK_ADC_PWR12_MANUAL             	0x1
+#define BIT_CTRL_ADC_PWR12_MANUAL(x)          	(((x) & BIT_MASK_ADC_PWR12_MANUAL) << BIT_SHIFT_ADC_PWR12_MANUAL)
+
+#define BIT_ADC_PWR_AUTO                      	BIT(0)
+#define BIT_SHIFT_ADC_PWR_AUTO                	0
+#define BIT_MASK_ADC_PWR_AUTO                 	0x1
+#define BIT_CTRL_ADC_PWR_AUTO(x)              	(((x) & BIT_MASK_ADC_PWR_AUTO) << BIT_SHIFT_ADC_PWR_AUTO)
+
+
+//2 REG_ADC_ANAPAR_AD0
+
+#define BIT_SHIFT_ADC_ANAPAR_AD0 2
+#define BIT_MASK_ADC_ANAPAR_AD0 0x3fffffff
+#define BIT_ADC_ANAPAR_AD0(x)                 	(((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
+#define BIT_CTRL_ADC_ANAPAR_AD0(x)            	(((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
+#define BIT_GET_ADC_ANAPAR_AD0(x)             	(((x) >> BIT_SHIFT_ADC_ANAPAR_AD0) & BIT_MASK_ADC_ANAPAR_AD0)
+
+#define BIT_ADC_AUDIO_EN                      	BIT(1)
+#define BIT_SHIFT_ADC_AUDIO_EN                	1
+#define BIT_MASK_ADC_AUDIO_EN                 	0x1
+#define BIT_CTRL_ADC_AUDIO_EN(x)              	(((x) & BIT_MASK_ADC_AUDIO_EN) << BIT_SHIFT_ADC_AUDIO_EN)
+
+#define BIT_ADC_EN_MANUAL                     	BIT(0)
+#define BIT_SHIFT_ADC_EN_MANUAL               	0
+#define BIT_MASK_ADC_EN_MANUAL                	0x1
+#define BIT_CTRL_ADC_EN_MANUAL(x)             	(((x) & BIT_MASK_ADC_EN_MANUAL) << BIT_SHIFT_ADC_EN_MANUAL)
+
+
+//2 REG_ADC_ANAPAR_AD1
+
+#define BIT_SHIFT_ADC_ANAPAR_AD1 0
+#define BIT_MASK_ADC_ANAPAR_AD1 0xffffffffL
+#define BIT_ADC_ANAPAR_AD1(x)                 	(((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
+#define BIT_CTRL_ADC_ANAPAR_AD1(x)            	(((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
+#define BIT_GET_ADC_ANAPAR_AD1(x)             	(((x) >> BIT_SHIFT_ADC_ANAPAR_AD1) & BIT_MASK_ADC_ANAPAR_AD1)
+
+
+//2 REG_ADC_ANAPAR_AD2
+
+#define BIT_SHIFT_ADC_ANAPAR_AD2 0
+#define BIT_MASK_ADC_ANAPAR_AD2 0xffffffffL
+#define BIT_ADC_ANAPAR_AD2(x)                 	(((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
+#define BIT_CTRL_ADC_ANAPAR_AD2(x)            	(((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
+#define BIT_GET_ADC_ANAPAR_AD2(x)             	(((x) >> BIT_SHIFT_ADC_ANAPAR_AD2) & BIT_MASK_ADC_ANAPAR_AD2)
+
+
+//2 REG_ADC_ANAPAR_AD3
+
+#define BIT_SHIFT_ADC_ANAPAR_AD3 0
+#define BIT_MASK_ADC_ANAPAR_AD3 0xffffffffL
+#define BIT_ADC_ANAPAR_AD3(x)                 	(((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
+#define BIT_CTRL_ADC_ANAPAR_AD3(x)            	(((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
+#define BIT_GET_ADC_ANAPAR_AD3(x)             	(((x) >> BIT_SHIFT_ADC_ANAPAR_AD3) & BIT_MASK_ADC_ANAPAR_AD3)
+
+
+//2 REG_ADC_ANAPAR_AD4
+
+#define BIT_SHIFT_ADC_ANAPAR_AD4 0
+#define BIT_MASK_ADC_ANAPAR_AD4 0xffffffffL
+#define BIT_ADC_ANAPAR_AD4(x)                 	(((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
+#define BIT_CTRL_ADC_ANAPAR_AD4(x)            	(((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
+#define BIT_GET_ADC_ANAPAR_AD4(x)             	(((x) >> BIT_SHIFT_ADC_ANAPAR_AD4) & BIT_MASK_ADC_ANAPAR_AD4)
+
+
+//2 REG_ADC_ANAPAR_AD5
+
+#define BIT_SHIFT_ADC_ANAPAR_AD5 0
+#define BIT_MASK_ADC_ANAPAR_AD5 0xffffffffL
+#define BIT_ADC_ANAPAR_AD5(x)                 	(((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
+#define BIT_CTRL_ADC_ANAPAR_AD5(x)            	(((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
+#define BIT_GET_ADC_ANAPAR_AD5(x)             	(((x) >> BIT_SHIFT_ADC_ANAPAR_AD5) & BIT_MASK_ADC_ANAPAR_AD5)
+
+
+//2 REG_ADC_CALI_DATA
+
+#define BIT_SHIFT_ADC_CALI_DATA_6 16
+#define BIT_MASK_ADC_CALI_DATA_6 0xffff
+#define BIT_ADC_CALI_DATA_6(x)                	(((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
+#define BIT_CTRL_ADC_CALI_DATA_6(x)           	(((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
+#define BIT_GET_ADC_CALI_DATA_6(x)            	(((x) >> BIT_SHIFT_ADC_CALI_DATA_6) & BIT_MASK_ADC_CALI_DATA_6)
+
+
+#define BIT_SHIFT_ADC_CALI_DATA_0 0
+#define BIT_MASK_ADC_CALI_DATA_0 0xffff
+#define BIT_ADC_CALI_DATA_0(x)                	(((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
+#define BIT_CTRL_ADC_CALI_DATA_0(x)           	(((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
+#define BIT_GET_ADC_CALI_DATA_0(x)            	(((x) >> BIT_SHIFT_ADC_CALI_DATA_0) & BIT_MASK_ADC_CALI_DATA_0)
+
+//================ Register Reg Field  =========================
+#define REG_ADC_FIFO_READ 0x0000
+#define REG_ADC_CONTROL 0x0004
+#define REG_ADC_INTR_EN 0x0008
+#define REG_ADC_INTR_STS 0x000C
+#define REG_ADC_COMP_VALUE_L 0x0010
+#define REG_ADC_COMP_VALUE_H 0x0014
+#define REG_ADC_COMP_SET 0x0018
+#define REG_ADC_POWER 0x001C
+#define REG_ADC_ANAPAR_AD0 0x0020
+#define REG_ADC_ANAPAR_AD1 0x0024
+#define REG_ADC_ANAPAR_AD2 0x0028
+#define REG_ADC_ANAPAR_AD3 0x002C
+#define REG_ADC_ANAPAR_AD4 0x0030
+#define REG_ADC_ANAPAR_AD5 0x0034
+#define REG_ADC_CALI_DATA 0x0038
+
+//================ ADC HAL related enumeration ==================
+
+//================ ADC Function Prototypes  =====================
+#define HAL_ADC_WRITE32(addr, value)    HAL_WRITE32(ADC_REG_BASE,addr,value)
+#define HAL_ADC_READ32(addr)            HAL_READ32(ADC_REG_BASE,addr)
+
+RTK_STATUS HalADCInit8195a(IN VOID *Data);
+RTK_STATUS HalADCDeInit8195a(IN VOID *Data);
+RTK_STATUS HalADCEnableRtl8195a(IN VOID *Data);
+RTK_STATUS HalADCIntrCtrl8195a(IN VOID *Data);
+u32 HalADCReceiveRtl8195a(IN VOID *Data);
+u32 HalADCReadRegRtl8195a(IN VOID *Data,IN  u8 I2CReg);
+
+#endif

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_dac.h

@@ -0,0 +1,294 @@
+#ifndef _RTL8195A_DAC_H_
+#define _RTL8195A_DAC_H_
+
+//================ Register Bit Field ==========================
+//2 REG_DAC0_FIFO_WR
+
+#define BIT_SHIFT_DAC0_FIFO_WO 0
+#define BIT_MASK_DAC0_FIFO_WO 0xffffffffL
+#define BIT_DAC0_FIFO_WO(x)                   	(((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
+#define BIT_CTRL_DAC0_FIFO_WO(x)              	(((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
+#define BIT_GET_DAC0_FIFO_WO(x)               	(((x) >> BIT_SHIFT_DAC0_FIFO_WO) & BIT_MASK_DAC0_FIFO_WO)
+
+
+//2 REG_DAC_CTRL
+
+#define BIT_SHIFT_DAC_DELTA_SIGMA 25
+#define BIT_MASK_DAC_DELTA_SIGMA 0x7
+#define BIT_DAC_DELTA_SIGMA(x)                	(((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
+#define BIT_CTRL_DAC_DELTA_SIGMA(x)           	(((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
+#define BIT_GET_DAC_DELTA_SIGMA(x)            	(((x) >> BIT_SHIFT_DAC_DELTA_SIGMA) & BIT_MASK_DAC_DELTA_SIGMA)
+
+#define BIT_DAC_BYPASS_DSC                    	BIT(24)
+#define BIT_SHIFT_DAC_BYPASS_DSC              	24
+#define BIT_MASK_DAC_BYPASS_DSC               	0x1
+#define BIT_CTRL_DAC_BYPASS_DSC(x)            	(((x) & BIT_MASK_DAC_BYPASS_DSC) << BIT_SHIFT_DAC_BYPASS_DSC)
+
+
+#define BIT_SHIFT_DAC_DSC_DBG_SEL 19
+#define BIT_MASK_DAC_DSC_DBG_SEL 0x3
+#define BIT_DAC_DSC_DBG_SEL(x)                	(((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
+#define BIT_CTRL_DAC_DSC_DBG_SEL(x)           	(((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
+#define BIT_GET_DAC_DSC_DBG_SEL(x)            	(((x) >> BIT_SHIFT_DAC_DSC_DBG_SEL) & BIT_MASK_DAC_DSC_DBG_SEL)
+
+
+#define BIT_SHIFT_DAC_DBG_SEL 16
+#define BIT_MASK_DAC_DBG_SEL 0x7
+#define BIT_DAC_DBG_SEL(x)                    	(((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
+#define BIT_CTRL_DAC_DBG_SEL(x)               	(((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
+#define BIT_GET_DAC_DBG_SEL(x)                	(((x) >> BIT_SHIFT_DAC_DBG_SEL) & BIT_MASK_DAC_DBG_SEL)
+
+
+#define BIT_SHIFT_DAC_BURST_SIZE 8
+#define BIT_MASK_DAC_BURST_SIZE 0xf
+#define BIT_DAC_BURST_SIZE(x)                 	(((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
+#define BIT_CTRL_DAC_BURST_SIZE(x)            	(((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
+#define BIT_GET_DAC_BURST_SIZE(x)             	(((x) >> BIT_SHIFT_DAC_BURST_SIZE) & BIT_MASK_DAC_BURST_SIZE)
+
+#define BIT_DAC_FILTER_SETTLE                 	BIT(4)
+#define BIT_SHIFT_DAC_FILTER_SETTLE           	4
+#define BIT_MASK_DAC_FILTER_SETTLE            	0x1
+#define BIT_CTRL_DAC_FILTER_SETTLE(x)         	(((x) & BIT_MASK_DAC_FILTER_SETTLE) << BIT_SHIFT_DAC_FILTER_SETTLE)
+
+#define BIT_DAC_OV_OPTION                     	BIT(3)
+#define BIT_SHIFT_DAC_OV_OPTION               	3
+#define BIT_MASK_DAC_OV_OPTION                	0x1
+#define BIT_CTRL_DAC_OV_OPTION(x)             	(((x) & BIT_MASK_DAC_OV_OPTION) << BIT_SHIFT_DAC_OV_OPTION)
+
+#define BIT_DAC_ENDIAN                        	BIT(2)
+#define BIT_SHIFT_DAC_ENDIAN                  	2
+#define BIT_MASK_DAC_ENDIAN                   	0x1
+#define BIT_CTRL_DAC_ENDIAN(x)                	(((x) & BIT_MASK_DAC_ENDIAN) << BIT_SHIFT_DAC_ENDIAN)
+
+#define BIT_DAC_SPEED                         	BIT(1)
+#define BIT_SHIFT_DAC_SPEED                   	1
+#define BIT_MASK_DAC_SPEED                    	0x1
+#define BIT_CTRL_DAC_SPEED(x)                 	(((x) & BIT_MASK_DAC_SPEED) << BIT_SHIFT_DAC_SPEED)
+
+#define BIT_DAC_FIFO_EN                       	BIT(0)
+#define BIT_SHIFT_DAC_FIFO_EN                 	0
+#define BIT_MASK_DAC_FIFO_EN                  	0x1
+#define BIT_CTRL_DAC_FIFO_EN(x)               	(((x) & BIT_MASK_DAC_FIFO_EN) << BIT_SHIFT_DAC_FIFO_EN)
+
+
+//2 REG_DAC_INTR_CTRL
+#define BIT_DAC_DSC_OVERFLOW1_EN              	BIT(6)
+#define BIT_SHIFT_DAC_DSC_OVERFLOW1_EN        	6
+#define BIT_MASK_DAC_DSC_OVERFLOW1_EN         	0x1
+#define BIT_CTRL_DAC_DSC_OVERFLOW1_EN(x)      	(((x) & BIT_MASK_DAC_DSC_OVERFLOW1_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW1_EN)
+
+#define BIT_DAC_DSC_OVERFLOW0_EN              	BIT(5)
+#define BIT_SHIFT_DAC_DSC_OVERFLOW0_EN        	5
+#define BIT_MASK_DAC_DSC_OVERFLOW0_EN         	0x1
+#define BIT_CTRL_DAC_DSC_OVERFLOW0_EN(x)      	(((x) & BIT_MASK_DAC_DSC_OVERFLOW0_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW0_EN)
+
+#define BIT_DAC__WRITE_ERROR_EN               	BIT(4)
+#define BIT_SHIFT_DAC__WRITE_ERROR_EN         	4
+#define BIT_MASK_DAC__WRITE_ERROR_EN          	0x1
+#define BIT_CTRL_DAC__WRITE_ERROR_EN(x)       	(((x) & BIT_MASK_DAC__WRITE_ERROR_EN) << BIT_SHIFT_DAC__WRITE_ERROR_EN)
+
+#define BIT_DAC_FIFO_STOP_EN                  	BIT(3)
+#define BIT_SHIFT_DAC_FIFO_STOP_EN            	3
+#define BIT_MASK_DAC_FIFO_STOP_EN             	0x1
+#define BIT_CTRL_DAC_FIFO_STOP_EN(x)          	(((x) & BIT_MASK_DAC_FIFO_STOP_EN) << BIT_SHIFT_DAC_FIFO_STOP_EN)
+
+#define BIT_DAC_FIFO_OVERFLOW_EN              	BIT(2)
+#define BIT_SHIFT_DAC_FIFO_OVERFLOW_EN        	2
+#define BIT_MASK_DAC_FIFO_OVERFLOW_EN         	0x1
+#define BIT_CTRL_DAC_FIFO_OVERFLOW_EN(x)      	(((x) & BIT_MASK_DAC_FIFO_OVERFLOW_EN) << BIT_SHIFT_DAC_FIFO_OVERFLOW_EN)
+
+#define BIT_DAC_FIFO_WR_REQ_EN                	BIT(1)
+#define BIT_SHIFT_DAC_FIFO_WR_REQ_EN          	1
+#define BIT_MASK_DAC_FIFO_WR_REQ_EN           	0x1
+#define BIT_CTRL_DAC_FIFO_WR_REQ_EN(x)        	(((x) & BIT_MASK_DAC_FIFO_WR_REQ_EN) << BIT_SHIFT_DAC_FIFO_WR_REQ_EN)
+
+#define BIT_DAC_FIFO_FULL_EN                  	BIT(0)
+#define BIT_SHIFT_DAC_FIFO_FULL_EN            	0
+#define BIT_MASK_DAC_FIFO_FULL_EN             	0x1
+#define BIT_CTRL_DAC_FIFO_FULL_EN(x)          	(((x) & BIT_MASK_DAC_FIFO_FULL_EN) << BIT_SHIFT_DAC_FIFO_FULL_EN)
+
+
+//2 REG_DAC_INTR_STS
+#define BIT_DAC_DSC_OVERFLOW1_ST              	BIT(6)
+#define BIT_SHIFT_DAC_DSC_OVERFLOW1_ST        	6
+#define BIT_MASK_DAC_DSC_OVERFLOW1_ST         	0x1
+#define BIT_CTRL_DAC_DSC_OVERFLOW1_ST(x)      	(((x) & BIT_MASK_DAC_DSC_OVERFLOW1_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW1_ST)
+
+#define BIT_DAC_DSC_OVERFLOW0_ST              	BIT(5)
+#define BIT_SHIFT_DAC_DSC_OVERFLOW0_ST        	5
+#define BIT_MASK_DAC_DSC_OVERFLOW0_ST         	0x1
+#define BIT_CTRL_DAC_DSC_OVERFLOW0_ST(x)      	(((x) & BIT_MASK_DAC_DSC_OVERFLOW0_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW0_ST)
+
+#define BIT_DAC__WRITE_ERROR_ST               	BIT(4)
+#define BIT_SHIFT_DAC__WRITE_ERROR_ST         	4
+#define BIT_MASK_DAC__WRITE_ERROR_ST          	0x1
+#define BIT_CTRL_DAC__WRITE_ERROR_ST(x)       	(((x) & BIT_MASK_DAC__WRITE_ERROR_ST) << BIT_SHIFT_DAC__WRITE_ERROR_ST)
+
+#define BIT_DAC_FIFO_STOP_ST                  	BIT(3)
+#define BIT_SHIFT_DAC_FIFO_STOP_ST            	3
+#define BIT_MASK_DAC_FIFO_STOP_ST             	0x1
+#define BIT_CTRL_DAC_FIFO_STOP_ST(x)          	(((x) & BIT_MASK_DAC_FIFO_STOP_ST) << BIT_SHIFT_DAC_FIFO_STOP_ST)
+
+#define BIT_DAC_FIFO_OVERFLOW_ST              	BIT(2)
+#define BIT_SHIFT_DAC_FIFO_OVERFLOW_ST        	2
+#define BIT_MASK_DAC_FIFO_OVERFLOW_ST         	0x1
+#define BIT_CTRL_DAC_FIFO_OVERFLOW_ST(x)      	(((x) & BIT_MASK_DAC_FIFO_OVERFLOW_ST) << BIT_SHIFT_DAC_FIFO_OVERFLOW_ST)
+
+#define BIT_DAC_FIFO_WR_REQ_ST                	BIT(1)
+#define BIT_SHIFT_DAC_FIFO_WR_REQ_ST          	1
+#define BIT_MASK_DAC_FIFO_WR_REQ_ST           	0x1
+#define BIT_CTRL_DAC_FIFO_WR_REQ_ST(x)        	(((x) & BIT_MASK_DAC_FIFO_WR_REQ_ST) << BIT_SHIFT_DAC_FIFO_WR_REQ_ST)
+
+#define BIT_DAC_FIFO_FULL_ST                  	BIT(0)
+#define BIT_SHIFT_DAC_FIFO_FULL_ST            	0
+#define BIT_MASK_DAC_FIFO_FULL_ST             	0x1
+#define BIT_CTRL_DAC_FIFO_FULL_ST(x)          	(((x) & BIT_MASK_DAC_FIFO_FULL_ST) << BIT_SHIFT_DAC_FIFO_FULL_ST)
+
+
+//2 REG_DAC_PWR_CTRL
+
+#define BIT_SHIFT_DAC_PWR_CUT_CNTR 16
+#define BIT_MASK_DAC_PWR_CUT_CNTR 0xff
+#define BIT_DAC_PWR_CUT_CNTR(x)               	(((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
+#define BIT_CTRL_DAC_PWR_CUT_CNTR(x)          	(((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
+#define BIT_GET_DAC_PWR_CUT_CNTR(x)           	(((x) >> BIT_SHIFT_DAC_PWR_CUT_CNTR) & BIT_MASK_DAC_PWR_CUT_CNTR)
+
+#define BIT_ST_DAC_FIFO_ON                    	BIT(11)
+#define BIT_SHIFT_ST_DAC_FIFO_ON              	11
+#define BIT_MASK_ST_DAC_FIFO_ON               	0x1
+#define BIT_CTRL_ST_DAC_FIFO_ON(x)            	(((x) & BIT_MASK_ST_DAC_FIFO_ON) << BIT_SHIFT_ST_DAC_FIFO_ON)
+
+#define BIT_ST_DAC_ISO_ON                     	BIT(10)
+#define BIT_SHIFT_ST_DAC_ISO_ON               	10
+#define BIT_MASK_ST_DAC_ISO_ON                	0x1
+#define BIT_CTRL_ST_DAC_ISO_ON(x)             	(((x) & BIT_MASK_ST_DAC_ISO_ON) << BIT_SHIFT_ST_DAC_ISO_ON)
+
+#define BIT_ST_DAC_PWR33_ON                   	BIT(9)
+#define BIT_SHIFT_ST_DAC_PWR33_ON             	9
+#define BIT_MASK_ST_DAC_PWR33_ON              	0x1
+#define BIT_CTRL_ST_DAC_PWR33_ON(x)           	(((x) & BIT_MASK_ST_DAC_PWR33_ON) << BIT_SHIFT_ST_DAC_PWR33_ON)
+
+#define BIT_ST_DAC_PWR12_ON                   	BIT(8)
+#define BIT_SHIFT_ST_DAC_PWR12_ON             	8
+#define BIT_MASK_ST_DAC_PWR12_ON              	0x1
+#define BIT_CTRL_ST_DAC_PWR12_ON(x)           	(((x) & BIT_MASK_ST_DAC_PWR12_ON) << BIT_SHIFT_ST_DAC_PWR12_ON)
+
+#define BIT_DAC_ISO_MANU                      	BIT(3)
+#define BIT_SHIFT_DAC_ISO_MANU                	3
+#define BIT_MASK_DAC_ISO_MANU                 	0x1
+#define BIT_CTRL_DAC_ISO_MANU(x)              	(((x) & BIT_MASK_DAC_ISO_MANU) << BIT_SHIFT_DAC_ISO_MANU)
+
+#define BIT_DAC_PWR33_MANU                    	BIT(2)
+#define BIT_SHIFT_DAC_PWR33_MANU              	2
+#define BIT_MASK_DAC_PWR33_MANU               	0x1
+#define BIT_CTRL_DAC_PWR33_MANU(x)            	(((x) & BIT_MASK_DAC_PWR33_MANU) << BIT_SHIFT_DAC_PWR33_MANU)
+
+#define BIT_DAC_PWR12_MANU                    	BIT(1)
+#define BIT_SHIFT_DAC_PWR12_MANU              	1
+#define BIT_MASK_DAC_PWR12_MANU               	0x1
+#define BIT_CTRL_DAC_PWR12_MANU(x)            	(((x) & BIT_MASK_DAC_PWR12_MANU) << BIT_SHIFT_DAC_PWR12_MANU)
+
+#define BIT_DAC_PWR_AUTO                      	BIT(0)
+#define BIT_SHIFT_DAC_PWR_AUTO                	0
+#define BIT_MASK_DAC_PWR_AUTO                 	0x1
+#define BIT_CTRL_DAC_PWR_AUTO(x)              	(((x) & BIT_MASK_DAC_PWR_AUTO) << BIT_SHIFT_DAC_PWR_AUTO)
+
+
+//2 REG_DAC_ANAPAR_DA0
+
+#define BIT_SHIFT_PWR_ALL_CNTR 12
+#define BIT_MASK_PWR_ALL_CNTR 0xfffff
+#define BIT_PWR_ALL_CNTR(x)                   	(((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
+#define BIT_CTRL_PWR_ALL_CNTR(x)              	(((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
+#define BIT_GET_PWR_ALL_CNTR(x)               	(((x) >> BIT_SHIFT_PWR_ALL_CNTR) & BIT_MASK_PWR_ALL_CNTR)
+
+
+#define BIT_SHIFT_PWR_FUP_CNTR 0
+#define BIT_MASK_PWR_FUP_CNTR 0xfff
+#define BIT_PWR_FUP_CNTR(x)                   	(((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
+#define BIT_CTRL_PWR_FUP_CNTR(x)              	(((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
+#define BIT_GET_PWR_FUP_CNTR(x)               	(((x) >> BIT_SHIFT_PWR_FUP_CNTR) & BIT_MASK_PWR_FUP_CNTR)
+
+
+//2 REG_DAC_ANAPAR_DA1
+#define BIT_FUP_EN                            	BIT(31)
+#define BIT_SHIFT_FUP_EN                      	31
+#define BIT_MASK_FUP_EN                       	0x1
+#define BIT_CTRL_FUP_EN(x)                    	(((x) & BIT_MASK_FUP_EN) << BIT_SHIFT_FUP_EN)
+
+
+#define BIT_SHIFT_ANAPAR_DA 8
+#define BIT_MASK_ANAPAR_DA 0x7fffff
+#define BIT_ANAPAR_DA(x)                      	(((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
+#define BIT_CTRL_ANAPAR_DA(x)                 	(((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
+#define BIT_GET_ANAPAR_DA(x)                  	(((x) >> BIT_SHIFT_ANAPAR_DA) & BIT_MASK_ANAPAR_DA)
+
+#define BIT_D_POW_DACVREF                     	BIT(7)
+#define BIT_SHIFT_D_POW_DACVREF               	7
+#define BIT_MASK_D_POW_DACVREF                	0x1
+#define BIT_CTRL_D_POW_DACVREF(x)             	(((x) & BIT_MASK_D_POW_DACVREF) << BIT_SHIFT_D_POW_DACVREF)
+
+#define BIT_D_POW_VREF2                       	BIT(6)
+#define BIT_SHIFT_D_POW_VREF2                 	6
+#define BIT_MASK_D_POW_VREF2                  	0x1
+#define BIT_CTRL_D_POW_VREF2(x)               	(((x) & BIT_MASK_D_POW_VREF2) << BIT_SHIFT_D_POW_VREF2)
+
+#define BIT_D_POW_MBIAS                       	BIT(5)
+#define BIT_SHIFT_D_POW_MBIAS                 	5
+#define BIT_MASK_D_POW_MBIAS                  	0x1
+#define BIT_CTRL_D_POW_MBIAS(x)               	(((x) & BIT_MASK_D_POW_MBIAS) << BIT_SHIFT_D_POW_MBIAS)
+
+#define BIT_D_POW_DIV4                        	BIT(4)
+#define BIT_SHIFT_D_POW_DIV4                  	4
+#define BIT_MASK_D_POW_DIV4                   	0x1
+#define BIT_CTRL_D_POW_DIV4(x)                	(((x) & BIT_MASK_D_POW_DIV4) << BIT_SHIFT_D_POW_DIV4)
+
+#define BIT_D_POW_DF1SE_R                     	BIT(3)
+#define BIT_SHIFT_D_POW_DF1SE_R               	3
+#define BIT_MASK_D_POW_DF1SE_R                	0x1
+#define BIT_CTRL_D_POW_DF1SE_R(x)             	(((x) & BIT_MASK_D_POW_DF1SE_R) << BIT_SHIFT_D_POW_DF1SE_R)
+
+#define BIT_D_POW_DF2SE_L                     	BIT(2)
+#define BIT_SHIFT_D_POW_DF2SE_L               	2
+#define BIT_MASK_D_POW_DF2SE_L                	0x1
+#define BIT_CTRL_D_POW_DF2SE_L(x)             	(((x) & BIT_MASK_D_POW_DF2SE_L) << BIT_SHIFT_D_POW_DF2SE_L)
+
+#define BIT_D_POW_DAC_R                       	BIT(1)
+#define BIT_SHIFT_D_POW_DAC_R                 	1
+#define BIT_MASK_D_POW_DAC_R                  	0x1
+#define BIT_CTRL_D_POW_DAC_R(x)               	(((x) & BIT_MASK_D_POW_DAC_R) << BIT_SHIFT_D_POW_DAC_R)
+
+#define BIT_D_POW_DAC_L                       	BIT(0)
+#define BIT_SHIFT_D_POW_DAC_L                 	0
+#define BIT_MASK_D_POW_DAC_L                  	0x1
+#define BIT_CTRL_D_POW_DAC_L(x)               	(((x) & BIT_MASK_D_POW_DAC_L) << BIT_SHIFT_D_POW_DAC_L)
+
+
+//================ Register Reg Field  =========================
+#define REG_DAC0_FIFO_WR 0x0000
+#define REG_DAC_CTRL 0x0004
+#define REG_DAC_INTR_CTRL 0x0008
+#define REG_DAC_INTR_STS 0x000C
+#define REG_DAC_PWR_CTRL 0x0010
+#define REG_DAC_ANAPAR_DA0 0x0014
+#define REG_DAC_ANAPAR_DA1 0x0018
+
+
+//================ DAC HAL related enumeration ==================
+
+
+//================ DAC HAL Macro  ===========================
+#define HAL_DAC_WRITE32(dacidx, addr, value)    HAL_WRITE32(DAC_REG_BASE+dacidx*0x800 \
+                                                        ,addr,value)
+#define HAL_DAC_READ32(dacidx, addr)            HAL_READ32(DAC_REG_BASE+dacidx*0x800,addr)
+
+
+//================ DAC Function Prototypes  =====================
+RTK_STATUS HalDACInit8195a(IN  VOID *Data);
+RTK_STATUS HalDACDeInit8195a(IN  VOID *Data);
+RTK_STATUS HalDACEnableRtl8195a(IN  VOID *Data);
+RTK_STATUS HalDACIntrCtrl8195a(IN  VOID    *Data);
+u8 HalDACSendRtl8195a(IN  VOID    *Data);
+u32 HalDACReadRegRtl8195a(IN  VOID    *Data,IN  u8      I2CReg);
+
+#endif

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gdma.h

@@ -0,0 +1,486 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_GDMA_H_
+#define _RTL8195A_GDMA_H_
+
+// Define GDMA Handshake interface with peripheral, 0 -> GDMA0, 1-> GDMA1
+// Set this Hnadshake interface map to register REG_PESOC_SOC_CTRL
+#define GDMA_HANDSHAKE_UART0_TX             0
+#define GDMA_HANDSHAKE_UART0_RX             1
+#define GDMA_HANDSHAKE_UART1_TX             2
+#define GDMA_HANDSHAKE_UART1_RX             3
+#define GDMA_HANDSHAKE_UART2_TX             14      // Only on GDMA 0, hardware fixed
+#define GDMA_HANDSHAKE_UART2_RX             14      // Only on GDMA 1, hardware fixed
+
+#define GDMA_HANDSHAKE_SSI0_TX              4
+#define GDMA_HANDSHAKE_SSI0_RX              5
+#define GDMA_HANDSHAKE_SSI1_TX              6
+#define GDMA_HANDSHAKE_SSI1_RX              7
+#define GDMA_HANDSHAKE_SSI2_TX              15      // Only on GDMA 0, hardware fixed
+#define GDMA_HANDSHAKE_SSI2_RX              15      // Only on GDMA 1, hardware fixed
+
+#define GDMA_HANDSHAKE_I2C0_TX              8
+#define GDMA_HANDSHAKE_I2C0_RX              9
+#define GDMA_HANDSHAKE_I2C1_TX              10
+#define GDMA_HANDSHAKE_I2C1_RX              11
+
+#define GDMA_HANDSHAKE_ADC                  12
+#define GDMA_HANDSHAKE_DAC0                 13      // Only on GDMA 0, hardware fixed
+#define GDMA_HANDSHAKE_DAC1                 13      // Only on GDMA 1, hardware fixed
+
+#define HAL_GDMAX_READ32(GdmaIndex, addr)     \
+                HAL_READ32(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
+#define HAL_GDMAX_WRITE32(GdmaIndex, addr, value)     \
+                HAL_WRITE32((GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF)), addr, value)
+#define HAL_GDMAX_READ16(GdmaIndex, addr)     \
+                HAL_READ16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
+#define HAL_GDMAX_WRITE16(GdmaIndex, addr, value)     \
+                HAL_WRITE16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
+#define HAL_GDMAX_READ8(GdmaIndex, addr)     \
+                HAL_READ8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
+#define HAL_GDMAX_WRITE8(GdmaIndex, addr, value)     \
+                HAL_WRITE8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
+
+
+#define GDMA_CH_MAX                 0x06
+
+#define REG_GDMA_CH_OFF                 0x058
+#define REG_GDMA_CH_SAR                 0x000
+#define REG_GDMA_CH_DAR                 0x008
+#define REG_GDMA_CH_LLP                 0x010
+#define REG_GDMA_CH_CTL                 0x018
+#define REG_GDMA_CH_SSTAT               0x020
+#define REG_GDMA_CH_DSTAT               0x028
+#define REG_GDMA_CH_SSTATAR             0x030
+#define REG_GDMA_CH_DSTATAR             0x038
+#define REG_GDMA_CH_CFG                 0x040
+#define REG_GDMA_CH_SGR                 0x048
+#define REG_GDMA_CH_DSR                 0x050
+
+//3 Interrupt Registers
+#define REG_GDMA_RAW_INT_BASE           0x2C0
+#define REG_GDMA_RAW_INT_TFR            0x2C0
+#define REG_GDMA_RAW_INT_BLOCK          0x2c8
+#define REG_GDMA_RAW_INT_SRC_TRAN       0x2D0
+#define REG_GDMA_RAW_INT_DST_TRAN       0x2D8
+#define REG_GDMA_RAW_INT_ERR            0x2E0
+
+#define REG_GDMA_STATUS_INT_BASE        0x2E8
+#define REG_GDMA_STATUS_INT_TFR         0x2E8
+#define REG_GDMA_STATUS_INT_BLOCK       0x2F0
+#define REG_GDMA_STATUS_INT_SRC_TRAN    0x2F8
+#define REG_GDMA_STATUS_INT_DST_TRAN    0x300
+#define REG_GDMA_STATUS_INT_ERR         0x308
+
+#define REG_GDMA_MASK_INT_BASE          0x310
+#define REG_GDMA_MASK_INT_TFR           0x310
+#define REG_GDMA_MASK_INT_BLOCK         0x318
+#define REG_GDMA_MASK_INT_SRC_TRAN      0x320
+#define REG_GDMA_MASK_INT_DST_TRAN      0x328
+#define REG_GDMA_MASK_INT_INT_ERR       0x330
+
+#define REG_GDMA_CLEAR_INT_BASE         0x338
+#define REG_GDMA_CLEAR_INT_TFR          0x338
+#define REG_GDMA_CLEAR_INT_BLOCK        0x340
+#define REG_GDMA_CLEAR_INT_SRC_TRAN     0x348
+#define REG_GDMA_CLEAR_INT_DST_TRAN     0x350
+#define REG_GDMA_CLEAR_INT_ERR          0x358
+#define REG_GDMA_STATUS_INT             0x360
+
+//3 Software handshaking Registers
+#define REG_GDMA_REQ_SRC                0x368
+#define REG_GDMA_REQ_DST                0x370
+#define REG_GDMA_REQ_SGL_REQ            0x378
+#define REG_GDMA_REQ_DST_REQ            0x380
+#define REG_GDMA_REQ_LST_SRC            0x388
+#define REG_GDMA_REQ_LST_DST            0x390
+
+//3 Miscellaneous Registers
+#define REG_GDMA_DMAC_CFG               0x398
+#define REG_GDMA_CH_EN                  0x3A0
+#define REG_GDMA_DMA_ID                 0x3A8
+#define REG_GDMA_DMA_TEST               0x3B0
+#define REG_GDMA_DMA_COM_PARAMS6        0x3C8
+#define REG_GDMA_DMA_COM_PARAMS5        0x3D0
+#define REG_GDMA_DMA_COM_PARAMS4        0x3D8
+#define REG_GDMA_DMA_COM_PARAMS3        0x3E0
+#define REG_GDMA_DMA_COM_PARAMS2        0x3E8
+#define REG_GDMA_DMA_COM_PARAMS1        0x3F0
+#define REG_GDMA_DMA_COM_PARAMS0        0x3F8
+
+//3 CTL Register Bit Control
+#define BIT_SHIFT_CTLX_LO_INT_EN 0
+#define BIT_MASK_CTLX_LO_INT_EN 0x1
+#define BIT_CTLX_LO_INT_EN(x)(((x) & BIT_MASK_CTLX_LO_INT_EN) << BIT_SHIFT_CTLX_LO_INT_EN)
+#define BIT_INVC_CTLX_LO_INT_EN (~(BIT_MASK_CTLX_LO_INT_EN << BIT_SHIFT_CTLX_LO_INT_EN))
+
+#define BIT_SHIFT_CTLX_LO_DST_TR_WIDTH 1
+#define BIT_MASK_CTLX_LO_DST_TR_WIDTH 0x7
+#define BIT_CTLX_LO_DST_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_DST_TR_WIDTH) << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH)
+#define BIT_INVC_CTLX_LO_DST_TR_WIDTH (~(BIT_MASK_CTLX_LO_DST_TR_WIDTH << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH))
+
+#define BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH 4
+#define BIT_MASK_CTLX_LO_SRC_TR_WIDTH 0x7
+#define BIT_CTLX_LO_SRC_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_SRC_TR_WIDTH) << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH)
+#define BIT_INVC_CTLX_LO_SRC_TR_WIDTH (~(BIT_MASK_CTLX_LO_SRC_TR_WIDTH << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH))
+
+#define BIT_SHIFT_CTLX_LO_DINC 7
+#define BIT_MASK_CTLX_LO_DINC 0x3
+#define BIT_CTLX_LO_DINC(x)(((x) & BIT_MASK_CTLX_LO_DINC) << BIT_SHIFT_CTLX_LO_DINC)
+#define BIT_INVC_CTLX_LO_DINC (~(BIT_MASK_CTLX_LO_DINC << BIT_SHIFT_CTLX_LO_DINC))
+
+#define BIT_SHIFT_CTLX_LO_SINC 9
+#define BIT_MASK_CTLX_LO_SINC 0x3
+#define BIT_CTLX_LO_SINC(x)(((x) & BIT_MASK_CTLX_LO_SINC) << BIT_SHIFT_CTLX_LO_SINC)
+#define BIT_INVC_CTLX_LO_SINC (~(BIT_MASK_CTLX_LO_SINC << BIT_SHIFT_CTLX_LO_SINC))
+
+#define BIT_SHIFT_CTLX_LO_DEST_MSIZE 11
+#define BIT_MASK_CTLX_LO_DEST_MSIZE 0x7
+#define BIT_CTLX_LO_DEST_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_DEST_MSIZE) << BIT_SHIFT_CTLX_LO_DEST_MSIZE)
+#define BIT_INVC_CTLX_LO_DEST_MSIZE (~(BIT_MASK_CTLX_LO_DEST_MSIZE << BIT_SHIFT_CTLX_LO_DEST_MSIZE))
+
+#define BIT_SHIFT_CTLX_LO_SRC_MSIZE 14
+#define BIT_MASK_CTLX_LO_SRC_MSIZE 0x7
+#define BIT_CTLX_LO_SRC_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_SRC_MSIZE) << BIT_SHIFT_CTLX_LO_SRC_MSIZE)
+#define BIT_INVC_CTLX_LO_SRC_MSIZE (~(BIT_MASK_CTLX_LO_SRC_MSIZE << BIT_SHIFT_CTLX_LO_SRC_MSIZE))
+
+
+#define BIT_SHIFT_CTLX_LO_SRC_GATHER_EN 17
+#define BIT_MASK_CTLX_LO_SRC_GATHER_EN 0x1
+#define BIT_CTLX_LO_SRC_GATHER_EN(x)(((x) & BIT_MASK_CTLX_LO_SRC_GATHER_EN) << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN)
+#define BIT_INVC_CTLX_LO_SRC_GATHER_EN (~(BIT_MASK_CTLX_LO_SRC_GATHER_EN << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN))
+
+
+#define BIT_SHIFT_CTLX_LO_DST_SCATTER_EN 18
+#define BIT_MASK_CTLX_LO_DST_SCATTER_EN 0x1
+#define BIT_CTLX_LO_DST_SCATTER_EN(x)(((x) & BIT_MASK_CTLX_LO_DST_SCATTER_EN) << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN)
+#define BIT_INVC_CTLX_LO_DST_SCATTER_EN (~(BIT_MASK_CTLX_LO_DST_SCATTER_EN << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN))
+
+
+#define BIT_SHIFT_CTLX_LO_TT_FC 20
+#define BIT_MASK_CTLX_LO_TT_FC 0x7
+#define BIT_CTLX_LO_TT_FC(x)(((x) & BIT_MASK_CTLX_LO_TT_FC) << BIT_SHIFT_CTLX_LO_TT_FC)
+#define BIT_INVC_CTLX_LO_TT_FC (~(BIT_MASK_CTLX_LO_TT_FC << BIT_SHIFT_CTLX_LO_TT_FC))
+
+
+#define BIT_SHIFT_CTLX_LO_DMS 23
+#define BIT_MASK_CTLX_LO_DMS 0x3
+#define BIT_CTLX_LO_DMS(x)(((x) & BIT_MASK_CTLX_LO_DMS) << BIT_MASK_CTLX_LO_DMS)
+#define BIT_INVC_CTLX_LO_DMS (~(BIT_MASK_CTLX_LO_DMS << BIT_SHIFT_CTLX_LO_DMS))
+
+
+#define BIT_SHIFT_CTLX_LO_SMS 25
+#define BIT_MASK_CTLX_LO_SMS 0x3
+#define BIT_CTLX_LO_SMS(x)(((x) & BIT_MASK_CTLX_LO_SMS) << BIT_SHIFT_CTLX_LO_SMS)
+#define BIT_INVC_CTLX_LO_SMS (~(BIT_MASK_CTLX_LO_SMS << BIT_SHIFT_CTLX_LO_SMS))
+
+
+#define BIT_SHIFT_CTLX_LO_LLP_DST_EN 27
+#define BIT_MASK_CTLX_LO_LLP_DST_EN 0x1
+#define BIT_CTLX_LO_LLP_DST_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_DST_EN) << BIT_SHIFT_CTLX_LO_LLP_DST_EN)
+#define BIT_INVC_CTLX_LO_LLP_DST_EN (~(BIT_MASK_CTLX_LO_LLP_DST_EN << BIT_SHIFT_CTLX_LO_LLP_DST_EN))
+
+#define BIT_SHIFT_CTLX_LO_LLP_SRC_EN 28
+#define BIT_MASK_CTLX_LO_LLP_SRC_EN 0x1
+#define BIT_CTLX_LO_LLP_SRC_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_SRC_EN) << BIT_SHIFT_CTLX_LO_LLP_SRC_EN)
+#define BIT_INVC_CTLX_LO_LLP_SRC_EN (~(BIT_MASK_CTLX_LO_LLP_SRC_EN << BIT_SHIFT_CTLX_LO_LLP_SRC_EN))
+
+
+#define BIT_SHIFT_CTLX_UP_BLOCK_BS 0
+#define BIT_MASK_CTLX_UP_BLOCK_BS 0xFFF
+#define BIT_CTLX_UP_BLOCK_BS(x)(((x) & BIT_MASK_CTLX_UP_BLOCK_BS) << BIT_SHIFT_CTLX_UP_BLOCK_BS)
+#define BIT_INVC_CTLX_UP_BLOCK_BS (~(BIT_MASK_CTLX_UP_BLOCK_BS << BIT_SHIFT_CTLX_UP_BLOCK_BS))
+
+
+#define BIT_SHIFT_CTLX_UP_DONE 12
+#define BIT_MASK_CTLX_UP_DONE 0x1
+#define BIT_CTLX_UP_DONE(x)(((x) & BIT_MASK_CTLX_UP_DONE) << BIT_SHIFT_CTLX_UP_DONE)
+#define BIT_INVC_CTLX_UP_DONE (~(BIT_MASK_CTLX_UP_DONE << BIT_SHIFT_CTLX_UP_DONE))
+
+
+//3 CFG Register Bit Control
+#define BIT_SHIFT_CFGX_LO_CH_PRIOR 5
+#define BIT_MASK_CFGX_LO_CH_PRIOR 0x7
+#define BIT_CFGX_LO_CH_PRIOR(x)(((x) & BIT_MASK_CFGX_LO_CH_PRIOR) << BIT_SHIFT_CFGX_LO_CH_PRIOR)
+#define BIT_INVC_CFGX_LO_CH_PRIOR (~(BIT_MASK_CFGX_LO_CH_PRIOR << BIT_SHIFT_CFGX_LO_CH_PRIOR))
+
+
+#define BIT_SHIFT_CFGX_LO_CH_SUSP 8
+#define BIT_MASK_CFGX_LO_CH_SUSP 0x1
+#define BIT_CFGX_LO_CH_SUSP(x)(((x) & BIT_MASK_CFGX_LO_CH_SUSP) << BIT_SHIFT_CFGX_LO_CH_SUSP)
+#define BIT_INVC_CFGX_LO_CH_SUSP (~(BIT_MASK_CFGX_LO_CH_SUSP << BIT_SHIFT_CFGX_LO_CH_SUSP))
+
+
+#define BIT_SHIFT_CFGX_LO_FIFO_EMPTY 9
+#define BIT_MASK_CFGX_LO_FIFO_EMPTY 0x1
+#define BIT_CFGX_LO_FIFO_EMPTY(x)(((x) & BIT_MASK_CFGX_LO_FIFO_EMPTY) << BIT_SHIFT_CFGX_LO_FIFO_EMPTY)
+#define BIT_INVC_CFGX_LO_FIFO_EMPTY (~(BIT_MASK_CFGX_LO_FIFO_EMPTY << BIT_SHIFT_CFGX_LO_FIFO_EMPTY))
+
+
+#define BIT_SHIFT_CFGX_LO_HS_SEL_DST 10
+#define BIT_MASK_CFGX_LO_HS_SEL_DST 0x1
+#define BIT_CFGX_LO_HS_SEL_DST(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_DST) << BIT_SHIFT_CFGX_LO_HS_SEL_DST)
+#define BIT_INVC_CFGX_LO_HS_SEL_DST (~(BIT_MASK_CFGX_LO_HS_SEL_DST << BIT_SHIFT_CFGX_LO_HS_SEL_DST))
+
+#define BIT_SHIFT_CFGX_LO_HS_SEL_SRC 11
+#define BIT_MASK_CFGX_LO_HS_SEL_SRC 0x1
+#define BIT_CFGX_LO_HS_SEL_SRC(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_SRC) << BIT_SHIFT_CFGX_LO_HS_SEL_SRC)
+#define BIT_INVC_CFGX_LO_HS_SEL_SRC (~(BIT_MASK_CFGX_LO_HS_SEL_SRC << BIT_SHIFT_CFGX_LO_HS_SEL_SRC))
+
+#define BIT_SHIFT_CFGX_LO_LOCK_CH_L 12
+#define BIT_MASK_CFGX_LO_LOCK_CH_L 0x3
+#define BIT_CFGX_LO_LOCK_CH_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH_L) << BIT_SHIFT_CFGX_LO_LOCK_CH_L)
+#define BIT_INVC_CFGX_LO_LOCK_CH_L (~(BIT_MASK_CFGX_LO_LOCK_CH_L << BIT_SHIFT_CFGX_LO_LOCK_CH_L))
+
+#define BIT_SHIFT_CFGX_LO_LOCK_B_L 14
+#define BIT_MASK_CFGX_LO_LOCK_B_L 0x3
+#define BIT_CFGX_LO_LOCK_B_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B_L) << BIT_SHIFT_CFGX_LO_LOCK_B_L)
+#define BIT_INVC_CFGX_LO_LOCK_B_L (~(BIT_MASK_CFGX_LO_LOCK_B_L << BIT_SHIFT_CFGX_LO_LOCK_B_L))
+
+#define BIT_SHIFT_CFGX_LO_LOCK_CH 16
+#define BIT_MASK_CFGX_LO_LOCK_CH 0x1
+#define BIT_CFGX_LO_LOCK_CH(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH) << BIT_SHIFT_CFGX_LO_LOCK_CH)
+#define BIT_INVC_CFGX_LO_LOCK_CH (~(BIT_MASK_CFGX_LO_LOCK_CH << BIT_SHIFT_CFGX_LO_LOCK_CH))
+
+#define BIT_SHIFT_CFGX_LO_LOCK_B 17
+#define BIT_MASK_CFGX_LO_LOCK_B 0x1
+#define BIT_CFGX_LO_LOCK_B(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B) << BIT_SHIFT_CFGX_LO_LOCK_B)
+#define BIT_INVC_CFGX_LO_LOCK_B (~(BIT_MASK_CFGX_LO_LOCK_B << BIT_SHIFT_CFGX_LO_LOCK_B))
+
+#define BIT_SHIFT_CFGX_LO_DST_HS_POL 18
+#define BIT_MASK_CFGX_LO_DST_HS_POL 0x1
+#define BIT_CFGX_LO_DST_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_DST_HS_POL) << BIT_SHIFT_CFGX_LO_DST_HS_POL)
+#define BIT_INVC_CFGX_LO_DST_HS_POL (~(BIT_MASK_CFGX_LO_DST_HS_POL << BIT_SHIFT_CFGX_LO_DST_HS_POL))
+
+#define BIT_SHIFT_CFGX_LO_SRC_HS_POL 19
+#define BIT_MASK_CFGX_LO_SRC_HS_POL 0x1
+#define BIT_CFGX_LO_SRC_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_SRC_HS_POL) << BIT_SHIFT_CFGX_LO_SRC_HS_POL)
+#define BIT_INVC_CFGX_LO_SRC_HS_POL (~(BIT_MASK_CFGX_LO_SRC_HS_POL << BIT_SHIFT_CFGX_LO_SRC_HS_POL))
+
+#define BIT_SHIFT_CFGX_LO_MAX_ABRST 20
+#define BIT_MASK_CFGX_LO_MAX_ABRST 0x3FF
+#define BIT_CFGX_LO_MAX_ABRST(x)(((x) & BIT_MASK_CFGX_LO_MAX_ABRST) << BIT_SHIFT_CFGX_LO_MAX_ABRST)
+#define BIT_INVC_CFGX_LO_MAX_ABRST (~(BIT_MASK_CFGX_LO_MAX_ABRST << BIT_SHIFT_CFGX_LO_MAX_ABRST))
+
+#define BIT_SHIFT_CFGX_LO_RELOAD_SRC 30
+#define BIT_MASK_CFGX_LO_RELOAD_SRC 0x1
+#define BIT_CFGX_LO_RELOAD_SRC(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_SRC) << BIT_SHIFT_CFGX_LO_RELOAD_SRC)
+#define BIT_INVC_CFGX_LO_RELOAD_SRC (~(BIT_MASK_CFGX_LO_RELOAD_SRC << BIT_SHIFT_CFGX_LO_RELOAD_SRC))
+
+#define BIT_SHIFT_CFGX_LO_RELOAD_DST 31
+#define BIT_MASK_CFGX_LO_RELOAD_DST 0x1
+#define BIT_CFGX_LO_RELOAD_DST(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_DST) << BIT_SHIFT_CFGX_LO_RELOAD_DST)
+#define BIT_INVC_CFGX_LO_RELOAD_DST (~(BIT_MASK_CFGX_LO_RELOAD_DST << BIT_SHIFT_CFGX_LO_RELOAD_DST))
+
+#define BIT_SHIFT_CFGX_UP_FCMODE 0
+#define BIT_MASK_CFGX_UP_FCMODE 0x1
+#define BIT_CFGX_UP_FCMODE(x)(((x) & BIT_MASK_CFGX_UP_FCMODE) << BIT_SHIFT_CFGX_UP_FCMODE)
+#define BIT_INVC_CFGX_UP_FCMODE (~(BIT_MASK_CFGX_UP_FCMODE << BIT_SHIFT_CFGX_UP_FCMODE))
+
+#define BIT_SHIFT_CFGX_UP_FIFO_MODE 1
+#define BIT_MASK_CFGX_UP_FIFO_MODE 0x1
+#define BIT_CFGX_UP_FIFO_MODE(x)(((x) & BIT_MASK_CFGX_UP_FIFO_MODE) << BIT_SHIFT_CFGX_UP_FIFO_MODE)
+#define BIT_INVC_CFGX_UP_FIFO_MODE (~(BIT_MASK_CFGX_UP_FIFO_MODE << BIT_SHIFT_CFGX_UP_FIFO_MODE))
+
+#define BIT_SHIFT_CFGX_UP_PROTCTL 2
+#define BIT_MASK_CFGX_UP_PROTCTL 0x7
+#define BIT_CFGX_UP_PROTCTL(x)(((x) & BIT_MASK_CFGX_UP_PROTCTL) << BIT_SHIFT_CFGX_UP_PROTCTL)
+#define BIT_INVC_CFGX_UP_PROTCTL (~(BIT_MASK_CFGX_UP_PROTCTL << BIT_SHIFT_CFGX_UP_PROTCTL))
+
+#define BIT_SHIFT_CFGX_UP_DS_UPD_EN 5
+#define BIT_MASK_CFGX_UP_DS_UPD_EN 0x1
+#define BIT_CFGX_UP_DS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_DS_UPD_EN) << BIT_SHIFT_CFGX_UP_DS_UPD_EN)
+#define BIT_INVC_CFGX_UP_DS_UPD_EN (~(BIT_MASK_CFGX_UP_DS_UPD_EN << BIT_SHIFT_CFGX_UP_DS_UPD_EN))
+
+#define BIT_SHIFT_CFGX_UP_SS_UPD_EN 6
+#define BIT_MASK_CFGX_UP_SS_UPD_EN 0x1
+#define BIT_CFGX_UP_SS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_SS_UPD_EN) << BIT_SHIFT_CFGX_UP_SS_UPD_EN)
+#define BIT_INVC_CFGX_UP_SS_UPD_EN (~(BIT_MASK_CFGX_UP_SS_UPD_EN << BIT_SHIFT_CFGX_UP_SS_UPD_EN))
+
+#define BIT_SHIFT_CFGX_UP_SRC_PER 7
+#define BIT_MASK_CFGX_UP_SRC_PER 0xF
+#define BIT_CFGX_UP_SRC_PER(x)(((x) & BIT_MASK_CFGX_UP_SRC_PER) << BIT_SHIFT_CFGX_UP_SRC_PER)
+#define BIT_INVC_CFGX_UP_SRC_PER (~(BIT_MASK_CFGX_UP_SRC_PER << BIT_SHIFT_CFGX_UP_SRC_PER))
+
+#define BIT_SHIFT_CFGX_UP_DEST_PER 11
+#define BIT_MASK_CFGX_UP_DEST_PER 0xF
+#define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER)
+#define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER))
+
+typedef enum _GDMA_CHANNEL_NUM_ {
+        GdmaNoCh    = 0x0000,
+        GdmaCh0     = 0x0101,
+        GdmaCh1     = 0x0202,
+        GdmaCh2     = 0x0404,
+        GdmaCh3     = 0x0808,
+        GdmaCh4     = 0x1010,
+        GdmaCh5     = 0x2020,
+        GdmaCh6     = 0x4040,
+        GdmaCh7     = 0x8080,
+        GdmaAllCh   = 0xffff
+}GDMA_CHANNEL_NUM, *PGDMA_CHANNEL_NUM;
+
+
+//3 CTL register struct
+
+typedef enum _GDMA_CTL_TT_FC_TYPE_ {
+        TTFCMemToMem    = 0x00,
+        TTFCMemToPeri   = 0x01,
+        TTFCPeriToMem   = 0x02
+}GDMA_CTL_TT_FC_TYPE, *PGDMA_CTL_TT_FC_TYPE;
+
+//Max type = Bus Width
+typedef enum _GDMA_CTL_TR_WIDTH_ {
+        TrWidthOneByte    = 0x00,
+        TrWidthTwoBytes   = 0x01,
+        TrWidthFourBytes  = 0x02
+}GDMA_CTL_TR_WIDTH, *PGDMA_CTL_TR_WIDTH;
+
+typedef enum _GDMA_CTL_MSIZE_ {
+        MsizeOne        = 0x00,
+        MsizeFour       = 0x01,
+        MsizeEight      = 0x02
+}GDMA_CTL_MSIZE, *PGDMA_CTL_MSIZE;
+
+typedef enum _GDMA_INC_TYPE_ {
+        IncType         = 0x00,
+        DecType         = 0x01,
+        NoChange        = 0x02
+}GDMA_INC_TYPE, *PGDMA_INC_TYPE;
+
+
+typedef struct _GDMA_CTL_REG_ {
+        GDMA_CTL_TT_FC_TYPE     TtFc;
+        GDMA_CTL_TR_WIDTH       DstTrWidth;
+        GDMA_CTL_TR_WIDTH       SrcTrWidth;
+        GDMA_INC_TYPE           Dinc;
+        GDMA_INC_TYPE           Sinc;
+        GDMA_CTL_MSIZE          DestMsize;
+        GDMA_CTL_MSIZE          SrcMsize;
+
+        u8                      IntEn           :1; // Bit 0
+        u8                      SrcGatherEn     :1; // Bit 1
+        u8                      DstScatterEn    :1; // Bit 2
+        u8                      LlpDstEn        :1; // Bit 3
+        u8                      LlpSrcEn        :1; // Bit 4
+        u8                      Done            :1; // Bit 5
+        u8                      Rsvd6To7        :2; //Bit 6 -7
+        u16                     BlockSize;
+        
+}GDMA_CTL_REG, *PGDMA_CTL_REG;
+
+
+//3 CFG Register Structure
+
+typedef enum _GDMA_CH_PRIORITY_ {
+    Prior0          = 0,
+    Prior1          = 1,
+    Prior2          = 2,
+    Prior3          = 3,
+    Prior4          = 4,
+    Prior5          = 5,
+    Prior6          = 6,
+    Prior7          = 7
+}GDMA_CH_PRIORITY, *PGDMA_CH_PRIORITY;
+
+typedef enum _GDMA_LOCK_LEVEL_ {
+    OverComplDmaTransfer        = 0x00,
+    OverComplDmaBlockTransfer   = 0x01,
+    OverComplDmaTransation      = 0x02
+}GDMA_LOCK_LEVEL, *PGDMA_LOCK_LEVEL;
+
+
+typedef struct _GDMA_CFG_REG_ {
+    GDMA_CH_PRIORITY        ChPrior;
+    GDMA_LOCK_LEVEL         LockBL;     
+    GDMA_LOCK_LEVEL         LockChL;     
+    u16                     MaxAbrst;
+    u8                      SrcPer;
+    u8                      DestPer;
+    u16                     ChSusp      :1; //Bit 0
+    u16                     FifoEmpty   :1; //Bit 1
+    u16                     HsSelDst    :1; //Bit 2
+    u16                     HsSelSrc    :1; //Bit 3
+    u16                     LockCh      :1; //Bit 4
+    u16                     LockB       :1; //Bit 5
+    u16                     DstHsPol    :1; //Bit 6
+    u16                     SrcHsPol    :1; //Bit 7
+    u16                     ReloadSrc   :1; //Bit 8
+    u16                     ReloadDst   :1; //Bit 9
+    u16                     FifoMode    :1; //Bit 10
+    u16                     DsUpdEn     :1; //Bit 11
+    u16                     SsUpdEn     :1; //Bit 12
+    u16                     Rsvd13To15  :3;
+}GDMA_CFG_REG, *PGDMA_CFG_REG;
+
+typedef enum _GDMA_ISR_TYPE_ {
+    TransferType        = 0x1,
+    BlockType           = 0x2,
+    SrcTransferType     = 0x4,
+    DstTransferType     = 0x8,
+    ErrType             = 0x10
+}GDMA_ISR_TYPE, *PGDMA_ISR_TYPE;
+
+
+VOID
+HalGdmaOnOffRtl8195a (
+    IN  VOID              *Data
+);
+
+BOOL
+HalGdamChInitRtl8195a(
+    IN  VOID     *Data
+);
+
+BOOL
+HalGdmaChSetingRtl8195a(
+    IN  VOID     *Data
+);
+
+BOOL
+HalGdmaChBlockSetingRtl8195a(
+    IN  VOID     *Data
+);
+
+
+VOID
+HalGdmaChDisRtl8195a (
+    IN  VOID              *Data
+);
+
+VOID
+HalGdmaChEnRtl8195a (
+    IN  VOID              *Data
+);
+
+VOID
+HalGdmaChIsrEnAndDisRtl8195a (
+    IN  VOID              *Data
+);
+
+u8
+HalGdmaChIsrCleanRtl8195a (
+    IN  VOID              *Data
+);
+
+VOID
+HalGdmaChCleanAutoSrcRtl8195a (
+    IN  VOID              *Data
+);
+
+VOID
+HalGdmaChCleanAutoDstRtl8195a (
+    IN  VOID              *Data
+); 
+
+
+
+#endif

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gpio.h

@@ -0,0 +1,352 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_GPIO_H_
+#define _RTL8195A_GPIO_H_
+
+#include "hal_api.h"
+#include "hal_gpio.h"
+
+#define GPIO_PORTA_DR           0x00        // data register
+#define GPIO_PORTA_DDR          0x04        // data direction
+#define GPIO_PORTA_CTRL         0x08        // data source control, we should keep it as default: data source from software
+
+#define GPIO_PORTB_DR           0x0c        // data register
+#define GPIO_PORTB_DDR          0x10        // data direction
+#define GPIO_PORTB_CTRL         0x14        // data source control, we should keep it as default: data source from software
+
+#define GPIO_PORTC_DR           0x18        // data register
+#define GPIO_PORTC_DDR          0x1c        // data direction
+#define GPIO_PORTC_CTRL         0x20        // data source control, we should keep it as default: data source from software
+
+//1 Only the PORTA can be configured to generate interrupts
+#define GPIO_INT_EN             0x30        // Interrupt enable register
+#define GPIO_INT_MASK           0x34        // Interrupt mask
+#define GPIO_INT_TYPE           0x38        // Interrupt type(level/edge) register
+#define GPIO_INT_POLARITY       0x3C        // Interrupt polarity(Active low/high) register
+#define GPIO_INT_STATUS         0x40        // Interrupt status
+#define GPIO_INT_RAWSTATUS      0x44        // Interrupt status without mask
+#define GPIO_DEBOUNCE           0x48        // Interrupt signal debounce
+#define GPIO_PORTA_EOI          0x4c        // Clear interrupt
+
+#define GPIO_EXT_PORTA          0x50        // GPIO IN read or OUT read back
+#define GPIO_EXT_PORTB          0x54        // GPIO IN read or OUT read back
+#define GPIO_EXT_PORTC          0x58        // GPIO IN read or OUT read back
+
+#define GPIO_INT_SYNC           0x60        // Is level-sensitive interrupt being sync sith PCLK
+
+enum {
+    HAL_GPIO_HIGHZ      = 0,
+    HAL_GPIO_PULL_LOW   = 1,
+    HAL_GPIO_PULL_HIGH  = 2
+};
+
+//======================================================
+// ROM Function prototype
+extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
+
+static __inline HAL_Status
+GPIO_Lock (
+    VOID
+)
+{
+    HAL_Status Status;
+
+    if (_pHAL_Gpio_Adapter->EnterCritical) {
+        _pHAL_Gpio_Adapter->EnterCritical();
+    }
+
+    if(_pHAL_Gpio_Adapter->Locked) {
+       Status = HAL_BUSY;
+    }
+    else {
+       _pHAL_Gpio_Adapter->Locked = 1;
+       Status = HAL_OK;
+    }
+
+    if (_pHAL_Gpio_Adapter->ExitCritical) {
+        _pHAL_Gpio_Adapter->ExitCritical();
+    }
+
+    return Status;
+}
+
+
+static __inline VOID
+GPIO_UnLock (
+    VOID
+)
+{
+    if (_pHAL_Gpio_Adapter->EnterCritical) {
+        _pHAL_Gpio_Adapter->EnterCritical();
+    }
+
+    _pHAL_Gpio_Adapter->Locked = 0;
+
+    if (_pHAL_Gpio_Adapter->ExitCritical) {
+        _pHAL_Gpio_Adapter->ExitCritical();
+    }
+}
+
+
+_LONG_CALL_ extern u32
+HAL_GPIO_IrqHandler_8195a(
+    IN VOID *pData
+);
+
+_LONG_CALL_ extern u32
+HAL_GPIO_MbedIrqHandler_8195a(
+    IN VOID *pData
+);
+
+_LONG_CALL_ HAL_Status 
+HAL_GPIO_IntCtrl_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin, 
+    u32 En
+);
+
+_LONG_CALL_ HAL_Status 
+HAL_GPIO_Init_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+_LONG_CALL_ HAL_Status 
+HAL_GPIO_DeInit_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+_LONG_CALL_ HAL_GPIO_PIN_STATE 
+HAL_GPIO_ReadPin_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+_LONG_CALL_ HAL_Status 
+HAL_GPIO_WritePin_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin,
+    HAL_GPIO_PIN_STATE Pin_State
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_RegIrq_8195a(
+    IN PIRQ_HANDLE pIrqHandle
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_UnRegIrq_8195a(
+    IN PIRQ_HANDLE pIrqHandle
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_UserRegIrq_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin,
+    VOID *IrqHandler,
+    VOID *IrqData
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_UserUnRegIrq_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_MaskIrq_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_UnMaskIrq_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_IntDebounce_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin,
+    u8 Enable
+);
+
+_LONG_CALL_ u32
+HAL_GPIO_GetIPPinName_8195a(
+    u32 chip_pin
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_PullCtrl_8195a(
+    u32 chip_pin,
+    u8 pull_type
+);
+
+_LONG_CALL_ u32 
+GPIO_GetChipPinName_8195a(
+    u32 port,
+    u32 pin
+);
+
+_LONG_CALL_ VOID 
+GPIO_PullCtrl_8195a(
+    u32 chip_pin,
+    u8 pull_type
+);
+
+_LONG_CALL_ VOID 
+GPIO_Int_SetType_8195a(
+    u8 pin_num,
+    u8 int_mode
+);
+
+
+_LONG_CALL_  HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN  *GPIO_Pin, u32 En);
+_LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr);
+
+HAL_Status
+HAL_GPIO_ClearISR_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+
+/********** HAL In-Line Functions **********/
+
+/**
+  * @brief  De-Initializes a GPIO Pin, reset it as default setting.
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @retval HAL_Status
+  */
+static __inline VOID 
+HAL_GPIO_DeInit(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    HAL_GPIO_DeInit_8195a(GPIO_Pin);
+}
+
+/**
+  * @brief  Reads the specified input port pin.
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @retval The input port pin current status(High or Low).
+  */
+static __inline s32 
+HAL_GPIO_ReadPin(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    return (s32)HAL_GPIO_ReadPin_8195a(GPIO_Pin);    
+}
+
+/**
+  * @brief  Write the specified output port pin.
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @param  Pin_State: The state going to be set to the assigned GPIO pin.
+  *
+  * @retval None
+  */
+static __inline VOID 
+HAL_GPIO_WritePin(
+    HAL_GPIO_PIN  *GPIO_Pin,
+    u32 Value
+)
+{
+    HAL_GPIO_WritePin_8195a(GPIO_Pin, (HAL_GPIO_PIN_STATE)Value);
+}
+
+/**
+  * @brief  To register a user interrupt handler for a specified pin
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @param  IrqHandler: The IRQ handler to be assigned to the specified pin
+  *
+  * @param  IrqData: The pointer will be pass the the IRQ handler
+  *
+  * @retval None
+  */
+static __inline VOID
+HAL_GPIO_UserRegIrq(
+    HAL_GPIO_PIN  *GPIO_Pin,
+    VOID *IrqHandler,
+    VOID *IrqData
+)
+{
+    HAL_GPIO_UserRegIrq_8195a(GPIO_Pin, IrqHandler, IrqData);
+}
+
+/**
+  * @brief  To un-register a user interrupt handler for a specified pin
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @retval None
+  */
+static __inline VOID
+HAL_GPIO_UserUnRegIrq(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    HAL_GPIO_UserUnRegIrq_8195a(GPIO_Pin);
+}
+
+
+/**
+  * @brief  Enable/Disable GPIO interrupt
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
+  *
+  * @param  En: Enable (1) or Disable (0)
+  *
+  * @retval HAL_Status
+  */
+static __inline VOID
+HAL_GPIO_IntCtrl(
+    HAL_GPIO_PIN  *GPIO_Pin, 
+    u32 En
+)
+{
+    HAL_GPIO_IntCtrl_8195a(GPIO_Pin, En);
+}
+
+/**
+  * @brief  Mask the interrupt of a specified pin
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @retval None
+  */
+static __inline VOID
+HAL_GPIO_MaskIrq(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
+}
+
+
+/**
+  * @brief  UnMask the interrupt of a specified pin
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @retval None
+  */
+static __inline VOID
+HAL_GPIO_UnMaskIrq(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    HAL_GPIO_ClearISR_8195a(GPIO_Pin);
+    HAL_GPIO_UnMaskIrq_8195a(GPIO_Pin);
+}
+
+
+#endif  // end of "#define _RTL8195A_GPIO_H_"
+

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h

@@ -0,0 +1,844 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL8195A_I2C_H_
+#define _RTL8195A_I2C_H_
+
+#include "hal_api.h"
+
+//================ Register Bit Field ==================
+//2 REG_DW_I2C_IC_CON
+#define BIT_IC_CON_IC_SLAVE_DISABLE           	BIT(6)
+#define BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE     	6
+#define BIT_MASK_IC_CON_IC_SLAVE_DISABLE      	0x1
+#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(x)   	(((x) & BIT_MASK_IC_CON_IC_SLAVE_DISABLE) << BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE)
+
+#define BIT_IC_CON_IC_RESTART_EN              	BIT(5)
+#define BIT_SHIFT_IC_CON_IC_RESTART_EN        	5
+#define BIT_MASK_IC_CON_IC_RESTART_EN         	0x1
+#define BIT_CTRL_IC_CON_IC_RESTART_EN(x)      	(((x) & BIT_MASK_IC_CON_IC_RESTART_EN) << BIT_SHIFT_IC_CON_IC_RESTART_EN)
+
+#define BIT_IC_CON_IC_10BITADDR_MASTER        	BIT(4)
+#define BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER  	4
+#define BIT_MASK_IC_CON_IC_10BITADDR_MASTER   	0x1
+#define BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(x)	(((x) & BIT_MASK_IC_CON_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER)
+
+#define BIT_IC_CON_IC_10BITADDR_SLAVE         	BIT(3)
+#define BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE   	3
+#define BIT_MASK_IC_CON_IC_10BITADDR_SLAVE    	0x1
+#define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(x) 	(((x) & BIT_MASK_IC_CON_IC_10BITADDR_SLAVE) << BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE)
+
+
+#define BIT_SHIFT_IC_CON_SPEED 1
+#define BIT_MASK_IC_CON_SPEED 0x3
+#define BIT_IC_CON_SPEED(x)                   	(((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
+#define BIT_CTRL_IC_CON_SPEED(x)              	(((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
+#define BIT_GET_IC_CON_SPEED(x)               	(((x) >> BIT_SHIFT_IC_CON_SPEED) & BIT_MASK_IC_CON_SPEED)
+
+#define BIT_IC_CON_MASTER_MODE                	BIT(0)
+#define BIT_SHIFT_IC_CON_MASTER_MODE          	0
+#define BIT_MASK_IC_CON_MASTER_MODE           	0x1
+#define BIT_CTRL_IC_CON_MASTER_MODE(x)        	(((x) & BIT_MASK_IC_CON_MASTER_MODE) << BIT_SHIFT_IC_CON_MASTER_MODE)
+
+
+//2 REG_DW_I2C_IC_TAR
+#define BIT_IC_TAR_IC_10BITADDR_MASTER        	BIT(12)
+#define BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER  	12
+#define BIT_MASK_IC_TAR_IC_10BITADDR_MASTER   	0x1
+#define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(x)	(((x) & BIT_MASK_IC_TAR_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER)
+
+#define BIT_IC_TAR_SPECIAL                    	BIT(11)
+#define BIT_SHIFT_IC_TAR_SPECIAL              	11
+#define BIT_MASK_IC_TAR_SPECIAL               	0x1
+#define BIT_CTRL_IC_TAR_SPECIAL(x)            	(((x) & BIT_MASK_IC_TAR_SPECIAL) << BIT_SHIFT_IC_TAR_SPECIAL)
+
+#define BIT_IC_TAR_GC_OR_START                	BIT(10)
+#define BIT_SHIFT_IC_TAR_GC_OR_START          	10
+#define BIT_MASK_IC_TAR_GC_OR_START           	0x1
+#define BIT_CTRL_IC_TAR_GC_OR_START(x)        	(((x) & BIT_MASK_IC_TAR_GC_OR_START) << BIT_SHIFT_IC_TAR_GC_OR_START)
+
+
+#define BIT_SHIFT_IC_TAR 0
+#define BIT_MASK_IC_TAR 0x3ff
+#define BIT_IC_TAR(x)                         	(((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
+#define BIT_CTRL_IC_TAR(x)                    	(((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
+#define BIT_GET_IC_TAR(x)                     	(((x) >> BIT_SHIFT_IC_TAR) & BIT_MASK_IC_TAR)
+
+
+//2 REG_DW_I2C_IC_SAR
+
+#define BIT_SHIFT_IC_SAR 0
+#define BIT_MASK_IC_SAR 0x3ff
+#define BIT_IC_SAR(x)                         	(((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
+#define BIT_CTRL_IC_SAR(x)                    	(((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
+#define BIT_GET_IC_SAR(x)                     	(((x) >> BIT_SHIFT_IC_SAR) & BIT_MASK_IC_SAR)
+
+
+//2 REG_DW_I2C_IC_HS_MADDR
+
+#define BIT_SHIFT_IC_HS_MADDR 0
+#define BIT_MASK_IC_HS_MADDR 0x7
+#define BIT_IC_HS_MADDR(x)                    	(((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
+#define BIT_CTRL_IC_HS_MADDR(x)               	(((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
+#define BIT_GET_IC_HS_MADDR(x)                	(((x) >> BIT_SHIFT_IC_HS_MADDR) & BIT_MASK_IC_HS_MADDR)
+
+
+//2 REG_DW_I2C_IC_DATA_CMD
+#define BIT_IC_DATA_CMD_RESTART               	BIT(10)
+#define BIT_SHIFT_IC_DATA_CMD_RESTART         	10
+#define BIT_MASK_IC_DATA_CMD_RESTART          	0x1
+#define BIT_CTRL_IC_DATA_CMD_RESTART(x)       	(((x) & BIT_MASK_IC_DATA_CMD_RESTART) << BIT_SHIFT_IC_DATA_CMD_RESTART)
+
+#define BIT_IC_DATA_CMD_STOP                  	BIT(9)
+#define BIT_SHIFT_IC_DATA_CMD_STOP            	9
+#define BIT_MASK_IC_DATA_CMD_STOP             	0x1
+#define BIT_CTRL_IC_DATA_CMD_STOP(x)          	(((x) & BIT_MASK_IC_DATA_CMD_STOP) << BIT_SHIFT_IC_DATA_CMD_STOP)
+
+#define BIT_IC_DATA_CMD_CMD                   	BIT(8)
+#define BIT_SHIFT_IC_DATA_CMD_CMD             	8
+#define BIT_MASK_IC_DATA_CMD_CMD              	0x1
+#define BIT_CTRL_IC_DATA_CMD_CMD(x)           	(((x) & BIT_MASK_IC_DATA_CMD_CMD) << BIT_SHIFT_IC_DATA_CMD_CMD)
+
+
+#define BIT_SHIFT_IC_DATA_CMD_DAT 0
+#define BIT_MASK_IC_DATA_CMD_DAT 0xff
+#define BIT_IC_DATA_CMD_DAT(x)                	(((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
+#define BIT_CTRL_IC_DATA_CMD_DAT(x)           	(((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
+#define BIT_GET_IC_DATA_CMD_DAT(x)            	(((x) >> BIT_SHIFT_IC_DATA_CMD_DAT) & BIT_MASK_IC_DATA_CMD_DAT)
+
+
+//2 REG_DW_I2C_IC_SS_SCL_HCNT
+
+#define BIT_SHIFT_IC_SS_SCL_HCNT 0
+#define BIT_MASK_IC_SS_SCL_HCNT 0xffff
+#define BIT_IC_SS_SCL_HCNT(x)                 	(((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
+#define BIT_CTRL_IC_SS_SCL_HCNT(x)            	(((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
+#define BIT_GET_IC_SS_SCL_HCNT(x)             	(((x) >> BIT_SHIFT_IC_SS_SCL_HCNT) & BIT_MASK_IC_SS_SCL_HCNT)
+
+
+//2 REG_DW_I2C_IC_SS_SCL_LCNT
+
+#define BIT_SHIFT_IC_SS_SCL_LCNT 0
+#define BIT_MASK_IC_SS_SCL_LCNT 0xffff
+#define BIT_IC_SS_SCL_LCNT(x)                 	(((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
+#define BIT_CTRL_IC_SS_SCL_LCNT(x)            	(((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
+#define BIT_GET_IC_SS_SCL_LCNT(x)             	(((x) >> BIT_SHIFT_IC_SS_SCL_LCNT) & BIT_MASK_IC_SS_SCL_LCNT)
+
+
+//2 REG_DW_I2C_IC_FS_SCL_HCNT
+
+#define BIT_SHIFT_IC_FS_SCL_HCNT 0
+#define BIT_MASK_IC_FS_SCL_HCNT 0xffff
+#define BIT_IC_FS_SCL_HCNT(x)                 	(((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
+#define BIT_CTRL_IC_FS_SCL_HCNT(x)            	(((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
+#define BIT_GET_IC_FS_SCL_HCNT(x)             	(((x) >> BIT_SHIFT_IC_FS_SCL_HCNT) & BIT_MASK_IC_FS_SCL_HCNT)
+
+
+//2 REG_DW_I2C_IC_FS_SCL_LCNT
+
+#define BIT_SHIFT_IC_FS_SCL_LCNT 0
+#define BIT_MASK_IC_FS_SCL_LCNT 0xffff
+#define BIT_IC_FS_SCL_LCNT(x)                 	(((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
+#define BIT_CTRL_IC_FS_SCL_LCNT(x)            	(((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
+#define BIT_GET_IC_FS_SCL_LCNT(x)             	(((x) >> BIT_SHIFT_IC_FS_SCL_LCNT) & BIT_MASK_IC_FS_SCL_LCNT)
+
+
+//2 REG_DW_I2C_IC_HS_SCL_HCNT
+
+#define BIT_SHIFT_IC_HS_SCL_HCNT 0
+#define BIT_MASK_IC_HS_SCL_HCNT 0xffff
+#define BIT_IC_HS_SCL_HCNT(x)                 	(((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
+#define BIT_CTRL_IC_HS_SCL_HCNT(x)            	(((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
+#define BIT_GET_IC_HS_SCL_HCNT(x)             	(((x) >> BIT_SHIFT_IC_HS_SCL_HCNT) & BIT_MASK_IC_HS_SCL_HCNT)
+
+
+//2 REG_DW_I2C_IC_HS_SCL_LCNT
+
+#define BIT_SHIFT_IC_HS_SCL_LCNT 0
+#define BIT_MASK_IC_HS_SCL_LCNT 0xffff
+#define BIT_IC_HS_SCL_LCNT(x)                 	(((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
+#define BIT_CTRL_IC_HS_SCL_LCNT(x)            	(((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
+#define BIT_GET_IC_HS_SCL_LCNT(x)             	(((x) >> BIT_SHIFT_IC_HS_SCL_LCNT) & BIT_MASK_IC_HS_SCL_LCNT)
+
+
+//2 REG_DW_I2C_IC_INTR_STAT
+#define BIT_IC_INTR_STAT_R_GEN_CALL           	BIT(11)
+#define BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL     	11
+#define BIT_MASK_IC_INTR_STAT_R_GEN_CALL      	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_GEN_CALL(x)   	(((x) & BIT_MASK_IC_INTR_STAT_R_GEN_CALL) << BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL)
+
+#define BIT_IC_INTR_STAT_R_START_DET          	BIT(10)
+#define BIT_SHIFT_IC_INTR_STAT_R_START_DET    	10
+#define BIT_MASK_IC_INTR_STAT_R_START_DET     	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_START_DET(x)  	(((x) & BIT_MASK_IC_INTR_STAT_R_START_DET) << BIT_SHIFT_IC_INTR_STAT_R_START_DET)
+
+#define BIT_IC_INTR_STAT_R_STOP_DET           	BIT(9)
+#define BIT_SHIFT_IC_INTR_STAT_R_STOP_DET     	9
+#define BIT_MASK_IC_INTR_STAT_R_STOP_DET      	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_STOP_DET(x)   	(((x) & BIT_MASK_IC_INTR_STAT_R_STOP_DET) << BIT_SHIFT_IC_INTR_STAT_R_STOP_DET)
+
+#define BIT_IC_INTR_STAT_R_ACTIVITY           	BIT(8)
+#define BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY     	8
+#define BIT_MASK_IC_INTR_STAT_R_ACTIVITY      	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_ACTIVITY(x)   	(((x) & BIT_MASK_IC_INTR_STAT_R_ACTIVITY) << BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY)
+
+#define BIT_IC_INTR_STAT_R_RX_DONE            	BIT(7)
+#define BIT_SHIFT_IC_INTR_STAT_R_RX_DONE      	7
+#define BIT_MASK_IC_INTR_STAT_R_RX_DONE       	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_RX_DONE(x)    	(((x) & BIT_MASK_IC_INTR_STAT_R_RX_DONE) << BIT_SHIFT_IC_INTR_STAT_R_RX_DONE)
+
+#define BIT_IC_INTR_STAT_R_TX_ABRT            	BIT(6)
+#define BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT      	6
+#define BIT_MASK_IC_INTR_STAT_R_TX_ABRT       	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(x)    	(((x) & BIT_MASK_IC_INTR_STAT_R_TX_ABRT) << BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT)
+
+#define BIT_IC_INTR_STAT_R_RD_REQ             	BIT(5)
+#define BIT_SHIFT_IC_INTR_STAT_R_RD_REQ       	5
+#define BIT_MASK_IC_INTR_STAT_R_RD_REQ        	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_RD_REQ(x)     	(((x) & BIT_MASK_IC_INTR_STAT_R_RD_REQ) << BIT_SHIFT_IC_INTR_STAT_R_RD_REQ)
+
+#define BIT_IC_INTR_STAT_R_TX_EMPTY           	BIT(4)
+#define BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY     	4
+#define BIT_MASK_IC_INTR_STAT_R_TX_EMPTY      	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_TX_EMPTY(x)   	(((x) & BIT_MASK_IC_INTR_STAT_R_TX_EMPTY) << BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY)
+
+#define BIT_IC_INTR_STAT_R_TX_OVER            	BIT(3)
+#define BIT_SHIFT_IC_INTR_STAT_R_TX_OVER      	3
+#define BIT_MASK_IC_INTR_STAT_R_TX_OVER       	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_TX_OVER(x)    	(((x) & BIT_MASK_IC_INTR_STAT_R_TX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_TX_OVER)
+
+#define BIT_IC_INTR_STAT_R_RX_FULL            	BIT(2)
+#define BIT_SHIFT_IC_INTR_STAT_R_RX_FULL      	2
+#define BIT_MASK_IC_INTR_STAT_R_RX_FULL       	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_RX_FULL(x)    	(((x) & BIT_MASK_IC_INTR_STAT_R_RX_FULL) << BIT_SHIFT_IC_INTR_STAT_R_RX_FULL)
+
+#define BIT_IC_INTR_STAT_R_RX_OVER            	BIT(1)
+#define BIT_SHIFT_IC_INTR_STAT_R_RX_OVER      	1
+#define BIT_MASK_IC_INTR_STAT_R_RX_OVER       	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_RX_OVER(x)    	(((x) & BIT_MASK_IC_INTR_STAT_R_RX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_RX_OVER)
+
+#define BIT_IC_INTR_STAT_R_RX_UNDER           	BIT(0)
+#define BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER     	0
+#define BIT_MASK_IC_INTR_STAT_R_RX_UNDER      	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(x)   	(((x) & BIT_MASK_IC_INTR_STAT_R_RX_UNDER) << BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER)
+
+
+//2 REG_DW_I2C_IC_INTR_MASK
+#define BIT_IC_INTR_MASK_M_GEN_CALL           	BIT(11)
+#define BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL     	11
+#define BIT_MASK_IC_INTR_MASK_M_GEN_CALL      	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_GEN_CALL(x)   	(((x) & BIT_MASK_IC_INTR_MASK_M_GEN_CALL) << BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL)
+
+#define BIT_IC_INTR_MASK_M_START_DET          	BIT(10)
+#define BIT_SHIFT_IC_INTR_MASK_M_START_DET    	10
+#define BIT_MASK_IC_INTR_MASK_M_START_DET     	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_START_DET(x)  	(((x) & BIT_MASK_IC_INTR_MASK_M_START_DET) << BIT_SHIFT_IC_INTR_MASK_M_START_DET)
+
+#define BIT_IC_INTR_MASK_M_STOP_DET           	BIT(9)
+#define BIT_SHIFT_IC_INTR_MASK_M_STOP_DET     	9
+#define BIT_MASK_IC_INTR_MASK_M_STOP_DET      	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_STOP_DET(x)   	(((x) & BIT_MASK_IC_INTR_MASK_M_STOP_DET) << BIT_SHIFT_IC_INTR_MASK_M_STOP_DET)
+
+#define BIT_IC_INTR_MASK_M_ACTIVITY           	BIT(8)
+#define BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY     	8
+#define BIT_MASK_IC_INTR_MASK_M_ACTIVITY      	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_ACTIVITY(x)   	(((x) & BIT_MASK_IC_INTR_MASK_M_ACTIVITY) << BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY)
+
+#define BIT_IC_INTR_MASK_M_RX_DONE            	BIT(7)
+#define BIT_SHIFT_IC_INTR_MASK_M_RX_DONE      	7
+#define BIT_MASK_IC_INTR_MASK_M_RX_DONE       	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_RX_DONE(x)    	(((x) & BIT_MASK_IC_INTR_MASK_M_RX_DONE) << BIT_SHIFT_IC_INTR_MASK_M_RX_DONE)
+
+#define BIT_IC_INTR_MASK_M_TX_ABRT            	BIT(6)
+#define BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT      	6
+#define BIT_MASK_IC_INTR_MASK_M_TX_ABRT       	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_TX_ABRT(x)    	(((x) & BIT_MASK_IC_INTR_MASK_M_TX_ABRT) << BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT)
+
+#define BIT_IC_INTR_MASK_M_RD_REQ             	BIT(5)
+#define BIT_SHIFT_IC_INTR_MASK_M_RD_REQ       	5
+#define BIT_MASK_IC_INTR_MASK_M_RD_REQ        	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_RD_REQ(x)     	(((x) & BIT_MASK_IC_INTR_MASK_M_RD_REQ) << BIT_SHIFT_IC_INTR_MASK_M_RD_REQ)
+
+#define BIT_IC_INTR_MASK_M_TX_EMPTY           	BIT(4)
+#define BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY     	4
+#define BIT_MASK_IC_INTR_MASK_M_TX_EMPTY      	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_TX_EMPTY(x)   	(((x) & BIT_MASK_IC_INTR_MASK_M_TX_EMPTY) << BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY)
+
+#define BIT_IC_INTR_MASK_M_TX_OVER            	BIT(3)
+#define BIT_SHIFT_IC_INTR_MASK_M_TX_OVER      	3
+#define BIT_MASK_IC_INTR_MASK_M_TX_OVER       	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_TX_OVER(x)    	(((x) & BIT_MASK_IC_INTR_MASK_M_TX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_TX_OVER)
+
+#define BIT_IC_INTR_MASK_M_RX_FULL            	BIT(2)
+#define BIT_SHIFT_IC_INTR_MASK_M_RX_FULL      	2
+#define BIT_MASK_IC_INTR_MASK_M_RX_FULL       	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_RX_FULL(x)    	(((x) & BIT_MASK_IC_INTR_MASK_M_RX_FULL) << BIT_SHIFT_IC_INTR_MASK_M_RX_FULL)
+
+#define BIT_IC_INTR_MASK_M_RX_OVER            	BIT(1)
+#define BIT_SHIFT_IC_INTR_MASK_M_RX_OVER      	1
+#define BIT_MASK_IC_INTR_MASK_M_RX_OVER       	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_RX_OVER(x)    	(((x) & BIT_MASK_IC_INTR_MASK_M_RX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_RX_OVER)
+
+#define BIT_IC_INTR_MASK_M_RX_UNDER           	BIT(0)
+#define BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER     	0
+#define BIT_MASK_IC_INTR_MASK_M_RX_UNDER      	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_RX_UNDER(x)   	(((x) & BIT_MASK_IC_INTR_MASK_M_RX_UNDER) << BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER)
+
+
+//2 REG_DW_I2C_IC_RAW_INTR_STAT
+#define BIT_IC_RAW_INTR_STAT_GEN_CALL         	BIT(11)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL   	11
+#define BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL    	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_GEN_CALL(x) 	(((x) & BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL) << BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL)
+
+#define BIT_IC_RAW_INTR_STAT_START_DET        	BIT(10)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_START_DET  	10
+#define BIT_MASK_IC_RAW_INTR_STAT_START_DET   	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_START_DET(x)	(((x) & BIT_MASK_IC_RAW_INTR_STAT_START_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_START_DET)
+
+#define BIT_IC_RAW_INTR_STAT_STOP_DET         	BIT(9)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET   	9
+#define BIT_MASK_IC_RAW_INTR_STAT_STOP_DET    	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_STOP_DET(x) 	(((x) & BIT_MASK_IC_RAW_INTR_STAT_STOP_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET)
+
+#define BIT_IC_RAW_INTR_STAT_ACTIVITY         	BIT(8)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY   	8
+#define BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY    	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_ACTIVITY(x) 	(((x) & BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY) << BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY)
+
+#define BIT_IC_RAW_INTR_STAT_RX_DONE          	BIT(7)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE    	7
+#define BIT_MASK_IC_RAW_INTR_STAT_RX_DONE     	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_RX_DONE(x)  	(((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_DONE) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE)
+
+#define BIT_IC_RAW_INTR_STAT_TX_ABRT          	BIT(6)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT    	6
+#define BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT     	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_TX_ABRT(x)  	(((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT)
+
+#define BIT_IC_RAW_INTR_STAT_RD_REQ           	BIT(5)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ     	5
+#define BIT_MASK_IC_RAW_INTR_STAT_RD_REQ      	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_RD_REQ(x)   	(((x) & BIT_MASK_IC_RAW_INTR_STAT_RD_REQ) << BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ)
+
+#define BIT_IC_RAW_INTR_STAT_TX_EMPTY         	BIT(4)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY   	4
+#define BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY    	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_TX_EMPTY(x) 	(((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY)
+
+#define BIT_IC_RAW_INTR_STAT_TX_OVER          	BIT(3)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER    	3
+#define BIT_MASK_IC_RAW_INTR_STAT_TX_OVER     	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_TX_OVER(x)  	(((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER)
+
+#define BIT_IC_RAW_INTR_STAT_RX_FULL          	BIT(2)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL    	2
+#define BIT_MASK_IC_RAW_INTR_STAT_RX_FULL     	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_RX_FULL(x)  	(((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_FULL) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL)
+
+#define BIT_IC_RAW_INTR_STAT_RX_OVER          	BIT(1)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER    	1
+#define BIT_MASK_IC_RAW_INTR_STAT_RX_OVER     	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_RX_OVER(x)  	(((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER)
+
+#define BIT_IC_RAW_INTR_STAT_RX_UNDER         	BIT(0)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER   	0
+#define BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER    	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_RX_UNDER(x) 	(((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER)
+
+
+//2 REG_DW_I2C_IC_RX_TL
+
+#define BIT_SHIFT_IC_RX_TL 0
+#define BIT_MASK_IC_RX_TL 0xff
+#define BIT_IC_RX_TL(x)                       	(((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
+#define BIT_CTRL_IC_RX_TL(x)                  	(((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
+#define BIT_GET_IC_RX_TL(x)                   	(((x) >> BIT_SHIFT_IC_RX_TL) & BIT_MASK_IC_RX_TL)
+
+
+//2 REG_DW_I2C_IC_TX_TL
+
+#define BIT_SHIFT_IC_TX_TL 0
+#define BIT_MASK_IC_TX_TL 0xff
+#define BIT_IC_TX_TL(x)                       	(((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
+#define BIT_CTRL_IC_TX_TL(x)                  	(((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
+#define BIT_GET_IC_TX_TL(x)                   	(((x) >> BIT_SHIFT_IC_TX_TL) & BIT_MASK_IC_TX_TL)
+
+
+//2 REG_DW_I2C_IC_CLR_INTR
+#define BIT_IC_CLR_INTR                       	BIT(0)
+#define BIT_SHIFT_IC_CLR_INTR                 	0
+#define BIT_MASK_IC_CLR_INTR                  	0x1
+#define BIT_CTRL_IC_CLR_INTR(x)               	(((x) & BIT_MASK_IC_CLR_INTR) << BIT_SHIFT_IC_CLR_INTR)
+
+
+//2 REG_DW_I2C_IC_CLR_RX_UNDER
+#define BIT_IC_CLR_RX_UNDER                   	BIT(0)
+#define BIT_SHIFT_IC_CLR_RX_UNDER             	0
+#define BIT_MASK_IC_CLR_RX_UNDER              	0x1
+#define BIT_CTRL_IC_CLR_RX_UNDER(x)           	(((x) & BIT_MASK_IC_CLR_RX_UNDER) << BIT_SHIFT_IC_CLR_RX_UNDER)
+
+
+//2 REG_DW_I2C_IC_CLR_RX_OVER
+#define BIT_IC_CLR_RX_OVER                    	BIT(0)
+#define BIT_SHIFT_IC_CLR_RX_OVER              	0
+#define BIT_MASK_IC_CLR_RX_OVER               	0x1
+#define BIT_CTRL_IC_CLR_RX_OVER(x)            	(((x) & BIT_MASK_IC_CLR_RX_OVER) << BIT_SHIFT_IC_CLR_RX_OVER)
+
+
+//2 REG_DW_I2C_IC_CLR_TX_OVER
+#define BIT_IC_CLR_TX_OVER                    	BIT(0)
+#define BIT_SHIFT_IC_CLR_TX_OVER              	0
+#define BIT_MASK_IC_CLR_TX_OVER               	0x1
+#define BIT_CTRL_IC_CLR_TX_OVER(x)            	(((x) & BIT_MASK_IC_CLR_TX_OVER) << BIT_SHIFT_IC_CLR_TX_OVER)
+
+
+//2 REG_DW_I2C_IC_CLR_RD_REQ
+#define BIT_IC_CLR_RD_REQ                     	BIT(0)
+#define BIT_SHIFT_IC_CLR_RD_REQ               	0
+#define BIT_MASK_IC_CLR_RD_REQ                	0x1
+#define BIT_CTRL_IC_CLR_RD_REQ(x)             	(((x) & BIT_MASK_IC_CLR_RD_REQ) << BIT_SHIFT_IC_CLR_RD_REQ)
+
+
+//2 REG_DW_I2C_IC_CLR_TX_ABRT
+#define BIT_CLR_RD_REQ                        	BIT(0)
+#define BIT_SHIFT_CLR_RD_REQ                  	0
+#define BIT_MASK_CLR_RD_REQ                   	0x1
+#define BIT_CTRL_CLR_RD_REQ(x)                	(((x) & BIT_MASK_CLR_RD_REQ) << BIT_SHIFT_CLR_RD_REQ)
+
+
+//2 REG_DW_I2C_IC_CLR_RX_DONE
+#define BIT_IC_CLR_RX_DONE                    	BIT(0)
+#define BIT_SHIFT_IC_CLR_RX_DONE              	0
+#define BIT_MASK_IC_CLR_RX_DONE               	0x1
+#define BIT_CTRL_IC_CLR_RX_DONE(x)            	(((x) & BIT_MASK_IC_CLR_RX_DONE) << BIT_SHIFT_IC_CLR_RX_DONE)
+
+
+//2 REG_DW_I2C_IC_CLR_ACTIVITY
+#define BIT_IC_CLR_ACTIVITY                   	BIT(0)
+#define BIT_SHIFT_IC_CLR_ACTIVITY             	0
+#define BIT_MASK_IC_CLR_ACTIVITY              	0x1
+#define BIT_CTRL_IC_CLR_ACTIVITY(x)           	(((x) & BIT_MASK_IC_CLR_ACTIVITY) << BIT_SHIFT_IC_CLR_ACTIVITY)
+
+
+//2 REG_DW_I2C_IC_CLR_STOP_DET
+#define BIT_IC_CLR_STOP_DET                   	BIT(0)
+#define BIT_SHIFT_IC_CLR_STOP_DET             	0
+#define BIT_MASK_IC_CLR_STOP_DET              	0x1
+#define BIT_CTRL_IC_CLR_STOP_DET(x)           	(((x) & BIT_MASK_IC_CLR_STOP_DET) << BIT_SHIFT_IC_CLR_STOP_DET)
+
+
+//2 REG_DW_I2C_IC_CLR_START_DET
+#define BIT_IC_CLR_START_DET                  	BIT(0)
+#define BIT_SHIFT_IC_CLR_START_DET            	0
+#define BIT_MASK_IC_CLR_START_DET             	0x1
+#define BIT_CTRL_IC_CLR_START_DET(x)          	(((x) & BIT_MASK_IC_CLR_START_DET) << BIT_SHIFT_IC_CLR_START_DET)
+
+
+//2 REG_DW_I2C_IC_CLR_GEN_CALL
+#define BIT_IC_CLR_GEN_CALL                   	BIT(0)
+#define BIT_SHIFT_IC_CLR_GEN_CALL             	0
+#define BIT_MASK_IC_CLR_GEN_CALL              	0x1
+#define BIT_CTRL_IC_CLR_GEN_CALL(x)           	(((x) & BIT_MASK_IC_CLR_GEN_CALL) << BIT_SHIFT_IC_CLR_GEN_CALL)
+
+
+//2 REG_DW_I2C_IC_ENABLE
+#define BIT_IC_ENABLE                         	BIT(0)
+#define BIT_SHIFT_IC_ENABLE                   	0
+#define BIT_MASK_IC_ENABLE                    	0x1
+#define BIT_CTRL_IC_ENABLE(x)                 	(((x) & BIT_MASK_IC_ENABLE) << BIT_SHIFT_IC_ENABLE)
+
+
+//2 REG_DW_I2C_IC_STATUS
+#define BIT_IC_STATUS_SLV_ACTIVITY            	BIT(6)
+#define BIT_SHIFT_IC_STATUS_SLV_ACTIVITY      	6
+#define BIT_MASK_IC_STATUS_SLV_ACTIVITY       	0x1
+#define BIT_CTRL_IC_STATUS_SLV_ACTIVITY(x)    	(((x) & BIT_MASK_IC_STATUS_SLV_ACTIVITY) << BIT_SHIFT_IC_STATUS_SLV_ACTIVITY)
+
+#define BIT_IC_STATUS_MST_ACTIVITY            	BIT(5)
+#define BIT_SHIFT_IC_STATUS_MST_ACTIVITY      	5
+#define BIT_MASK_IC_STATUS_MST_ACTIVITY       	0x1
+#define BIT_CTRL_IC_STATUS_MST_ACTIVITY(x)    	(((x) & BIT_MASK_IC_STATUS_MST_ACTIVITY) << BIT_SHIFT_IC_STATUS_MST_ACTIVITY)
+
+#define BIT_IC_STATUS_RFF                     	BIT(4)
+#define BIT_SHIFT_IC_STATUS_RFF               	4
+#define BIT_MASK_IC_STATUS_RFF                	0x1
+#define BIT_CTRL_IC_STATUS_RFF(x)             	(((x) & BIT_MASK_IC_STATUS_RFF) << BIT_SHIFT_IC_STATUS_RFF)
+
+#define BIT_IC_STATUS_RFNE                    	BIT(3)
+#define BIT_SHIFT_IC_STATUS_RFNE              	3
+#define BIT_MASK_IC_STATUS_RFNE               	0x1
+#define BIT_CTRL_IC_STATUS_RFNE(x)            	(((x) & BIT_MASK_IC_STATUS_RFNE) << BIT_SHIFT_IC_STATUS_RFNE)
+
+#define BIT_IC_STATUS_TFE                     	BIT(2)
+#define BIT_SHIFT_IC_STATUS_TFE               	2
+#define BIT_MASK_IC_STATUS_TFE                	0x1
+#define BIT_CTRL_IC_STATUS_TFE(x)             	(((x) & BIT_MASK_IC_STATUS_TFE) << BIT_SHIFT_IC_STATUS_TFE)
+
+#define BIT_IC_STATUS_TFNF                    	BIT(1)
+#define BIT_SHIFT_IC_STATUS_TFNF              	1
+#define BIT_MASK_IC_STATUS_TFNF               	0x1
+#define BIT_CTRL_IC_STATUS_TFNF(x)            	(((x) & BIT_MASK_IC_STATUS_TFNF) << BIT_SHIFT_IC_STATUS_TFNF)
+
+#define BIT_IC_STATUS_ACTIVITY                	BIT(0)
+#define BIT_SHIFT_IC_STATUS_ACTIVITY          	0
+#define BIT_MASK_IC_STATUS_ACTIVITY           	0x1
+#define BIT_CTRL_IC_STATUS_ACTIVITY(x)        	(((x) & BIT_MASK_IC_STATUS_ACTIVITY) << BIT_SHIFT_IC_STATUS_ACTIVITY)
+
+
+//2 REG_DW_I2C_IC_TXFLR
+
+#define BIT_SHIFT_IC_TXFLR 0
+#define BIT_MASK_IC_TXFLR 0x3f
+#define BIT_IC_TXFLR(x)                       	(((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
+#define BIT_CTRL_IC_TXFLR(x)                  	(((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
+#define BIT_GET_IC_TXFLR(x)                   	(((x) >> BIT_SHIFT_IC_TXFLR) & BIT_MASK_IC_TXFLR)
+
+
+//2 REG_DW_I2C_IC_RXFLR
+
+#define BIT_SHIFT_IC_RXFLR 0
+#define BIT_MASK_IC_RXFLR 0x1f
+#define BIT_IC_RXFLR(x)                       	(((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
+#define BIT_CTRL_IC_RXFLR(x)                  	(((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
+#define BIT_GET_IC_RXFLR(x)                   	(((x) >> BIT_SHIFT_IC_RXFLR) & BIT_MASK_IC_RXFLR)
+
+
+//2 REG_DW_I2C_IC_SDA_HOLD
+
+#define BIT_SHIFT_IC_SDA_HOLD 0
+#define BIT_MASK_IC_SDA_HOLD 0xffff
+#define BIT_IC_SDA_HOLD(x)                    	(((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
+#define BIT_CTRL_IC_SDA_HOLD(x)               	(((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
+#define BIT_GET_IC_SDA_HOLD(x)                	(((x) >> BIT_SHIFT_IC_SDA_HOLD) & BIT_MASK_IC_SDA_HOLD)
+
+
+//2 REG_DW_I2C_IC_TX_ABRT_SOURCE
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 	BIT(15)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX	15
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST	BIT(14)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST	14
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO	BIT(13)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO	13
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO)
+
+#define BIT_IC_TX_ABRT_SOURCE_ARB_LOST        	BIT(12)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST  	12
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST   	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ARB_LOST(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 	BIT(11)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS	11
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT	BIT(10)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT	10
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT	BIT(9)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT	9
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 	BIT(8)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT	8
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET	BIT(7)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET	7
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET  	BIT(6)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET	6
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 	BIT(5)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ	5
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK	BIT(4)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK	4
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK	BIT(3)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK	3
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK	BIT(2)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK	2
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK	BIT(1)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK	1
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK	BIT(0)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK	0
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK)
+
+
+//2 REG_DW_I2C_IC_SLV_DATA_NACK_ONLY
+#define BIT_IC_SLV_DATA_NACK_ONLY             	BIT(0)
+#define BIT_SHIFT_IC_SLV_DATA_NACK_ONLY       	0
+#define BIT_MASK_IC_SLV_DATA_NACK_ONLY        	0x1
+#define BIT_CTRL_IC_SLV_DATA_NACK_ONLY(x)     	(((x) & BIT_MASK_IC_SLV_DATA_NACK_ONLY) << BIT_SHIFT_IC_SLV_DATA_NACK_ONLY)
+
+
+//2 REG_DW_I2C_IC_DMA_CR
+#define BIT_IC_DMA_CR_TDMAE                   	BIT(1)
+#define BIT_SHIFT_IC_DMA_CR_TDMAE             	1
+#define BIT_MASK_IC_DMA_CR_TDMAE              	0x1
+#define BIT_CTRL_IC_DMA_CR_TDMAE(x)           	(((x) & BIT_MASK_IC_DMA_CR_TDMAE) << BIT_SHIFT_IC_DMA_CR_TDMAE)
+
+#define BIT_IC_DMA_CR_RDMAE                   	BIT(0)
+#define BIT_SHIFT_IC_DMA_CR_RDMAE             	0
+#define BIT_MASK_IC_DMA_CR_RDMAE              	0x1
+#define BIT_CTRL_IC_DMA_CR_RDMAE(x)           	(((x) & BIT_MASK_IC_DMA_CR_RDMAE) << BIT_SHIFT_IC_DMA_CR_RDMAE)
+
+
+//2 REG_DW_I2C_IC_DMA_TDLR
+
+#define BIT_SHIFT_IC_DMA_TDLR_DMATDL 0
+#define BIT_MASK_IC_DMA_TDLR_DMATDL 0x1f
+#define BIT_IC_DMA_TDLR_DMATDL(x)             	(((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
+#define BIT_CTRL_IC_DMA_TDLR_DMATDL(x)        	(((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
+#define BIT_GET_IC_DMA_TDLR_DMATDL(x)         	(((x) >> BIT_SHIFT_IC_DMA_TDLR_DMATDL) & BIT_MASK_IC_DMA_TDLR_DMATDL)
+
+
+//2 REG_DW_I2C_IC_DMA_RDLR
+
+#define BIT_SHIFT_IC_DMA_RDLR_DMARDL 0
+#define BIT_MASK_IC_DMA_RDLR_DMARDL 0xf
+#define BIT_IC_DMA_RDLR_DMARDL(x)             	(((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
+#define BIT_CTRL_IC_DMA_RDLR_DMARDL(x)        	(((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
+#define BIT_GET_IC_DMA_RDLR_DMARDL(x)         	(((x) >> BIT_SHIFT_IC_DMA_RDLR_DMARDL) & BIT_MASK_IC_DMA_RDLR_DMARDL)
+
+
+//2 REG_DW_I2C_IC_SDA_SETUP
+
+#define BIT_SHIFT_IC_SDA_SETUP 0
+#define BIT_MASK_IC_SDA_SETUP 0xff
+#define BIT_IC_SDA_SETUP(x)                   	(((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
+#define BIT_CTRL_IC_SDA_SETUP(x)              	(((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
+#define BIT_GET_IC_SDA_SETUP(x)               	(((x) >> BIT_SHIFT_IC_SDA_SETUP) & BIT_MASK_IC_SDA_SETUP)
+
+
+//2 REG_DW_I2C_IC_ACK_GENERAL_CALL
+#define BIT_IC_ACK_GENERAL_CALL               	BIT(0)
+#define BIT_SHIFT_IC_ACK_GENERAL_CALL         	0
+#define BIT_MASK_IC_ACK_GENERAL_CALL          	0x1
+#define BIT_CTRL_IC_ACK_GENERAL_CALL(x)       	(((x) & BIT_MASK_IC_ACK_GENERAL_CALL) << BIT_SHIFT_IC_ACK_GENERAL_CALL)
+
+
+//2 REG_DW_I2C_IC_ENABLE_STATUS
+#define BIT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 	BIT(2)
+#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST	2
+#define BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST	0x1
+#define BIT_CTRL_IC_ENABLE_STATUS_SLV_RX_DATA_LOST(x)	(((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST)
+
+#define BIT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY	BIT(1)
+#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY	1
+#define BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY	0x1
+#define BIT_CTRL_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY(x)	(((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY)
+
+#define BIT_IC_ENABLE_STATUS_IC_EN            	BIT(0)
+#define BIT_SHIFT_IC_ENABLE_STATUS_IC_EN      	0
+#define BIT_MASK_IC_ENABLE_STATUS_IC_EN       	0x1
+#define BIT_CTRL_IC_ENABLE_STATUS_IC_EN(x)    	(((x) & BIT_MASK_IC_ENABLE_STATUS_IC_EN) << BIT_SHIFT_IC_ENABLE_STATUS_IC_EN)
+
+
+//2 REG_DW_I2C_IC_COMP_PARAM_1
+
+#define BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 16
+#define BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 0xff
+#define BIT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
+#define BIT_CTRL_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
+#define BIT_GET_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x)	(((x) >> BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
+
+
+#define BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 8
+#define BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 0xff
+#define BIT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
+#define BIT_CTRL_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
+#define BIT_GET_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x)	(((x) >> BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
+
+#define BIT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS	BIT(7)
+#define BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS	7
+#define BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS	0x1
+#define BIT_CTRL_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) << BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS)
+
+#define BIT_IC_COMP_PARAM_1_HAS_DMA           	BIT(6)
+#define BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA     	6
+#define BIT_MASK_IC_COMP_PARAM_1_HAS_DMA      	0x1
+#define BIT_CTRL_IC_COMP_PARAM_1_HAS_DMA(x)   	(((x) & BIT_MASK_IC_COMP_PARAM_1_HAS_DMA) << BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA)
+
+#define BIT_IC_COMP_PARAM_1_INTR_IO           	BIT(5)
+#define BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO     	5
+#define BIT_MASK_IC_COMP_PARAM_1_INTR_IO      	0x1
+#define BIT_CTRL_IC_COMP_PARAM_1_INTR_IO(x)   	(((x) & BIT_MASK_IC_COMP_PARAM_1_INTR_IO) << BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO)
+
+#define BIT_IC_COMP_PARAM_1_HC_COUNT_VALUES   	BIT(4)
+#define BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES	4
+#define BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES	0x1
+#define BIT_CTRL_IC_COMP_PARAM_1_HC_COUNT_VALUES(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES) << BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES)
+
+
+#define BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE 2
+#define BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE 0x3
+#define BIT_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) 	(((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
+#define BIT_CTRL_IC_COMP_PARAM_1_MAX_SPEED_MODE(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
+#define BIT_GET_IC_COMP_PARAM_1_MAX_SPEED_MODE(x)	(((x) >> BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE)
+
+
+#define BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH 0
+#define BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH 0x3
+#define BIT_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) 	(((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
+#define BIT_CTRL_IC_COMP_PARAM_1_APB_DATA_WIDTH(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
+#define BIT_GET_IC_COMP_PARAM_1_APB_DATA_WIDTH(x)	(((x) >> BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH)
+
+
+//2 REG_DW_I2C_IC_COMP_VERSION
+
+#define BIT_SHIFT_IC_COMP_VERSION 0
+#define BIT_MASK_IC_COMP_VERSION 0xffffffffL
+#define BIT_IC_COMP_VERSION(x)                	(((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
+#define BIT_CTRL_IC_COMP_VERSION(x)           	(((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
+#define BIT_GET_IC_COMP_VERSION(x)            	(((x) >> BIT_SHIFT_IC_COMP_VERSION) & BIT_MASK_IC_COMP_VERSION)
+
+
+//2 REG_DW_I2C_IC_COMP_TYPE
+
+#define BIT_SHIFT_IC_COMP_TYPE 0
+#define BIT_MASK_IC_COMP_TYPE 0xffffffffL
+#define BIT_IC_COMP_TYPE(x)                   	(((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
+#define BIT_CTRL_IC_COMP_TYPE(x)              	(((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
+#define BIT_GET_IC_COMP_TYPE(x)               	(((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE)
+
+//======================== Register Address Definition ========================
+#define REG_DW_I2C_IC_CON 0x0000
+#define REG_DW_I2C_IC_TAR 0x0004
+#define REG_DW_I2C_IC_SAR 0x0008
+#define REG_DW_I2C_IC_HS_MADDR 0x000C
+#define REG_DW_I2C_IC_DATA_CMD 0x0010
+#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014
+#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018
+#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C
+#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020
+#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024
+#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028
+#define REG_DW_I2C_IC_INTR_STAT 0x002C
+#define REG_DW_I2C_IC_INTR_MASK 0x0030
+#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034
+#define REG_DW_I2C_IC_RX_TL 0x0038
+#define REG_DW_I2C_IC_TX_TL 0x003C
+#define REG_DW_I2C_IC_CLR_INTR 0x0040
+#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044
+#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048
+#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C
+#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050
+#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054
+#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058
+#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C
+#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060
+#define REG_DW_I2C_IC_CLR_START_DET 0x0064
+#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068
+#define REG_DW_I2C_IC_ENABLE 0x006C
+#define REG_DW_I2C_IC_STATUS 0x0070
+#define REG_DW_I2C_IC_TXFLR 0x0074
+#define REG_DW_I2C_IC_RXFLR 0x0078
+#define REG_DW_I2C_IC_SDA_HOLD 0x007C
+#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080
+#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084
+#define REG_DW_I2C_IC_DMA_CR 0x0088
+#define REG_DW_I2C_IC_DMA_TDLR 0x008C
+#define REG_DW_I2C_IC_DMA_RDLR 0x0090
+#define REG_DW_I2C_IC_SDA_SETUP 0x0094
+#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098
+#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C
+#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4
+#define REG_DW_I2C_IC_COMP_VERSION 0x00F8
+#define REG_DW_I2C_IC_COMP_TYPE 0x00FC
+
+//======================================================
+// I2C related enumeration
+// I2C Address Mode
+typedef enum _I2C_ADDR_MODE_   {
+    I2C_ADDR_7BIT   =   0,
+    I2C_ADDR_10BIT  =   1,  
+}I2C_ADDR_MODE,*PI2C_ADDR_MODE;
+
+// I2C Speed Mode
+typedef enum _I2C_SPD_MODE_   {
+    I2C_SS_MODE     =   1,
+    I2C_FS_MODE     =   2,
+    I2C_HS_MODE     =   3,
+}I2C_SPD_MODE,*PI2C_SPD_MODE;
+
+//I2C Timing Parameters
+#define I2C_SS_MIN_SCL_HTIME    4000    //the unit is ns.
+#define I2C_SS_MIN_SCL_LTIME    4700    //the unit is ns.
+
+#define I2C_FS_MIN_SCL_HTIME    600     //the unit is ns.
+#define I2C_FS_MIN_SCL_LTIME    1300    //the unit is ns.
+
+#define I2C_HS_MIN_SCL_HTIME_100    60      //the unit is ns, with bus loading = 100pf
+#define I2C_HS_MIN_SCL_LTIME_100    120     //the unit is ns., with bus loading = 100pf
+
+#define I2C_HS_MIN_SCL_HTIME_400    160     //the unit is ns, with bus loading = 400pf
+#define I2C_HS_MIN_SCL_LTIME_400    320     //the unit is ns., with bus loading = 400pf
+
+
+//======================================================
+//I2C Essential functions and macros
+_LONG_CALL_ VOID HalI2CWrite32(IN u8 I2CIdx, IN u8 I2CReg, IN u32 I2CVal);
+_LONG_CALL_ u32 HalI2CRead32(IN u8 I2CIdx, IN u8 I2CReg);
+
+#define HAL_I2C_WRITE32(I2CIdx, addr, value)    HalI2CWrite32(I2CIdx,addr,value)
+#define HAL_I2C_READ32(I2CIdx, addr)            HalI2CRead32(I2CIdx,addr)
+
+// Rtl8195a I2C function prototypes
+_LONG_CALL_ HAL_Status HalI2CEnableRtl8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CInit8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CDeInit8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CSendRtl8195a(IN VOID *Data);
+_LONG_CALL_ u8 HalI2CReceiveRtl8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CIntrCtrl8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CClrIntrRtl8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CClrAllIntrRtl8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data);
+_LONG_CALL_ u32 HalI2CReadRegRtl8195a(IN VOID *Data, IN u8 I2CReg);
+_LONG_CALL_ HAL_Status HalI2CWriteRegRtl8195a(IN VOID *Data, IN u8 I2CReg, IN u32 RegVal);
+_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data);
+
+//Rtl8195a I2C V02 function prototype
+_LONG_CALL_ HAL_Status HalI2CSendRtl8195aV02(IN  VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195aV02(IN  VOID *Data);
+//Rtl8195a I2C V02 function prototype  END
+
+#endif

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2s.h

@@ -0,0 +1,617 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_I2S_H_
+#define _RTL8195A_I2S_H_
+
+
+//=============== Register Bit Field Definition ====================
+// REG_I2S_CONTROL
+#define BIT_CTLX_I2S_EN                         BIT(0)
+#define BIT_SHIFT_CTLX_I2S_EN                   0
+#define BIT_MASK_CTLX_I2S_EN                    0x1
+#define BIT_CTRL_CTLX_I2S_EN(x)                 (((x) & BIT_MASK_CTLX_I2S_EN) << BIT_SHIFT_CTLX_I2S_EN)
+
+#define BIT_SHIFT_CTLX_I2S_TRX_ACT              1
+#define BIT_MASK_CTLX_I2S_TRX_ACT               0x3
+#define BIT_CTRL_CTLX_I2S_TRX_ACT(x)            (((x) & BIT_MASK_CTLX_I2S_TRX_ACT) << BIT_SHIFT_CTLX_I2S_TRX_ACT)
+#define BIT_GET_CTLX_I2S_TRX_ACT(x)             (((x) >> BIT_SHIFT_CTLX_I2S_TRX_ACT) & BIT_MASK_CTLX_I2S_TRX_ACT)
+
+#define BIT_SHIFT_CTLX_I2S_CH_NUM               3
+#define BIT_MASK_CTLX_I2S_CH_NUM                0x3
+#define BIT_CTRL_CTLX_I2S_CH_NUM(x)             (((x) & BIT_MASK_CTLX_I2S_CH_NUM) << BIT_SHIFT_CTLX_I2S_CH_NUM)
+#define BIT_GET_CTLX_I2S_CH_NUM(x)              (((x) >> BIT_SHIFT_CTLX_I2S_CH_NUM) & BIT_MASK_CTLX_I2S_CH_NUM)
+
+#define BIT_CTLX_I2S_WL                         BIT(6)
+#define BIT_SHIFT_CTLX_I2S_WL                   6
+#define BIT_MASK_CTLX_I2S_WL                    0x1
+#define BIT_CTRL_CTLX_I2S_WL(x)                 (((x) & BIT_MASK_CTLX_I2S_WL) << BIT_SHIFT_CTLX_I2S_WL)
+
+#define BIT_CTLX_I2S_LRSWAP                     BIT(10)
+#define BIT_SHIFT_CTLX_I2S_LRSWAP               10
+#define BIT_MASK_CTLX_I2S_LRSWAP                0x1
+#define BIT_CTRL_CTLX_I2S_LRSWAP(x)             (((x) & BIT_MASK_CTLX_I2S_LRSWAP) << BIT_SHIFT_CTLX_I2S_LRSWAP)
+
+#define BIT_CTLX_I2S_SCK_INV                    BIT(11)
+#define BIT_SHIFT_CTLX_I2S_SCK_INV              11
+#define BIT_MASK_CTLX_I2S_SCK_INV               0x1
+#define BIT_CTRL_CTLX_I2S_SCK_INV(x)            (((x) & BIT_MASK_CTLX_I2S_SCK_INV) << BIT_SHIFT_CTLX_I2S_SCK_INV)
+
+#define BIT_CTLX_I2S_ENDIAN_SWAP                BIT(12)
+#define BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP          12
+#define BIT_MASK_CTLX_I2S_ENDIAN_SWAP           0x1
+#define BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(x)        (((x) & BIT_MASK_CTLX_I2S_ENDIAN_SWAP) << BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP)
+
+#define BIT_CTLX_I2S_SLAVE_MODE                 BIT(29)
+#define BIT_SHIFT_CTLX_I2S_SLAVE_MODE           29
+#define BIT_MASK_CTLX_I2S_SLAVE_MODE            0x1
+#define BIT_CTRL_CTLX_I2S_SLAVE_MODE(x)         (((x) & BIT_MASK_CTLX_I2S_SLAVE_MODE) << BIT_SHIFT_CTLX_I2S_SLAVE_MODE)
+
+#define BIT_CTLX_I2S_CLK_SRC                    BIT(30)
+#define BIT_SHIFT_CTLX_I2S_CLK_SRC              30
+#define BIT_MASK_CTLX_I2S_CLK_SRC               0x1
+#define BIT_CTRL_CTLX_I2S_CLK_SRC(x)            (((x) & BIT_MASK_CTLX_I2S_CLK_SRC) << BIT_SHIFT_CTLX_I2S_CLK_SRC)
+
+#define BIT_CTLX_I2S_SW_RSTN                    BIT(31)
+#define BIT_SHIFT_CTLX_I2S_SW_RSTN              31
+#define BIT_MASK_CTLX_I2S_SW_RSTN               0x1
+#define BIT_CTRL_CTLX_I2S_SW_RSTN(x)            (((x) & BIT_MASK_CTLX_I2S_SW_RSTN) << BIT_SHIFT_CTLX_I2S_SW_RSTN)
+
+// REG_I2S_SETTING
+#define BIT_SHIFT_SETTING_I2S_PAGE_SZ           0
+#define BIT_MASK_SETTING_I2S_PAGE_SZ            0xFFF
+#define BIT_CTRL_SETTING_I2S_PAGE_SZ(x)         (((x) & BIT_MASK_SETTING_I2S_PAGE_SZ) << BIT_SHIFT_SETTING_I2S_PAGE_SZ)
+#define BIT_GET_SETTING_I2S_PAGE_SZ(x)          (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_SZ) & BIT_MASK_SETTING_I2S_PAGE_SZ)
+
+#define BIT_SHIFT_SETTING_I2S_PAGE_NUM          12
+#define BIT_MASK_SETTING_I2S_PAGE_NUM           0x3
+#define BIT_CTRL_SETTING_I2S_PAGE_NUM(x)        (((x) & BIT_MASK_SETTING_I2S_PAGE_NUM) << BIT_SHIFT_SETTING_I2S_PAGE_NUM)
+#define BIT_GET_SETTING_I2S_PAGE_NUM(x)         (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_NUM) & BIT_MASK_SETTING_I2S_PAGE_NUM)
+
+#define BIT_SHIFT_SETTING_I2S_SAMPLE_RATE       14
+#define BIT_MASK_SETTING_I2S_SAMPLE_RATE        0x7
+#define BIT_CTRL_SETTING_I2S_SAMPLE_RATE(x)     (((x) & BIT_MASK_SETTING_I2S_SAMPLE_RATE) << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE)
+#define BIT_GET_SETTING_I2S_SAMPLE_RATE(x)      (((x) >> BIT_SHIFT_SETTING_I2S_SAMPLE_RATE) & BIT_MASK_SETTING_I2S_SAMPLE_RATE)
+
+// i2s trx page own bit
+#define BIT_PAGE_I2S_OWN_BIT                    BIT(31)
+#define BIT_SHIFT_PAGE_I2S_OWN_BIT              31
+#define BIT_MASK_PAGE_I2S_OWN_BIT               0x1
+#define BIT_CTRL_PAGE_I2S_OWN_BIT(x)            (((x) & BIT_MASK_PAGE_I2S_OWN_BIT) << BIT_SHIFT_PAGE_I2S_OWN_BIT)
+
+//=============== Register Address Definition ====================
+#define REG_I2S_PAGE_OWN_OFF   0x004
+
+#define REG_I2S_CTL            0x000
+#define REG_I2S_TX_PAGE_PTR    0x004
+#define REG_I2S_RX_PAGE_PTR    0x008
+#define REG_I2S_SETTING        0x00C
+
+#define REG_I2S_TX_MASK_INT    0x010
+#define REG_I2S_TX_STATUS_INT  0x014
+#define REG_I2S_RX_MASK_INT    0x018
+#define REG_I2S_RX_STATUS_INT  0x01c
+
+
+#define REG_I2S_TX_PAGE0_OWN   0x020
+#define REG_I2S_TX_PAGE1_OWN   0x024
+#define REG_I2S_TX_PAGE2_OWN   0x028
+#define REG_I2S_TX_PAGE3_OWN   0x02C
+#define REG_I2S_RX_PAGE0_OWN   0x030
+#define REG_I2S_RX_PAGE1_OWN   0x034
+#define REG_I2S_RX_PAGE2_OWN   0x038
+#define REG_I2S_RX_PAGE3_OWN   0x03C
+
+/*I2S Essential Functions and Macros*/
+VOID
+HalI2SWrite32(
+    IN  u8      I2SIdx,
+    IN  u8      I2SReg,
+    IN  u32     I2SVal
+);
+
+u32
+HalI2SRead32(
+    IN  u8      I2SIdx,
+    IN  u8      I2SReg
+);
+
+/*
+#define HAL_I2SX_READ32(I2sIndex, addr)     \
+                HAL_READ32(I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF), addr)
+#define HAL_I2SX_WRITE32(I2sIndex, addr, value)     \
+                HAL_WRITE32((I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF)), addr, value)
+*/
+
+#define HAL_I2S_WRITE32(I2SIdx, addr, value)    HalI2SWrite32(I2SIdx,addr,value)
+#define HAL_I2S_READ32(I2SIdx, addr)            HalI2SRead32(I2SIdx,addr)
+
+/* I2S debug output*/
+#define I2S_PREFIX      "RTL8195A[i2s]: "
+#define I2S_PREFIX_LVL  "    [i2s_DBG]: "
+
+typedef enum _I2S_DBG_LVL_ {
+    HAL_I2S_LVL         =   0x01,
+    SAL_I2S_LVL         =   0x02,
+    VERI_I2S_LVL        =   0x03,
+}I2S_DBG_LVL,*PI2S_DBG_LVL;
+
+#ifdef CONFIG_DEBUG_LOG
+#ifdef CONFIG_DEBUG_LOG_I2S_HAL
+
+    #define DBG_8195A_I2S(...)  do{ \
+        _DbgDump("\r"I2S_PREFIX __VA_ARGS__);\
+    }while(0)
+
+
+    #define I2SDBGLVL   0xFF   
+    #define DBG_8195A_I2S_LVL(LVL,...)  do{\
+            if (LVL&I2SDBGLVL){\
+                _DbgDump("\r"I2S_PREFIX_LVL __VA_ARGS__);\
+            }\
+    }while(0)
+#else
+    #define DBG_I2S_LOG_PERD    100
+    #define DBG_8195A_I2S(...)
+    #define DBG_8195A_I2S_LVL(...)
+#endif
+#else
+    #define DBG_I2S_LOG_PERD    100
+    #define DBG_8195A_I2S(...)
+    #define DBG_8195A_I2S_LVL(...)
+#endif
+
+/*
+#define REG_I2S_PAGE_OWN_OFF   0x004
+#define REG_I2S_CTL            0x000
+#define REG_I2S_TX_PAGE_PTR    0x004
+#define REG_I2S_RX_PAGE_PTR    0x008
+#define REG_I2S_SETTING        0x00C
+
+#define REG_I2S_TX_MASK_INT    0x010
+#define REG_I2S_TX_STATUS_INT  0x014
+#define REG_I2S_RX_MASK_INT    0x018
+#define REG_I2S_RX_STATUS_INT  0x01c
+
+
+
+#define REG_I2S_TX_PAGE0_OWN   0x020
+#define REG_I2S_TX_PAGE1_OWN   0x024
+#define REG_I2S_TX_PAGE2_OWN   0x028
+#define REG_I2S_TX_PAGE3_OWN   0x02C
+#define REG_I2S_RX_PAGE0_OWN   0x030
+#define REG_I2S_RX_PAGE1_OWN   0x034
+#define REG_I2S_RX_PAGE2_OWN   0x038
+#define REG_I2S_RX_PAGE3_OWN   0x03C
+*/
+/* template 
+#define BIT_SHIFT_CTLX_ 7
+#define BIT_MASK_CTLX_  0x1
+#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
+#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
+*//*
+#define BIT_SHIFT_CTLX_IIS_EN 0
+#define BIT_MASK_CTLX_IIS_EN  0x1
+#define BIT_CTLX_IIS_EN(x) (((x) & BIT_MASK_CTLX_IIS_EN) << BIT_SHIFT_CTLX_IIS_EN)
+#define BIT_INV_CTLX_IIS_EN (~(BIT_MASK_CTLX_IIS_EN << BIT_SHIFT_CTLX_IIS_EN))
+
+#define BIT_SHIFT_CTLX_TRX 1
+#define BIT_MASK_CTLX_TRX 0x3
+#define BIT_CTLX_TRX(x) (((x) & BIT_MASK_CTLX_TRX) << BIT_SHIFT_CTLX_TRX)
+#define BIT_INV_CTLX_TRX (~(BIT_MASK_CTLX_TRX << BIT_SHIFT_CTLX_TRX))
+
+#define BIT_SHIFT_CTLX_CH_NUM 3
+#define BIT_MASK_CTLX_CH_NUM  0x3
+#define BIT_CTLX_CH_NUM(x) (((x) & BIT_MASK_CTLX_CH_NUM) << BIT_SHIFT_CTLX_CH_NUM)
+#define BIT_INV_CTLX_CH_NUM (~(BIT_MASK_CTLX_CH_NUM << BIT_SHIFT_CTLX_CH_NUM))
+
+#define BIT_SHIFT_CTLX_EDGE_SW 5
+#define BIT_MASK_CTLX_EDGE_SW  0x1
+#define BIT_CTLX_EDGE_SW(x) (((x) & BIT_MASK_CTLX_EDGE_SW) << BIT_SHIFT_CTLX_EDGE_SW)
+#define BIT_INV_CTLX_EDGE_SW (~(BIT_MASK_CTLX_EDGE_SW << BIT_SHIFT_CTLX_EDGE_SW))
+
+#define BIT_SHIFT_CTLX_WL 6
+#define BIT_MASK_CTLX_WL  0x1
+#define BIT_CTLX_WL(x) (((x) & BIT_MASK_CTLX_WL) << BIT_SHIFT_CTLX_WL)
+#define BIT_INV_CTLX_WL (~(BIT_MASK_CTLX_WL << BIT_SHIFT_CTLX_WL))
+
+#define BIT_SHIFT_CTLX_LOOP_BACK 7
+#define BIT_MASK_CTLX_LOOP_BACK  0x1
+#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
+#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
+
+
+#define BIT_SHIFT_CTLX_FORMAT 8
+#define BIT_MASK_CTLX_FORMAT  0x3
+#define BIT_CTLX_FORMAT(x) (((x) & BIT_MASK_CTLX_FORMAT) << BIT_SHIFT_CTLX_FORMAT)
+#define BIT_INV_CTLX_FORMAT (~(BIT_MASK_CTLX_FORMAT << BIT_SHIFT_CTLX_FORMAT))
+
+#define BIT_SHIFT_CTLX_LRSWAP 10
+#define BIT_MASK_CTLX_LRSWAP  0x1
+#define BIT_CTLX_LRSWAP(x) (((x) & BIT_MASK_CTLX_LRSWAP) << BIT_SHIFT_CTLX_LRSWAP)
+#define BIT_INV_CTLX_LRSWAP (~(BIT_MASK_CTLX_LRSWAP << BIT_SHIFT_CTLX_LRSWAP))
+
+#define BIT_SHIFT_CTLX_SCK_INV 11
+#define BIT_MASK_CTLX_SCK_INV  0x1
+#define BIT_CTLX_SCK_INV(x) (((x) & BIT_MASK_CTLX_SCK_INV) << BIT_SHIFT_CTLX_SCK_INV)
+#define BIT_INV_CTLX_SCK_INV (~(BIT_MASK_CTLX_SCK_INV << BIT_SHIFT_CTLX_SCK_INV))
+
+#define BIT_SHIFT_CTLX_ENDIAN_SWAP 12
+#define BIT_MASK_CTLX_ENDIAN_SWAP  0x1
+#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
+#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
+
+
+#define BIT_SHIFT_CTLX_DEBUG_SWITCH 15
+#define BIT_MASK_CTLX_DEBUG_SWITCH  0x3
+#define BIT_CTLX_DEBUG_SWITCH(x) (((x) & BIT_MASK_CTLX_DEBUG_SWITCH) << BIT_SHIFT_CTLX_DEBUG_SWITCH)
+#define BIT_INV_CTLX_DEBUG_SWITCH (~(BIT_MASK_CTLX_DEBUG_SWITCH << BIT_SHIFT_CTLX_DEBUG_SWITCH))
+
+#define BIT_SHIFT_CTLX_SLAVE_SEL 29
+#define BIT_MASK_CTLX_SLAVE_SEL  0x1
+#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
+#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
+
+
+#define BIT_SHIFT_CTLX_CLK_SRC 30
+#define BIT_MASK_CTLX_CLK_SRC  0x1
+#define BIT_CTLX_CLK_SRC(x) (((x) & BIT_MASK_CTLX_CLK_SRC) << BIT_SHIFT_CTLX_CLK_SRC)
+#define BIT_INV_CTLX_CLK_SRC (~(BIT_MASK_CTLX_CLK_SRC << BIT_SHIFT_CTLX_CLK_SRC))
+
+
+
+#define BIT_SHIFT_CTLX_SW_RSTN 31
+#define BIT_MASK_CTLX_SW_RSTN  0x1
+#define BIT_CTLX_SW_RSTN(x) (((x) & BIT_MASK_CTLX_SW_RSTN) << BIT_SHIFT_CTLX_SW_RSTN)
+#define BIT_INV_CTLX_SW_RSTN (~(BIT_MASK_CTLX_SW_RSTN << BIT_SHIFT_CTLX_SW_RSTN))
+
+
+#define BIT_SHIFT_SETTING_PAGE_SZ 0
+#define BIT_MASK_SETTING_PAGE_SZ  0xFFF
+#define BIT_SETTING_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_PAGE_SZ) << BIT_SHIFT_SETTING_PAGE_SZ)
+#define BIT_INV_SETTING_PAGE_SZ (~(BIT_MASK_SETTING_PAGE_SZ << BIT_SHIFT_SETTING_PAGE_SZ))
+
+#define BIT_SHIFT_SETTING_PAGE_NUM 12
+#define BIT_MASK_SETTING_PAGE_NUM  0x3
+#define BIT_SETTING_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_PAGE_NUM) << BIT_SHIFT_SETTING_PAGE_NUM)
+#define BIT_INV_SETTING_PAGE_NUM (~(BIT_MASK_SETTING_PAGE_NUM << BIT_SHIFT_SETTING_PAGE_NUM))
+
+#define BIT_SHIFT_SETTING_SAMPLE_RATE 14
+#define BIT_MASK_SETTING_SAMPLE_RATE  0x7
+#define BIT_SETTING_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_SAMPLE_RATE) << BIT_SHIFT_SETTING_SAMPLE_RATE)
+#define BIT_INV_SETTING_SAMPLE_RATE (~(BIT_MASK_SETTING_SAMPLE_RATE << BIT_SHIFT_SETTING_SAMPLE_RATE))
+*/
+
+typedef enum _I2S_CTL_FORMAT {
+    FormatI2s             = 0x00,
+    FormatLeftJustified   = 0x01,
+    FormatRightJustified  = 0x02
+}I2S_CTL_FORMAT, *PI2S_CTL_FORMAT;
+
+typedef enum _I2S_CTL_CHNUM {
+    ChannelStereo      = 0x00,
+    Channel5p1         = 0x01,
+    ChannelMono        = 0x02
+}I2S_CTL_CHNUM, *PI2S_CTL_CHNUM;
+
+typedef enum _I2S_CTL_TRX_ACT {
+    RxOnly             = 0x00,
+    TxOnly             = 0x01,
+    TXRX               = 0x02
+}I2S_CTL_TRX_ACT, *PI2S_CTL_TRX_ACT;
+/*
+typedef struct _I2S_CTL_REG_ {
+    I2S_CTL_FORMAT         Format;
+    I2S_CTL_CHNUM          ChNum;
+    I2S_CTL_TRX_ACT        TrxAct;
+
+    u32                    I2s_En         :1; // Bit 0
+    u32                    Rsvd1to4       :4; // Bit 1-4 is TrxAct, ChNum
+    u32                    EdgeSw         :1; // Bit 5 Edge switch
+    u32                    WordLength     :1; // Bit 6
+    u32                    LoopBack       :1; // Bit 7
+    u32                    Rsvd8to9       :2; // Bit 8-9 is Format
+    u32                    DacLrSwap      :1; // Bit 10
+    u32                    SckInv         :1; // Bit 11
+    u32                    EndianSwap     :1; // Bit 12
+    u32                    Rsvd13to14     :2; // Bit 11-14
+    u32                    DebugSwitch    :2; // Bit 15-16
+    u32                    Rsvd17to28    :12; // Bit 17-28
+    u32                    SlaveMode      :1; // Bit 29
+    u32                    SR44p1KHz      :1; // Bit 30
+    u32                    SwRstn         :1; // Bit 31
+} I2S_CTL_REG, *PI2S_CTL_REG;
+*/
+typedef enum _I2S_SETTING_PAGE_NUM {
+    I2s1Page           = 0x00,
+    I2s2Page           = 0x01,
+    I2s3Page           = 0x02,
+    I2s4Page           = 0x03
+}I2S_SETTING_PAGE_NUM, *PI2S_SETTING_PAGE_NUM;
+
+//sampling rate
+typedef enum _I2S_SETTING_SR {
+    I2sSR8K            = 0x00,
+    I2sSR16K           = 0x01,
+    I2sSR24K           = 0x02,
+    I2sSR32K           = 0x03,
+    I2sSR48K           = 0x05,
+    I2sSR44p1K         = 0x15,
+    I2sSR96K           = 0x06,
+    I2sSR88p2K         = 0x16
+}I2S_SETTING_SR, *PI2S_SETTING_SR;
+/*
+typedef struct _I2S_SETTING_REG_ {
+    I2S_SETTING_PAGE_NUM     PageNum;
+    I2S_SETTING_SR           SampleRate;
+
+    u32                      PageSize:12; // Bit 0-11
+}I2S_SETTING_REG, *PI2S_SETTING_REG;
+
+typedef enum _I2S_TX_ISR {
+    I2sTxP0OK          = 0x01,
+    I2sTxP1OK          = 0x02,
+    I2sTxP2OK          = 0x04,
+    I2sTxP3OK          = 0x08,
+    I2sTxPageUn        = 0x10,
+    I2sTxFifoEmpty     = 0x20
+}I2S_TX_ISR, *PI2S_TX_ISR;
+
+typedef enum _I2S_RX_ISR {
+    I2sRxP0OK          = 0x01,
+    I2sRxP1OK          = 0x02,
+    I2sRxP2OK          = 0x04,
+    I2sRxP3OK          = 0x08,
+    I2sRxPageUn        = 0x10,
+    I2sRxFifoFull      = 0x20
+}I2S_RX_ISR, *PI2S_RX_ISR;
+*/
+
+/* Hal I2S function prototype*/
+RTK_STATUS
+HalI2SInitRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SInitRtl8195a_Patch(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SDeInitRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2STxRtl8195a(
+    IN  VOID    *Data,
+	IN  u8      *pBuff
+);
+
+RTK_STATUS
+HalI2SRxRtl8195a(
+    IN  VOID    *Data,
+	OUT u8      *pBuff
+);
+
+RTK_STATUS
+HalI2SEnableRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SIntrCtrlRtl8195a(
+    IN  VOID    *Data
+);
+
+u32
+HalI2SReadRegRtl8195a(
+    IN  VOID    *Data,
+    IN  u8      I2SReg
+);
+
+RTK_STATUS
+HalI2SSetRateRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SSetWordLenRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SSetChNumRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SSetPageNumRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SSetPageSizeRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SSetDirectionRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SSetDMABufRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SClrIntrRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SClrAllIntrRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SDMACtrlRtl8195a(
+    IN  VOID    *Data
+);
+
+u8
+HalI2SGetTxPageRtl8195a(
+    IN  VOID    *Data
+);
+
+u8
+HalI2SGetRxPageRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SPageSendRtl8195a(
+    IN  VOID    *Data,
+	IN  u8      PageIdx
+);
+
+#if 0
+RTK_STATUS
+HalI2SPageRecvRtl8195a(
+    IN  VOID    *Data,
+	IN u8      PageIdx
+);
+#else
+RTK_STATUS
+HalI2SPageRecvRtl8195a(
+    IN  VOID    *Data
+);
+#endif
+
+RTK_STATUS
+HalI2SClearAllOwnBitRtl8195a(
+    IN  VOID    *Data
+);
+
+
+// HAL functions Wrapper
+static __inline VOID
+HalI2SSetRate(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetRateRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SSetWordLen(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetWordLenRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SSetChNum(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetChNumRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SSetPageNum(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetPageNumRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SSetPageSize(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetPageSizeRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SSetDirection(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetDirectionRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SSetDMABuf(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetDMABufRtl8195a(Data);
+}
+
+static __inline u8
+HalI2SGetTxPage(
+    IN  VOID    *Data
+)
+{
+    return HalI2SGetTxPageRtl8195a(Data);
+}
+
+static __inline u8
+HalI2SGetRxPage(
+    IN  VOID    *Data
+)
+{
+    return HalI2SGetRxPageRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SPageSend(
+    IN  VOID    *Data,
+	IN  u8      PageIdx
+)
+{
+    HalI2SPageSendRtl8195a(Data, PageIdx);
+}
+
+#if 0
+static __inline VOID
+HalI2SPageRecv(
+    IN  VOID    *Data,
+	IN u8      PageIdx
+)
+{
+    HalI2SPageRecvRtl8195a(Data, PageIdx);
+}
+#else
+static __inline VOID
+HalI2SPageRecv(
+    IN  VOID    *Data
+)
+{
+    HalI2SPageRecvRtl8195a(Data);
+}
+#endif
+
+static __inline VOID
+HalI2SClearAllOwnBit(
+    IN  VOID    *Data
+)
+{
+    HalI2SClearAllOwnBitRtl8195a(Data);
+}
+
+#endif /* _RTL8195A_I2S_H_ */
+
+

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_mii.h

@@ -0,0 +1,674 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_MII_H_
+#define _RTL8195A_MII_H_
+
+#include "basic_types.h"
+#include "hal_api.h"
+
+
+#define ETHERNET_REG_BASE     0x40050000
+#define ETHERNET_MODULE_BASE  ETHERNET_REG_BASE + 0x0000
+#define CPU_INTERFACE_BASE    ETHERNET_REG_BASE + 0x1300
+
+/* Ethernet Module registers */
+#define REG_RTL_MII_IDR0    0x0000  // Table 2 IDR0 (Offset 0000h-0003h, R/W)
+#define REG_RTL_MII_IDR4    0x0004  // Table 3 IDR4 (Offset 0004h-0007h, R/W)
+#define REG_RTL_MII_MAR0    0x0008  // Table 4 MAR0 (Offset 0008h-000bh, R/W)
+#define REG_RTL_MII_MAR4    0x000C  // Table 5 MAR4 (Offset 000ch-000fh, R/W)
+#define REG_RTL_MII_CR      0x0038  // Table 21 Command Register          (COM_REG, Offset 0038-003Bh, R/W)
+#define REG_RTL_MII_IMRISR  0x003C  // Table 22 + Table 23
+#define REG_RTL_MII_TCR     0x0040  // Table 24 Transmit Configuration Register (TC_REG, Offset 0040h-0043h, R/W)
+#define REG_RTL_MII_RCR     0x0044  // Table 25 Receive Configuration Register  (RC_REG, Offset 0044h-0047h, R/W)
+#define REG_RTL_MII_CTCR    0x0048  // Table 26 CPU Tag Control Register  (CPUTAG_REG, Offset 0048h-004bh, R/W)
+#define REG_RTL_MII_CONFIG  0x004C  // Table 27 Configuration Register (CONFIG_REG, Offset 004ch-004fh, R/W)
+#define REG_RTL_MII_CTCR1   0x0050  // Table 28 CPUTAG1 Register          (CPUTAG1_REG, Offset 0050h-0053h, R/W)
+#define REG_RTL_MII_MSR     0x0058  // Table 29 Media Status Register     (MS_reg: Offset 0058h – 005bh, R/W)
+#define REG_RTL_MII_MIIAR   0x005C  // Table 30 MII Access Register (MIIA_REG, Offset 005c-005fh, R/W)
+#define REG_RTL_MII_VR      0x0064  // Table 32 VLAN Register (VLAN_REG, Offset 0064-0067h, R/W)
+#define REG_RTL_MII_IMR0    0x00D0  // Table 50 IMR0_REG (IMR0_REG, Offset D0h-D3h)
+#define REG_RTL_MII_IMR1    0x00D4  // Table 51 IMR1_REG (IMR1_REG, Offset d4h-d7h)
+#define REG_RTL_MII_ISR1    0x00D8  // Table 52 ISR1 Register (ISR1_REG, Offset D8h-DBh)
+#define REG_RTL_MII_INTR    0x00DC  // Table 53 Interrupt routing register (INTR_REG, Offset DCh-DFh)
+#define REG_RTL_MII_CCR     0x00E4  // Table xx Clock Control Register (CLKCTL_REG, Offset E4h-E7h)
+
+/* CPU Interface registers */
+#define REG_RTL_MII_TXFDP1  0x1300  // Table 55 TxFDP1 register (TXFDP1_REG, offset 1300h-1303h)
+#define REG_RTL_MII_TXCDO1  0x1304  // Table 56 TxCDO1 register (TXCDO1_REG, offset 1304h-1305h)
+#define REG_RTL_MII_TXFDP2  0x1310  // Table 57 TxFDP2 register (TXFDP2_REG, offset 1310h-1313h)
+#define REG_RTL_MII_TXCDO2  0x1314  // Table 58 TxCDO2 register (TXCDO2_REG, offset 1314h-1315h)
+#define REG_RTL_MII_TXFDP3  0x1320  // Table 59 TxFDP3 register (TXFDP3_REG, offset 1320h-1323h)
+#define REG_RTL_MII_TXCDO3  0x1324  // Table 60 TxCDO3 register (TXCDO3_REG, offset 1324h-1325h)
+#define REG_RTL_MII_TXFDP4  0x1330  // Table 61 TxFDP4 register (TXFDP4_REG, offset 1330h-1333h)
+#define REG_RTL_MII_TXCDO4  0x1334  // Table 62 TxCDO4 register (TXCDO4_REG, offset 1334h-1335h)
+#define REG_RTL_MII_TXFDP5  0x1340  // Table 63 TxFDP5 register (TXFDP5_REG, offset 1340h-1343h)
+#define REG_RTL_MII_TXCDO5  0x1344  // Table 64 TxCDO5 register (TXCDO5_REG, offset 1344h-1345h)
+#define REG_RTL_MII_RXFDP2  0x1390  // Table 66 RxFDP2 register (RXFDP#_REG, offset 1390h-1393h)
+#define REG_RTL_MII_RXFDP1  0x13F0  // Table 71 RxFDP1 register (RXFDP1_REG, offset 13F0h-13F3h)
+#define REG_RTL_MII_RXRS1   0x13F6  // Table 73 Rx Ring Size1 register (RX_RS1_REG, offset 13F6h-13F7h)
+
+#define REG_RTL_MII_RX_PSE1   0x142C  // Table 77 Rx_Pse_Des_Thres_1_h (RX_PSE1_REG, Offset 142ch)
+#define REG_RTL_MII_ETNRXCPU1 0x1430  // Table 79 EhtrntRxCPU_Des_Num1 (ETNRXCPU1_REG, Offset 1430h-1433h)
+#define REG_RTL_MII_IOCMD     0x1434  // Table 80 Ethernet_IO_CMD (ETN_IO_CMD_REG, Offset 1434h-1437h)
+#define REG_RTL_MII_IOCMD1    0x1438  // Table 81 Ethernet_IO_CMD1 (IO_CMD1_REG: Offset 1438h-143bh)
+
+
+#define HAL_MII_READ32(addr)         \
+    HAL_READ32(ETHERNET_REG_BASE, addr)
+#define HAL_MII_WRITE32(addr, value) \
+    HAL_WRITE32(ETHERNET_REG_BASE, addr, value)
+#define HAL_MII_READ16(addr)         \
+    HAL_READ16(ETHERNET_REG_BASE, addr)
+#define HAL_MII_WRITE16(addr, value) \
+    HAL_WRITE16(ETHERNET_REG_BASE, addr, value)
+#define HAL_MII_READ8(addr)          \
+    HAL_READ8(ETHERNET_REG_BASE, addr)
+#define HAL_MII_WRITE8(addr, value)  \
+    HAL_WRITE8(ETHERNET_REG_BASE, addr, value)
+
+#define  CMD_CONFIG  0x00081000
+
+//2014-04-29 yclin (disable [27] r_en_precise_dma)
+// #define CMD1_CONFIG  0x39000000
+#define CMD1_CONFIG  0x31000000
+
+// #define MAX_RX_DESC_SIZE  6
+#define MAX_RX_DESC_SIZE  1
+#define MAX_TX_DESC_SIZE  5
+
+// 0058h
+#define BIT_SHIFT_MSR_FORCE_SPEED_SELECT    16
+#define BIT_MASK_MSR_FORCE_SPEED_SELECT     0x3
+#define BIT_MSR_FORCE_SPEED_SELECT(x)(((x) & BIT_MASK_MSR_FORCE_SPEED_SELECT) << BIT_SHIFT_MSR_FORCE_SPEED_SELECT)
+#define BIT_INVC_MSR_FORCE_SPEED_SELECT (~(BIT_MASK_MSR_FORCE_SPEED_SELECT << BIT_SHIFT_MSR_FORCE_SPEED_SELECT))
+
+#define BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE    10
+#define BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE     0x1
+#define BIT_MSR_FORCE_SPEED_MODE_ENABLE(x)(((x) & BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE) << BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE)
+#define BIT_INVC_MSR_FORCE_SPEED_MODE_ENABLE (~(BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE << BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE))
+
+// 1434h
+#define BIT_SHIFT_IOCMD_RXENABLE      5
+#define BIT_MASK_IOCMD_RXENABLE       0x1
+#define BIT_IOCMD_RXENABLE(x)(((x) & BIT_MASK_IOCMD_RXENABLE) << BIT_SHIFT_IOCMD_RXENABLE)
+#define BIT_INVC_IOCMD_RXENABLE (~(BIT_MASK_IOCMD_RXENABLE << BIT_SHIFT_IOCMD_RXENABLE))
+
+#define BIT_SHIFT_IOCMD_TXENABLE      4
+#define BIT_MASK_IOCMD_TXENABLE       0x1
+#define BIT_IOCMD_TXENABLE(x)(((x) & BIT_MASK_IOCMD_TXENABLE) << BIT_SHIFT_IOCMD_TXENABLE)
+#define BIT_INVC_IOCMD_TXENABLE (~(BIT_MASK_IOCMD_TXENABLE << BIT_SHIFT_IOCMD_TXENABLE))
+
+#define BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE      0
+#define BIT_MASK_IOCMD_FIRST_DMATX_ENABLE       0x1
+#define BIT_IOCMD_FIRST_DMATX_ENABLE(x)(((x) & BIT_MASK_IOCMD_FIRST_DMATX_ENABLE) << BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE)
+#define BIT_INVC_IOCMD_FIRST_DMATX_ENABLE (~(BIT_MASK_IOCMD_FIRST_DMATX_ENABLE << BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE))
+
+// 1438h
+#define BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE    16
+#define BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE     0x1
+#define BIT_IOCMD1_FIRST_DMARX_ENABLE(x)(((x) & BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE) << BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE)
+#define BIT_INVC_IOCMD1_FIRST_DMARX_ENABLE (~(BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE << BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE))
+
+
+/**
+ * 1.4.1.7 Tx command descriptor used in RL6266
+ *   5 dobule words
+ */
+typedef struct _TX_INFO_ {
+    union {
+        struct {
+            u32 own:1;          //31
+            u32 eor:1;          //30
+            u32 fs:1;           //29
+            u32 ls:1;           //28
+            u32 ipcs:1;         //27
+            u32 l4cs:1;         //26
+            u32 keep:1;         //25
+            u32 blu:1;          //24
+            u32 crc:1;          //23
+            u32 vsel:1;         //22
+            u32 dislrn:1;       //21
+            u32 cputag_ipcs:1;  //20
+            u32 cputag_l4cs:1;  //19
+            u32 cputag_psel:1;  //18
+            u32 rsvd:1;         //17
+            u32 data_length:17; //0~16
+        } bit;
+        u32 dw; //double word
+    } opts1;
+
+    u32 addr;
+
+    union {
+        struct {
+            u32 cputag:1;          //31
+            u32 aspri:1;           //30
+            u32 cputag_pri:3;      //27~29
+            u32 tx_vlan_action:2;  //25~26
+            u32 tx_pppoe_action:2; //23~24
+            u32 tx_pppoe_idx:3;    //20~22
+            u32 efid:1;            //19
+            u32 enhance_fid:3;     //16~18
+            u32 vidl:8;            // 8~15
+            u32 prio:3;            // 5~7
+            u32 cfi:1;             // 4
+            u32 vidh:4;            // 0~3
+        } bit;
+        u32 dw; //double word
+    } opts2;
+
+    union {
+        struct {
+            u32 extspa:3;           //29~31
+            u32 tx_portmask:6;      //23~28
+            u32 tx_dst_stream_id:7; //16~22
+            u32 rsvd:14;            // 2~15
+            u32 l34keep:1;          // 1
+            u32 ptp:1;              // 0
+        } bit;
+        u32 dw; //double word
+    } opts3;
+
+    union {
+        struct {
+            u32 lgsen:1;  //31
+            u32 lgmss:11; //20~30
+            u32 rsvd:20;  // 0~19
+        } bit;
+        u32 dw; //double word
+    } opts4;
+
+} TX_INFO, *PTX_INFO;
+
+typedef struct _RX_INFO_ {
+    union{
+        struct{
+            u32 own:1;          //31
+            u32 eor:1;          //30
+            u32 fs:1;           //29
+            u32 ls:1;           //28
+            u32 crcerr:1;       //27
+            u32 ipv4csf:1;      //26
+            u32 l4csf:1;        //25
+            u32 rcdf:1;         //24
+            u32 ipfrag:1;       //23
+            u32 pppoetag:1;     //22
+            u32 rwt:1;          //21
+            u32 pkttype:4;      //20-17
+            u32 l3routing:1;    //16
+            u32 origformat:1;   //15
+            u32 pctrl:1;        //14
+#ifdef CONFIG_RG_JUMBO_FRAME
+            u32 data_length:14; //13~0
+#else
+            u32 rsvd:2;         //13~12
+            u32 data_length:12; //11~0
+#endif
+        }bit;
+        u32 dw; //double word
+    }opts1;
+
+    u32 addr;
+
+    union{
+        struct{
+            u32 cputag:1;               //31
+            u32 ptp_in_cpu_tag_exist:1; //30
+            u32 svlan_tag_exist:1;      //29
+            u32 rsvd_2:2;               //27~28
+            u32 pon_stream_id:7;        //20~26
+            u32 rsvd_1:3;               //17~19
+            u32 ctagva:1;               //16
+            u32 cvlan_tag:16;           //15~0
+        }bit;
+        u32 dw; //double word
+    }opts2;
+
+    union{
+        struct{
+            u32 src_port_num:5;      //27~31
+            u32 dst_port_mask:6;     //21~26
+            u32 reason:8;            //13~20
+            u32 internal_priority:3; //10~12
+            u32 ext_port_ttl_1:5;    //5~9
+            u32 rsvd:5;              //4~0
+        }bit;
+        u32 dw; //double word
+    }opts3;
+} RX_INFO, *PRX_INFO;
+
+/**
+ * GMAC_STATUS_REGS
+ */
+// TX/RX Descriptor Common
+#define BIT_SHIFT_GMAC_DESCOWN        31
+#define BIT_MASK_GMAC_DESCOWN        0x1
+#define BIT_GMAC_DESCOWN(x)(((x) & BIT_MASK_GMAC_DESCOWN) << BIT_SHIFT_GMAC_DESCOWN)
+#define BIT_INVC_GMAC_DESCOWN (~(BIT_MASK_GMAC_DESCOWN << BIT_SHIFT_GMAC_DESCOWN))
+
+#define BIT_SHIFT_GMAC_RINGEND        30
+#define BIT_MASK_GMAC_RINGEND        0x1
+#define BIT_GMAC_RINGEND(x)(((x) & BIT_MASK_GMAC_RINGEND) << BIT_SHIFT_GMAC_RINGEND)
+#define BIT_INVC_GMAC_RINGEND (~(BIT_MASK_GMAC_RINGEND << BIT_SHIFT_GMAC_RINGEND))
+
+#define BIT_SHIFT_GMAC_FIRSTFRAG      29
+#define BIT_MASK_GMAC_FIRSTFRAG      0x1
+#define BIT_GMAC_FIRSTFRAG(x)(((x) & BIT_MASK_GMAC_FIRSTFRAG) << BIT_SHIFT_GMAC_FIRSTFRAG)
+#define BIT_INVC_GMAC_FIRSTFRAG (~(BIT_MASK_GMAC_FIRSTFRAG << BIT_SHIFT_GMAC_FIRSTFRAG))
+
+#define BIT_SHIFT_GMAC_LASTFRAG       28
+#define BIT_MASK_GMAC_LASTFRAG       0x1
+#define BIT_GMAC_LASTFRAG(x)(((x) & BIT_MASK_GMAC_LASTFRAG) << BIT_SHIFT_GMAC_LASTFRAG)
+#define BIT_INVC_GMAC_LASTFRAG (~(BIT_MASK_GMAC_LASTFRAG << BIT_SHIFT_GMAC_LASTFRAG))
+
+// TX Descriptor opts1
+#define BIT_SHIFT_GMAC_IPCS           27
+#define BIT_MASK_GMAC_IPCS           0x1
+#define BIT_GMAC_IPCS(x)(((x) & BIT_MASK_GMAC_IPCS) << BIT_SHIFT_GMAC_IPCS)
+#define BIT_INVC_GMAC_IPCS (~(BIT_MASK_GMAC_IPCS << BIT_SHIFT_GMAC_IPCS))
+
+#define BIT_SHIFT_GMAC_L4CS           26
+#define BIT_MASK_GMAC_L4CS           0x1
+#define BIT_GMAC_L4CS(x)(((x) & BIT_MASK_GMAC_L4CS) << BIT_SHIFT_GMAC_L4CS)
+#define BIT_INVC_GMAC_L4CS (~(BIT_MASK_GMAC_L4CS << BIT_SHIFT_GMAC_L4CS))
+
+#define BIT_SHIFT_GMAC_KEEP           25
+#define BIT_MASK_GMAC_KEEP           0x1
+#define BIT_GMAC_KEEP(x)(((x) & BIT_MASK_GMAC_KEEP) << BIT_SHIFT_GMAC_KEEP)
+#define BIT_INVC_GMAC_KEEP (~(BIT_MASK_GMAC_KEEP << BIT_SHIFT_GMAC_KEEP))
+
+#define BIT_SHIFT_GMAC_BLU            24
+#define BIT_MASK_GMAC_BLU            0x1
+#define BIT_GMAC_BLU(x)(((x) & BIT_MASK_GMAC_BLU) << BIT_SHIFT_GMAC_BLU)
+#define BIT_INVC_GMAC_BLU (~(BIT_MASK_GMAC_BLU << BIT_SHIFT_GMAC_BLU))
+
+#define BIT_SHIFT_GMAC_TXCRC          23
+#define BIT_MASK_GMAC_TXCRC          0x1
+#define BIT_GMAC_TXCRC(x)(((x) & BIT_MASK_GMAC_TXCRC) << BIT_SHIFT_GMAC_TXCRC)
+#define BIT_INVC_GMAC_TXCRC (~(BIT_MASK_GMAC_TXCRC << BIT_SHIFT_GMAC_TXCRC))
+
+#define BIT_SHIFT_GMAC_VSEL           22
+#define BIT_MASK_GMAC_VSEL           0x1
+#define BIT_GMAC_VSEL(x)(((x) & BIT_MASK_GMAC_VSEL) << BIT_SHIFT_GMAC_VSEL)
+#define BIT_INVC_GMAC_VSEL (~(BIT_MASK_GMAC_VSEL << BIT_SHIFT_GMAC_VSEL))
+
+#define BIT_SHIFT_GMAC_DISLRN         21
+#define BIT_MASK_GMAC_DISLRN         0x1
+#define BIT_GMAC_DISLRN(x)(((x) & BIT_MASK_GMAC_DISLRN) << BIT_SHIFT_GMAC_DISLRN)
+#define BIT_INVC_GMAC_DISLRN (~(BIT_MASK_GMAC_DISLRN << BIT_SHIFT_GMAC_DISLRN))
+
+#define BIT_SHIFT_GMAC_CPUTAG_IPCS    20
+#define BIT_MASK_GMAC_CPUTAG_IPCS    0x1
+#define BIT_GMAC_CPUTAG_IPCS(x)(((x) & BIT_MASK_GMAC_CPUTAG_IPCS) << BIT_SHIFT_GMAC_CPUTAG_IPCS)
+#define BIT_INVC_GMAC_CPUTAG_IPCS (~(BIT_MASK_GMAC_CPUTAG_IPCS << BIT_SHIFT_GMAC_CPUTAG_IPCS))
+
+#define BIT_SHIFT_GMAC_CPUTAG_L4CS    19
+#define BIT_MASK_GMAC_CPUTAG_L4CS    0x1
+#define BIT_GMAC_CPUTAG_L4CS(x)(((x) & BIT_MASK_GMAC_CPUTAG_L4CS) << BIT_SHIFT_GMAC_CPUTAG_L4CS)
+#define BIT_INVC_GMAC_CPUTAG_L4CS (~(BIT_MASK_GMAC_CPUTAG_L4CS << BIT_SHIFT_GMAC_CPUTAG_L4CS))
+
+#define BIT_SHIFT_GMAC_CPUTAG_PSEL    18
+#define BIT_MASK_GMAC_CPUTAG_PSEL    0x1
+#define BIT_GMAC_CPUTAG_PSEL(x)(((x) & BIT_MASK_GMAC_CPUTAG_PSEL) << BIT_SHIFT_GMAC_CPUTAG_PSEL)
+#define BIT_INVC_GMAC_CPUTAG_PSEL (~(BIT_MASK_GMAC_CPUTAG_PSEL << BIT_SHIFT_GMAC_CPUTAG_PSEL))
+
+
+#if 0
+enum RE8670_STATUS_REGS
+{
+    /*TX/RX share */
+    DescOwn     = (1 << 31), /* Descriptor is owned by NIC */
+    RingEnd     = (1 << 30), /* End of descriptor ring */
+    FirstFrag       = (1 << 29), /* First segment of a packet */
+    LastFrag        = (1 << 28), /* Final segment of a packet */
+
+    /*Tx descriptor opt1*/
+    IPCS        = (1 << 27),
+    L4CS        = (1 << 26),
+    KEEP        = (1 << 25),
+    BLU         = (1 << 24),
+    TxCRC       = (1 << 23),
+    VSEL        = (1 << 22),
+    DisLrn      = (1 << 21),
+    CPUTag_ipcs     = (1 << 20),
+    CPUTag_l4cs = (1 << 19),
+
+    /*Tx descriptor opt2*/
+    CPUTag      = (1 << 31),
+    aspri       = (1 << 30),
+    CPRI        = (1 << 27),
+    TxVLAN_int  = (0 << 25),  //intact
+    TxVLAN_ins  = (1 << 25),  //insert
+    TxVLAN_rm   = (2 << 25),  //remove
+    TxVLAN_re   = (3 << 25),  //remark
+    //TxPPPoEAct    = (1 << 23),
+    TxPPPoEAct  = 23,
+    //TxPPPoEIdx    = (1 << 20),
+    TxPPPoEIdx  = 20,
+    Efid            = (1 << 19),
+    //Enhan_Fid = (1 << 16),
+    Enhan_Fid   = 16,
+    /*Tx descriptor opt3*/
+    SrcExtPort  = 29,
+    TxDesPortM  = 23,
+    TxDesStrID  = 16,
+    TxDesVCM    = 0,
+    /*Tx descriptor opt4*/
+    /*Rx descriptor  opt1*/
+    CRCErr  = (1 << 27),
+    IPV4CSF     = (1 << 26),
+    L4CSF       = (1 << 25),
+    RCDF        = (1 << 24),
+    IP_FRAG     = (1 << 23),
+    PPPoE_tag   = (1 << 22),
+    RWT         = (1 << 21),
+    PktType     = (1 << 17),
+    RxProtoIP   = 1,
+    RxProtoPPTP = 2,
+    RxProtoICMP = 3,
+    RxProtoIGMP = 4,
+    RxProtoTCP  = 5,   
+    RxProtoUDP  = 6,
+    RxProtoIPv6 = 7,
+    RxProtoICMPv6   = 8,
+    RxProtoTCPv6    = 9,
+    RxProtoUDPv6    = 10,
+    L3route     = (1 << 16),
+    OrigFormat  = (1 << 15),
+    PCTRL       = (1 << 14),
+    /*Rx descriptor opt2*/
+    PTPinCPU    = (1 << 30),
+    SVlanTag        = (1 << 29),
+    /*Rx descriptor opt3*/
+    SrcPort     = (1 << 27),
+    DesPortM    = (1 << 21),
+    Reason      = (1 << 13),
+    IntPriority = (1 << 10),
+    ExtPortTTL  = (1 << 5),
+};
+
+enum _DescStatusBit {
+    DescOwn     = (1 << 31), /* Descriptor is owned by NIC */
+    RingEnd     = (1 << 30), /* End of descriptor ring */
+    FirstFrag   = (1 << 29), /* First segment of a packet */
+    LastFrag    = (1 << 28), /* Final segment of a packet */
+
+    /* Tx private */
+    LargeSend   = (1 << 27), /* TCP Large Send Offload (TSO) */
+    MSSShift    = 16,        /* MSS value position */
+    MSSMask     = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
+    IPCS        = (1 << 18), /* Calculate IP checksum */
+    UDPCS       = (1 << 17), /* Calculate UDP/IP checksum */
+    TCPCS       = (1 << 16), /* Calculate TCP/IP checksum */
+    TxVlanTag   = (1 << 17), /* Add VLAN tag */
+
+    /* Rx private */
+    PID1        = (1 << 18), /* Protocol ID bit 1/2 */
+    PID0        = (1 << 17), /* Protocol ID bit 2/2 */
+
+#define RxProtoUDP  (PID1)
+#define RxProtoTCP  (PID0)
+#define RxProtoIP   (PID1 | PID0)
+#define RxProtoMask RxProtoIP
+
+    IPFail      = (1 << 16), /* IP checksum failed */
+    UDPFail     = (1 << 15), /* UDP/IP checksum failed */
+    TCPFail     = (1 << 14), /* TCP/IP checksum failed */
+    RxVlanTag   = (1 << 16), /* VLAN tag available */
+};
+#endif
+
+typedef struct _PHY_MODE_INFO_ {
+    u8 PhyAddress;
+    u8 PhyMode;
+    u8 PhyInterface;
+} PHY_MODE_INFO, *PPHY_MODE_INFO;
+
+typedef enum _PHY_MODE_SWITCH_ {
+    PHY_MODE_DISABLE = 0,
+    PHY_MODE_ENABLE  = 1
+} PHY_MODE_SWITCH, *PPHY_MODE_SWITCH;
+
+typedef enum _PHY_INTERFACE_SELECT_ {
+    PHY_INTERFACE_ONE_WORKS  = 0,
+    PHY_INTERFACE_ZERO_WORKS = 1
+} PHY_INTERFACE_SELECT, *PPHY_INTERFACE_SELECT;
+
+typedef enum _GMAC_MSR_FORCE_SPEED_ {
+    FORCE_SPD_100M = 0,
+    FORCE_SPD_10M  = 1,
+    FORCE_SPD_GIGA = 2,
+    NO_FORCE_SPD   = 3
+}GMAC_MSR_FORCE_SPEED, *PGMAC_MSR_FORCE_SPEED;
+
+// typedef enum _GMAC_INTERRUPT_MASK_ {
+//     GMAC_IMR_ROK      = BIT0,
+//     GMAC_IMR_CNT_WRAP = BIT1,
+//     GMAC_IMR_RER_RUNT = BIT2,
+//     // BIT3 Reserved
+//     GMAC_IMR_RER_OVF  = BIT4,
+//     GMAC_IMR_RDU      = BIT5,
+//     GMAC_IMR_TOK_TI   = BIT6,
+//     GMAC_IMR_TER      = BIT7,
+//     GMAC_IMR_LINKCHG  = BIT8,
+//     GMAC_IMR_TDU      = BIT9,
+//     GMAC_IMR_SWINT    = BIT10,
+//     GMAC_IMR_RDU2     = BIT11,
+//     GMAC_IMR_RDU3     = BIT12,
+//     GMAC_IMR_RDU4     = BIT13,
+//     GMAC_IMR_RDU5     = BIT14,
+//     GMAC_IMR_RDU6     = BIT15,
+// } GMAC_INTERRUPT_MASK, *PGMAC_INTERRUPT_MASK;
+
+typedef enum _GMAC_INTERRUPT_MASK_ {
+    GMAC_IMR_ROK      = BIT16,
+    GMAC_IMR_CNT_WRAP = BIT17,
+    GMAC_IMR_RER_RUNT = BIT18,
+    // BIT19 Reserved
+    GMAC_IMR_RER_OVF  = BIT20,
+    GMAC_IMR_RDU      = BIT21,
+    GMAC_IMR_TOK_TI   = BIT22,
+    GMAC_IMR_TER      = BIT23,
+    GMAC_IMR_LINKCHG  = BIT24,
+    GMAC_IMR_TDU      = BIT25,
+    GMAC_IMR_SWINT    = BIT26,
+    GMAC_IMR_RDU2     = BIT27,
+    GMAC_IMR_RDU3     = BIT28,
+    GMAC_IMR_RDU4     = BIT29,
+    GMAC_IMR_RDU5     = BIT30,
+    GMAC_IMR_RDU6     = BIT31,
+} GMAC_INTERRUPT_MASK, *PGMAC_INTERRUPT_MASK;
+
+typedef enum _GMAC_INTERRUPT_STATUS_ {
+    GMAC_ISR_ROK      = BIT0,
+    GMAC_ISR_CNT_WRAP = BIT1,
+    GMAC_ISR_RER_RUNT = BIT2,
+    // BIT3 Reserved
+    GMAC_ISR_RER_OVF  = BIT4,
+    GMAC_ISR_RDU      = BIT5,
+    GMAC_ISR_TOK_TI   = BIT6,
+    GMAC_ISR_TER      = BIT7,
+    GMAC_ISR_LINKCHG  = BIT8,
+    GMAC_ISR_TDU      = BIT9,
+    GMAC_ISR_SWINT    = BIT10,
+    GMAC_ISR_RDU2     = BIT11,
+    GMAC_ISR_RDU3     = BIT12,
+    GMAC_ISR_RDU4     = BIT13,
+    GMAC_ISR_RDU5     = BIT14,
+    GMAC_ISR_RDU6     = BIT15,
+} GMAC_INTERRUPT_STATUS, *PGMAC_INTERRUPT_STATUS;
+
+typedef enum _GMAC_TX_VLAN_ACTION_ {
+    INTACT			= 0,
+    INSERT_VLAN_HDR = 1,
+    REMOVE_VLAN_HDR = 2,
+    REMARKING_VID   = 3
+}GMAC_TX_VLAN_ACTION, *PGMAC_TX_VLAN_ACTION;
+
+typedef enum _GMAC_RX_PACKET_TYPE_ {
+    TYPE_ETHERNET	= 0,
+    TYPE_IPV4		= 1,
+    TYPE_IPV4_PPTP	= 2,
+    TYPE_IPV4_ICMP	= 3,
+	TYPE_IPV4_IGMP	= 4,
+	TYPE_IPV4_TCP	= 5,
+	TYPE_IPV4_UDP	= 6,
+	TYPE_IPV6		= 7,
+	TYPE_ICMPV6		= 8,
+	TYPE_IPV6_TCP	= 9,
+	TYPE_IPV6_UDP	= 10	
+}GMAC_RX_PACKET_TYPE, *PGMAC_RX_PACKET_TYPE;
+
+
+/*
+
+// Memory Map of DW_apb_ssi
+#define REG_DW_SSI_CTRLR0          0x00  // 16 bits
+#define REG_DW_SSI_CTRLR1          0x04  // 16 bits
+#define REG_DW_SSI_SSIENR          0x08  //  1 bit
+#define REG_DW_SSI_RX_SAMPLE_DLY   0xF0  //  8 bits
+#define REG_DW_SSI_RSVD_0          0xF4  // 32 bits
+#define REG_DW_SSI_RSVD_1          0xF8  // 32 bits
+#define REG_DW_SSI_RSVD_2          0xFC  // 32 bits
+
+// CTRLR0          0x00  // 16 bits, 6.2.1
+// DFS Reset Value: 0x7
+#define BIT_SHIFT_CTRLR0_DFS       0
+#define BIT_MASK_CTRLR0_DFS        0xF
+#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS)
+#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS))
+
+#define BIT_SHIFT_CTRLR0_FRF       4
+#define BIT_MASK_CTRLR0_FRF        0x3
+#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF)
+#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF))
+
+#define BIT_SHIFT_CTRLR0_SCPH      6
+#define BIT_MASK_CTRLR0_SCPH       0x1
+#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH)
+#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH))
+
+// CTRLR1          0x04  // 16 bits
+#define BIT_SHIFT_CTRLR1_NDF    0
+#define BIT_MASK_CTRLR1_NDF     0xFFFF
+#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF)
+#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF))
+
+// TXFLTR          0x18        // Variable Length
+#define BIT_SHIFT_TXFTLR_TFT    0
+#define BIT_MASK_TXFTLR_TFT     0x3F  // (TX_ABW-1):0
+#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT)
+#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT))
+
+// TXFLR           0x20  // see     [READ ONLY]
+#define BIT_MASK_TXFLR_TXTFL    0x7F  // (TX_ABW):0
+
+// RXFLR           0x24  // see     [READ ONLY]
+#define BIT_MASK_RXFLR_RXTFL    0x7F  // (RX_ABW):0
+
+// SR              0x28  //  7 bits [READ ONLY]
+#define BIT_SR_BUSY  BIT0
+#define BIT_SR_TFNF  BIT1
+#define BIT_SR_TFE   BIT2
+#define BIT_SR_RFNE  BIT3
+#define BIT_SR_RFF   BIT4
+#define BIT_SR_TXE   BIT5
+#define BIT_SR_DCOL  BIT6
+
+#define BIT_IMR_TXEIM  BIT0
+#define BIT_IMR_TXOIM  BIT1
+#define BIT_IMR_RXUIM  BIT2
+#define BIT_IMR_RXOIM  BIT3
+#define BIT_IMR_RXFIM  BIT4
+#define BIT_IMR_MSTIM  BIT5
+
+// ISR             0x30  //  6 bits [READ ONLY]
+#define BIT_ISR_TXEIS  BIT0
+#define BIT_ISR_TXOIS  BIT1
+#define BIT_ISR_RXUIS  BIT2
+#define BIT_ISR_RXOIS  BIT3
+#define BIT_ISR_RXFIS  BIT4
+#define BIT_ISR_MSTIS  BIT5
+
+*/
+
+BOOL
+HalMiiGmacInitRtl8195a(
+        IN VOID *Data
+        );
+
+BOOL
+HalMiiInitRtl8195a(
+        IN VOID *Data
+        );
+
+BOOL
+HalMiiGmacResetRtl8195a(
+        IN VOID *Data
+        );
+
+BOOL
+HalMiiGmacEnablePhyModeRtl8195a(
+        IN VOID *Data
+        );
+
+u32
+HalMiiGmacXmitRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalMiiGmacCleanTxRingRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalMiiGmacFillTxInfoRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalMiiGmacFillRxInfoRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalMiiGmacTxRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalMiiGmacRxRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalMiiGmacSetDefaultEthIoCmdRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalMiiGmacInitIrqRtl8195a(
+        IN VOID *Data
+        );
+
+u32
+HalMiiGmacGetInterruptStatusRtl8195a(
+		VOID
+        );
+
+VOID
+HalMiiGmacClearInterruptStatusRtl8195a(
+        u32 IsrStatus
+        );
+
+#endif
+

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_nfc.h

@@ -0,0 +1,153 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_NFC_H_
+#define _RTL8195A_NFC_H_
+
+#include "hal_api.h"
+#include "osdep_api.h"
+#ifdef CONFIG_NFC_VERIFY
+#include "../test/nfc/rtl8195a_nfc_test.h"
+#endif
+
+#if CONFIG_NFC_NORMAL
+//===================== Register Bit Field Definition =====================
+// TODO:
+//===================== Register Address Definition =====================
+//TODO:
+#include "osdep_api.h"
+#define N2A_Q_LENGTH 10
+#define N2ARLENGTH    4
+//#define NFCTAGLENGTH 36 // maximum 36*4=144 bytes
+#define NFCTAG_BASE  0x7F000
+#define NFCTAG_PAGESIZE 256
+#define NFCTAG_MAXPAGEIDX 16//(4*(1024/NFCTAG_PAGESIZE))
+#define A2NWCLENGTH    4
+
+#define FLASHAPPLENGTH 31
+#define FLASHAPP_BASE  0x7E000
+#define FLASH_PAGESIZE 128
+#define FLASH_MAXPAGEIDX 32//(4*(1024/FLASH_PAGESIZE))
+
+typedef struct _A2N_CATCH_W_ {
+    //u8          Vaild;
+    u8          A2NCatchRPage;
+    u32         A2NCatchWData[A2NWCLENGTH];
+}A2N_CATCH_W_QUEUE, *PA2N_CATCH_W_QUEUE;
+
+typedef struct _A2N_MAILBOX_Q_ {
+    u8          Length;
+    u8          Response;
+    u32         Content[A2NWCLENGTH+1];
+}A2N_MAILBOX_Q,*PA2N_MAILBOX_Q;
+
+typedef struct _N2A_CATCH_R_ {
+    u8          Vaild;
+    u8          N2ACatchRPage;
+    u32         N2ACatchRData[N2ARLENGTH];
+}N2A_CATCH_R_QUEUE, *PN2A_CATCH_R_QUEUE;
+
+
+typedef struct _N2A_R_ {
+    u8          Vaild;
+    u8          N2ARPage;
+}N2A_R_QUEUE, *PN2A_R_QUEUE;
+
+typedef struct _N2A_W_ {
+    u8          Vaild;
+    u8          N2AWPage;
+    u32         N2AWData;
+}N2A_W_QUEUE, *PN2A_W_QUEUE;
+
+typedef struct _NFC_ADAPTER_ {
+    u8          Function;
+    u32         NFCIsr;
+    u8          N2ABoxOpen;
+    u8          A2NSeq;
+    //u8          NFCTagFlashWIdx;
+    //u8          NFCTagFlashRIdx;
+//    u32         NFCTag[NFCTAGLENGTH];
+#if !TASK_SCHEDULER_DISABLED
+    _Sema       VeriSema;
+#else
+    u32         VeriSema;
+#endif  
+#ifdef PLATFORM_FREERTOS
+    xTaskHandle NFCTask;
+#else
+    u32         NFCTask;
+#endif
+#ifdef CONFIG_NFC_VERIFY
+    //N2A Write Tag
+    u8          N2AWQRIdx;
+    u8          N2AWQWIdx;
+    N2A_W_QUEUE N2AWQ[N2A_Q_LENGTH];
+    //N2A Read Tag
+    u8          N2ARQRIdx;
+    u8          N2ARQWIdx;
+    N2A_R_QUEUE N2ARQ[N2A_Q_LENGTH];
+    //N2A Read Catch
+    u8          N2ARCRIdx;
+    u8          N2ARCWIdx;
+    N2A_CATCH_R_QUEUE N2ACatchR[N2A_Q_LENGTH];
+#endif
+    //A2N Write Catch
+    //u8          A2NWCRIdx;
+    //u8          A2NWCWIdx;
+    //A2N_CATCH_W_QUEUE A2NCatchW[N2A_Q_LENGTH];
+
+    //A2N Write mailbox queue
+    u8          A2NWMailBox;
+    u8          A2NWQRIdx;
+    u8          A2NWQWIdx;          
+    A2N_MAILBOX_Q A2NMAILQ[N2A_Q_LENGTH];
+
+    u8          TaskStop;
+    void        *nfc_obj;
+}NFC_ADAPTER, *PNFC_ADAPTER;
+
+typedef enum _N2A_CMD_ {
+    TAG_READ            = 0,
+    TAG_WRITE           = 1,
+    CATCH_READ_DATA     = 2,
+    NFC_R_PRESENT       = 4,
+    N2A_MAILBOX_STATE   = 5,
+    EXT_CLK_REQ         = 6,
+    MAX_N2ACMD
+};
+
+typedef enum _A2N_CMD_ {
+    TAG_READ_DATA       = 0,
+    CATCH_READ          = 2,
+    CATCH_WRITE         = 3,
+    A2N_MAILBOX_STATE   = 4,
+    CONFIRM_N2A_BOX_STATE = 5,
+    EXT_CLK_RSP         = 6,
+    MAX_A2NCMD
+};
+
+// Callback event defination
+typedef enum _NFC_HAL_EVENT_ {
+    NFC_HAL_READER_PRESENT = (1<<0),
+    NFC_HAL_READ = (1<<1),
+    NFC_HAL_WRITE = (1<<2),
+    NFC_HAL_ERR = (1<<3),
+    NFC_HAL_CACHE_RD = (1<<4)    
+}NFC_CB_EVENT, *PNFC_CB_EVENT;
+
+VOID A2NWriteCatch(IN VOID *pNFCAdapte, IN u8 N2AWPage,
+    IN u8 Length, IN u32 *WData);
+VOID A2NReadCatch(IN VOID *pNFCAdapte, IN u8   A2NRPage);
+VOID HalNFCDmemInit(IN u32 *pTagData, IN u32 TagLen);
+VOID HalNFCInit(PNFC_ADAPTER pNFCAdp);
+VOID HalNFCDeinit(PNFC_ADAPTER pNFCAdp);
+VOID HalNFCFwDownload(VOID);
+#endif  //CONFIG_NFC_NORMAL
+#endif

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pcm.h

@@ -0,0 +1,449 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_PCM_H_
+#define _RTL8195A_PCM_H_
+
+#include "basic_types.h"
+#include "hal_api.h"
+
+#define HAL_PCMX_READ32(PcmIndex, addr)     \
+                HAL_READ32(PCM0_REG_BASE+ (PcmIndex*PCM1_REG_OFF), addr)
+#define HAL_PCMX_WRITE32(PcmIndex, addr, value)     \
+                HAL_WRITE32((PCM0_REG_BASE+ (PcmIndex*PCM1_REG_OFF)), addr, value)
+
+#define REG_PCM_TRXBSA_OFF     0x004
+#define REG_PCM_CTL            0x000
+#define REG_PCM_CHCNR03        0x004
+#define REG_PCM_TSR03          0x008
+#define REG_PCM_BSIZE03        0x00C
+
+#define REG_PCM_CH0TXBSA       0x010
+#define REG_PCM_CH1TXBSA       0x014
+#define REG_PCM_CH2TXBSA       0x018
+#define REG_PCM_CH3TXBSA       0x01c
+#define REG_PCM_CH0RXBSA       0x020
+#define REG_PCM_CH1RXBSA       0x024
+#define REG_PCM_CH2RXBSA       0x028
+#define REG_PCM_CH3RXBSA       0x02c
+
+#define REG_PCM_IMR03          0x030
+#define REG_PCM_ISR03          0x034
+
+#define REG_PCM_CHCNR47        0x038
+#define REG_PCM_TSR47          0x03c
+#define REG_PCM_BSIZE47        0x040
+#define REG_PCM_CH4TXBSA       0x044
+#define REG_PCM_CH5TXBSA       0x048
+#define REG_PCM_CH6TXBSA       0x04c
+#define REG_PCM_CH7TXBSA       0x050
+#define REG_PCM_CH4RXBSA       0x054
+#define REG_PCM_CH5RXBSA       0x058
+#define REG_PCM_CH6RXBSA       0x05c
+#define REG_PCM_CH7RXBSA       0x060
+
+#define REG_PCM_IMR47          0x064
+#define REG_PCM_ISR47          0x068
+
+#define REG_PCM_CHCNR811       0x06c
+#define REG_PCM_TSR811         0x070
+#define REG_PCM_BSIZE811       0x074
+#define REG_PCM_CH8TXBSA       0x078
+#define REG_PCM_CH9TXBSA       0x07c
+#define REG_PCM_CH10TXBSA      0x080
+#define REG_PCM_CH11TXBSA      0x084
+#define REG_PCM_CH8RXBSA       0x088
+#define REG_PCM_CH9RXBSA       0x08c
+#define REG_PCM_CH10RXBSA      0x090
+#define REG_PCM_CH11RXBSA      0x094
+
+#define REG_PCM_IMR811         0x098
+#define REG_PCM_ISR811         0x09c
+
+#define REG_PCM_CHCNR1215      0x0a0
+#define REG_PCM_TSR1215        0x0a4
+#define REG_PCM_BSIZE1215      0x0a8
+#define REG_PCM_CH12TXBSA      0x0ac
+#define REG_PCM_CH13TXBSA      0x0b0
+#define REG_PCM_CH14TXBSA      0x0b4
+#define REG_PCM_CH15TXBSA      0x0b8
+#define REG_PCM_CH12RXBSA      0x0bc
+#define REG_PCM_CH13RXBSA      0x0c0
+#define REG_PCM_CH14RXBSA      0x0c4
+#define REG_PCM_CH15RXBSA      0x0c8
+
+#define REG_PCM_IMR1215        0x0cc
+#define REG_PCM_ISR1215        0x0d0
+
+#define REG_PCM_INTMAP         0x0d4
+#define REG_PCM_WTSR03         0x0d8
+#define REG_PCM_WTSR47         0x0dc
+
+#define REG_PCM_RX_BUFOW       0x0e0
+
+/* template 
+#define BIT_SHIFT_CTLX_ 7
+#define BIT_MASK_CTLX_  0x1
+#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
+#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
+*/
+#define BIT_SHIFT_CTLX_SLAVE_SEL 8
+#define BIT_MASK_CTLX_SLAVE_SEL  0x1
+#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
+#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
+
+#define BIT_SHIFT_CTLX_FSINV 9
+#define BIT_MASK_CTLX_FSINV 0x1
+#define BIT_CTLX_FSINV(x) (((x) & BIT_MASK_CTLX_FSINV) << BIT_SHIFT_CTLX_FSINV)
+#define BIT_INV_CTLX_FSINV (~(BIT_MASK_CTLX_FSINV << BIT_SHIFT_CTLX_FSINV))
+
+#define BIT_SHIFT_CTLX_PCM_EN 12
+#define BIT_MASK_CTLX_PCM_EN  0x1
+#define BIT_CTLX_PCM_EN(x) (((x) & BIT_MASK_CTLX_PCM_EN) << BIT_SHIFT_CTLX_PCM_EN)
+#define BIT_INV_CTLX_PCM_EN (~(BIT_MASK_CTLX_PCM_EN << BIT_SHIFT_CTLX_PCM_EN))
+
+#define BIT_SHIFT_CTLX_LINEARMODE 13
+#define BIT_MASK_CTLX_LINEARMODE  0x1
+#define BIT_CTLX_LINEARMODE(x) (((x) & BIT_MASK_CTLX_LINEARMODE) << BIT_SHIFT_CTLX_LINEARMODE)
+#define BIT_INV_CTLX_LINEARMODE (~(BIT_MASK_CTLX_LINEARMODE << BIT_SHIFT_CTLX_LINEARMODE))
+
+#define BIT_SHIFT_CTLX_LOOP_BACK 14
+#define BIT_MASK_CTLX_LOOP_BACK  0x1
+#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
+#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
+
+#define BIT_SHIFT_CTLX_ENDIAN_SWAP 17
+#define BIT_MASK_CTLX_ENDIAN_SWAP  0x1
+#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
+#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
+
+#define BIT_SHIFT_CHCNR03_CH0RE 24
+#define BIT_MASK_CHCNR03_CH0RE  0x1
+#define BIT_CHCNR03_CH0RE(x) (((x) & BIT_MASK_CHCNR03_CH0RE) << BIT_SHIFT_CHCNR03_CH0RE)
+#define BIT_INV_CHCNR03_CH0RE (~(BIT_MASK_CHCNR03_CH0RE << BIT_SHIFT_CHCNR03_CH0RE))
+
+#define BIT_SHIFT_CHCNR03_CH0TE 25
+#define BIT_MASK_CHCNR03_CH0TE  0x1
+#define BIT_CHCNR03_CH0TE(x) (((x) & BIT_MASK_CHCNR03_CH0TE) << BIT_SHIFT_CHCNR03_CH0TE)
+#define BIT_INV_CHCNR03_CH0TE (~(BIT_MASK_CHCNR03_CH0TE << BIT_SHIFT_CHCNR03_CH0TE))
+
+#define BIT_SHIFT_CHCNR03_CH1RE 16
+#define BIT_MASK_CHCNR03_CH1RE  0x1
+#define BIT_CHCNR03_CH1RE(x) (((x) & BIT_MASK_CHCNR03_CH1RE) << BIT_SHIFT_CHCNR03_CH1RE)
+#define BIT_INV_CHCNR03_CH1RE (~(BIT_MASK_CHCNR03_CH1RE << BIT_SHIFT_CHCNR03_CH1RE))
+
+#define BIT_SHIFT_CHCNR03_CH1TE 17
+#define BIT_MASK_CHCNR03_CH1TE  0x1
+#define BIT_CHCNR03_CH1TE(x) (((x) & BIT_MASK_CHCNR03_CH1TE) << BIT_SHIFT_CHCNR03_CH1TE)
+#define BIT_INV_CHCNR03_CH1TE (~(BIT_MASK_CHCNR03_CH1TE << BIT_SHIFT_CHCNR03_CH1TE))
+
+#define BIT_SHIFT_CHCNR03_CH2RE 8
+#define BIT_MASK_CHCNR03_CH2RE  0x1
+#define BIT_CHCNR03_CH2RE(x) (((x) & BIT_MASK_CHCNR03_CH2RE) << BIT_SHIFT_CHCNR03_CH2RE)
+#define BIT_INV_CHCNR03_CH2RE (~(BIT_MASK_CHCNR03_CH2RE << BIT_SHIFT_CHCNR03_CH2RE))
+
+#define BIT_SHIFT_CHCNR03_CH2TE 9
+#define BIT_MASK_CHCNR03_CH2TE  0x1
+#define BIT_CHCNR03_CH2TE(x) (((x) & BIT_MASK_CHCNR03_CH2TE) << BIT_SHIFT_CHCNR03_CH2TE)
+#define BIT_INV_CHCNR03_CH2TE (~(BIT_MASK_CHCNR03_CH2TE << BIT_SHIFT_CHCNR03_CH2TE))
+
+#define BIT_SHIFT_CHCNR03_CH3RE 0
+#define BIT_MASK_CHCNR03_CH3RE  0x1
+#define BIT_CHCNR03_CH3RE(x) (((x) & BIT_MASK_CHCNR03_CH3RE) << BIT_SHIFT_CHCNR03_CH3RE)
+#define BIT_INV_CHCNR03_CH3RE (~(BIT_MASK_CHCNR03_CH3RE << BIT_SHIFT_CHCNR03_CH3RE))
+
+#define BIT_SHIFT_CHCNR03_CH3TE 1
+#define BIT_MASK_CHCNR03_CH3TE  0x1
+#define BIT_CHCNR03_CH3TE(x) (((x) & BIT_MASK_CHCNR03_CH3TE) << BIT_SHIFT_CHCNR03_CH3TE)
+#define BIT_INV_CHCNR03_CH3TE (~(BIT_MASK_CHCNR03_CH3TE << BIT_SHIFT_CHCNR03_CH3TE))
+
+#define BIT_SHIFT_CHCNR03_CH0MUA 26
+#define BIT_MASK_CHCNR03_CH0MUA  0x1
+#define BIT_CHCNR03_CH0MUA(x) (((x) & BIT_MASK_CHCNR03_CH0MUA) << BIT_SHIFT_CHCNR03_CH0MUA)
+#define BIT_INV_CHCNR03_CH0MUA (~(BIT_MASK_CHCNR03_CH0MUA << BIT_SHIFT_CHCNR03_CH0MUA))
+
+#define BIT_SHIFT_CHCNR03_CH0BAND 27
+#define BIT_MASK_CHCNR03_CH0BAND  0x1
+#define BIT_CHCNR03_CH0BAND(x) (((x) & BIT_MASK_CHCNR03_CH0BAND) << BIT_SHIFT_CHCNR03_CH0BAND)
+#define BIT_INV_CHCNR03_CH0BAND (~(BIT_MASK_CHCNR03_CH0BAND << BIT_SHIFT_CHCNR03_CH0BAND))
+
+#define BIT_SHIFT_TSR03_CH0TSA 24
+#define BIT_MASK_TSR03_CH0TSA  0x1F
+#define BIT_TSR03_CH0TSA(x) (((x) & BIT_MASK_TSR03_CH0TSA) << BIT_SHIFT_TSR03_CH0TSA)
+#define BIT_INV_TSR03_CH0TSA (~(BIT_MASK_TSR03_CH0TSA << BIT_SHIFT_TSR03_CH0TSA))
+
+#define BIT_SHIFT_BSIZE03_CH0BSIZE 24
+#define BIT_MASK_BSIZE03_CH0BSIZE  0xFF
+#define BIT_BSIZE03_CH0BSIZE(x) (((x) & BIT_MASK_BSIZE03_CH0BSIZE) << BIT_SHIFT_BSIZE03_CH0BSIZE)
+#define BIT_INV_BSIZE03_CH0BSIZE (~(BIT_MASK_BSIZE03_CH0BSIZE << BIT_SHIFT_BSIZE03_CH0BSIZE))
+
+typedef struct _PCM_CTL_REG_ {
+    u32                    FCNT           :8; // Bit 0-7
+    u32                    SlaveMode      :1; // Bit 8
+    u32                    FsInv          :1; // Bit 9 
+    u32                    Rsvd10to11     :1; // Bit 10-11
+    u32                    Pcm_En         :1; // Bit 12
+    u32                    LinearMode     :1; // Bit 13
+    u32                    LoopBack       :1; // Bit 14
+    u32                    Rsvd15to16     :2; // Bit 15-16
+    u32                    EndianSwap     :1; // Bit 17
+    u32                    Rsvd18to31    :14; // Bit 18-31
+} PCM_CTL_REG, *PPCM_CTL_REG;
+
+
+
+typedef struct _PCM_CHCNR03_REG_ {
+    u32                      CH3RE     :1; // Bit 0
+    u32                      CH3TE     :1; // Bit 1
+    u32                      CH3MuA    :1; // Bit 2
+    u32                      CH3Band   :1; // Bit 3
+    u32                      CH3SlicSel:4; // Bit 4-7
+    u32                      CH2RE     :1; // Bit 8
+    u32                      CH2TE     :1; // Bit 9
+    u32                      CH2MuA    :1; // Bit 10
+    u32                      CH2Band   :1; // Bit 11
+    u32                      CH2SlicSel:4; // Bit 12-15
+    u32                      CH1RE     :1; // Bit 16
+    u32                      CH1TE     :1; // Bit 17
+    u32                      CH1MuA    :1; // Bit 18
+    u32                      CH1Band   :1; // Bit 19
+    u32                      CH1SlicSel:4; // Bit 20-23
+    u32                      CH0RE     :1; // Bit 24
+    u32                      CH0TE     :1; // Bit 25
+    u32                      CH0MuA    :1; // Bit 26
+    u32                      CH0Band   :1; // Bit 27
+    u32                      CH0SlicSel:4; // Bit 28-31
+}PCM_CHCNR03_REG, *PPCM_CHCNR03_REG;
+
+typedef struct _PCM_TSR03_REG_ {
+    u32                      CH3TSA    :5; // Bit 0-4
+    u32                      Rsvd5to7  :3; // Bit 5-7
+    u32                      CH2TSA    :5; // Bit 8-12
+    u32                      Rsvd13to15:3; // Bit 13-15
+    u32                      CH1TSA    :5; // Bit 16-20
+    u32                      Rsvd21to23:3; // Bit 21-23
+    u32                      CH0TSA    :5; // Bit 24-28
+    u32                      Rsvd29to31:3; // Bit 29-31
+}PCM_TSR03_REG, *PPCM_TSR03_REG;
+
+typedef struct _PCM_BSIZE03_REG_ {
+    u32                      CH3BSize  :8; // Bit 0-7
+    u32                      CH2BSize  :8; // Bit 8-15
+    u32                      CH1BSize  :8; // Bit 16-23
+    u32                      CH0BSize  :8; // Bit 24-31
+}PCM_BSIZE03_REG, *PPCM_BSIZE03_REG;
+
+typedef struct _PCM_ISR03_REG_ {
+    u32                      CH3RXP1UA :1; // Bit 0
+    u32                      CH3RXP0UA :1; // Bit 1
+    u32                      CH3TXP1UA :1; // Bit 2
+    u32                      CH3TXP0UA :1; // Bit 3
+    u32                      CH3RXP1IP :1; // Bit 4
+    u32                      CH3RXP0IP :1; // Bit 5
+    u32                      CH3TXP1IP :1; // Bit 6
+    u32                      CH3TXP0IP :1; // Bit 7
+    u32                      CH2RXP1UA :1; // Bit 8
+    u32                      CH2RXP0UA :1; // Bit 9
+    u32                      CH2TXP1UA :1; // Bit 10
+    u32                      CH2TXP0UA :1; // Bit 11
+    u32                      CH2RXP1IP :1; // Bit 12
+    u32                      CH2RXP0IP :1; // Bit 13
+    u32                      CH2TXP1IP :1; // Bit 14
+    u32                      CH2TXP0IP :1; // Bit 15
+    u32                      CH1RXP1UA :1; // Bit 16
+    u32                      CH1RXP0UA :1; // Bit 17
+    u32                      CH1TXP1UA :1; // Bit 18
+    u32                      CH1TXP0UA :1; // Bit 19
+    u32                      CH1RXP1IP :1; // Bit 20
+    u32                      CH1RXP0IP :1; // Bit 21
+    u32                      CH1TXP1IP :1; // Bit 22
+    u32                      CH1TXP0IP :1; // Bit 23
+    u32                      CH0RXP1UA :1; // Bit 24
+    u32                      CH0RXP0UA :1; // Bit 25
+    u32                      CH0TXP1UA :1; // Bit 26
+    u32                      CH0TXP0UA :1; // Bit 27
+    u32                      CH0RXP1IP :1; // Bit 28
+    u32                      CH0RXP0IP :1; // Bit 29
+    u32                      CH0TXP1IP :1; // Bit 30
+    u32                      CH0TXP0IP :1; // Bit 31
+}PCM_ISR03_REG, *PPCM_ISR03_REG;
+
+typedef enum _PCM_ISR015 {
+    PcmCh3P1RBU          = 0x00000001, //ch0-3
+    PcmCh3P0RBU          = 0x00000002,
+    PcmCh3P1TBU          = 0x00000004,
+    PcmCh3P0TBU          = 0x00000008,
+    PcmCh3P1ROK          = 0x00000010,
+    PcmCh3P0ROK          = 0x00000020,
+    PcmCh3P1TOK          = 0x00000040,
+    PcmCh3P0TOK          = 0x00000080,
+    PcmCh2P1RBU          = 0x00000100,
+    PcmCh2P0RBU          = 0x00000200,
+    PcmCh2P1TBU          = 0x00000400,
+    PcmCh2P0TBU          = 0x00000800,
+    PcmCh2P1ROK          = 0x00001000,
+    PcmCh2P0ROK          = 0x00002000,
+    PcmCh2P1TOK          = 0x00004000,
+    PcmCh2P0TOK          = 0x00008000,
+    PcmCh1P1RBU          = 0x00010000,
+    PcmCh1P0RBU          = 0x00020000,
+    PcmCh1P1TBU          = 0x00040000,
+    PcmCh1P0TBU          = 0x00080000,
+    PcmCh1P1ROK          = 0x00100000,
+    PcmCh1P0ROK          = 0x00200000,
+    PcmCh1P1TOK          = 0x00400000,
+    PcmCh1P0TOK          = 0x00800000,
+    PcmCh0P1RBU          = 0x01000000,
+    PcmCh0P0RBU          = 0x02000000,
+    PcmCh0P1TBU          = 0x04000000,
+    PcmCh0P0TBU          = 0x08000000,
+    PcmCh0P1ROK          = 0x10000000,
+    PcmCh0P0ROK          = 0x20000000,
+    PcmCh0P1TOK          = 0x40000000,
+    PcmCh0P0TOK          = 0x80000000,
+
+    PcmCh7P1RBU          = 0x00000001, //ch4-7
+    PcmCh7P0RBU          = 0x00000002,
+    PcmCh7P1TBU          = 0x00000004,
+    PcmCh7P0TBU          = 0x00000008,
+    PcmCh7P1ROK          = 0x00000010,
+    PcmCh7P0ROK          = 0x00000020,
+    PcmCh7P1TOK          = 0x00000040,
+    PcmCh7P0TOK          = 0x00000080,
+    PcmCh6P1RBU          = 0x00000100,
+    PcmCh6P0RBU          = 0x00000200,
+    PcmCh6P1TBU          = 0x00000400,
+    PcmCh6P0TBU          = 0x00000800,
+    PcmCh6P1ROK          = 0x00001000,
+    PcmCh6P0ROK          = 0x00002000,
+    PcmCh6P1TOK          = 0x00004000,
+    PcmCh6P0TOK          = 0x00008000,
+    PcmCh5P1RBU          = 0x00010000,
+    PcmCh5P0RBU          = 0x00020000,
+    PcmCh5P1TBU          = 0x00040000,
+    PcmCh5P0TBU          = 0x00080000,
+    PcmCh5P1ROK          = 0x00100000,
+    PcmCh5P0ROK          = 0x00200000,
+    PcmCh5P1TOK          = 0x00400000,
+    PcmCh5P0TOK          = 0x00800000,
+    PcmCh4P1RBU          = 0x01000000,
+    PcmCh4P0RBU          = 0x02000000,
+    PcmCh4P1TBU          = 0x04000000,
+    PcmCh4P0TBU          = 0x08000000,
+    PcmCh4P1ROK          = 0x10000000,
+    PcmCh4P0ROK          = 0x20000000,
+    PcmCh4P1TOK          = 0x40000000,
+    PcmCh4P0TOK          = 0x80000000,
+
+    PcmCh11P1RBU         = 0x00000001, //ch8-11
+    PcmCh11P0RBU         = 0x00000002,
+    PcmCh11P1TBU         = 0x00000004,
+    PcmCh11P0TBU         = 0x00000008,
+    PcmCh11P1ROK         = 0x00000010,
+    PcmCh11P0ROK         = 0x00000020,
+    PcmCh11P1TOK         = 0x00000040,
+    PcmCh11P0TOK         = 0x00000080,
+    PcmCh10P1RBU         = 0x00000100,
+    PcmCh10P0RBU         = 0x00000200,
+    PcmCh10P1TBU         = 0x00000400,
+    PcmCh10P0TBU         = 0x00000800,
+    PcmCh10P1ROK         = 0x00001000,
+    PcmCh10P0ROK         = 0x00002000,
+    PcmCh10P1TOK         = 0x00004000,
+    PcmCh10P0TOK         = 0x00008000,
+    PcmCh9P1RBU          = 0x00010000,
+    PcmCh9P0RBU          = 0x00020000,
+    PcmCh9P1TBU          = 0x00040000,
+    PcmCh9P0TBU          = 0x00080000,
+    PcmCh9P1ROK          = 0x00100000,
+    PcmCh9P0ROK          = 0x00200000,
+    PcmCh9P1TOK          = 0x00400000,
+    PcmCh9P0TOK          = 0x00800000,
+    PcmCh8P1RBU          = 0x01000000,
+    PcmCh8P0RBU          = 0x02000000,
+    PcmCh8P1TBU          = 0x04000000,
+    PcmCh8P0TBU          = 0x08000000,
+    PcmCh8P1ROK          = 0x10000000,
+    PcmCh8P0ROK          = 0x20000000,
+    PcmCh8P1TOK          = 0x40000000,
+    PcmCh8P0TOK          = 0x80000000,
+
+    PcmCh15P1RBU         = 0x00000001, //ch12-15
+    PcmCh15P0RBU         = 0x00000002,
+    PcmCh15P1TBU         = 0x00000004,
+    PcmCh15P0TBU         = 0x00000008,
+    PcmCh15P1ROK         = 0x00000010,
+    PcmCh15P0ROK         = 0x00000020,
+    PcmCh15P1TOK         = 0x00000040,
+    PcmCh15P0TOK         = 0x00000080,
+    PcmCh14P1RBU         = 0x00000100,
+    PcmCh14P0RBU         = 0x00000200,
+    PcmCh14P1TBU         = 0x00000400,
+    PcmCh14P0TBU         = 0x00000800,
+    PcmCh14P1ROK         = 0x00001000,
+    PcmCh14P0ROK         = 0x00002000,
+    PcmCh14P1TOK         = 0x00004000,
+    PcmCh14P0TOK         = 0x00008000,
+    PcmCh13P1RBU         = 0x00010000,
+    PcmCh13P0RBU         = 0x00020000,
+    PcmCh13P1TBU         = 0x00040000,
+    PcmCh13P0TBU         = 0x00080000,
+    PcmCh13P1ROK         = 0x00100000,
+    PcmCh13P0ROK         = 0x00200000,
+    PcmCh13P1TOK         = 0x00400000,
+    PcmCh13P0TOK         = 0x00800000,
+    PcmCh12P1RBU         = 0x01000000,
+    PcmCh12P0RBU         = 0x02000000,
+    PcmCh12P1TBU         = 0x04000000,
+    PcmCh12P0TBU         = 0x08000000,
+    PcmCh12P1ROK         = 0x10000000,
+    PcmCh12P0ROK         = 0x20000000,
+    PcmCh12P1TOK         = 0x40000000,
+    PcmCh12P0TOK         = 0x80000000
+}PCM_ISR015, *PPCM_ISR015;
+
+VOID
+HalPcmOnOffRtl8195a(
+    IN  VOID              *Data
+);
+
+BOOL
+HalPcmInitRtl8195a(
+    IN  VOID		  *Data
+);
+
+BOOL
+HalPcmSettingRtl8195a(
+    IN  VOID		  *Data
+);
+
+BOOL
+HalPcmEnRtl8195a(
+    IN  VOID		  *Data
+);
+
+BOOL
+HalPcmIsrEnAndDisRtl8195a(
+    IN  VOID		  *Data
+);
+
+BOOL
+HalPcmDumpRegRtl8195a(
+    IN  VOID		  *Data
+);
+
+BOOL
+HalPcmRtl8195a(
+    IN  VOID		  *Data
+);
+
+#endif /* _RTL8195A_PCM_H_ */
+
+

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h

@@ -0,0 +1,37 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_PWM_H_
+#define _RTL8195A_PWM_H_
+
+extern void
+HAL_Pwm_SetDuty_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt,
+    u32 period,
+    u32 pulse_width
+);
+
+extern HAL_Status 
+HAL_Pwm_Init_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt
+);
+
+extern void 
+HAL_Pwm_Enable_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt
+);
+
+extern void 
+HAL_Pwm_Disable_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt
+);
+
+
+#endif

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h

@@ -0,0 +1,946 @@
+	/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_SDIO_H_
+#define _RTL8195A_SDIO_H_
+
+#include "hal_api.h"
+#include "hal_util.h"
+#if defined(CONFIG_SDIO_BOOT_SIM) || defined(CONFIG_SDIO_BOOT_ROM)
+#define SDIO_BOOT_DRIVER                            1   // is this SDIO driver works for booting
+#else
+#include "osdep_api.h"
+#define SDIO_BOOT_DRIVER                            0   // is this SDIO driver works for booting
+#endif
+#define SDIO_DEBUG									1
+#define SDIO_MP_MODE								1	// if includes MP mode function
+#define SDIO_MAX_WAIT_RX_DMA						100	// Wait RX DMA done
+#define SDIO_RX_PKT_SIZE_OVER_16K					0	/* is support SDIO RX packet size > 16K. if true, 
+															a big packet will be transmited via multiple RX_BD */
+#define SDIO_MAILBOX_SIZE                           10  // the maximum number of message block can be stored in this mailbox
+#define SDIO_PERIODICAL_TIMER_INTERVAL              2000    // in ms, the interval of SDIO periodical timer
+#define SDIO_AVG_TP_WIN_SIZE                        20      // the number of entry to log the byte count for every periodical timer statistic, to calculate throughput
+
+#define HAL_SDIO_READ32(addr)            			HAL_READ32(SDIO_DEVICE_REG_BASE, addr)
+#define HAL_SDIO_WRITE32(addr, value)    			HAL_WRITE32(SDIO_DEVICE_REG_BASE, addr, value)
+#define HAL_SDIO_READ16(addr)						HAL_READ16(SDIO_DEVICE_REG_BASE, addr)
+#define HAL_SDIO_WRITE16(addr, value)    			HAL_WRITE16(SDIO_DEVICE_REG_BASE, addr, value)
+#define HAL_SDIO_READ8(addr)						HAL_READ8(SDIO_DEVICE_REG_BASE, addr)
+#define HAL_SDIO_WRITE8(addr, value)    			HAL_WRITE8(SDIO_DEVICE_REG_BASE, addr, value)
+
+/*****  Register Address *****/
+#define REG_SPDIO_TXBD_ADDR 						0xA0        // 4 Bytes
+#define REG_SPDIO_TXBD_SIZE							0xA4        // 4 Bytes
+#define REG_SPDIO_TXBD_WPTR							0xA8        // 2 Bytes
+#define REG_SPDIO_TXBD_RPTR							0xAC        // 2 Bytes
+#define REG_SPDIO_RXBD_ADDR							0xB0		// 4 Bytes
+#define REG_SPDIO_RXBD_SIZE							0xB4		// 2 Bytes
+#define REG_SPDIO_RXBD_C2H_WPTR						0xB6		// 2 Bytes
+#define REG_SPDIO_RXBD_C2H_RPTR						0xB8		// 2 Bytes
+#define REG_SPDIO_HCI_RX_REQ						0xBA		// 1 Byte
+#define REG_SPDIO_CPU_RST_DMA						0xBB		// 1 Byte
+#define REG_SPDIO_RX_REQ_ADDR						0xBC		// 2 Bytes
+#define REG_SPDIO_CPU_INT_MASK						0xC0		// 2 Bytes
+#define REG_SPDIO_CPU_INT_STAS						0xC2		// 2 Bytes
+#define REG_SPDIO_CCPWM								0xC4		// 1 Byts
+#define REG_SPDIO_CPU_IND							0xC5		// 1 Byte
+#define REG_SPDIO_CCPWM2							0xC6		// 2 Bytes
+#define REG_SPDIO_CPU_H2C_MSG						0xC8		// 4 Bytes
+#define REG_SPDIO_CPU_C2H_MSG						0xCC		// 4 Bytes
+#define REG_SPDIO_CRPWM								0xD0		// 1 Bytes
+#define REG_SPDIO_CRPWM2							0xD2		// 2 Bytes
+#define REG_SPDIO_AHB_DMA_CTRL						0xD4		// 4 Bytes
+#define REG_SPDIO_RXBD_CNT					        0xD8		// 4 Bytes
+#define REG_SPDIO_TX_BUF_UNIT_SZ			        0xD9		// 1 Bytes
+#define REG_SPDIO_RX_BD_FREE_CNT			        0xDA		// 2 Bytes
+#define REG_SPDIO_CPU_H2C_MSG_EXT					0xDC		// 4 Bytes
+#define REG_SPDIO_CPU_C2H_MSG_EXT					0xE0		// 4 Bytes
+
+// Register REG_SPDIO_CPU_RST_DMA
+#define BIT_CPU_RST_SDIO_DMA						BIT(7)
+
+// Register REG_SPDIO_CPU_INT_MASK, REG_SPDIO_CPU_INT_STAS
+#define BIT_TXFIFO_H2C_OVF							BIT(0)
+#define BIT_H2C_BUS_RES_FAIL						BIT(1)
+#define BIT_H2C_DMA_OK								BIT(2)
+#define BIT_C2H_DMA_OK								BIT(3)
+#define BIT_H2C_MSG_INT								BIT(4)
+#define BIT_RPWM1_INT								BIT(5)
+#define BIT_RPWM2_INT								BIT(6)
+#define BIT_SDIO_RST_CMD_INT						BIT(7)
+#define BIT_RXBD_FLAG_ERR_INT						BIT(8)
+#define BIT_RX_BD_AVAI_INT							BIT(9)
+#define BIT_HOST_WAKE_CPU_INT						BIT(10)
+
+// Register REG_SPDIO_CPU_IND
+#define BIT_SYSTEM_TRX_RDY_IND						BIT(0)
+
+// Register REG_SPDIO_HCI_RX_REQ
+#define BIT_HCI_RX_REQ								BIT(0)
+
+/* Register for SOC_HCI_COM_FUN_EN */
+#define BIT_SOC_HCI_SDIOD_OFF_EN					BIT(1)		// SDIO Function Block on Power_Off domain
+#define BIT_SOC_HCI_SDIOD_ON_EN						BIT(0)		// SDIO Function Block on Power_On domain
+
+/* Register REG_PESOC_HCI_CLK_CTRL0 */
+#define BIT_SOC_SLPCK_SDIO_HST_EN					BIT(3)		// SDIO_HST clock enable when CPU sleep command 
+#define BIT_SOC_ACTCK_SDIO_HST_EN					BIT(2)		// SDIO_HST clock enable in CPU run mode 
+#define BIT_SOC_SLPCK_SDIO_DEV_EN					BIT(1)		// SDIO_DEV clock enable when CPU sleep command
+#define BIT_SOC_ACTCK_SDIO_DEV_EN					BIT(0)		// SDIO_DEV clock enable in CPU run mode
+
+/***** Structer for each Register *****/
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+// Little Endian
+// Register REG_SPDIO_HCI_RX_REQ @ 0xBA
+typedef struct _SPDIO_HCI_RX_REQ {
+	u8 HCI_RX_REQ:1;		/* bit[0], CPU trigger this bit to enable SDIO IP RX transfer by fetch BD info */
+	u8 Reserved:7;			/* bit[7:1], Reserved */
+} SPDIO_HCI_RX_REQ, *PSPDIO_HCI_RX_REQ;
+
+// Register REG_SPDIO_CPU_RST_DMA @ 0xBB
+typedef struct _SPDIO_CPU_RST_DMA {
+	u8 Reserved:7;			/* bit[6:0], Reserved */
+	u8 CPU_RST_SDIO:1;		/* bit[7], CPU set this bit to reset SDIO DMA */
+} SPDIO_CPU_RST_DMA, *PSPDIO_CPU_RST_DMA;
+
+// Register REG_SPDIO_CPU_INT_MASK @ 0xC0
+typedef struct _SPDIO_CPU_INT_MASK {
+	u16 TXFIFO_H2C_OVF:1;		/* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */
+	u16 H2C_BUS_RES_FAIL:1;		/* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */
+	u16 H2C_DMA_OK:1;			/* bit[2], set 0 to mask H2C_DMA_OK_INT */
+	u16 C2H_DMA_OK:1;			/* bit[3], set 0 to mask C2H_DMA_OK_INT */
+	u16 H2C_MSG_INT:1;			/* bit[4], set 0 to mask H2C_MSG_INT_INT */
+	u16 RPWM_INT:1;				/* bit[5], set 0 to mask RPWM_INT */
+	u16 RPWM2_INT:1;			/* bit[6], set 0 to mask RPWM2_INT */
+	u16 SDIO_RST_CMD_INT:1;		/* bit[7], set 0 to mask SDIO_RST_CMD_INT */
+	u16 BD_FLAG_ERR_INT:1;		/* bit[8], set 0 to mask BD_FLAG_ERR_INT */
+	u16 Reserved:7;				/* bit[15:9], Reserved */
+} SPDIO_CPU_INT_MASK, *PSPDIO_CPU_INT_MASK;
+
+// Register REG_SPDIO_CPU_INT_STATUS @ 0xC2
+typedef struct _SPDIO_CPU_INT_STAS {
+	u16 TXFIFO_H2C_OVF:1;		/* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */
+	u16 H2C_BUS_RES_FAIL:1;		/* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */
+	u16 H2C_DMA_OK:1;			/* bit[2], set 0 to mask H2C_DMA_OK_INT */
+	u16 C2H_DMA_OK:1;			/* bit[3], set 0 to mask C2H_DMA_OK_INT */
+	u16 H2C_MSG_INT:1;			/* bit[4], set 0 to mask H2C_MSG_INT_INT */
+	u16 RPWM_INT:1;				/* bit[5], set 0 to mask RPWM_INT */
+	u16 RPWM2_INT:1;			/* bit[6], set 0 to mask RPWM2_INT */
+	u16 SDIO_RST_CMD_INT:1;		/* bit[7], set 0 to mask SDIO_RST_CMD_INT */
+	u16 BD_FLAG_ERR_INT:1;		/* bit[8], set 0 to mask BD_FLAG_ERR_INT */
+	u16 Reserved:7;				/* bit[15:9], Reserved */
+} SPDIO_CPU_INT_STAS, *PSPDIO_CPU_INT_STAS;
+
+// Register REG_SPDIO_CCPWM @ 0xC4
+typedef struct _SPDIO_CCPWM {
+	u8 :1;					/* bit[0] */
+	u8 WLAN_TRX:1;			/* bit[1], 0: WLAN Off; 1: WLAN On */
+	u8 RPS_ST:1;			/* bit[2], 0/1: AP Register Sleep/Active state */
+	u8 WWLAN:1;				/* bit[3], 0/1: "Wake on WLAN"/"Normal" state */
+	u8 Reserved:3;			/* bit[6:4], Reserved */
+	u8 TOGGLING:1;			/* bit[7], issue interrupt when 0->1 or 1->0 */
+} SPDIO_CCPWM, *PSPDIO_CCPWM;
+
+// Register REG_SPDIO_CPU_IND @ 0xC5
+typedef struct _SPDIO_CPU_IND {
+	u8 SYS_TRX_RDY:1;		/* bit[0], To indicate the Host system that CPU is ready for TRX
+								, to be sync to 0x87[0] */
+	u8 Reserved:7;			/* bit[7:1], Reserved */
+} SPDIO_CPU_IND, *PSPDIO_CPU_IND;
+
+// Register REG_SPDIO_CPU_H2C_MSG @ 0xC8
+typedef struct _SPDIO_CPU_H2C_MSG {
+	u32 CPU_H2C_MSG:30;		/* bit[30:0], Host CPU to FW message, sync from REG_SDIO_H2C_MSG */
+	u32 Reserved:1;			/* bit[31], Reserved */
+} SPDIO_CPU_H2C_MSG, *PSPDIO_CPU_H2C_MSG;
+
+// Register REG_SPDIO_CPU_C2H_MSG @ 0xCC
+typedef struct _SPDIO_CPU_C2H_MSG {
+	u32 CPU_C2H_MSG:30;		/* bit[30:0], FW to Host CPU message, sync to REG_SDIO_C2H_MSG */
+	u32 Reserved:1;			/* bit[31], Reserved */
+} SPDIO_CPU_C2H_MSG, *PSPDIO_CPU_C2H_MSG;
+
+// Register REG_SPDIO_CRPWM @ 0xD0
+typedef struct _SPDIO_CRPWM {
+	u8 :1;					/* bit[0] */
+	u8 WLAN_TRX:1;			/* bit[1], 0: WLAN Off; 1: WLAN On */
+	u8 RPS_ST:1;			/* bit[2], 0/1: AP Register Sleep/Active state */
+	u8 WWLAN:1;				/* bit[3], 0/1: "Wake on WLAN"/"Normal" state */
+	u8 Reserved:3;			/* bit[6:4], Reserved */
+	u8 TOGGLING:1;			/* bit[7], issue interrupt when 0->1 or 1->0 */
+} SPDIO_CRPWM, *PSPDIO_CRPWM;
+
+// Register REG_SPDIO_AHB_DMA_CTRL @ 0xD4
+typedef struct _SPDIO_AHB_DMA_CTRL {
+	u32 TXFF_WLEVEL:7;		/* bit[6:0], SPDIO TX FIFO water level */
+	u32 :1;					/* bit[7] */
+	u32 RXFF_WLEVEL:7;		/* bit[14:8], SPDIO RX FIFO water level */
+	u32 :1;					/* bit[15] */
+	u32 AHB_DMA_CS:4;		/* bit[19:16], AHB DMA state */
+	u32 :1;					/* bit[20] */
+	u32 AHB_MASTER_RDY:1;	/* bit[21], AHB Master Hready signal */
+	u32 AHB_DMA_TRANS:2;	/* bit[23:22], AHB DMA Trans value, for debugging */
+	u32 AHB_BUSY_WAIT_CNT:4;	/* bit[27:24], timeout for AHB controller to wait busy */
+	u32 AHB_BURST_TYPE:3;	/* bit[30:28], AHB burst type */
+	u32 DISPATCH_TXAGG:1;	/* bit[31], Enable to dispatch aggregated TX packet */
+} SPDIO_AHB_DMA_CTRL, *PSPDIO_AHB_DMA_CTRL;
+
+#else	/* else of '#if LITTLE_ENDIAN' */
+// Big Endian
+typedef struct _SPDIO_HCI_RX_REQ {
+	u8 Reserved:7;		/* bit[7:1], Reserved */
+	u8 HCI_RX_REQ:1;		/* bit[0], CPU trigger this bit to enable SDIO IP RX transfer by fetch BD info */
+} SPDIO_HCI_RX_REQ, *PSPDIO_HCI_RX_REQ;
+
+// Register REG_SPDIO_CPU_RST_DMA @ 0xBB
+typedef struct _SPDIO_CPU_RST_DMA {
+	u8 CPU_RST_SDIO:1;		/* bit[7], CPU set this bit to reset SDIO DMA */
+	u8 Reserved:7;			/* bit[6:0], Reserved */
+} SPDIO_CPU_RST_DMA, *PSPDIO_CPU_RST_DMA;
+
+// Register REG_SPDIO_CPU_INT_MASK @ 0xC0
+typedef struct _SPDIO_CPU_INT_MASK {
+	u16 Reserved:7;				/* bit[15:9], Reserved */
+	u16 BD_FLAG_ERR_INT:1;		/* bit[8], set 0 to mask BD_FLAG_ERR_INT */
+	u16 SDIO_RST_CMD_INT:1;		/* bit[7], set 0 to mask SDIO_RST_CMD_INT */
+	u16 RPWM2_INT:1;			/* bit[6], set 0 to mask RPWM2_INT */
+	u16 RPWM_INT:1;				/* bit[5], set 0 to mask RPWM_INT */
+	u16 H2C_MSG_INT:1;			/* bit[4], set 0 to mask H2C_MSG_INT_INT */
+	u16 C2H_DMA_OK:1;			/* bit[3], set 0 to mask C2H_DMA_OK_INT */
+	u16 H2C_DMA_OK:1;			/* bit[2], set 0 to mask H2C_DMA_OK_INT */
+	u16 H2C_BUS_RES_FAIL:1;		/* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */
+	u16 TXFIFO_H2C_OVF:1;		/* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */
+} SPDIO_CPU_INT_MASK, *PSPDIO_CPU_INT_MASK;
+
+// Register REG_SPDIO_CPU_INT_STAS @ 0xC2
+typedef struct _SPDIO_CPU_INT_STAS {
+	u16 Reserved:7;				/* bit[15:9], Reserved */
+	u16 BD_FLAG_ERR_INT:1;		/* bit[8], set 0 to mask BD_FLAG_ERR_INT */
+	u16 SDIO_RST_CMD_INT:1;		/* bit[7], set 0 to mask SDIO_RST_CMD_INT */
+	u16 RPWM2_INT:1;			/* bit[6], set 0 to mask RPWM2_INT */
+	u16 RPWM_INT:1;				/* bit[5], set 0 to mask RPWM_INT */
+	u16 H2C_MSG_INT:1;			/* bit[4], set 0 to mask H2C_MSG_INT_INT */
+	u16 C2H_DMA_OK:1;			/* bit[3], set 0 to mask C2H_DMA_OK_INT */
+	u16 H2C_DMA_OK:1;			/* bit[2], set 0 to mask H2C_DMA_OK_INT */
+	u16 H2C_BUS_RES_FAIL:1;		/* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */
+	u16 TXFIFO_H2C_OVF:1;		/* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */
+} SPDIO_CPU_INT_STAS, *PSPDIO_CPU_INT_STAS;
+
+// Register REG_SPDIO_CCPWM @ 0xC4
+typedef struct _SPDIO_CCPWM {
+	u8 TOGGLING:1;			/* bit[7], issue interrupt when 0->1 or 1->0 */
+	u8 Reserved:3;			/* bit[6:4], Reserved */
+	u8 WWLAN:1;				/* bit[3], 0/1: "Wake on WLAN"/"Normal" state */
+	u8 RPS_ST:1;			/* bit[2], 0/1: AP Register Sleep/Active state */
+	u8 WLAN_TRX:1;			/* bit[1], 0: WLAN Off; 1: WLAN On */
+	u8 :1;					/* bit[0] */
+} SPDIO_CCPWM, *PSPDIO_CCPWM;
+
+// Register REG_SPDIO_CPU_IND @ 0xC5
+typedef struct _SPDIO_CPU_IND {
+	u8 Reserved:7;			/* bit[7:1], Reserved */
+	u8 SYS_TRX_RDY:1;		/* bit[0], To indicate the Host system that CPU is ready for TRX
+								, to be sync to 0x87[0] */
+} SPDIO_CPU_IND, *PSPDIO_CPU_IND;
+
+// Register REG_SPDIO_CPU_H2C_MSG @ 0xC8
+typedef struct _SPDIO_CPU_H2C_MSG {
+	u32 Reserved:1;			/* bit[31], Reserved */
+	u32 CPU_H2C_MSG:30;		/* bit[30:0], Host CPU to FW message */
+} SPDIO_CPU_H2C_MSG, *PSPDIO_CPU_H2C_MSG;
+
+// Register REG_SPDIO_CPU_C2H_MSG @ 0xCC
+typedef struct _SPDIO_CPU_C2H_MSG {
+	u32 Reserved:1;			/* bit[31], Reserved */
+	u32 CPU_C2H_MSG:30;		/* bit[30:0], FW to Host CPU message, sync to REG_SDIO_C2H_MSG */
+} SPDIO_CPU_C2H_MSG, *PSPDIO_CPU_C2H_MSG;
+
+// Register REG_SPDIO_CRPWM @ 0xD0
+typedef struct _SPDIO_CRPWM {
+	u8 TOGGLING:1;			/* bit[7], issue interrupt when 0->1 or 1->0 */
+	u8 Reserved:3;			/* bit[6:4], Reserved */
+	u8 WWLAN:1;				/* bit[3], 0/1: "Wake on WLAN"/"Normal" state */
+	u8 RPS_ST:1;			/* bit[2], 0/1: AP Register Sleep/Active state */
+	u8 WLAN_TRX:1;			/* bit[1], 0: WLAN Off; 1: WLAN On */
+	u8 :1;					/* bit[0] */
+} SPDIO_CRPWM, *PSPDIO_CRPWM;
+
+// Register REG_SPDIO_AHB_DMA_CTRL @ 0xD4
+typedef struct _SPDIO_AHB_DMA_CTRL {
+    u32 DISPATCH_TXAGG:1;   /* bit[31], Enable to dispatch aggregated TX packet */
+    u32 AHB_BURST_TYPE:3;   /* bit[30:28], AHB burst type */
+    u32 AHB_BUSY_WAIT_CNT:4;    /* bit[27:24], timeout for AHB controller to wait busy */
+    u32 AHB_DMA_TRANS:2;    /* bit[23:22], AHB DMA Trans value, for debugging */
+    u32 AHB_MASTER_RDY:1;   /* bit[21], AHB Master Hready signal */
+    u32 :1;                 /* bit[20] */
+    u32 AHB_DMA_CS:4;       /* bit[19:16], AHB DMA state */
+    u32 :1;                 /* bit[15] */
+    u32 RXFF_WLEVEL:7;      /* bit[14:8], SPDIO RX FIFO water level */
+    u32 :1;                 /* bit[7] */
+    u32 TXFF_WLEVEL:7;      /* bit[6:0], SPDIO TX FIFO water level */
+} SPDIO_AHB_DMA_CTRL, *PSPDIO_AHB_DMA_CTRL;
+
+#endif	/* end of '#if LITTLE_ENDIAN' */
+
+
+//#define TX_FIFO_ADDR								0x0000
+//#define TX_FIFO_SIZE								0x8000
+
+//TX BD setting
+#if SDIO_BOOT_DRIVER
+// for build ROM library
+#define SDIO_TX_BD_NUM								2	// Number of TX BD
+#define SDIO_TX_BD_BUF_SIZE							(2048+32)    // the size of a TX BD pointed buffer, WLan header = 26 bytes
+#define SDIO_TX_PKT_NUM								10	// Number of TX packet handler
+
+//RX BD setting
+#define RX_BD_FREE_TH								4   // trigger the interrupt when free RX BD over this threshold
+
+#define MAX_RX_BD_BUF_SIZE			                16380	// the Maximum size for a RX_BD point to, make it 4-bytes aligned
+
+#define SDIO_RX_PKT_NUM								3	// Number of RX packet handler
+//#define SDIO_RX_BD_NUM								10	// Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least
+#define SDIO_RX_BD_NUM								(SDIO_RX_PKT_NUM*2)	// Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least
+#define SDIO_RX_BD_BUF_SIZE							(2048+24)    // the size of a RX BD pointed buffer, sizeof(RX Desc)  = 26 bytes
+#define MIN_RX_BD_SEND_PKT							2	/* the minum needed RX_BD to send a Packet to Host, we need 2: 
+															one for RX_Desc, the other for payload */
+
+// CCPWM2 bit map definition for Firmware download
+#define SDIO_INIT_DONE                               (BIT0)
+#define SDIO_MEM_WR_DONE                            (BIT1)
+#define SDIO_MEM_RD_DONE                            (BIT2)
+#define SDIO_MEM_ST_DONE                            (BIT3)
+
+#define SDIO_CPWM2_TOGGLE                           (BIT15)
+
+#else
+#define SDIO_TX_BD_NUM								24	// Number of TX BD
+#define SDIO_TX_BD_BUF_SIZE							(2048+32)    // the size of a TX BD pointed buffer, WLan header = 26 bytes
+#define SDIO_TX_PKT_NUM								128	// Number of TX packet handler
+
+//RX BD setting
+#define RX_BD_FREE_TH								5   // trigger the interrupt when free RX BD over this threshold
+
+#define SDIO_RX_BD_BUF_SIZE							2048
+#define MAX_RX_BD_BUF_SIZE			                16380	// the Maximum size for a RX_BD point to, make it 4-bytes aligned
+
+//#define SDIO_TX_FIFO_SIZE							(1024*64)	// 64K
+#define SDIO_RX_BD_NUM								24	// Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least
+#define SDIO_RX_PKT_NUM								128	// Number of RX packet handler
+#define MIN_RX_BD_SEND_PKT							2	/* the minum needed RX_BD to send a Packet to Host, we need 2: 
+															one for RX_Desc, the other for payload */
+#endif
+
+#define SDIO_IRQ_PRIORITY							10
+
+/* SDIO Events */
+#define SDIO_EVENT_IRQ								BIT(0)		// Interrupt triggered
+#define SDIO_EVENT_RX_PKT_RDY						BIT(1)		// A new SDIO packet ready
+#define SDIO_EVENT_C2H_DMA_DONE						BIT(2)		// Interrupt of C2H DMA done triggered
+#define SDIO_EVENT_DUMP                             BIT(3)      // SDIO status dump periodically Enable
+#define SDIO_EVENT_TXBD_REFILL                      BIT(4)      // To refill TX BD buffer
+#define SDIO_EVENT_EXIT								BIT(28)		// Request to exit the SDIO task
+#define SDIO_EVENT_MP_STOPPED						BIT(29)		// The SDIO task is stopped
+#define SDIO_EVENT_TX_STOPPED						BIT(30)		// The SDIO task is stopped
+#define SDIO_EVENT_RX_STOPPED						BIT(31)		// The SDIO task is stopped
+
+#define SDIO_TASK_PRIORITY							1	// it can be 0(lowest) ~ configMAX_PRIORITIES-1(highest)
+#define SDIO_MP_TASK_PRIORITY                       2	// it can be 0(lowest) ~ configMAX_PRIORITIES-1(highest)
+//#if SDIO_TASK_PRIORITY > (configMAX_PRIORITIES - 1)
+#if SDIO_TASK_PRIORITY > (4 - 1)
+#error "SDIO Task Priority Should be 0~(configMAX_PRIORITIES-1)"
+#endif
+
+//#define TX_RX_PACKET_SIZE							0x144
+
+typedef struct _SDIO_TX_BD_ {
+	u32	Address;    /* The TX buffer physical address, it must be 4-bytes aligned */
+}SDIO_TX_BD, *PSDIO_TX_BD;
+
+#define TX_BD_STRUCTURE_SIZE	(sizeof(SDIO_TX_BD))	
+
+
+/* The RX Buffer Descriptor format */
+
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+typedef struct _SDIO_RX_BD_ {
+	u32 BuffSize:14;		/* bit[13:0], RX Buffer Size, Maximum 16384-1 */
+	u32 LS:1;					/* bit[14], is the Last Segment ? */
+	u32 FS:1;					/* bit[15], is the First Segment ? */
+	u32 Seq:16;				/* bit[31:16], The sequence number, it's no use for now */
+	u32 PhyAddr;			/* The RX buffer physical address, it must be 4-bytes aligned */
+} SDIO_RX_BD, *PSDIO_RX_BD;
+#else
+typedef struct _SDIO_RX_BD_ {
+	u32 Seq:16;				/* bit[31:16], The sequence number, be used for ?? */
+	u32 FS:1;					/* bit[15], is the First Segment ? */
+	u32 LS:1;					/* bit[14], is the Last Segment ? */
+	u32 BuffSize:14;		/* bit[13:0], RX Buffer Size, Maximum 16384 */
+	u32 PhyAddr;			/* The RX buffer physical address, it must be 4-bytes aligned */
+} SDIO_RX_BD, *PSDIO_RX_BD;
+#endif
+#define RX_BD_STRUCTURE_SIZE	(sizeof(SDIO_RX_BD))	
+
+// TODO: This data structer just for test, we should modify it for the normal driver
+typedef struct _SDIO_TX_DESC{
+	// u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	txpktsize:16;       // bit[15:0]
+	u32	offset:8;    		// bit[23:16], store the sizeof(SDIO_TX_DESC)
+	u32	bus_agg_num:8;		// bit[31:24], the bus aggregation number
+#else
+    u32 bus_agg_num:8;      // bit[31:24], the bus aggregation number
+    u32 offset:8;           // bit[23:16], store the sizeof(SDIO_TX_DESC)
+    u32 txpktsize:16;       // bit[15:0]
+#endif
+
+	// u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+    u32 type:8;             // bit[7:0], the packet type
+    u32 rsvd0:24;
+#else
+    u32 rsvd0:24;
+    u32 type:8;             // bit[7:0], the packet type
+#endif
+
+	// u4Byte 2
+	u32	rsvd1;
+	
+	// u4Byte 3
+	u32	rsvd2;
+	
+	// u4Byte 4
+	u32	rsvd3;
+
+	// u4Byte 5
+	u32	rsvd4;
+} SDIO_TX_DESC, *PSDIO_TX_DESC;
+
+// TX Desc for Memory Write command
+typedef struct _SDIO_TX_DESC_MW{
+	// u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	txpktsize:16;       // bit[15:0]
+	u32	offset:8;    		// bit[23:16], store the sizeof(SDIO_TX_DESC)
+	u32	bus_agg_num:8;		// bit[31:24], the bus aggregation number
+#else
+    u32 bus_agg_num:8;      // bit[31:24], the bus aggregation number
+    u32 offset:8;           // bit[23:16], store the sizeof(SDIO_TX_DESC)
+    u32 txpktsize:16;       // bit[15:0]
+#endif
+
+	// u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+    u32 type:8;             // bit[7:0], the packet type
+    u32 reply:1;            // bit[8], request to send a reply message
+    u32 rsvd0:23;
+#else
+    u32 rsvd0:23;
+    u32 reply:1;            // bit[8], request to send a reply message
+    u32 type:8;             // bit[7:0], the packet type
+#endif
+
+	// u4Byte 2
+	u32	start_addr;         // memory write start address
+	
+	// u4Byte 3
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+    u32 write_len:16;       // bit[15:0], the length to write
+    u32 rsvd2:16;           // bit[31:16]
+#else
+    u32 rsvd2:16;           // bit[31:16]
+    u32 write_len:16;       // bit[15:0], the length to write
+#endif
+	
+	// u4Byte 4
+	u32	rsvd3;
+
+	// u4Byte 5
+	u32	rsvd4;
+} SDIO_TX_DESC_MW, *PSDIO_TX_DESC_MW;
+
+// TX Desc for Memory Read command
+typedef struct _SDIO_TX_DESC_MR{
+	// u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	txpktsize:16;       // bit[15:0]
+	u32	offset:8;    		// bit[23:16], store the sizeof(SDIO_TX_DESC)
+	u32	bus_agg_num:8;		// bit[31:24], the bus aggregation number
+#else
+    u32 bus_agg_num:8;      // bit[31:24], the bus aggregation number
+    u32 offset:8;           // bit[23:16], store the sizeof(SDIO_TX_DESC)
+    u32 txpktsize:16;       // bit[15:0]
+#endif
+
+	// u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+    u32 type:8;             // bit[7:0], the packet type
+    u32 rsvd0:24;
+#else
+    u32 rsvd0:24;
+    u32 type:8;             // bit[7:0], the packet type
+#endif
+
+	// u4Byte 2
+	u32	start_addr;         // memory write start address
+	
+	// u4Byte 3
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+    u32 read_len:16;        // bit[15:0], the length to read
+    u32 rsvd2:16;           // bit[31:16]
+#else
+    u32 rsvd2:16;           // bit[31:16]
+    u32 read_len:16;        // bit[15:0], the length to read
+#endif
+	
+	// u4Byte 4
+	u32	rsvd3;
+
+	// u4Byte 5
+	u32	rsvd4;
+} SDIO_TX_DESC_MR, *PSDIO_TX_DESC_MR;
+
+// TX Desc for Memory Set command
+typedef struct _SDIO_TX_DESC_MS{
+	// u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	txpktsize:16;       // bit[15:0]
+	u32	offset:8;    		// bit[23:16], store the sizeof(SDIO_TX_DESC)
+	u32	bus_agg_num:8;		// bit[31:24], the bus aggregation number
+#else
+    u32 bus_agg_num:8;      // bit[31:24], the bus aggregation number
+    u32 offset:8;           // bit[23:16], store the sizeof(SDIO_TX_DESC)
+    u32 txpktsize:16;       // bit[15:0]
+#endif
+
+	// u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+    u32 type:8;             // bit[7:0], the packet type
+    u32 data:8;             // bit[8:15], the value to be written to the memory
+    u32 reply:1;            // bit[16], request to send a reply message
+    u32 rsvd0:15;
+#else
+    u32 rsvd0:15;
+    u32 reply:1;            // bit[16], request to send a reply message
+    u32 data:8;             // bit[8:15], the value to be written to the memory
+    u32 type:8;             // bit[7:0], the packet type
+#endif
+
+	// u4Byte 2
+	u32	start_addr;         // memory write start address
+	
+	// u4Byte 3
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+    u32 write_len:16;       // bit[15:0], the length to write
+    u32 rsvd2:16;           // bit[31:16]
+#else
+    u32 rsvd2:16;           // bit[31:16]
+    u32 write_len:16;       // bit[15:0], the length to write
+#endif
+	
+	// u4Byte 4
+	u32	rsvd3;
+
+	// u4Byte 5
+	u32	rsvd4;
+} SDIO_TX_DESC_MS, *PSDIO_TX_DESC_MS;
+
+// TX Desc for Jump to Start command
+typedef struct _SDIO_TX_DESC_JS{
+	// u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	txpktsize:16;       // bit[15:0]
+	u32	offset:8;    		// bit[23:16], store the sizeof(SDIO_TX_DESC)
+	u32	bus_agg_num:8;		// bit[31:24], the bus aggregation number
+#else
+    u32 bus_agg_num:8;      // bit[31:24], the bus aggregation number
+    u32 offset:8;           // bit[23:16], store the sizeof(SDIO_TX_DESC)
+    u32 txpktsize:16;       // bit[15:0]
+#endif
+
+	// u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+    u32 type:8;             // bit[7:0], the packet type
+    u32 rsvd0:24;
+#else
+    u32 rsvd0:24;
+    u32 type:8;             // bit[7:0], the packet type
+#endif
+
+	// u4Byte 2
+	u32	start_fun;         // the pointer of the startup function 
+	
+	// u4Byte 3
+	u32	rsvd2;
+	
+	// u4Byte 4
+	u32	rsvd3;
+
+	// u4Byte 5
+	u32	rsvd4;
+} SDIO_TX_DESC_JS, *PSDIO_TX_DESC_JS;
+
+
+#define SIZE_TX_DESC	(sizeof(SDIO_TX_DESC))
+// define the TX BD buffer size with unite of 64 byets
+/* Be carefull!! the setting of hardware's TX BD buffer size may exceed the real size of 
+   the TX BD buffer size, and then it may cause the hardware DMA write the buffer overflow */
+#define SDIO_TX_BUF_SZ_UNIT          64
+#define SDIO_TX_BD_BUF_USIZE        ((((SDIO_TX_BD_BUF_SIZE+sizeof(SDIO_TX_DESC)-1)/SDIO_TX_BUF_SZ_UNIT)+1)&0xff)
+
+typedef struct _SDIO_TX_BD_BUFFER_ {
+		SDIO_TX_DESC TX_Desc;
+		u8 TX_Buffer[SDIO_TX_BD_BUF_SIZE];
+}SDIO_TX_BD_BUFFER, *PSDIO_TX_BD_BUFFER;
+
+
+// TODO: This data structer just for test, we should modify it for the normal driver
+typedef struct _SDIO_RX_DESC{
+	// u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	pkt_len:16;     // bit[15:0], the packet size
+	u32	offset:8;    	// bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+	u32	rsvd0:6;        // bit[29:24]
+	u32	icv:1;          // bit[30], ICV error
+	u32	crc:1;          // bit[31], CRC error
+#else
+	u32	crc:1;          // bit[31], CRC error
+	u32	icv:1;          // bit[30], ICV error
+	u32	rsvd0:6;        // bit[29:24]
+	u32	offset:8;    	// bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+	u32	pkt_len:16;     // bit[15:0], the packet size
+#endif
+
+	// u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	type:8;         // bit[7:0], the type of this packet
+	u32	rsvd1:24;       // bit[31:8]
+#else
+    u32 rsvd1:24;       // bit[31:8]
+    u32 type:8;         // bit[7:0], the type of this packet
+#endif
+
+	// u4Byte 2
+	u32	rsvd2;
+	
+	// u4Byte 3
+	u32	rsvd3;
+	
+	// u4Byte 4
+	u32	rsvd4;
+
+	// u4Byte 5
+	u32	rsvd5;
+} SDIO_RX_DESC, *PSDIO_RX_DESC;
+
+// For memory read command
+typedef struct _SDIO_RX_DESC_MR{
+	// u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	pkt_len:16;     // bit[15:0], the packet size
+	u32	offset:8;    	// bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+	u32	rsvd0:8;        // bit[31:24]
+#else
+	u32	rsvd0:8;        // bit[31:24]
+	u32	offset:8;    	// bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+	u32	pkt_len:16;     // bit[15:0], the packet size
+#endif
+
+	// u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	type:8;         // bit[7:0], the type of this packet
+	u32	rsvd1:24;       // bit[31:8]
+#else
+    u32 rsvd1:24;       // bit[31:8]
+    u32 type:8;         // bit[7:0], the type of this packet
+#endif
+
+	// u4Byte 2
+	u32	start_addr;
+	
+	// u4Byte 3
+	u32	rsvd2;
+	
+	// u4Byte 4
+	u32	rsvd3;
+
+	// u4Byte 5
+	u32	rsvd4;
+} SDIO_RX_DESC_MR, *PSDIO_RX_DESC_MR;
+
+// For memory write reply command
+typedef struct _SDIO_RX_DESC_MW{
+	// u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	pkt_len:16;     // bit[15:0], the packet size
+	u32	offset:8;    	// bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+	u32	rsvd0:8;        // bit[31:24]
+#else
+	u32	rsvd0:8;        // bit[31:24]
+	u32	offset:8;    	// bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+	u32	pkt_len:16;     // bit[15:0], the packet size
+#endif
+
+	// u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	type:8;         // bit[7:0], the type of this packet
+	u32	rsvd1:24;       // bit[31:8]
+#else
+    u32 rsvd1:24;       // bit[31:8]
+    u32 type:8;         // bit[7:0], the type of this packet
+#endif
+
+	// u4Byte 2
+	u32	start_addr;
+	
+	// u4Byte 3
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+    u32 write_len:16;   // bit[15:0], the type of this packet
+    u32 result:8;      // bit[23:16], the result of memory write command
+    u32 rsvd2:8;       // bit[31:24]
+#else
+    u32 rsvd2:8;       // bit[31:24]
+    u32 result:8;      // bit[23:16], the result of memory write command
+    u32 write_len:16;   // bit[15:0], the type of this packet
+#endif
+	
+	// u4Byte 4
+	u32	rsvd3;
+
+	// u4Byte 5
+	u32	rsvd4;
+} SDIO_RX_DESC_MW, *PSDIO_RX_DESC_MW;
+
+// For memory set reply command
+typedef struct _SDIO_RX_DESC_MS{
+	// u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	pkt_len:16;     // bit[15:0], the packet size
+	u32	offset:8;    	// bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+	u32	rsvd0:8;        // bit[31:24]
+#else
+	u32	rsvd0:8;        // bit[31:24]
+	u32	offset:8;    	// bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+	u32	pkt_len:16;     // bit[15:0], the packet size
+#endif
+
+	// u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	type:8;         // bit[7:0], the type of this packet
+	u32	rsvd1:24;       // bit[31:8]
+#else
+    u32 rsvd1:24;       // bit[31:8]
+    u32 type:8;         // bit[7:0], the type of this packet
+#endif
+
+	// u4Byte 2
+	u32	start_addr;
+	
+	// u4Byte 3
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+    u32 write_len:16;   // bit[15:0], the type of this packet
+    u32 result:8;      // bit[23:16], the result of memory write command
+    u32 rsvd2:8;       // bit[31:24]
+#else
+    u32 rsvd2:8;       // bit[31:24]
+    u32 result:8;      // bit[23:16], the result of memory write command
+    u32 write_len:16;   // bit[15:0], the type of this packet
+#endif
+	
+	// u4Byte 4
+	u32	rsvd3;
+
+	// u4Byte 5
+	u32	rsvd4;
+} SDIO_RX_DESC_MS, *PSDIO_RX_DESC_MS;
+
+#define SIZE_RX_DESC	(sizeof(SDIO_RX_DESC))
+
+typedef struct _SDIO_RX_BD_BUFFER_ {
+		SDIO_RX_DESC RX_Desc;
+		u8 RX_Buffer[SDIO_RX_BD_BUF_SIZE];
+}SDIO_RX_BD_BUFFER, *PSDIO_RX_BD_BUFFER;
+
+
+/* The data structer for a packet fordwarding to the WLan driver to transmit it */
+// TODO: This data structer just for test, we may need modify it for the normal driver
+typedef struct _SDIO_TX_PACKET_ {
+	u8 *pHeader;		// Point to the 1st byte of the packets
+	u16	PktSize;		// the size (bytes) of this packet
+	_LIST list;			// the link list to chain packets
+	u8 isDyna;          // is Dynamic allocated
+} SDIO_TX_PACKET, *PSDIO_TX_PACKET;
+
+/* the data structer to bind a TX_BD with a TX Packet */
+typedef struct _SDIO_TX_BD_HANDLE_ {
+	SDIO_TX_BD *pTXBD;		// Point to the TX_BD buffer
+	SDIO_TX_PACKET *pPkt;	// point to the Tx Packet
+	u8 isPktEnd;		// For a packet over 1 BD , this flag to indicate is this BD contains a packet end
+	u8 isFree;		// is this TX BD free 
+} SDIO_TX_BD_HANDLE, *PSDIO_TX_BD_HANDLE;
+
+/* The data structer for a packet which from the WLan driver to send to the Host */
+// TODO: This data structer just for test, we may need modify it for the normal driver
+
+#if SDIO_BOOT_DRIVER
+typedef struct _SDIO_RX_PACKET_ {
+//	SDIO_RX_DESC RxDesc;	// The RX Descriptor for this packet, to be send to Host ahead this packet
+	u8 *pData;				// point to the head of payload of this packet
+    u16 Offset;         // the offset from the pData to the payload buffer
+	_LIST list;			// the link list to chain packets
+	u8 PktBuf[SDIO_RX_BD_BUF_SIZE];       // the Rx_Desc + payload data buffer, the first 24 bytes is reserved for RX_DESC
+} SDIO_RX_PACKET, *PSDIO_RX_PACKET;
+#else
+typedef struct _SDIO_RX_PACKET_ {
+	SDIO_RX_DESC RxDesc;	// The RX Descriptor for this packet, to be send to Host ahead this packet
+	u8 *pData;				// point to the head of payload of this packet
+    u16 Offset;         // the offset from the pData to the payload buffer
+	_LIST list;			// the link list to chain packets
+	u8 isDyna;          // is Dynamic allocated
+} SDIO_RX_PACKET, *PSDIO_RX_PACKET;
+#endif
+
+/* the data structer to bind a RX_BD with a RX Packet */
+typedef struct _SDIO_RX_BD_HANDLE_ {
+	SDIO_RX_BD *pRXBD;		// Point to the RX_BD buffer
+	SDIO_RX_PACKET *pPkt;	// point to the Rx Packet
+	u8 isPktEnd;		// For a packet over 1 BD , this flag to indicate is this BD contains a packet end
+	u8 isFree;		// is this RX BD free (DMA done and its RX packet has been freed)
+} SDIO_RX_BD_HANDLE, *PSDIO_RX_BD_HANDLE;
+
+#if SDIO_MP_MODE
+typedef struct _SDIO_MP_CMD_ {
+	u8 cmd_name[16];
+	u32	cmd_type;
+} SDIO_MP_CMD, *PSDIO_MP_CMD;
+
+typedef enum _SDIO_MP_CMD_TYPE_{
+	SDIO_MP_START=1,
+	SDIO_MP_STOP=2,
+	SDIO_MP_LOOPBACK=3,
+	SDIO_MP_STATUS=4,
+	SDIO_MP_READ_REG8=5,
+	SDIO_MP_READ_REG16=6,
+	SDIO_MP_READ_REG32=7,
+	SDIO_MP_WRITE_REG8=8,
+	SDIO_MP_WRITE_REG16=9,
+	SDIO_MP_WRITE_REG32=10,
+	SDIO_MP_WAKEUP=11,	// wakeup the SDIO task manually, for debugging
+    SDIO_MP_DUMP=12,    // start/stop to dump the SDIO status periodically
+    SDIO_MP_CTX=13,     // setup continue TX test
+    SDIO_MP_CRX=14,     // setup continue RX test
+    SDIO_MP_CRX_DA=15,    // setup continue RX with dynamic allocate RX Buf test
+    SDIO_MP_CRX_STOP=16,    // setup continue RX test
+    SDIO_MP_DBG_MSG=17,    // Debug message On/Off
+	
+}SDIO_MP_CMD_TYPE;
+
+typedef enum _SDIO_CRX_MODE_{
+    SDIO_CRX_STATIC_BUF = 1,
+    SDIO_CRX_DYNA_BUF = 2,
+} SDIO_CRX_MODE;
+
+typedef struct _SDIO_MP_RX_PACKET_ {
+	_LIST list;         // this member MUST be the 1st one, the link list to chain packets
+	u8 *pData;          // point to the head of payload of this packet
+	u16 Offset;        // the offset from the pData to the payload
+	u16 DataLen;        // the data length of this packet
+} SDIO_MP_RX_PACKET, *PSDIO_MP_RX_PACKET;
+
+#endif	// end of '#if SDIO_MP_MODE'
+
+#define SDIO_CMD_TX_ETH         0x83    // request to TX a 802.3 packet
+#define SDIO_CMD_TX_WLN         0x81    // request to TX a 802.11 packet
+#define SDIO_CMD_H2C            0x11    // H2C(host to device) command packet
+#define SDIO_CMD_MEMRD          0x51    // request to read a block of memory data
+#define SDIO_CMD_MEMWR          0x53    // request to write a block of memory
+#define SDIO_CMD_MEMST          0x55    // request to set a block of memory with a value
+#define SDIO_CMD_STARTUP        0x61    // request to jump to the start up function
+
+#define SDIO_CMD_RX_ETH         0x82    // indicate a RX 802.3 packet
+#define SDIO_CMD_RX_WLN         0x80    // indicate a RX 802.11 packet
+#define SDIO_CMD_C2H            0x10    // C2H(device to host) command packet
+#define SDIO_CMD_MEMRD_RSP      0x50    // response to memory block read command
+#define SDIO_CMD_MEMWR_RSP      0x52    // response to memory write command
+#define SDIO_CMD_MEMST_RSP      0x54    // response to memory set command
+#define SDIO_CMD_STARTED        0x60    // indicate the program has jumped to the given function
+
+#ifdef CONFIG_SDIO_DEVICE_VERIFY
+
+#define TX_BD_STRUCTURE_NUM							10
+#define RX_BD_STRUCTURE_NUM							10
+#define TX_BD_BUFFER_SIZE							0x1000//0x2000//0x800
+#define RX_BD_BUFFER_SIZE							0x400//0x800
+
+#define SDIO_RAM_ADDR_BASE							0x20080000
+#define SDIO_BUFFER_HEAD(addr)						SDIO_RAM_ADDR_BASE + addr
+#define HAL_SDIO_BUFFER_READ8(addr)					HAL_READ8(SDIO_RAM_ADDR_BASE, addr)
+#define HAL_SDIO_BUFFER_READ32(addr)				HAL_READ32(SDIO_RAM_ADDR_BASE, addr)
+#define HAL_SDIO_BUFFER_WRITE32(addr, value)		HAL_WRITE32(SDIO_RAM_ADDR_BASE, addr, value)
+
+//#define RX_BD_ADDR									0x8000
+//#define RX_BUFFER_ADDR								0x8050
+
+typedef enum _SDIO_TEST_FUNC_ {
+        SDIO_TEST_INIT,			// 0
+		SDIO_TEST_INT_ON,		// 1
+		SDIO_TEST_INT_OFF,		// 2
+		SDIO_HCI_RX_REQ,		// 3
+		SDIO_RESET_TXFIFIO,		// 4
+		SDIO_CPU_RST_DMA,		// 5
+		SDIO_CPU_CLR_INT_REG,   // 6
+		SDIO_TIMER_TEST,		// 7
+		SDIO_TEST_DEBUG,		// 8
+		SDIO_TEST,              // 9
+		SDIO_HELP = 0xff
+}SDIO_TEST_FUNC, *PSDIO_TEST_FUNC;
+
+typedef struct _SDIO_TEST_ADAPTER_ {
+	u32 TXWritePtr;
+	u32 TXReadPtr;
+	u16 RXWritePtr;
+	u16 RXReadPtr;
+	u16 IntMask;
+	u16 IntStatus;
+} SDIO_TEST_ADAPTER, *PSDIO_TEST_ADAPTER;
+
+
+VOID
+MovePKTToRX(
+	IN  u32	 Source,  IN  u32  Destination,  IN  u32  PKTSize
+);
+
+BOOL
+PacketProcess(
+	IN SDIO_TEST_ADAPTER *pDevStatus
+);
+
+VOID 
+SdioDeviceIrqHandleFunc(
+	IN	VOID	*DATA
+);
+
+VOID
+SdioDeviceTestApp(
+    IN  u32      Data
+);
+
+VOID
+InitRXBD(VOID);
+
+VOID
+InitTXFIFO(VOID);
+
+VOID
+IrqRegister(VOID);
+
+#endif	// end of "#ifdef CONFIG_SDIO_DEVICE_VERIFY"
+
+#endif	/* #ifndef _RTL8195A_SDIO_H_ */

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio_host.h

@@ -0,0 +1,295 @@
+	/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_SDIO_HOST_H_
+#define _RTL8195A_SDIO_HOST_H_
+
+#include "hal_api.h"
+#include "osdep_api.h"
+
+
+
+
+#ifdef CONFIG_SDIO_HOST_VERIFY
+
+#define HAL_MMC_HOST_READ32(addr)            			HAL_READ32(SDIO_HOST_REG_BASE, addr)
+#define HAL_MMC_HOST_WRITE32(addr, value)    			HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value)
+#define HAL_MMC_HOST_READ16(addr)						HAL_READ16(SDIO_HOST_REG_BASE, addr)
+#define HAL_MMC_HOST_WRITE16(addr, value)    			HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value)
+#define HAL_MMC_HOST_READ8(addr)						HAL_READ8(SDIO_HOST_REG_BASE, addr)
+#define HAL_MMC_HOST_WRITE8(addr, value)    			HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value)
+
+/* RTL8195A Register */
+// REG_SOC_HCI_COM_FUNC_EN (0x214)
+#define SD_DEVICE_IP_ON_BLK					BIT0
+#define SD_DEVICE_IP_OFF_BLK				BIT1
+#define SD_HOST_IP_BLK						BIT2
+
+// REG_PESOC_HCI_CLK_CTRL0 (0x240)
+#define SD_HOST_CLKEN_IN_CPU_RUN_MODE		BIT2
+
+// REG_HCI_PINMUX_CTRL (0x2A0)
+#define SD_DEVICE_MODE_PINMUX_EN			BIT0
+#define SD_HOST_MODE_PINMUX_EN				BIT1
+
+// 0x40059000
+#define SD_HOST_CARD_DETECT_CIRCUIT			BIT10
+
+
+	
+/* SD Host Register */
+#define REG_SDMA_SYS_ADDR_ARG				0x00 // 4byte
+#define REG_BLOCK_SIZE						0x04 // 2byte
+#define REG_BLOCK_COUNT						0x06 // 2byte
+#define REG_ARGUMENT1						0x08 // 4byte
+#define REG_TRANSFER_MODE					0x0C // 2byte
+#define REG_COMMAND							0x0E // 2byte
+#define REG_RESPONSE0						0x10 // 4byte
+#define REG_RESPONSE2						0x14 // 4byte
+#define REG_RESPONSE4						0x18 // 4byte
+#define REG_RESPONSE6						0x1C // 4byte
+#define REG_BUFFER_DATA_PORT				0x20 // 4byte
+#define REG_PRESENT_STATE					0x24 // 4byte
+#define REG_HOST_CONTROL1					0x28 // 1byte
+#define REG_POWER_CONTROL					0x29 // 1byte
+#define REG_BLOCK_GAP_CONTROL				0x2A // 1byte
+#define REG_WAKEUP_CONTROL					0x2B // 1byte
+#define REG_CLOCK_CONTROL					0x2C // 2byte
+#define REG_TIMEOUT_CONTROL					0x2E // 1byte
+#define REG_SW_RESET						0x2F // 1byte
+#define REG_NORMAL_INT_STATUS				0x30 // 2byte
+#define REG_ERROR_INT_STATUS				0x32 // 2byte
+#define REG_NORMAL_INT_STATUS_ENABLE		0x34 // 2byte
+#define	REG_ERROR_INT_STATUS_ENABLE			0x36 // 2byte
+#define REG_NORMAL_INT_SIGNAL_ENABLE		0x38 // 2byte
+#define REG_ERROR_INT_SIGNAL_ENABLE			0x3A // 2byte
+#define REG_CAPABILITIES					0x40 // 8byte
+#define REG_ADMA_ADDRESS					0x58 // 8byte
+
+// Transfer Mode (0x0C)
+#define BIT_DMA_EN							BIT0
+#define BIT_BLK_CNT_EN						BIT1
+#define BIT_AUTO_CMD12_EN					BIT2
+#define BIT_AUTO_CMD23_EN					BIT3
+#define BIT_READ_TRANS						BIT4
+#define BIT_MULTI_BLK						BIT5
+
+// Present State (0x24)
+#define BIT_CMD_INHIBIT_CMD					BIT0
+#define BIT_CMD_INHIBIT_DAT					BIT1
+#define BIT_CARD_INSERTED					BIT16
+#define BIT_WRITE_PROTECT_SWITCH_PIN		BIT19
+
+// Power Control (0x29)
+#define BIT_POWER_33						0xE
+#define BIT_POWER_30						0xC
+#define BIT_POWER_18						0xA
+
+// Clock Control (0x2C)
+#define BIT_INTERNAL_CLK_EN					BIT0
+#define BIT_INTERNAL_CLK_STABLE				BIT1
+#define BIT_SD_CLK_EN						BIT2
+
+// Software Reset (0x2F)
+#define BIT_SW_RESET_ALL					BIT0
+#define BIT_SW_RESET_CMD_LINE				BIT1
+#define BIT_SW_RESET_DAT_LINE				BIT2
+	
+// Norma Interrupt Status (0x30)
+#define BIT_COMMAND_COMPLETE				BIT0
+#define BIT_TRANSFER_COMPLETE				BIT1
+#define BIT_BLOCK_GAP_EVENT					BIT2
+#define BIT_DMA_INT							BIT3
+#define BIT_BUFFER_WRITE_RDY				BIT4
+#define BIT_BUFFER_READ_RDY					BIT5
+#define BIT_CARD_INSERTION					BIT6
+#define BIT_CARD_REMOVAL					BIT7
+#define BIT_CARD_INT						BIT8
+#define BIT_ERROR_INT						BIT15
+
+// Error Interrupt Status (0x32)
+#define BIT_DATA_TIME_OUT_ERROR				BIT4
+#define BIT_DATA_CRC_ERROR					BIT5
+#define BIT_ADMA_ERROR						BIT9
+
+// Capabilities (0x40)
+#define BIT_VDD_33							BIT24
+#define BIT_VDD_30							BIT25
+#define BIT_VDD_18							BIT26
+
+
+#define ENABLE								1
+#define DISABLE 							0
+
+#define ADMA_DESC_NUM						50
+
+#define BUFFER_UNIT_SIZE					512
+	
+typedef enum _MMC_HOST_TEST_FUNC_ {
+	MMC_HOST_TEST_HW_INIT,			// 0
+	MMC_HOST_TEST_CARD_INIT,		// 1
+	MMC_HOST_TEST_SEND_CMD, 		// 2
+	MMC_HOST_TEST_DEBUG,			// 3
+	MMC_HOST_TEST_SW_RESET,			// 4
+	MMC_HOST_TEST_READ_SINGLE,		// 5
+	MMC_HOST_TEST_WRITE_SINGLE,		// 6
+	MMC_HOST_TEST_READ_MULTI,		// 7
+	MMC_HOST_TEST_WRITE_MULTI,		// 8
+	MMC_HOST_TEST_SINGLE_LONGRUN,	// 9
+	MMC_HOST_TEST_MULTI_LONGRUN,	// 10
+	MMC_HOST_TEST_CARD_DETECTION,	// 11
+	MMC_HOST_TEST_WRITE_PROTECT,	// 12
+	MMC_HOST_TEST_REGISTER_RW		// 13
+}MMC_HOST_TEST_FUNC;
+	
+typedef enum _RESPONSE_TYPE_ {
+	No_Response,					// 00b
+	Response_136,					// 01b
+	Response_48,					// 10b
+	Response_48_Busy				// 11b
+}RESPONSE_TYPE;
+	
+typedef enum _COMMAND_TYPE_ {
+	Normal, 						// 00b
+	Suspend,						// 01b
+	Resume, 						// 10b
+	Abort							// 11b
+}COMMAND_TYPE;
+	
+typedef enum _DATA_PRESENT_ {
+	No_Data_Present,				// 00b
+	Data_Present,					// 01b
+}DATA_PRESENT;
+
+typedef enum _SUPPLY_VOLTAGE_ {
+	MMC_VDD_27_28	= BIT15,
+	MMC_VDD_28_29	= BIT16,
+	MMC_VDD_29_30	= BIT17,
+	MMC_VDD_30_31	= BIT18,
+	MMC_VDD_31_32	= BIT19,
+	MMC_VDD_32_33	= BIT20,
+	MMC_VDD_33_34	= BIT21,
+	MMC_VDD_34_35	= BIT22,
+	MMC_VDD_35_36	= BIT23,
+}SUPPLY_VOLTAGE;
+	
+typedef enum _COMMAND_INDEX_ {
+	GO_IDLE_STATE			= 0,
+	ALL_SEND_CID			= 2,
+	SEND_RELATIVE_ADDR		= 3,
+	SET_BUS_WIDTH			= 6,
+	SELECT_CARD				= 7,
+	SEND_IF_COND			= 8,
+	SEND_CSD				= 9,
+	STOP_TRANSMISSION		= 12,
+	SEND_STATUS				= 13,
+	READ_SINGLE_BLOCK   	= 17,
+	READ_MULTIPLE_BLOCK 	= 18,
+	WRITE_BLOCK				= 24,
+	WRITE_MULTIPLE_BLOCK	= 25,
+	SD_SEND_OP_COND 		= 41,
+	APP_CMD					= 55,
+}COMMAND_INDEX;
+
+typedef enum _TRANSFER_CONFIG_ {
+	Read_Data				= 0,
+	Write_Data				= 1,
+	Single_Block			= 0,
+	Multiple_Block			= 1,
+}TRANSFER_CONFIG;
+
+typedef enum _ERROR_STATUS_ {
+	General_Error,					// 0
+	CRC_Error,						// 1	
+	TIME_OUT_ERROR,					// 2
+	CRC_Error_NeedCMD12,			// 3
+	Transfer_OK						// 4
+}ERROR_STATUS;
+
+typedef enum _CARD_CURRENT_STATE_ {
+	IDLE_STATE,
+	READY_STATE,
+	IDENT_STATE,
+	STBY_STATE,
+	TRAN_STATE,
+	DATA_STATE,
+	RCV_STATE,
+	PRG_STATE,
+	DIS_STATE,
+	UNKNOWN_STATE
+}CARD_CURRENT_STATE;
+
+typedef struct _COMMAND_FORMAT_
+{
+	u16 Resp_Type:2;
+	u16 Rsvd0:1;
+	u16 CMD_CRC_Chk:1;
+	u16 CMD_Idx_Chk:1;
+	u16 Data_Present:1;
+	u16 CMD_Type:2;
+	u16 CMD_Idx:6;
+	u16 Rsvd1:2;
+}COMMAND_FORMAT, *PCOMMAND_FPRMAT;
+
+typedef struct _MMC_COMMAND
+{
+	COMMAND_FORMAT	Cmd_Format;
+	u32 Arg;
+}MMC_COMMAND;
+
+typedef struct _MMC_HOST_
+{
+	u32 OCR_Avail;
+	u32 Resp[4];
+	u32 CID[4];
+	u32 RCA;
+}MMC_HOST, *PMMC_HOST;
+
+typedef struct _ADMA_ATTR_
+{
+	u16 Valid:1;
+	u16 End:1;
+	u16 Int:1;
+	u16 Rsvd1:1;
+	u16 Act1:1;
+	u16 Act2:1;
+	u16 Rsvd2:10;
+}ADMA_ATTR, *PADMA_ATTR;
+// 24 bytes
+typedef struct _ADMA_DESC_TABLE_
+{
+	// 1st buffer desc
+	ADMA_ATTR Attribute1;
+	u16	Length1;
+	u32 Address1;
+	// 2nd buffer desc
+	ADMA_ATTR Attribute2;
+	u16	Length2;
+	u32 Address2;
+	// 3rd buffer desc
+	ADMA_ATTR Attribute3;
+	u16	Length3;
+	u32 Address3;
+}ADMA_DESC_TABLE, *PADMA_DESC_TABLE;
+// 1024 bytes
+typedef struct _ADMA_BUFFER_
+{
+	u8 Data1[512];  /* 1st buffer */
+	u8 Data2[512];  /* 2nd buffer */
+}ADMA_BUFFER, *PADMA_BUFFER;
+
+
+VOID
+SdHostTestApp(
+    IN  u8      *argv[]
+);
+#endif	// end of "#ifdef CONFIG_SDIO_HOST_VERIFY"
+
+#endif	/* #ifndef _RTL8195A_SDIO_HOST_H_ */

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdr.h

@@ -0,0 +1,379 @@
+#ifndef _RTL8195A_SDR_H
+#define _RTL8195A_SDR_H
+
+#define MS_0_CTRL_BASE            BSP_MS_I_DRAMC_0_BASE
+#define MS_0_CTRL_PHY_BASE        (BSP_MS_I_DRAMC_0_BASE)
+#define MS_0_WRAP_BASE            (MS_0_CTRL_BASE + 0x200)
+
+#define MS_1_CTRL_BASE            BSP_MS_I_DRAMC_1_BASE
+#define MS_1_CTRL_PHY_BASE        (BSP_MS_I_DRAMC_1_BASE)
+#define MS_1_WRAP_BASE            (MS_1_CTRL_BASE + 0x200)
+
+#define MS_PCTL_CCR_OFFSET        0x000
+#define MS_PCTL_DCR_OFFSET        0x004
+#define MS_PCTL_IOCR_OFFSET       0x008
+#define MS_PCTL_CSR_OFFSET        0x00c
+#define MS_PCTL_DRR_OFFSET        0x010
+#define MS_PCTL_TPR0_OFFSET       0x014
+#define MS_PCTL_TPR1_OFFSET       0x018
+#define MS_PCTL_TPR2_OFFSET       0x01c
+#define MS_PCTL_MR_OFFSET         0x020
+#define MS_PCTL_EMR1_OFFSET       0x024
+#define MS_PCTL_EMR2_OFFSET       0x028
+#define MS_PCTL_EMR3_OFFSET       0x02c
+#define MS_PCTL_CSR2_OFFSET       0x030       
+#define MS_PCTL_SRST_OFFSET       0x034      
+#define MS_PCTL_DTR2_OFFSET       0x038
+#define MS_PCTL_DTR3_OFFSET       0x03c
+#define MS_PCTL_GDLLCR_OFFSET     0x040
+#define MS_PCTL_DLLCR0_OFFSET     0x044
+#define MS_PCTL_DLLCR1_OFFSET     0x048
+#define MS_PCTL_DLLCR2_OFFSET     0x04c
+#define MS_PCTL_DLLCR3_OFFSET     0x050
+#define MS_PCTL_DLLCR4_OFFSET     0x054
+#define MS_PCTL_DLLCR5_OFFSET     0x058
+#define MS_PCTL_DLLCR6_OFFSET     0x05c
+#define MS_PCTL_DLLCR7_OFFSET     0x060
+#define MS_PCTL_DLLCR8_OFFSET     0x064
+#define MS_PCTL_DQTR0_OFFSET      0x068
+#define MS_PCTL_DQTR1_OFFSET      0x06c
+#define MS_PCTL_DQTR2_OFFSET      0x070
+#define MS_PCTL_DQTR3_OFFSET      0x074
+#define MS_PCTL_DQTR4_OFFSET      0x078
+#define MS_PCTL_DQTR5_OFFSET      0x07c
+#define MS_PCTL_DQTR6_OFFSET      0x080
+#define MS_PCTL_DQTR7_OFFSET      0x084
+#define MS_PCTL_DQSTR_OFFSET      0x088
+#define MS_PCTL_DQSBTR_OFFSET     0x08c
+#define MS_PCTL_ODTCR_OFFSET      0x090
+#define MS_PCTL_DTR0_OFFSET       0x094
+#define MS_PCTL_DTR1_OFFSET       0x098
+#define MS_PCTL_DTAR_OFFSET       0x09c
+#define MS_PCTL_ZQCR0_OFFSET      0x0a0
+#define MS_PCTL_ZQCR1_OFFSET      0x0a4
+#define MS_PCTL_ZQSR_OFFSET       0x0a8
+#define MS_PCTL_RSLR0_OFFSET      0x0ac
+#define MS_PCTL_RSLR1_OFFSET      0x0b0
+#define MS_PCTL_RSLR2_OFFSET      0x0b4
+#define MS_PCTL_RSLR3_OFFSET      0x0b8
+#define MS_PCTL_RDGR0_OFFSET      0x0bc
+#define MS_PCTL_RDGR1_OFFSET      0x0c0
+#define MS_PCTL_RDGR2_OFFSET      0x0c4
+#define MS_PCTL_RDGR3_OFFSET      0x0c8
+#define MS_PCTL_MXSL_OFFSET       0x0cc       
+
+#define MS_PCTL_BCR_OFFSET        0x0d0
+#define MS_PCTL_BALR0_OFFSET      0x0d4
+#define MS_PCTL_BALR1_OFFSET      0x0d8
+#define MS_PCTL_BDR0_OFFSET       0x0dc
+#define MS_PCTL_BDR1_OFFSET       0x0e0
+#define MS_PCTL_BBR_OFFSET        0x0e4
+#define MS_PCTL_BSR_OFFSET        0x0e8
+#define MS_PCTL_BYR_OFFSET        0x0ec
+#define MS_PCTL_BFA_OFFSET        0x0f0
+#define MS_PCTL_IDR_OFFSET        0x0f8
+#define MS_PCTL_ERR_OFFSET        0x0fc
+
+#define MS_WRAP_SCR_OFFSET        0x224
+#define MS_WRAP_QCR_OFFSET        0x230
+#define MS_WRAP_PCR_OFFSET        0x234
+#define MS_WRAP_QTR0_OFFSET       0x240
+#define MS_WRAP_QTR1_OFFSET       0x244
+#define MS_WRAP_QTR2_OFFSET       0x248
+#define MS_WRAP_QTR3_OFFSET       0x24c
+#define MS_WRAP_QTR4_OFFSET       0x250
+#define MS_WRAP_QTR5_OFFSET       0x254
+#define MS_WRAP_QTR6_OFFSET       0x258
+#define MS_WRAP_QTR7_OFFSET       0x25c
+#define MS_WRAP_QTR8_OFFSET       0x260
+#define MS_WRAP_QTR9_OFFSET       0x264
+#define MS_WRAP_QTR10_OFFSET      0x268
+#define MS_WRAP_QTR11_OFFSET      0x26c
+#define MS_WRAP_QTR12_OFFSET      0x270
+#define MS_WRAP_QTR13_OFFSET      0x274
+#define MS_WRAP_QTR14_OFFSET      0x278
+#define MS_WRAP_QTR15_OFFSET      0x27c
+
+#define MS_PHY_DLY0               0x100  
+#define MS_PHY_DLY1_RST           0x104  
+#define MS_PHY_DLY_CLK            0x108  
+#define MS_PHY_DLY_ST             0x10c  
+#define MS_PHY_DLY_NUM            0x100 
+
+#define PCTL_CCR_INIT_BFO          0
+#define PCTL_CCR_INIT_BFW          1
+#define PCTL_CCR_DTT_BFO           1
+#define PCTL_CCR_DTT_BFW           1
+#define PCTL_CCR_BTT_BFO           2
+#define PCTL_CCR_BTT_BFW           1
+#define PCTL_CCR_DPIT_BFO          3 
+#define PCTL_CCR_DPIT_BFW          1
+#define PCTL_CCR_FLUSH_FIFO_BFO    8 
+#define PCTL_CCR_FLUSH_FIFO_BFW    1
+
+#define PCTL_DCR_DDR3_BFO          0
+#define PCTL_DCR_DDR3_BFW          1
+#define PCTL_DCR_SDR_BFO           1
+#define PCTL_DCR_SDR_BFW           1
+#define PCTL_DCR_DQ32_BFO          4
+#define PCTL_DCR_DQ32_BFW          1
+#define PCTL_DCR_DFI_RATE_BFO      8
+#define PCTL_DCR_DFI_RATE_BFW      3
+
+#define PCTL_IOCR_RD_PIPE_BFO      8
+#define PCTL_IOCR_RD_PIPE_BFW      4
+#define PCTL_IOCR_TPHY_WD_BFO      12
+#define PCTL_IOCR_TPHY_WD_BFW      5
+#define PCTL_IOCR_TPHY_WL_BFO      17
+#define PCTL_IOCR_TPHY_WL_BFW      3
+#define PCTL_IOCR_TPHY_RD_EN_BFO   20
+#define PCTL_IOCR_TPHY_RD_EN_BFW   5
+
+#define PCTL_CSR_MEM_IDLE_BFO      8
+#define PCTL_CSR_MEM_IDLE_BFW      1
+#define PCTL_CSR_DT_IDLE_BFO       9 
+#define PCTL_CSR_DT_IDLE_BFW       1
+#define PCTL_CSR_BIST_IDLE_BFO     10
+#define PCTL_CSR_BIST_IDLE_BFW     1
+#define PCTL_CSR_DT_FAIL_BFO       11
+#define PCTL_CSR_DT_FAIL_BFW       1
+#define PCTL_CSR_BT_FAIL_BFO       12
+#define PCTL_CSR_BT_FAIL_BFW       1
+
+#define PCTL_DRR_TRFC_BFO          0
+#define PCTL_DRR_TRFC_BFW          7
+#define PCTL_DRR_TREF_BFO          8 
+#define PCTL_DRR_TREF_BFW          24
+#define PCTL_DRR_REF_NUM_BFO       24
+#define PCTL_DRR_REF_NUM_BFW       4
+#define PCTL_DRR_REF_DIS_BFO       28
+#define PCTL_DRR_REF_DIS_BFW       1
+
+#define PCTL_TPR0_TRP_BFO          0
+#define PCTL_TPR0_TRP_BFW          4
+#define PCTL_TPR0_TRAS_BFO         4 
+#define PCTL_TPR0_TRAS_BFW         5 
+#define PCTL_TPR0_TWR_BFO          9 
+#define PCTL_TPR0_TWR_BFW          4
+#define PCTL_TPR0_TRTP_BFO         13
+#define PCTL_TPR0_TRTP_BFW         3
+
+#define PCTL_TPR1_TRRD_BFO         0
+#define PCTL_TPR1_TRRD_BFW         4
+#define PCTL_TPR1_TRC_BFO          4 
+#define PCTL_TPR1_TRC_BFW          6 
+#define PCTL_TPR1_TRCD_BFO         10
+#define PCTL_TPR1_TRCD_BFW         4
+#define PCTL_TPR1_TCCD_BFO         14
+#define PCTL_TPR1_TCCD_BFW         3
+#define PCTL_TPR1_TWTR_BFO         17
+#define PCTL_TPR1_TWTR_BFW         3
+#define PCTL_TPR1_TRTW_BFO         20
+#define PCTL_TPR1_TRTW_BFW         4
+
+#define PCTL_TPR2_INIT_REF_NUM_BFO 0
+#define PCTL_TPR2_INIT_REF_NUM_BFW 4
+#define PCTL_TPR2_INIT_NS_EN_BFO   4 
+#define PCTL_TPR2_INIT_NS_EN_BFW   1 
+#define PCTL_TPR2_TMRD_BFO         5 
+#define PCTL_TPR2_TMRD_BFW         2
+
+#define PCTL_MR_BL_BFO             0 
+#define PCTL_MR_BL_BFW             3
+#define PCTL_MR_BT_BFO             3 
+#define PCTL_MR_BT_BFW             1
+#define PCTL_MR_CAS_BFO            4 
+#define PCTL_MR_CAS_BFW            3
+#define PCTL_MR_OP_BFO             8 
+#define PCTL_MR_OP_BFW             12
+
+#define PCTL_EMR1_ADDLAT_BFO       3 
+#define PCTL_EMR1_ADDLAT_BFW       3
+
+#define PCTL_CMD_DPIN_RSTN_BFO     0 
+#define PCTL_CMD_DPIN_RSTN_BFW     1
+#define PCTL_CMD_DPIN_CKE_BFO      1 
+#define PCTL_CMD_DPIN_CKE_BFW      1
+#define PCTL_CMD_DPIN_ODT_BFO      2 
+#define PCTL_CMD_DPIN_ODT_BFW      1 
+
+#define PCTL_BCR_STOP_BFO          0 
+#define PCTL_BCR_STOP_BFW          1
+#define PCTL_BCR_CMP_BFO           1 
+#define PCTL_BCR_CMP_BFW           1
+#define PCTL_BCR_LOOP_BFO          2 
+#define PCTL_BCR_LOOP_BFW          1 
+#define PCTL_BCR_DIS_MASK_BFO      3 
+#define PCTL_BCR_DIS_MASK_BFW      1
+#define PCTL_BCR_AT_STOP_BFO       4 
+#define PCTL_BCR_AT_STOP_BFW       1
+#define PCTL_BCR_FLUSH_CMD_BFO     8 
+#define PCTL_BCR_FLUSH_CMD_BFW     1
+#define PCTL_BCR_FLUSH_WD_BFO      9 
+#define PCTL_BCR_FLUSH_WD_BFW      1
+#define PCTL_BCR_FLUSH_RGD_BFO     10
+#define PCTL_BCR_FLUSH_RGD_BFW     1
+#define PCTL_BCR_FLUSH_RD_BFO      11
+#define PCTL_BCR_FLUSH_RD_BFW      1
+#define PCTL_BCR_FLUSH_RD_EXPC_BFO 16
+#define PCTL_BCR_FLUSH_RD_EXPC_BFW 14
+
+#define PCTL_BST_ERR_FST_TH_BFO    0 
+#define PCTL_BST_ERR_FST_TH_BFW    12
+#define PCTL_BST_ERR_CNT_BFO       16
+#define PCTL_BST_ERR_CNT_BFW       14
+
+#define PCTL_BSRAM0_CMD_LEVEL_BFO  0 
+#define PCTL_BSRAM0_CMD_LEVEL_BFW  12
+#define PCTL_BSRAM0_WD_LEVEL_BFO   16
+#define PCTL_BSRAM0_WD_LEVEL_BFW   14
+
+#define PCTL_BSRAM1_RG_LEVEL_BFO   0 
+#define PCTL_BSRAM1_RG_LEVEL_BFW   14
+#define PCTL_BSRAM1_RD_LEVEL_BFO   16
+#define PCTL_BSRAM1_RD_LEVEL_BFW   14
+
+#define WRAP_MISC_PAGE_SIZE_BFO    0 
+#define WRAP_MISC_PAGE_SIZE_BFW    4
+#define WRAP_MISC_BANK_SIZE_BFO    4 
+#define WRAP_MISC_BANK_SIZE_BFW    2
+#define WRAP_MISC_BST_SIZE_BFO     6 
+#define WRAP_MISC_BST_SIZE_BFW     2 
+#define WRAP_MISC_DDR_PARAL_BFO    8 
+#define WRAP_MISC_DDR_PARAL_BFW    1
+
+struct ms_rxi310_portmap {
+  volatile unsigned int ccr;           /* 0x000 */
+  volatile unsigned int dcr;           /* 0x004 */
+  volatile unsigned int iocr;          /* 0x008 */
+  volatile unsigned int csr;           /* 0x00c */
+  volatile unsigned int drr;           /* 0x010 */
+  volatile unsigned int tpr0;          /* 0x014 */
+  volatile unsigned int tpr1;          /* 0x018 */
+  volatile unsigned int tpr2;          /* 0x01c */
+  volatile unsigned int mr;            /* 0x020 */
+  volatile unsigned int emr1;          /* 0x024 */
+  volatile unsigned int emr2;          /* 0x028 */
+  volatile unsigned int emr3;          /* 0x02c */
+  volatile unsigned int cdpin;         /* 0x030 */
+  volatile unsigned int tdpin;         /* 0x034 */
+  volatile unsigned int dtr2;          /* 0x038 */
+  volatile unsigned int dtr3;          /* 0x03c */
+  volatile unsigned int gdllcr;        /* 0x040 */
+  volatile unsigned int dllcr0;        /* 0x044 */
+  volatile unsigned int dllcr1;        /* 0x048 */
+  volatile unsigned int dllcr2;        /* 0x04c */
+  volatile unsigned int dllcr3;        /* 0x050 */
+  volatile unsigned int dllcr4;        /* 0x054 */
+  volatile unsigned int dllcr5;        /* 0x058 */
+  volatile unsigned int dllcr6;        /* 0x05c */
+  volatile unsigned int dllcr7;        /* 0x060 */
+  volatile unsigned int dllcr8;        /* 0x064 */
+  volatile unsigned int dqtr0;         /* 0x068 */
+  volatile unsigned int dqtr1;         /* 0x06c */
+  volatile unsigned int dqtr2;         /* 0x070 */
+  volatile unsigned int dqtr3;         /* 0x074 */
+  volatile unsigned int dqtr4;         /* 0x078 */
+  volatile unsigned int dqtr5;         /* 0x07c */
+  volatile unsigned int dqtr6;         /* 0x080 */
+  volatile unsigned int dqtr7;         /* 0x084 */
+  volatile unsigned int dqstr;         /* 0x088 */
+  volatile unsigned int dqsbtr;        /* 0x08c */
+  volatile unsigned int odtcr;         /* 0x090 */
+  volatile unsigned int dtr0;          /* 0x094 */
+  volatile unsigned int dtr1;          /* 0x098 */
+  volatile unsigned int dtar;          /* 0x09c */
+  volatile unsigned int zqcr0;         /* 0x0a0 */
+  volatile unsigned int zqcr1;         /* 0x0a4 */
+  volatile unsigned int zqsr;          /* 0x0a8 */
+  volatile unsigned int rslr0;         /* 0x0ac */
+  volatile unsigned int rslr1;         /* 0x0b0 */
+  volatile unsigned int rslr2;         /* 0x0b4 */
+  volatile unsigned int rslr3;         /* 0x0b8 */
+  volatile unsigned int rdgr0;         /* 0x0bc */
+  volatile unsigned int rdgr1;         /* 0x0c0 */
+  volatile unsigned int rdgr2;         /* 0x0c4 */
+  volatile unsigned int rdgr3;         /* 0x0c8 */
+  volatile unsigned int mxsl;          /* 0x0cc */
+  volatile unsigned int bcr;           /* 0x0d0 */
+  volatile unsigned int bst;           /* 0x0d4 */
+  volatile unsigned int bsram0;        /* 0x0d8 */
+  volatile unsigned int bsram1;        /* 0x0dc */
+  volatile unsigned int bdr1;          /* 0x0e0 */
+  volatile unsigned int bbr;           /* 0x0e4 */
+  volatile unsigned int bsr;           /* 0x0e8 */
+  volatile unsigned int byr;           /* 0x0ec */
+  volatile unsigned int bfa;           /* 0x0f0 */
+  volatile unsigned int pctl_svn;      /* 0x0f4 */
+  volatile unsigned int pctl_idr;      /* 0x0f8 */
+  volatile unsigned int err;           /* 0x0fc */
+
+  // SDR_PHY CONTROL REGISTER
+  volatile unsigned int phy_dly0;      /* 0x100 */
+  volatile unsigned int phy_dly1_rst;  /* 0x104 */
+  volatile unsigned int phy_dly_clk;   /* 0x108 */
+  volatile unsigned int phy_dly_st;    /* 0x10c */
+  volatile unsigned int phy_dly_num;   /* 0x110 */
+  volatile unsigned int reserved0[68];
+
+  // WRAP CONTROL REGISTER
+  volatile unsigned int misc;          /* 0x224 */
+  volatile unsigned int cq_ver;        /* 0x228 */
+  volatile unsigned int cq_mon;        /* 0x22c */
+  volatile unsigned int wq_ver;        /* 0x230 */
+  volatile unsigned int wq_mon;        /* 0x234 */
+  volatile unsigned int rq_ver;        /* 0x240 */
+  volatile unsigned int rq_mon;        /* 0x244 */
+  volatile unsigned int reserved1[22];          
+  volatile unsigned int wwrap_idr;     /* 0x2a0 */
+  volatile unsigned int wrap_svn;      /* 0x2a4 */
+
+}; //ms_rxi310_portmap
+
+#define QFIFO_CMD_BANK_BFO             (35 - QFIFO_CMD_WRRD_BFO) // [38:35]
+#define QFIFO_CMD_BANK_BFW              4                 
+#define QFIFO_CMD_PAGE_BFO             (20 - QFIFO_CMD_WRRD_BFO) // [34:20]
+#define QFIFO_CMD_PAGE_BFW              15 
+#define QFIFO_CMD_COLU_BFO             (7  - QFIFO_CMD_WRRD_BFO) // [19: 7]
+#define QFIFO_CMD_COLU_BFW              13 // [19: 7]
+#define QFIFO_BST_LEN_BFO              (3  - QFIFO_CMD_WRRD_BFO) // [6:3]
+#define QFIFO_BST_LEN_BFW               4  // [6:3]
+#define QFIFO_CMD_WRRD_BFO              2                        // [2], remove bit[1:0]
+#define QFIFO_CMD_WRRD_BFW              1  // [2], remove bit[1:0]
+
+//====================================================//
+
+#define REG_SDR_CCR                 0x00
+#define REG_SDR_DCR                 0x04
+#define REG_SDR_IOCR                0x08
+#define REG_SDR_CSR                 0x0C
+#define REG_SDR_DRR                 0x10
+#define REG_SDR_TPR0                0x14
+#define REG_SDR_TPR1                0x18
+#define REG_SDR_TPR2                0x1C
+#define REG_SDR_MR                  0x20
+#define REG_SDR_EMR1                0x24
+#define REG_SDR_EMR2                0x28
+#define REG_SDR_EMR3                0x2C
+#define REG_SDR_CMD_DPIN            0x30
+#define REG_SDR_TIE_DPIN            0x34
+#define REG_SDR_BCR                 0xD0
+#define REG_SDR_BST                 0xD4
+#define REG_SDR_BSRAM0              0xD8
+#define REG_SDR_BSRAM1              0xDC
+#define REG_SDR_PCTL_SVN_ID         0xF4
+#define REG_SDR_PCTL_IDR            0xF8
+#define REG_SDR_DLY0                0x100
+
+#define REG_SDR_DLY1                0x104
+#define REG_SDR_DCM_RST             0x104
+
+#define REG_SDR_DLY_CLK_PHA         0x108
+#define REG_SDR_DLY_ST              0x10C
+
+#define REG_SDR_MISC                0x224
+#define REG_SDR_OCP_WRAP_IDR        0x2A0
+#define REG_SDR_OCP_WRAP_VERSION    0x2A4
+
+
+#endif  // end of "#ifndef _RTL8195A_SDR_H"

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h

@@ -0,0 +1,990 @@
+#ifndef _RTL8195A_SPI_FLASH_H
+#define _RTL8195A_SPI_FLASH_H
+
+#define CPU_OPT_WIDTH 0x1F
+
+//2 REG_NOT_VALID
+
+//2 REG_SPIC_CTRLR0
+
+#define BIT_SHIFT_CK_MTIMES 23
+#define BIT_MASK_CK_MTIMES 0x1f
+#define BIT_CK_MTIMES(x)                      	(((x) & BIT_MASK_CK_MTIMES) << BIT_SHIFT_CK_MTIMES)
+#define BIT_CTRL_CK_MTIMES(x)                 	(((x) & BIT_MASK_CK_MTIMES) << BIT_SHIFT_CK_MTIMES)
+#define BIT_GET_CK_MTIMES(x)                  	(((x) >> BIT_SHIFT_CK_MTIMES) & BIT_MASK_CK_MTIMES)
+
+#define BIT_FAST_RD                           	BIT(22)
+#define BIT_SHIFT_FAST_RD                     	22
+#define BIT_MASK_FAST_RD                      	0x1
+#define BIT_CTRL_FAST_RD(x)                   	(((x) & BIT_MASK_FAST_RD) << BIT_SHIFT_FAST_RD)
+
+
+#define BIT_SHIFT_CMD_CH 20
+#define BIT_MASK_CMD_CH 0x3
+#define BIT_CMD_CH(x)                         	(((x) & BIT_MASK_CMD_CH) << BIT_SHIFT_CMD_CH)
+#define BIT_CTRL_CMD_CH(x)                    	(((x) & BIT_MASK_CMD_CH) << BIT_SHIFT_CMD_CH)
+#define BIT_GET_CMD_CH(x)                     	(((x) >> BIT_SHIFT_CMD_CH) & BIT_MASK_CMD_CH)
+
+
+#define BIT_SHIFT_DATA_CH 18
+#define BIT_MASK_DATA_CH 0x3
+#define BIT_DATA_CH(x)                        	(((x) & BIT_MASK_DATA_CH) << BIT_SHIFT_DATA_CH)
+#define BIT_CTRL_DATA_CH(x)                   	(((x) & BIT_MASK_DATA_CH) << BIT_SHIFT_DATA_CH)
+#define BIT_GET_DATA_CH(x)                    	(((x) >> BIT_SHIFT_DATA_CH) & BIT_MASK_DATA_CH)
+
+
+#define BIT_SHIFT_ADDR_CH 16
+#define BIT_MASK_ADDR_CH 0x3
+#define BIT_ADDR_CH(x)                        	(((x) & BIT_MASK_ADDR_CH) << BIT_SHIFT_ADDR_CH)
+#define BIT_CTRL_ADDR_CH(x)                   	(((x) & BIT_MASK_ADDR_CH) << BIT_SHIFT_ADDR_CH)
+#define BIT_GET_ADDR_CH(x)                    	(((x) >> BIT_SHIFT_ADDR_CH) & BIT_MASK_ADDR_CH)
+
+
+#define BIT_SHIFT_TMOD 8
+#define BIT_MASK_TMOD 0x3
+#define BIT_TMOD(x)                           	(((x) & BIT_MASK_TMOD) << BIT_SHIFT_TMOD)
+#define BIT_CTRL_TMOD(x)                      	(((x) & BIT_MASK_TMOD) << BIT_SHIFT_TMOD)
+#define BIT_GET_TMOD(x)                       	(((x) >> BIT_SHIFT_TMOD) & BIT_MASK_TMOD)
+
+#define BIT_SCPOL                             	BIT(7)
+#define BIT_SHIFT_SCPOL                       	7
+#define BIT_MASK_SCPOL                        	0x1
+#define BIT_CTRL_SCPOL(x)                     	(((x) & BIT_MASK_SCPOL) << BIT_SHIFT_SCPOL)
+
+#define BIT_SCPH                              	BIT(6)
+#define BIT_SHIFT_SCPH                        	6
+#define BIT_MASK_SCPH                         	0x1
+#define BIT_CTRL_SCPH(x)                      	(((x) & BIT_MASK_SCPH) << BIT_SHIFT_SCPH)
+
+//2 REG_SPIC_CTRLR1
+
+#define BIT_SHIFT_NDF 0
+#define BIT_MASK_NDF 0xfff
+#define BIT_NDF(x)                            	(((x) & BIT_MASK_NDF) << BIT_SHIFT_NDF)
+#define BIT_CTRL_NDF(x)                       	(((x) & BIT_MASK_NDF) << BIT_SHIFT_NDF)
+#define BIT_GET_NDF(x)                        	(((x) >> BIT_SHIFT_NDF) & BIT_MASK_NDF)
+
+
+//2 REG_SPIC_SSIENR
+#define BIT_ATCK_CMD                          	BIT(1)
+#define BIT_SHIFT_ATCK_CMD                    	1
+#define BIT_MASK_ATCK_CMD                     	0x1
+#define BIT_CTRL_ATCK_CMD(x)                  	(((x) & BIT_MASK_ATCK_CMD) << BIT_SHIFT_ATCK_CMD)
+
+#define BIT_SPIC_EN                           	BIT(0)
+#define BIT_SHIFT_SPIC_EN                     	0
+#define BIT_MASK_SPIC_EN                      	0x1
+#define BIT_CTRL_SPIC_EN(x)                   	(((x) & BIT_MASK_SPIC_EN) << BIT_SHIFT_SPIC_EN)
+
+//2 REG_SPIC_MWCR
+
+//2 REG_SPIC_SER
+#define BIT_SER                               	BIT(0)
+#define BIT_SHIFT_SER                         	0
+#define BIT_MASK_SER                          	0x1
+#define BIT_CTRL_SER(x)                       	(((x) & BIT_MASK_SER) << BIT_SHIFT_SER)
+
+//2 REG_SPIC_BAUDR
+
+#define BIT_SHIFT_SCKDV 0
+#define BIT_MASK_SCKDV 0xffff
+#define BIT_SCKDV(x)                          	(((x) & BIT_MASK_SCKDV) << BIT_SHIFT_SCKDV)
+#define BIT_CTRL_SCKDV(x)                     	(((x) & BIT_MASK_SCKDV) << BIT_SHIFT_SCKDV)
+#define BIT_GET_SCKDV(x)                      	(((x) >> BIT_SHIFT_SCKDV) & BIT_MASK_SCKDV)
+
+
+//2 REG_SPIC_TXFTLR
+
+#define BIT_SHIFT_TFT 0
+#define BIT_MASK_TFT 0x1f
+#define BIT_TFT(x)                            	(((x) & BIT_MASK_TFT) << BIT_SHIFT_TFT)
+#define BIT_CTRL_TFT(x)                       	(((x) & BIT_MASK_TFT) << BIT_SHIFT_TFT)
+#define BIT_GET_TFT(x)                        	(((x) >> BIT_SHIFT_TFT) & BIT_MASK_TFT)
+
+
+//2 REG_SPIC_RXFTLR
+
+#define BIT_SHIFT_RFT 0
+#define BIT_MASK_RFT 0x1f
+#define BIT_RFT(x)                            	(((x) & BIT_MASK_RFT) << BIT_SHIFT_RFT)
+#define BIT_CTRL_RFT(x)                       	(((x) & BIT_MASK_RFT) << BIT_SHIFT_RFT)
+#define BIT_GET_RFT(x)                        	(((x) >> BIT_SHIFT_RFT) & BIT_MASK_RFT)
+
+
+//2 REG_SPIC_TXFLR
+
+#define BIT_SHIFT_TXFL 0
+#define BIT_MASK_TXFL 0x3f
+#define BIT_TXFL(x)                           	(((x) & BIT_MASK_TXFL) << BIT_SHIFT_TXFL)
+#define BIT_CTRL_TXFL(x)                      	(((x) & BIT_MASK_TXFL) << BIT_SHIFT_TXFL)
+#define BIT_GET_TXFL(x)                       	(((x) >> BIT_SHIFT_TXFL) & BIT_MASK_TXFL)
+
+
+//2 REG_SPIC_RXFLR
+
+#define BIT_SHIFT_RXFL 0
+#define BIT_MASK_RXFL 0x3f
+#define BIT_RXFL(x)                           	(((x) & BIT_MASK_RXFL) << BIT_SHIFT_RXFL)
+#define BIT_CTRL_RXFL(x)                      	(((x) & BIT_MASK_RXFL) << BIT_SHIFT_RXFL)
+#define BIT_GET_RXFL(x)                       	(((x) >> BIT_SHIFT_RXFL) & BIT_MASK_RXFL)
+
+
+//2 REG_SPIC_SR
+#define BIT_TXE                               	BIT(5)
+#define BIT_SHIFT_TXE                         	5
+#define BIT_MASK_TXE                          	0x1
+#define BIT_CTRL_TXE(x)                       	(((x) & BIT_MASK_TXE) << BIT_SHIFT_TXE)
+
+#define BIT_RFF                               	BIT(4)
+#define BIT_SHIFT_RFF                         	4
+#define BIT_MASK_RFF                          	0x1
+#define BIT_CTRL_RFF(x)                       	(((x) & BIT_MASK_RFF) << BIT_SHIFT_RFF)
+
+#define BIT_RFNE                              	BIT(3)
+#define BIT_SHIFT_RFNE                        	3
+#define BIT_MASK_RFNE                         	0x1
+#define BIT_CTRL_RFNE(x)                      	(((x) & BIT_MASK_RFNE) << BIT_SHIFT_RFNE)
+
+#define BIT_TFE                               	BIT(2)
+#define BIT_SHIFT_TFE                         	2
+#define BIT_MASK_TFE                          	0x1
+#define BIT_CTRL_TFE(x)                       	(((x) & BIT_MASK_TFE) << BIT_SHIFT_TFE)
+
+#define BIT_TFNF                              	BIT(1)
+#define BIT_SHIFT_TFNF                        	1
+#define BIT_MASK_TFNF                         	0x1
+#define BIT_CTRL_TFNF(x)                      	(((x) & BIT_MASK_TFNF) << BIT_SHIFT_TFNF)
+
+#define BIT_BUSY                              	BIT(0)
+#define BIT_SHIFT_BUSY                        	0
+#define BIT_MASK_BUSY                         	0x1
+#define BIT_CTRL_BUSY(x)                      	(((x) & BIT_MASK_BUSY) << BIT_SHIFT_BUSY)
+
+//2 REG_SPIC_IMR
+#define BIT_TXSIM                             	BIT(9)
+#define BIT_SHIFT_TXSIM                       	9
+#define BIT_MASK_TXSIM                        	0x1
+#define BIT_CTRL_TXSIM(x)                     	(((x) & BIT_MASK_TXSIM) << BIT_SHIFT_TXSIM)
+
+#define BIT_ACEIM                             	BIT(8)
+#define BIT_SHIFT_ACEIM                       	8
+#define BIT_MASK_ACEIM                        	0x1
+#define BIT_CTRL_ACEIM(x)                     	(((x) & BIT_MASK_ACEIM) << BIT_SHIFT_ACEIM)
+
+#define BIT_BYEIM                             	BIT(7)
+#define BIT_SHIFT_BYEIM                       	7
+#define BIT_MASK_BYEIM                        	0x1
+#define BIT_CTRL_BYEIM(x)                     	(((x) & BIT_MASK_BYEIM) << BIT_SHIFT_BYEIM)
+
+#define BIT_WBEIM                             	BIT(6)
+#define BIT_SHIFT_WBEIM                       	6
+#define BIT_MASK_WBEIM                        	0x1
+#define BIT_CTRL_WBEIM(x)                     	(((x) & BIT_MASK_WBEIM) << BIT_SHIFT_WBEIM)
+
+#define BIT_FSEIM                             	BIT(5)
+#define BIT_SHIFT_FSEIM                       	5
+#define BIT_MASK_FSEIM                        	0x1
+#define BIT_CTRL_FSEIM(x)                     	(((x) & BIT_MASK_FSEIM) << BIT_SHIFT_FSEIM)
+
+#define BIT_RXFIM                             	BIT(4)
+#define BIT_SHIFT_RXFIM                       	4
+#define BIT_MASK_RXFIM                        	0x1
+#define BIT_CTRL_RXFIM(x)                     	(((x) & BIT_MASK_RXFIM) << BIT_SHIFT_RXFIM)
+
+#define BIT_RXOIM                             	BIT(3)
+#define BIT_SHIFT_RXOIM                       	3
+#define BIT_MASK_RXOIM                        	0x1
+#define BIT_CTRL_RXOIM(x)                     	(((x) & BIT_MASK_RXOIM) << BIT_SHIFT_RXOIM)
+
+#define BIT_RXUIM                             	BIT(2)
+#define BIT_SHIFT_RXUIM                       	2
+#define BIT_MASK_RXUIM                        	0x1
+#define BIT_CTRL_RXUIM(x)                     	(((x) & BIT_MASK_RXUIM) << BIT_SHIFT_RXUIM)
+
+#define BIT_TXOIM                             	BIT(1)
+#define BIT_SHIFT_TXOIM                       	1
+#define BIT_MASK_TXOIM                        	0x1
+#define BIT_CTRL_TXOIM(x)                     	(((x) & BIT_MASK_TXOIM) << BIT_SHIFT_TXOIM)
+
+#define BIT_TXEIM                             	BIT(0)
+#define BIT_SHIFT_TXEIM                       	0
+#define BIT_MASK_TXEIM                        	0x1
+#define BIT_CTRL_TXEIM(x)                     	(((x) & BIT_MASK_TXEIM) << BIT_SHIFT_TXEIM)
+
+//2 REG_SPIC_ISR
+#define BIT_TXSIS                             	BIT(9)
+#define BIT_SHIFT_TXSIS                       	9
+#define BIT_MASK_TXSIS                        	0x1
+#define BIT_CTRL_TXSIS(x)                     	(((x) & BIT_MASK_TXSIS) << BIT_SHIFT_TXSIS)
+
+#define BIT_ACEIS                             	BIT(8)
+#define BIT_SHIFT_ACEIS                       	8
+#define BIT_MASK_ACEIS                        	0x1
+#define BIT_CTRL_ACEIS(x)                     	(((x) & BIT_MASK_ACEIS) << BIT_SHIFT_ACEIS)
+
+#define BIT_BYEIS                             	BIT(7)
+#define BIT_SHIFT_BYEIS                       	7
+#define BIT_MASK_BYEIS                        	0x1
+#define BIT_CTRL_BYEIS(x)                     	(((x) & BIT_MASK_BYEIS) << BIT_SHIFT_BYEIS)
+
+#define BIT_WBEIS                             	BIT(6)
+#define BIT_SHIFT_WBEIS                       	6
+#define BIT_MASK_WBEIS                        	0x1
+#define BIT_CTRL_WBEIS(x)                     	(((x) & BIT_MASK_WBEIS) << BIT_SHIFT_WBEIS)
+
+#define BIT_FSEIS                             	BIT(5)
+#define BIT_SHIFT_FSEIS                       	5
+#define BIT_MASK_FSEIS                        	0x1
+#define BIT_CTRL_FSEIS(x)                     	(((x) & BIT_MASK_FSEIS) << BIT_SHIFT_FSEIS)
+
+#define BIT_RXFIS                             	BIT(4)
+#define BIT_SHIFT_RXFIS                       	4
+#define BIT_MASK_RXFIS                        	0x1
+#define BIT_CTRL_RXFIS(x)                     	(((x) & BIT_MASK_RXFIS) << BIT_SHIFT_RXFIS)
+
+#define BIT_RXOIS                             	BIT(3)
+#define BIT_SHIFT_RXOIS                       	3
+#define BIT_MASK_RXOIS                        	0x1
+#define BIT_CTRL_RXOIS(x)                     	(((x) & BIT_MASK_RXOIS) << BIT_SHIFT_RXOIS)
+
+#define BIT_RXUIS                             	BIT(2)
+#define BIT_SHIFT_RXUIS                       	2
+#define BIT_MASK_RXUIS                        	0x1
+#define BIT_CTRL_RXUIS(x)                     	(((x) & BIT_MASK_RXUIS) << BIT_SHIFT_RXUIS)
+
+#define BIT_TXOIS                             	BIT(1)
+#define BIT_SHIFT_TXOIS                       	1
+#define BIT_MASK_TXOIS                        	0x1
+#define BIT_CTRL_TXOIS(x)                     	(((x) & BIT_MASK_TXOIS) << BIT_SHIFT_TXOIS)
+
+#define BIT_TXEIS                             	BIT(0)
+#define BIT_SHIFT_TXEIS                       	0
+#define BIT_MASK_TXEIS                        	0x1
+#define BIT_CTRL_TXEIS(x)                     	(((x) & BIT_MASK_TXEIS) << BIT_SHIFT_TXEIS)
+
+//2 REG_SPIC_RISR
+#define BIT_ACEIR                             	BIT(8)
+#define BIT_SHIFT_ACEIR                       	8
+#define BIT_MASK_ACEIR                        	0x1
+#define BIT_CTRL_ACEIR(x)                     	(((x) & BIT_MASK_ACEIR) << BIT_SHIFT_ACEIR)
+
+#define BIT_BYEIR                             	BIT(7)
+#define BIT_SHIFT_BYEIR                       	7
+#define BIT_MASK_BYEIR                        	0x1
+#define BIT_CTRL_BYEIR(x)                     	(((x) & BIT_MASK_BYEIR) << BIT_SHIFT_BYEIR)
+
+#define BIT_WBEIR                             	BIT(6)
+#define BIT_SHIFT_WBEIR                       	6
+#define BIT_MASK_WBEIR                        	0x1
+#define BIT_CTRL_WBEIR(x)                     	(((x) & BIT_MASK_WBEIR) << BIT_SHIFT_WBEIR)
+
+#define BIT_FSEIR                             	BIT(5)
+#define BIT_SHIFT_FSEIR                       	5
+#define BIT_MASK_FSEIR                        	0x1
+#define BIT_CTRL_FSEIR(x)                     	(((x) & BIT_MASK_FSEIR) << BIT_SHIFT_FSEIR)
+
+#define BIT_RXFIR                             	BIT(4)
+#define BIT_SHIFT_RXFIR                       	4
+#define BIT_MASK_RXFIR                        	0x1
+#define BIT_CTRL_RXFIR(x)                     	(((x) & BIT_MASK_RXFIR) << BIT_SHIFT_RXFIR)
+
+#define BIT_RXOIR                             	BIT(3)
+#define BIT_SHIFT_RXOIR                       	3
+#define BIT_MASK_RXOIR                        	0x1
+#define BIT_CTRL_RXOIR(x)                     	(((x) & BIT_MASK_RXOIR) << BIT_SHIFT_RXOIR)
+
+#define BIT_RXUIR                             	BIT(2)
+#define BIT_SHIFT_RXUIR                       	2
+#define BIT_MASK_RXUIR                        	0x1
+#define BIT_CTRL_RXUIR(x)                     	(((x) & BIT_MASK_RXUIR) << BIT_SHIFT_RXUIR)
+
+#define BIT_TXOIR                             	BIT(1)
+#define BIT_SHIFT_TXOIR                       	1
+#define BIT_MASK_TXOIR                        	0x1
+#define BIT_CTRL_TXOIR(x)                     	(((x) & BIT_MASK_TXOIR) << BIT_SHIFT_TXOIR)
+
+#define BIT_TXEIR                             	BIT(0)
+#define BIT_SHIFT_TXEIR                       	0
+#define BIT_MASK_TXEIR                        	0x1
+#define BIT_CTRL_TXEIR(x)                     	(((x) & BIT_MASK_TXEIR) << BIT_SHIFT_TXEIR)
+
+//2 REG_SPIC_TXOICR
+#define BIT_TXOICR                            	BIT(0)
+#define BIT_SHIFT_TXOICR                      	0
+#define BIT_MASK_TXOICR                       	0x1
+#define BIT_CTRL_TXOICR(x)                    	(((x) & BIT_MASK_TXOICR) << BIT_SHIFT_TXOICR)
+
+//2 REG_SPIC_RXOICR
+#define BIT_RXOCIR                            	BIT(0)
+#define BIT_SHIFT_RXOCIR                      	0
+#define BIT_MASK_RXOCIR                       	0x1
+#define BIT_CTRL_RXOCIR(x)                    	(((x) & BIT_MASK_RXOCIR) << BIT_SHIFT_RXOCIR)
+
+//2 REG_SPC_RXUICR
+#define BIT_RXUICR                            	BIT(0)
+#define BIT_SHIFT_RXUICR                      	0
+#define BIT_MASK_RXUICR                       	0x1
+#define BIT_CTRL_RXUICR(x)                    	(((x) & BIT_MASK_RXUICR) << BIT_SHIFT_RXUICR)
+
+//2 REG_SPIC_MSTICR
+#define BIT_MSTICR                            	BIT(0)
+#define BIT_SHIFT_MSTICR                      	0
+#define BIT_MASK_MSTICR                       	0x1
+#define BIT_CTRL_MSTICR(x)                    	(((x) & BIT_MASK_MSTICR) << BIT_SHIFT_MSTICR)
+
+//2 REG_SPIC_ICR
+
+#define BIT_SHIFT_ICR 0
+#define BIT_MASK_ICR 0xff
+#define BIT_ICR(x)                            	(((x) & BIT_MASK_ICR) << BIT_SHIFT_ICR)
+#define BIT_CTRL_ICR(x)                       	(((x) & BIT_MASK_ICR) << BIT_SHIFT_ICR)
+#define BIT_GET_ICR(x)                        	(((x) >> BIT_SHIFT_ICR) & BIT_MASK_ICR)
+
+
+//2 REG_SPIC_DMACR
+
+//2 REG_SPIC_DMATDLR0
+
+//2 REG_SPIC_DMATDLR1
+
+//2 REG_SPIC_IDR
+
+#define BIT_SHIFT_IDCODE 0
+#define BIT_MASK_IDCODE 0xffffffffL
+#define BIT_IDCODE(x)                         	(((x) & BIT_MASK_IDCODE) << BIT_SHIFT_IDCODE)
+#define BIT_CTRL_IDCODE(x)                    	(((x) & BIT_MASK_IDCODE) << BIT_SHIFT_IDCODE)
+#define BIT_GET_IDCODE(x)                     	(((x) >> BIT_SHIFT_IDCODE) & BIT_MASK_IDCODE)
+
+
+//2 REG_SPIC_VERSION
+
+#define BIT_SHIFT_SPIC_VERSION 0
+#define BIT_MASK_SPIC_VERSION 0xffffffffL
+#define BIT_SPIC_VERSION(x)                   	(((x) & BIT_MASK_SPIC_VERSION) << BIT_SHIFT_SPIC_VERSION)
+#define BIT_CTRL_SPIC_VERSION(x)              	(((x) & BIT_MASK_SPIC_VERSION) << BIT_SHIFT_SPIC_VERSION)
+#define BIT_GET_SPIC_VERSION(x)               	(((x) >> BIT_SHIFT_SPIC_VERSION) & BIT_MASK_SPIC_VERSION)
+
+
+//2 REG_SPIC_DR0
+
+#define BIT_SHIFT_DR0 0
+#define BIT_MASK_DR0 0xffffffffL
+#define BIT_DR0(x)                            	(((x) & BIT_MASK_DR0) << BIT_SHIFT_DR0)
+#define BIT_CTRL_DR0(x)                       	(((x) & BIT_MASK_DR0) << BIT_SHIFT_DR0)
+#define BIT_GET_DR0(x)                        	(((x) >> BIT_SHIFT_DR0) & BIT_MASK_DR0)
+
+
+//2 REG_SPIC_DR1
+
+#define BIT_SHIFT_DR1 0
+#define BIT_MASK_DR1 0xffffffffL
+#define BIT_DR1(x)                            	(((x) & BIT_MASK_DR1) << BIT_SHIFT_DR1)
+#define BIT_CTRL_DR1(x)                       	(((x) & BIT_MASK_DR1) << BIT_SHIFT_DR1)
+#define BIT_GET_DR1(x)                        	(((x) >> BIT_SHIFT_DR1) & BIT_MASK_DR1)
+
+
+//2 REG_SPIC_DR2
+
+#define BIT_SHIFT_DR2 0
+#define BIT_MASK_DR2 0xffffffffL
+#define BIT_DR2(x)                            	(((x) & BIT_MASK_DR2) << BIT_SHIFT_DR2)
+#define BIT_CTRL_DR2(x)                       	(((x) & BIT_MASK_DR2) << BIT_SHIFT_DR2)
+#define BIT_GET_DR2(x)                        	(((x) >> BIT_SHIFT_DR2) & BIT_MASK_DR2)
+
+
+//2 REG_SPIC_DR3
+
+#define BIT_SHIFT_DR3 0
+#define BIT_MASK_DR3 0xffffffffL
+#define BIT_DR3(x)                            	(((x) & BIT_MASK_DR3) << BIT_SHIFT_DR3)
+#define BIT_CTRL_DR3(x)                       	(((x) & BIT_MASK_DR3) << BIT_SHIFT_DR3)
+#define BIT_GET_DR3(x)                        	(((x) >> BIT_SHIFT_DR3) & BIT_MASK_DR3)
+
+
+//2 REG_SPIC_DR4
+
+#define BIT_SHIFT_DR4 0
+#define BIT_MASK_DR4 0xffffffffL
+#define BIT_DR4(x)                            	(((x) & BIT_MASK_DR4) << BIT_SHIFT_DR4)
+#define BIT_CTRL_DR4(x)                       	(((x) & BIT_MASK_DR4) << BIT_SHIFT_DR4)
+#define BIT_GET_DR4(x)                        	(((x) >> BIT_SHIFT_DR4) & BIT_MASK_DR4)
+
+
+//2 REG_SPIC_DR5
+
+#define BIT_SHIFT_DR5 0
+#define BIT_MASK_DR5 0xffffffffL
+#define BIT_DR5(x)                            	(((x) & BIT_MASK_DR5) << BIT_SHIFT_DR5)
+#define BIT_CTRL_DR5(x)                       	(((x) & BIT_MASK_DR5) << BIT_SHIFT_DR5)
+#define BIT_GET_DR5(x)                        	(((x) >> BIT_SHIFT_DR5) & BIT_MASK_DR5)
+
+
+//2 REG_SPIC_DR6
+
+#define BIT_SHIFT_DR6 0
+#define BIT_MASK_DR6 0xffffffffL
+#define BIT_DR6(x)                            	(((x) & BIT_MASK_DR6) << BIT_SHIFT_DR6)
+#define BIT_CTRL_DR6(x)                       	(((x) & BIT_MASK_DR6) << BIT_SHIFT_DR6)
+#define BIT_GET_DR6(x)                        	(((x) >> BIT_SHIFT_DR6) & BIT_MASK_DR6)
+
+
+//2 REG_SPIC_DR7
+
+#define BIT_SHIFT_DR7 0
+#define BIT_MASK_DR7 0xffffffffL
+#define BIT_DR7(x)                            	(((x) & BIT_MASK_DR7) << BIT_SHIFT_DR7)
+#define BIT_CTRL_DR7(x)                       	(((x) & BIT_MASK_DR7) << BIT_SHIFT_DR7)
+#define BIT_GET_DR7(x)                        	(((x) >> BIT_SHIFT_DR7) & BIT_MASK_DR7)
+
+
+//2 REG_SPIC_DR8
+
+#define BIT_SHIFT_DR8 0
+#define BIT_MASK_DR8 0xffffffffL
+#define BIT_DR8(x)                            	(((x) & BIT_MASK_DR8) << BIT_SHIFT_DR8)
+#define BIT_CTRL_DR8(x)                       	(((x) & BIT_MASK_DR8) << BIT_SHIFT_DR8)
+#define BIT_GET_DR8(x)                        	(((x) >> BIT_SHIFT_DR8) & BIT_MASK_DR8)
+
+
+//2 REG_SPIC_DR9
+
+#define BIT_SHIFT_DR9 0
+#define BIT_MASK_DR9 0xffffffffL
+#define BIT_DR9(x)                            	(((x) & BIT_MASK_DR9) << BIT_SHIFT_DR9)
+#define BIT_CTRL_DR9(x)                       	(((x) & BIT_MASK_DR9) << BIT_SHIFT_DR9)
+#define BIT_GET_DR9(x)                        	(((x) >> BIT_SHIFT_DR9) & BIT_MASK_DR9)
+
+
+//2 REG_SPIC_DR10
+
+#define BIT_SHIFT_DR10 0
+#define BIT_MASK_DR10 0xffffffffL
+#define BIT_DR10(x)                           	(((x) & BIT_MASK_DR10) << BIT_SHIFT_DR10)
+#define BIT_CTRL_DR10(x)                      	(((x) & BIT_MASK_DR10) << BIT_SHIFT_DR10)
+#define BIT_GET_DR10(x)                       	(((x) >> BIT_SHIFT_DR10) & BIT_MASK_DR10)
+
+
+//2 REG_SPIC_DR11
+
+#define BIT_SHIFT_DR11 0
+#define BIT_MASK_DR11 0xffffffffL
+#define BIT_DR11(x)                           	(((x) & BIT_MASK_DR11) << BIT_SHIFT_DR11)
+#define BIT_CTRL_DR11(x)                      	(((x) & BIT_MASK_DR11) << BIT_SHIFT_DR11)
+#define BIT_GET_DR11(x)                       	(((x) >> BIT_SHIFT_DR11) & BIT_MASK_DR11)
+
+
+//2 REG_SPIC_DR12
+
+#define BIT_SHIFT_DR12 0
+#define BIT_MASK_DR12 0xffffffffL
+#define BIT_DR12(x)                           	(((x) & BIT_MASK_DR12) << BIT_SHIFT_DR12)
+#define BIT_CTRL_DR12(x)                      	(((x) & BIT_MASK_DR12) << BIT_SHIFT_DR12)
+#define BIT_GET_DR12(x)                       	(((x) >> BIT_SHIFT_DR12) & BIT_MASK_DR12)
+
+
+//2 REG_SPIC_DR13
+
+#define BIT_SHIFT_DR13 0
+#define BIT_MASK_DR13 0xffffffffL
+#define BIT_DR13(x)                           	(((x) & BIT_MASK_DR13) << BIT_SHIFT_DR13)
+#define BIT_CTRL_DR13(x)                      	(((x) & BIT_MASK_DR13) << BIT_SHIFT_DR13)
+#define BIT_GET_DR13(x)                       	(((x) >> BIT_SHIFT_DR13) & BIT_MASK_DR13)
+
+
+//2 REG_SPIC_DR14
+
+#define BIT_SHIFT_DR14 0
+#define BIT_MASK_DR14 0xffffffffL
+#define BIT_DR14(x)                           	(((x) & BIT_MASK_DR14) << BIT_SHIFT_DR14)
+#define BIT_CTRL_DR14(x)                      	(((x) & BIT_MASK_DR14) << BIT_SHIFT_DR14)
+#define BIT_GET_DR14(x)                       	(((x) >> BIT_SHIFT_DR14) & BIT_MASK_DR14)
+
+
+//2 REG_SPIC_DR15
+
+#define BIT_SHIFT_DR15 0
+#define BIT_MASK_DR15 0xffffffffL
+#define BIT_DR15(x)                           	(((x) & BIT_MASK_DR15) << BIT_SHIFT_DR15)
+#define BIT_CTRL_DR15(x)                      	(((x) & BIT_MASK_DR15) << BIT_SHIFT_DR15)
+#define BIT_GET_DR15(x)                       	(((x) >> BIT_SHIFT_DR15) & BIT_MASK_DR15)
+
+
+//2 REG_SPIC_DR16
+
+#define BIT_SHIFT_DR16 0
+#define BIT_MASK_DR16 0xffffffffL
+#define BIT_DR16(x)                           	(((x) & BIT_MASK_DR16) << BIT_SHIFT_DR16)
+#define BIT_CTRL_DR16(x)                      	(((x) & BIT_MASK_DR16) << BIT_SHIFT_DR16)
+#define BIT_GET_DR16(x)                       	(((x) >> BIT_SHIFT_DR16) & BIT_MASK_DR16)
+
+
+//2 REG_SPIC_DR17
+
+#define BIT_SHIFT_DR17 0
+#define BIT_MASK_DR17 0xffffffffL
+#define BIT_DR17(x)                           	(((x) & BIT_MASK_DR17) << BIT_SHIFT_DR17)
+#define BIT_CTRL_DR17(x)                      	(((x) & BIT_MASK_DR17) << BIT_SHIFT_DR17)
+#define BIT_GET_DR17(x)                       	(((x) >> BIT_SHIFT_DR17) & BIT_MASK_DR17)
+
+
+//2 REG_SPIC_DR18
+
+#define BIT_SHIFT_DR18 0
+#define BIT_MASK_DR18 0xffffffffL
+#define BIT_DR18(x)                           	(((x) & BIT_MASK_DR18) << BIT_SHIFT_DR18)
+#define BIT_CTRL_DR18(x)                      	(((x) & BIT_MASK_DR18) << BIT_SHIFT_DR18)
+#define BIT_GET_DR18(x)                       	(((x) >> BIT_SHIFT_DR18) & BIT_MASK_DR18)
+
+
+//2 REG_SPIC_DR19
+
+#define BIT_SHIFT_DR19 0
+#define BIT_MASK_DR19 0xffffffffL
+#define BIT_DR19(x)                           	(((x) & BIT_MASK_DR19) << BIT_SHIFT_DR19)
+#define BIT_CTRL_DR19(x)                      	(((x) & BIT_MASK_DR19) << BIT_SHIFT_DR19)
+#define BIT_GET_DR19(x)                       	(((x) >> BIT_SHIFT_DR19) & BIT_MASK_DR19)
+
+
+//2 REG_SPIC_DR20
+
+#define BIT_SHIFT_DR20 0
+#define BIT_MASK_DR20 0xffffffffL
+#define BIT_DR20(x)                           	(((x) & BIT_MASK_DR20) << BIT_SHIFT_DR20)
+#define BIT_CTRL_DR20(x)                      	(((x) & BIT_MASK_DR20) << BIT_SHIFT_DR20)
+#define BIT_GET_DR20(x)                       	(((x) >> BIT_SHIFT_DR20) & BIT_MASK_DR20)
+
+
+//2 REG_SPIC_DR21
+
+#define BIT_SHIFT_DR21 0
+#define BIT_MASK_DR21 0xffffffffL
+#define BIT_DR21(x)                           	(((x) & BIT_MASK_DR21) << BIT_SHIFT_DR21)
+#define BIT_CTRL_DR21(x)                      	(((x) & BIT_MASK_DR21) << BIT_SHIFT_DR21)
+#define BIT_GET_DR21(x)                       	(((x) >> BIT_SHIFT_DR21) & BIT_MASK_DR21)
+
+
+//2 REG_SPIC_DR22
+
+#define BIT_SHIFT_DR22 0
+#define BIT_MASK_DR22 0xffffffffL
+#define BIT_DR22(x)                           	(((x) & BIT_MASK_DR22) << BIT_SHIFT_DR22)
+#define BIT_CTRL_DR22(x)                      	(((x) & BIT_MASK_DR22) << BIT_SHIFT_DR22)
+#define BIT_GET_DR22(x)                       	(((x) >> BIT_SHIFT_DR22) & BIT_MASK_DR22)
+
+
+//2 REG_SPIC_DR23
+
+#define BIT_SHIFT_DR23 0
+#define BIT_MASK_DR23 0xffffffffL
+#define BIT_DR23(x)                           	(((x) & BIT_MASK_DR23) << BIT_SHIFT_DR23)
+#define BIT_CTRL_DR23(x)                      	(((x) & BIT_MASK_DR23) << BIT_SHIFT_DR23)
+#define BIT_GET_DR23(x)                       	(((x) >> BIT_SHIFT_DR23) & BIT_MASK_DR23)
+
+
+//2 REG_SPIC_DR24
+
+#define BIT_SHIFT_DR24 0
+#define BIT_MASK_DR24 0xffffffffL
+#define BIT_DR24(x)                           	(((x) & BIT_MASK_DR24) << BIT_SHIFT_DR24)
+#define BIT_CTRL_DR24(x)                      	(((x) & BIT_MASK_DR24) << BIT_SHIFT_DR24)
+#define BIT_GET_DR24(x)                       	(((x) >> BIT_SHIFT_DR24) & BIT_MASK_DR24)
+
+
+//2 REG_SPIC_DR25
+
+#define BIT_SHIFT_DR25 0
+#define BIT_MASK_DR25 0xffffffffL
+#define BIT_DR25(x)                           	(((x) & BIT_MASK_DR25) << BIT_SHIFT_DR25)
+#define BIT_CTRL_DR25(x)                      	(((x) & BIT_MASK_DR25) << BIT_SHIFT_DR25)
+#define BIT_GET_DR25(x)                       	(((x) >> BIT_SHIFT_DR25) & BIT_MASK_DR25)
+
+
+//2 REG_SPIC_DR26
+
+#define BIT_SHIFT_DR26 0
+#define BIT_MASK_DR26 0xffffffffL
+#define BIT_DR26(x)                           	(((x) & BIT_MASK_DR26) << BIT_SHIFT_DR26)
+#define BIT_CTRL_DR26(x)                      	(((x) & BIT_MASK_DR26) << BIT_SHIFT_DR26)
+#define BIT_GET_DR26(x)                       	(((x) >> BIT_SHIFT_DR26) & BIT_MASK_DR26)
+
+
+//2 REG_SPIC_DR27
+
+#define BIT_SHIFT_DR27 0
+#define BIT_MASK_DR27 0xffffffffL
+#define BIT_DR27(x)                           	(((x) & BIT_MASK_DR27) << BIT_SHIFT_DR27)
+#define BIT_CTRL_DR27(x)                      	(((x) & BIT_MASK_DR27) << BIT_SHIFT_DR27)
+#define BIT_GET_DR27(x)                       	(((x) >> BIT_SHIFT_DR27) & BIT_MASK_DR27)
+
+
+//2 REG_SPIC_DR28
+
+#define BIT_SHIFT_DR28 0
+#define BIT_MASK_DR28 0xffffffffL
+#define BIT_DR28(x)                           	(((x) & BIT_MASK_DR28) << BIT_SHIFT_DR28)
+#define BIT_CTRL_DR28(x)                      	(((x) & BIT_MASK_DR28) << BIT_SHIFT_DR28)
+#define BIT_GET_DR28(x)                       	(((x) >> BIT_SHIFT_DR28) & BIT_MASK_DR28)
+
+
+//2 REG_SPIC_DR29
+
+#define BIT_SHIFT_DR29 0
+#define BIT_MASK_DR29 0xffffffffL
+#define BIT_DR29(x)                           	(((x) & BIT_MASK_DR29) << BIT_SHIFT_DR29)
+#define BIT_CTRL_DR29(x)                      	(((x) & BIT_MASK_DR29) << BIT_SHIFT_DR29)
+#define BIT_GET_DR29(x)                       	(((x) >> BIT_SHIFT_DR29) & BIT_MASK_DR29)
+
+
+//2 REG_SPIC_DR30
+
+#define BIT_SHIFT_DR30 0
+#define BIT_MASK_DR30 0xffffffffL
+#define BIT_DR30(x)                           	(((x) & BIT_MASK_DR30) << BIT_SHIFT_DR30)
+#define BIT_CTRL_DR30(x)                      	(((x) & BIT_MASK_DR30) << BIT_SHIFT_DR30)
+#define BIT_GET_DR30(x)                       	(((x) >> BIT_SHIFT_DR30) & BIT_MASK_DR30)
+
+
+//2 REG_SPIC_DR31
+
+#define BIT_SHIFT_DR31 0
+#define BIT_MASK_DR31 0xffffffffL
+#define BIT_DR31(x)                           	(((x) & BIT_MASK_DR31) << BIT_SHIFT_DR31)
+#define BIT_CTRL_DR31(x)                      	(((x) & BIT_MASK_DR31) << BIT_SHIFT_DR31)
+#define BIT_GET_DR31(x)                       	(((x) >> BIT_SHIFT_DR31) & BIT_MASK_DR31)
+
+
+//2 REG_SPIC_READ_FAST_SINGLE
+
+#define BIT_SHIFT_FRD_CMD 0
+#define BIT_MASK_FRD_CMD 0xff
+#define BIT_FRD_CMD(x)                        	(((x) & BIT_MASK_FRD_CMD) << BIT_SHIFT_FRD_CMD)
+#define BIT_CTRL_FRD_CMD(x)                   	(((x) & BIT_MASK_FRD_CMD) << BIT_SHIFT_FRD_CMD)
+#define BIT_GET_FRD_CMD(x)                    	(((x) >> BIT_SHIFT_FRD_CMD) & BIT_MASK_FRD_CMD)
+
+
+//2 REG_SPIC_READ_DUAL_DATA
+
+#define BIT_SHIFT_RD_DUAL_O_CMD 0
+#define BIT_MASK_RD_DUAL_O_CMD 0xff
+#define BIT_RD_DUAL_O_CMD(x)                  	(((x) & BIT_MASK_RD_DUAL_O_CMD) << BIT_SHIFT_RD_DUAL_O_CMD)
+#define BIT_CTRL_RD_DUAL_O_CMD(x)             	(((x) & BIT_MASK_RD_DUAL_O_CMD) << BIT_SHIFT_RD_DUAL_O_CMD)
+#define BIT_GET_RD_DUAL_O_CMD(x)              	(((x) >> BIT_SHIFT_RD_DUAL_O_CMD) & BIT_MASK_RD_DUAL_O_CMD)
+
+
+//2 REG_SPIC_READ_DUAL_ADDR_DATA
+
+#define BIT_SHIFT_RD_DUAL_IO_CMD 0
+#define BIT_MASK_RD_DUAL_IO_CMD 0xff
+#define BIT_RD_DUAL_IO_CMD(x)                 	(((x) & BIT_MASK_RD_DUAL_IO_CMD) << BIT_SHIFT_RD_DUAL_IO_CMD)
+#define BIT_CTRL_RD_DUAL_IO_CMD(x)            	(((x) & BIT_MASK_RD_DUAL_IO_CMD) << BIT_SHIFT_RD_DUAL_IO_CMD)
+#define BIT_GET_RD_DUAL_IO_CMD(x)             	(((x) >> BIT_SHIFT_RD_DUAL_IO_CMD) & BIT_MASK_RD_DUAL_IO_CMD)
+
+
+//2 REG_SPIC_READ_QUAD_DATA
+
+#define BIT_SHIFT_RD_QUAD_O_CMD 0
+#define BIT_MASK_RD_QUAD_O_CMD 0xff
+#define BIT_RD_QUAD_O_CMD(x)                  	(((x) & BIT_MASK_RD_QUAD_O_CMD) << BIT_SHIFT_RD_QUAD_O_CMD)
+#define BIT_CTRL_RD_QUAD_O_CMD(x)             	(((x) & BIT_MASK_RD_QUAD_O_CMD) << BIT_SHIFT_RD_QUAD_O_CMD)
+#define BIT_GET_RD_QUAD_O_CMD(x)              	(((x) >> BIT_SHIFT_RD_QUAD_O_CMD) & BIT_MASK_RD_QUAD_O_CMD)
+
+
+//2 REG_SPIC_READ_QUAD_ADDR_DATA
+
+#define BIT_SHIFT_RD_QUAD_IO_CMD 0
+#define BIT_MASK_RD_QUAD_IO_CMD 0xff
+#define BIT_RD_QUAD_IO_CMD(x)                 	(((x) & BIT_MASK_RD_QUAD_IO_CMD) << BIT_SHIFT_RD_QUAD_IO_CMD)
+#define BIT_CTRL_RD_QUAD_IO_CMD(x)            	(((x) & BIT_MASK_RD_QUAD_IO_CMD) << BIT_SHIFT_RD_QUAD_IO_CMD)
+#define BIT_GET_RD_QUAD_IO_CMD(x)             	(((x) >> BIT_SHIFT_RD_QUAD_IO_CMD) & BIT_MASK_RD_QUAD_IO_CMD)
+
+
+//2 REG_SPIC_WRITE_SIGNLE
+
+#define BIT_SHIFT_WR_CMD 0
+#define BIT_MASK_WR_CMD 0xff
+#define BIT_WR_CMD(x)                         	(((x) & BIT_MASK_WR_CMD) << BIT_SHIFT_WR_CMD)
+#define BIT_CTRL_WR_CMD(x)                    	(((x) & BIT_MASK_WR_CMD) << BIT_SHIFT_WR_CMD)
+#define BIT_GET_WR_CMD(x)                     	(((x) >> BIT_SHIFT_WR_CMD) & BIT_MASK_WR_CMD)
+
+
+//2 REG_SPIC_WRITE_DUAL_DATA
+
+#define BIT_SHIFT_WR_DUAL_I_CMD 0
+#define BIT_MASK_WR_DUAL_I_CMD 0xff
+#define BIT_WR_DUAL_I_CMD(x)                  	(((x) & BIT_MASK_WR_DUAL_I_CMD) << BIT_SHIFT_WR_DUAL_I_CMD)
+#define BIT_CTRL_WR_DUAL_I_CMD(x)             	(((x) & BIT_MASK_WR_DUAL_I_CMD) << BIT_SHIFT_WR_DUAL_I_CMD)
+#define BIT_GET_WR_DUAL_I_CMD(x)              	(((x) >> BIT_SHIFT_WR_DUAL_I_CMD) & BIT_MASK_WR_DUAL_I_CMD)
+
+
+//2 REG_SPIC_WRITE_DUAL_ADDR_DATA
+
+#define BIT_SHIFT_WR_DUAL_II_CMD 0
+#define BIT_MASK_WR_DUAL_II_CMD 0xff
+#define BIT_WR_DUAL_II_CMD(x)                 	(((x) & BIT_MASK_WR_DUAL_II_CMD) << BIT_SHIFT_WR_DUAL_II_CMD)
+#define BIT_CTRL_WR_DUAL_II_CMD(x)            	(((x) & BIT_MASK_WR_DUAL_II_CMD) << BIT_SHIFT_WR_DUAL_II_CMD)
+#define BIT_GET_WR_DUAL_II_CMD(x)             	(((x) >> BIT_SHIFT_WR_DUAL_II_CMD) & BIT_MASK_WR_DUAL_II_CMD)
+
+
+//2 REG_SPIC_WRITE_QUAD_DATA
+
+#define BIT_SHIFT_WR_QUAD_I_CMD 0
+#define BIT_MASK_WR_QUAD_I_CMD 0xff
+#define BIT_WR_QUAD_I_CMD(x)                  	(((x) & BIT_MASK_WR_QUAD_I_CMD) << BIT_SHIFT_WR_QUAD_I_CMD)
+#define BIT_CTRL_WR_QUAD_I_CMD(x)             	(((x) & BIT_MASK_WR_QUAD_I_CMD) << BIT_SHIFT_WR_QUAD_I_CMD)
+#define BIT_GET_WR_QUAD_I_CMD(x)              	(((x) >> BIT_SHIFT_WR_QUAD_I_CMD) & BIT_MASK_WR_QUAD_I_CMD)
+
+
+//2 REG_SPIC_WRITE_QUAD_ADDR_DATA
+
+#define BIT_SHIFT_WR_QUAD_II_CMD 0
+#define BIT_MASK_WR_QUAD_II_CMD 0xff
+#define BIT_WR_QUAD_II_CMD(x)                 	(((x) & BIT_MASK_WR_QUAD_II_CMD) << BIT_SHIFT_WR_QUAD_II_CMD)
+#define BIT_CTRL_WR_QUAD_II_CMD(x)            	(((x) & BIT_MASK_WR_QUAD_II_CMD) << BIT_SHIFT_WR_QUAD_II_CMD)
+#define BIT_GET_WR_QUAD_II_CMD(x)             	(((x) >> BIT_SHIFT_WR_QUAD_II_CMD) & BIT_MASK_WR_QUAD_II_CMD)
+
+
+//2 REG_SPIC_WRITE_ENABLE
+
+#define BIT_SHIFT_WR_EN_CMD 0
+#define BIT_MASK_WR_EN_CMD 0xff
+#define BIT_WR_EN_CMD(x)                      	(((x) & BIT_MASK_WR_EN_CMD) << BIT_SHIFT_WR_EN_CMD)
+#define BIT_CTRL_WR_EN_CMD(x)                 	(((x) & BIT_MASK_WR_EN_CMD) << BIT_SHIFT_WR_EN_CMD)
+#define BIT_GET_WR_EN_CMD(x)                  	(((x) >> BIT_SHIFT_WR_EN_CMD) & BIT_MASK_WR_EN_CMD)
+
+
+//2 REG_SPIC_READ_STATUS
+
+#define BIT_SHIFT_RD_ST_CMD 0
+#define BIT_MASK_RD_ST_CMD 0xff
+#define BIT_RD_ST_CMD(x)                      	(((x) & BIT_MASK_RD_ST_CMD) << BIT_SHIFT_RD_ST_CMD)
+#define BIT_CTRL_RD_ST_CMD(x)                 	(((x) & BIT_MASK_RD_ST_CMD) << BIT_SHIFT_RD_ST_CMD)
+#define BIT_GET_RD_ST_CMD(x)                  	(((x) >> BIT_SHIFT_RD_ST_CMD) & BIT_MASK_RD_ST_CMD)
+
+
+//2 REG_SPIC_CTRLR2
+
+#define BIT_SHIFT_FIFO_ENTRY 4
+#define BIT_MASK_FIFO_ENTRY 0xf
+#define BIT_FIFO_ENTRY(x)                     	(((x) & BIT_MASK_FIFO_ENTRY) << BIT_SHIFT_FIFO_ENTRY)
+#define BIT_CTRL_FIFO_ENTRY(x)                	(((x) & BIT_MASK_FIFO_ENTRY) << BIT_SHIFT_FIFO_ENTRY)
+#define BIT_GET_FIFO_ENTRY(x)                 	(((x) >> BIT_SHIFT_FIFO_ENTRY) & BIT_MASK_FIFO_ENTRY)
+
+#define BIT_WR_SEQ                            	BIT(3)
+#define BIT_SHIFT_WR_SEQ                      	3
+#define BIT_MASK_WR_SEQ                       	0x1
+#define BIT_CTRL_WR_SEQ(x)                    	(((x) & BIT_MASK_WR_SEQ) << BIT_SHIFT_WR_SEQ)
+
+#define BIT_WPN_DNUM                          	BIT(2)
+#define BIT_SHIFT_WPN_DNUM                    	2
+#define BIT_MASK_WPN_DNUM                     	0x1
+#define BIT_CTRL_WPN_DNUM(x)                  	(((x) & BIT_MASK_WPN_DNUM) << BIT_SHIFT_WPN_DNUM)
+
+#define BIT_WPN_SET                           	BIT(1)
+#define BIT_SHIFT_WPN_SET                     	1
+#define BIT_MASK_WPN_SET                      	0x1
+#define BIT_CTRL_WPN_SET(x)                   	(((x) & BIT_MASK_WPN_SET) << BIT_SHIFT_WPN_SET)
+
+#define BIT_SO_DUM                            	BIT(0)
+#define BIT_SHIFT_SO_DUM                      	0
+#define BIT_MASK_SO_DUM                       	0x1
+#define BIT_CTRL_SO_DUM(x)                    	(((x) & BIT_MASK_SO_DUM) << BIT_SHIFT_SO_DUM)
+
+//2 REG_SPIC_FBAUDR
+
+#define BIT_SHIFT_FSCKDV 0
+#define BIT_MASK_FSCKDV 0xfff
+#define BIT_FSCKDV(x)                         	(((x) & BIT_MASK_FSCKDV) << BIT_SHIFT_FSCKDV)
+#define BIT_CTRL_FSCKDV(x)                    	(((x) & BIT_MASK_FSCKDV) << BIT_SHIFT_FSCKDV)
+#define BIT_GET_FSCKDV(x)                     	(((x) >> BIT_SHIFT_FSCKDV) & BIT_MASK_FSCKDV)
+
+
+//2 REG_SPIC_ADDR_LENGTH
+
+#define BIT_SHIFT_ADDR_PHASE_LENGTH 0
+#define BIT_MASK_ADDR_PHASE_LENGTH 0x3
+#define BIT_ADDR_PHASE_LENGTH(x)              	(((x) & BIT_MASK_ADDR_PHASE_LENGTH) << BIT_SHIFT_ADDR_PHASE_LENGTH)
+#define BIT_CTRL_ADDR_PHASE_LENGTH(x)         	(((x) & BIT_MASK_ADDR_PHASE_LENGTH) << BIT_SHIFT_ADDR_PHASE_LENGTH)
+#define BIT_GET_ADDR_PHASE_LENGTH(x)          	(((x) >> BIT_SHIFT_ADDR_PHASE_LENGTH) & BIT_MASK_ADDR_PHASE_LENGTH)
+
+
+//2 REG_SPIC_AUTO_LENGTH
+
+#define BIT_SHIFT_CS_H_WR_DUM_LEN 28
+#define BIT_MASK_CS_H_WR_DUM_LEN 0xf
+#define BIT_CS_H_WR_DUM_LEN(x)                	(((x) & BIT_MASK_CS_H_WR_DUM_LEN) << BIT_SHIFT_CS_H_WR_DUM_LEN)
+#define BIT_CTRL_CS_H_WR_DUM_LEN(x)           	(((x) & BIT_MASK_CS_H_WR_DUM_LEN) << BIT_SHIFT_CS_H_WR_DUM_LEN)
+#define BIT_GET_CS_H_WR_DUM_LEN(x)            	(((x) >> BIT_SHIFT_CS_H_WR_DUM_LEN) & BIT_MASK_CS_H_WR_DUM_LEN)
+
+
+#define BIT_SHIFT_CS_H_RD_DUM_LEN 26
+#define BIT_MASK_CS_H_RD_DUM_LEN 0x3
+#define BIT_CS_H_RD_DUM_LEN(x)                	(((x) & BIT_MASK_CS_H_RD_DUM_LEN) << BIT_SHIFT_CS_H_RD_DUM_LEN)
+#define BIT_CTRL_CS_H_RD_DUM_LEN(x)           	(((x) & BIT_MASK_CS_H_RD_DUM_LEN) << BIT_SHIFT_CS_H_RD_DUM_LEN)
+#define BIT_GET_CS_H_RD_DUM_LEN(x)            	(((x) >> BIT_SHIFT_CS_H_RD_DUM_LEN) & BIT_MASK_CS_H_RD_DUM_LEN)
+
+
+#define BIT_SHIFT_AUTO_DUM_LEN 18
+#define BIT_MASK_AUTO_DUM_LEN 0xff
+#define BIT_AUTO_DUM_LEN(x)                   	(((x) & BIT_MASK_AUTO_DUM_LEN) << BIT_SHIFT_AUTO_DUM_LEN)
+#define BIT_CTRL_AUTO_DUM_LEN(x)              	(((x) & BIT_MASK_AUTO_DUM_LEN) << BIT_SHIFT_AUTO_DUM_LEN)
+#define BIT_GET_AUTO_DUM_LEN(x)               	(((x) >> BIT_SHIFT_AUTO_DUM_LEN) & BIT_MASK_AUTO_DUM_LEN)
+
+
+#define BIT_SHIFT_AUTO_ADDR__LENGTH 16
+#define BIT_MASK_AUTO_ADDR__LENGTH 0x3
+#define BIT_AUTO_ADDR__LENGTH(x)              	(((x) & BIT_MASK_AUTO_ADDR__LENGTH) << BIT_SHIFT_AUTO_ADDR__LENGTH)
+#define BIT_CTRL_AUTO_ADDR__LENGTH(x)         	(((x) & BIT_MASK_AUTO_ADDR__LENGTH) << BIT_SHIFT_AUTO_ADDR__LENGTH)
+#define BIT_GET_AUTO_ADDR__LENGTH(x)          	(((x) >> BIT_SHIFT_AUTO_ADDR__LENGTH) & BIT_MASK_AUTO_ADDR__LENGTH)
+
+
+#define BIT_SHIFT_RD_DUMMY_LENGTH 0
+#define BIT_MASK_RD_DUMMY_LENGTH 0xffff
+#define BIT_RD_DUMMY_LENGTH(x)                	(((x) & BIT_MASK_RD_DUMMY_LENGTH) << BIT_SHIFT_RD_DUMMY_LENGTH)
+#define BIT_CTRL_RD_DUMMY_LENGTH(x)           	(((x) & BIT_MASK_RD_DUMMY_LENGTH) << BIT_SHIFT_RD_DUMMY_LENGTH)
+#define BIT_GET_RD_DUMMY_LENGTH(x)            	(((x) >> BIT_SHIFT_RD_DUMMY_LENGTH) & BIT_MASK_RD_DUMMY_LENGTH)
+
+
+//2 REG_SPIC_VALID_CMD
+#define BIT_WR_BLOCKING                       	BIT(9)
+#define BIT_SHIFT_WR_BLOCKING                 	9
+#define BIT_MASK_WR_BLOCKING                  	0x1
+#define BIT_CTRL_WR_BLOCKING(x)               	(((x) & BIT_MASK_WR_BLOCKING) << BIT_SHIFT_WR_BLOCKING)
+
+#define BIT_WR_QUAD_II                        	BIT(8)
+#define BIT_SHIFT_WR_QUAD_II                  	8
+#define BIT_MASK_WR_QUAD_II                   	0x1
+#define BIT_CTRL_WR_QUAD_II(x)                	(((x) & BIT_MASK_WR_QUAD_II) << BIT_SHIFT_WR_QUAD_II)
+
+#define BIT_WR_QUAD_I                         	BIT(7)
+#define BIT_SHIFT_WR_QUAD_I                   	7
+#define BIT_MASK_WR_QUAD_I                    	0x1
+#define BIT_CTRL_WR_QUAD_I(x)                 	(((x) & BIT_MASK_WR_QUAD_I) << BIT_SHIFT_WR_QUAD_I)
+
+#define BIT_WR_DUAL_II                        	BIT(6)
+#define BIT_SHIFT_WR_DUAL_II                  	6
+#define BIT_MASK_WR_DUAL_II                   	0x1
+#define BIT_CTRL_WR_DUAL_II(x)                	(((x) & BIT_MASK_WR_DUAL_II) << BIT_SHIFT_WR_DUAL_II)
+
+#define BIT_WR_DUAL_I                         	BIT(5)
+#define BIT_SHIFT_WR_DUAL_I                   	5
+#define BIT_MASK_WR_DUAL_I                    	0x1
+#define BIT_CTRL_WR_DUAL_I(x)                 	(((x) & BIT_MASK_WR_DUAL_I) << BIT_SHIFT_WR_DUAL_I)
+
+#define BIT_RD_QUAD_IO                        	BIT(4)
+#define BIT_SHIFT_RD_QUAD_IO                  	4
+#define BIT_MASK_RD_QUAD_IO                   	0x1
+#define BIT_CTRL_RD_QUAD_IO(x)                	(((x) & BIT_MASK_RD_QUAD_IO) << BIT_SHIFT_RD_QUAD_IO)
+
+#define BIT_RD_QUAD_O                         	BIT(3)
+#define BIT_SHIFT_RD_QUAD_O                   	3
+#define BIT_MASK_RD_QUAD_O                    	0x1
+#define BIT_CTRL_RD_QUAD_O(x)                 	(((x) & BIT_MASK_RD_QUAD_O) << BIT_SHIFT_RD_QUAD_O)
+
+#define BIT_RD_DUAL_IO                        	BIT(2)
+#define BIT_SHIFT_RD_DUAL_IO                  	2
+#define BIT_MASK_RD_DUAL_IO                   	0x1
+#define BIT_CTRL_RD_DUAL_IO(x)                	(((x) & BIT_MASK_RD_DUAL_IO) << BIT_SHIFT_RD_DUAL_IO)
+
+#define BIT_RD_DUAL_I                         	BIT(1)
+#define BIT_SHIFT_RD_DUAL_I                   	1
+#define BIT_MASK_RD_DUAL_I                    	0x1
+#define BIT_CTRL_RD_DUAL_I(x)                 	(((x) & BIT_MASK_RD_DUAL_I) << BIT_SHIFT_RD_DUAL_I)
+
+#define BIT_FRD_SINGEL                        	BIT(0)
+#define BIT_SHIFT_FRD_SINGEL                  	0
+#define BIT_MASK_FRD_SINGEL                   	0x1
+#define BIT_CTRL_FRD_SINGEL(x)                	(((x) & BIT_MASK_FRD_SINGEL) << BIT_SHIFT_FRD_SINGEL)
+
+//2 REG_SPIC_FLASE_SIZE
+
+#define BIT_SHIFT_FLASE_SIZE 0
+#define BIT_MASK_FLASE_SIZE 0xf
+#define BIT_FLASE_SIZE(x)                     	(((x) & BIT_MASK_FLASE_SIZE) << BIT_SHIFT_FLASE_SIZE)
+#define BIT_CTRL_FLASE_SIZE(x)                	(((x) & BIT_MASK_FLASE_SIZE) << BIT_SHIFT_FLASE_SIZE)
+#define BIT_GET_FLASE_SIZE(x)                 	(((x) >> BIT_SHIFT_FLASE_SIZE) & BIT_MASK_FLASE_SIZE)
+
+
+//2 REG_SPIC_FLUSH_FIFO
+#define BIT_FLUSH_FIFO                        	BIT(0)
+#define BIT_SHIFT_FLUSH_FIFO                  	0
+#define BIT_MASK_FLUSH_FIFO                   	0x1
+#define BIT_CTRL_FLUSH_FIFO(x)                	(((x) & BIT_MASK_FLUSH_FIFO) << BIT_SHIFT_FLUSH_FIFO)
+
+//=================== Register Address Definition ============================//
+#define REG_SPIC_CTRLR0 0x0000//O
+#define REG_SPIC_CTRLR1 0x0004//O
+#define REG_SPIC_SSIENR 0x0008//O
+#define REG_SPIC_MWCR 0x000C
+#define REG_SPIC_SER 0x0010//O
+#define REG_SPIC_BAUDR 0x0014//O
+#define REG_SPIC_TXFTLR 0x0018
+#define REG_SPIC_RXFTLR 0x001C//O
+#define REG_SPIC_TXFLR 0x0020//O
+#define REG_SPIC_RXFLR 0x0024
+#define REG_SPIC_SR 0x0028
+#define REG_SPIC_IMR 0x002C//O
+#define REG_SPIC_ISR 0x0030
+#define REG_SPIC_RISR 0x0034
+#define REG_SPIC_TXOICR 0x0038
+#define REG_SPIC_RXOICR 0x003C
+#define REG_SPC_RXUICR 0x0040
+#define REG_SPIC_MSTICR 0x0044
+#define REG_SPIC_ICR 0x0048
+#define REG_SPIC_DMACR 0x004C
+#define REG_SPIC_DMATDLR0 0x0050
+#define REG_SPIC_DMATDLR1 0x0054
+#define REG_SPIC_IDR 0x0058
+#define REG_SPIC_VERSION 0x005C
+#define REG_SPIC_DR0 0x0060
+#define REG_SPIC_DR1 0x0064
+#define REG_SPIC_DR2 0x0068
+#define REG_SPIC_DR3 0x006C
+#define REG_SPIC_DR4 0x0070
+#define REG_SPIC_DR5 0x0074
+#define REG_SPIC_DR6 0x0078
+#define REG_SPIC_DR7 0x007C
+#define REG_SPIC_DR8 0x0080
+#define REG_SPIC_DR9 0x0084
+#define REG_SPIC_DR10 0x0088
+#define REG_SPIC_DR11 0x008C
+#define REG_SPIC_DR12 0x0090
+#define REG_SPIC_DR13 0x0094
+#define REG_SPIC_DR14 0x0098
+#define REG_SPIC_DR15 0x009C
+#define REG_SPIC_DR16 0x00A0
+#define REG_SPIC_DR17 0x00A4
+#define REG_SPIC_DR18 0x00A8
+#define REG_SPIC_DR19 0x00AC
+#define REG_SPIC_DR20 0x00B0
+#define REG_SPIC_DR21 0x00B4
+#define REG_SPIC_DR22 0x00B8
+#define REG_SPIC_DR23 0x00BC
+#define REG_SPIC_DR24 0x00C0
+#define REG_SPIC_DR25 0x00C4
+#define REG_SPIC_DR26 0x00C8
+#define REG_SPIC_DR27 0x00CC
+#define REG_SPIC_DR28 0x00D0
+#define REG_SPIC_DR29 0x00D4
+#define REG_SPIC_DR30 0x00D8
+#define REG_SPIC_DR31 0x00DC
+#define REG_SPIC_READ_FAST_SINGLE 0x00E0//O
+#define REG_SPIC_READ_DUAL_DATA 0x00E4//O
+#define REG_SPIC_READ_DUAL_ADDR_DATA 0x00E8//O
+#define REG_SPIC_READ_QUAD_DATA 0x00EC//O
+#define REG_SPIC_READ_QUAD_ADDR_DATA 0x00F0//O
+#define REG_SPIC_WRITE_SIGNLE 0x00F4//O
+#define REG_SPIC_WRITE_DUAL_DATA 0x00F8//O
+#define REG_SPIC_WRITE_DUAL_ADDR_DATA 0x00FC//O
+#define REG_SPIC_WRITE_QUAD_DATA 0x0100//O
+#define REG_SPIC_WRITE_QUAD_ADDR_DATA 0x0104//O
+#define REG_SPIC_WRITE_ENABLE 0x0108//O
+#define REG_SPIC_READ_STATUS 0x010C//O
+#define REG_SPIC_CTRLR2 0x0110//O
+#define REG_SPIC_FBAUDR 0x0114//O
+#define REG_SPIC_ADDR_LENGTH 0x0118//O
+#define REG_SPIC_AUTO_LENGTH 0x011C//O
+#define REG_SPIC_VALID_CMD 0x0120//O
+#define REG_SPIC_FLASE_SIZE 0x0124//O
+#define REG_SPIC_FLUSH_FIFO 0x0128//O
+
+#endif  // end of "#ifndef _RTL8195A_SPI_FLASH_H"

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_ssi.h

@@ -0,0 +1,495 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL8195A_SSI_H_
+#define _RTL8195A_SSI_H_
+
+#define SSI_DUMMY_DATA      0x00        // for master mode, we need to push a Dummy data to TX FIFO for read
+
+#define SSI_CLK_SPI1        (PLATFORM_CLOCK/2)
+#define SSI_CLK_SPI0_2      (PLATFORM_CLOCK/4)
+
+/* Parameters of DW_apb_ssi for RTL8195A */
+#define SSI_TX_FIFO_DEPTH  64
+#define TX_ABW              6  // 1-8, log2(SSI_TX_FIFO_DEPTH)
+#define SSI_RX_FIFO_DEPTH  64
+#define RX_ABW              6  // 1-8, log2(SSI_RX_FIFO_DEPTH)
+
+#define SSI0_REG_BASE  0x40042000
+#define SSI1_REG_BASE  0x40042400
+#define SSI2_REG_BASE  0x40042800
+
+/* Memory Map of DW_apb_ssi */
+#define REG_DW_SSI_CTRLR0          0x00  // 16 bits
+#define REG_DW_SSI_CTRLR1          0x04  // 16 bits
+#define REG_DW_SSI_SSIENR          0x08  //  1 bit
+#define REG_DW_SSI_MWCR            0x0C  //  3 bits
+#define REG_DW_SSI_SER             0x10  //
+#define REG_DW_SSI_BAUDR           0x14  // 16 bits
+#define REG_DW_SSI_TXFTLR          0x18  //  TX_ABW
+#define REG_DW_SSI_RXFTLR          0x1C  //  RX_ABW
+#define REG_DW_SSI_TXFLR           0x20  //
+#define REG_DW_SSI_RXFLR           0x24  //
+#define REG_DW_SSI_SR              0x28  //  7 bits
+#define REG_DW_SSI_IMR             0x2C  //
+#define REG_DW_SSI_ISR             0x30  //  6 bits
+#define REG_DW_SSI_RISR            0x34  //  6 bits
+#define REG_DW_SSI_TXOICR          0x38  //  1 bits
+#define REG_DW_SSI_RXOICR          0x3C  //  1 bits
+#define REG_DW_SSI_RXUICR          0x40  //  1 bits
+#define REG_DW_SSI_MSTICR          0x44  //  1 bits
+#define REG_DW_SSI_ICR             0x48  //  1 bits
+#define REG_DW_SSI_DMACR           0x4C  //  2 bits
+#define REG_DW_SSI_DMATDLR         0x50  //  TX_ABW
+#define REG_DW_SSI_DMARDLR         0x54  //  RX_ABW
+#define REG_DW_SSI_IDR             0x58  // 32 bits
+#define REG_DW_SSI_COMP_VERSION    0x5C  // 32 bits
+#define REG_DW_SSI_DR              0x60  // 16 bits 0x60-0xEC
+#define REG_DW_SSI_RX_SAMPLE_DLY   0xF0  //  8 bits
+#define REG_DW_SSI_RSVD_0          0xF4  // 32 bits
+#define REG_DW_SSI_RSVD_1          0xF8  // 32 bits
+#define REG_DW_SSI_RSVD_2          0xFC  // 32 bits
+
+// CTRLR0          0x00  // 16 bits, 6.2.1
+// DFS Reset Value: 0x7
+#define BIT_SHIFT_CTRLR0_DFS       0
+#define BIT_MASK_CTRLR0_DFS        0xF
+#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS)
+#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS))
+
+#define BIT_SHIFT_CTRLR0_FRF       4
+#define BIT_MASK_CTRLR0_FRF        0x3
+#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF)
+#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF))
+
+#define BIT_SHIFT_CTRLR0_SCPH      6
+#define BIT_MASK_CTRLR0_SCPH       0x1
+#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH)
+#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH))
+
+#define BIT_SHIFT_CTRLR0_SCPOL     7
+#define BIT_MASK_CTRLR0_SCPOL      0x1
+#define BIT_CTRLR0_SCPOL(x)(((x) & BIT_MASK_CTRLR0_SCPOL) << BIT_SHIFT_CTRLR0_SCPOL)
+#define BIT_INVC_CTRLR0_SCPOL (~(BIT_MASK_CTRLR0_SCPOL << BIT_SHIFT_CTRLR0_SCPOL))
+
+#define BIT_SHIFT_CTRLR0_TMOD      8
+#define BIT_MASK_CTRLR0_TMOD       0x3
+#define BIT_CTRLR0_TMOD(x)(((x) & BIT_MASK_CTRLR0_TMOD) << BIT_SHIFT_CTRLR0_TMOD)
+#define BIT_INVC_CTRLR0_TMOD (~(BIT_MASK_CTRLR0_TMOD << BIT_SHIFT_CTRLR0_TMOD))
+
+#define BIT_SHIFT_CTRLR0_SLV_OE    10
+#define BIT_MASK_CTRLR0_SLV_OE     0x1
+#define BIT_CTRLR0_SLV_OE(x)(((x) & BIT_MASK_CTRLR0_SLV_OE) << BIT_SHIFT_CTRLR0_SLV_OE)
+#define BIT_INVC_CTRLR0_SLV_OE (~(BIT_MASK_CTRLR0_SLV_OE << BIT_SHIFT_CTRLR0_SLV_OE))
+
+#define BIT_SHIFT_CTRLR0_SRL       11
+#define BIT_MASK_CTRLR0_SRL        0x1
+#define BIT_CTRLR0_SRL(x)(((x) & BIT_MASK_CTRLR0_SRL) << BIT_SHIFT_CTRLR0_SRL)
+#define BIT_INVC_CTRLR0_SRL (~(BIT_MASK_CTRLR0_SRL << BIT_SHIFT_CTRLR0_SRL))
+
+#define BIT_SHIFT_CTRLR0_CFS       12
+#define BIT_MASK_CTRLR0_CFS        0xF
+#define BIT_CTRLR0_CFS(x)(((x) & BIT_MASK_CTRLR0_CFS) << BIT_SHIFT_CTRLR0_CFS)
+#define BIT_INVC_CTRLR0_CFS (~(BIT_MASK_CTRLR0_CFS << BIT_SHIFT_CTRLR0_CFS))
+
+// CTRLR1          0x04  // 16 bits
+#define BIT_SHIFT_CTRLR1_NDF    0
+#define BIT_MASK_CTRLR1_NDF     0xFFFF
+#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF)
+#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF))
+
+// SSIENR          0x08  //  1 bit
+#define BIT_SHIFT_SSIENR_SSI_EN    0
+#define BIT_MASK_SSIENR_SSI_EN     0x1
+#define BIT_SSIENR_SSI_EN(x)(((x) & BIT_MASK_SSIENR_SSI_EN) << BIT_SHIFT_SSIENR_SSI_EN)
+#define BIT_INVC_SSIENR_SSI_EN (~(BIT_MASK_SSIENR_SSI_EN << BIT_SHIFT_SSIENR_SSI_EN))
+
+// MWCR            0x0c  //  3 bits
+#define BIT_SHIFT_MWCR_MWMOD    0
+#define BIT_MASK_MWCR_MWMOD     0x1
+#define BIT_MWCR_MWMOD(x)(((x) & BIT_MASK_MWCR_MWMOD) << BIT_SHIFT_MWCR_MWMOD)
+#define BIT_INVC_MWCR_MWMOD (~(BIT_MASK_MWCR_MWMOD << BIT_SHIFT_MWCR_MWMOD))
+
+#define BIT_SHIFT_MWCR_MDD      1
+#define BIT_MASK_MWCR_MDD       0x1
+#define BIT_MWCR_MDD(x)(((x) & BIT_MASK_MWCR_MDD) << BIT_SHIFT_MWCR_MDD)
+#define BIT_INVC_MWCR_MDD (~(BIT_MASK_MWCR_MDD << BIT_SHIFT_MWCR_MDD))
+
+#define BIT_SHIFT_MWCR_MHS      2
+#define BIT_MASK_MWCR_MHS       0x1
+#define BIT_MWCR_MHS(x)(((x) & BIT_MASK_MWCR_MHS) << BIT_SHIFT_MWCR_MHS)
+#define BIT_INVC_MWCR_MHS (~(BIT_MASK_MWCR_MHS << BIT_SHIFT_MWCR_MHS))
+
+// SER             0x10   // Variable Length
+#define BIT_SHIFT_SER_SER    0
+#define BIT_MASK_SER_SER     0xFF
+#define BIT_SER_SER(x)(((x) & BIT_MASK_SER_SER) << BIT_SHIFT_SER_SER)
+#define BIT_INVC_SER_SER (~(BIT_MASK_SER_SER << BIT_SHIFT_SER_SER))
+
+// BAUDR           0x14  // 16 bits
+#define BIT_SHIFT_BAUDR_SCKDV    0
+#define BIT_MASK_BAUDR_SCKDV     0xFFFF
+#define BIT_BAUDR_SCKDV(x)(((x) & BIT_MASK_BAUDR_SCKDV) << BIT_SHIFT_BAUDR_SCKDV)
+#define BIT_INVC_BAUDR_SCKDV (~(BIT_MASK_BAUDR_SCKDV << BIT_SHIFT_BAUDR_SCKDV))
+
+// TXFLTR          0x18        // Variable Length
+#define BIT_SHIFT_TXFTLR_TFT    0
+#define BIT_MASK_TXFTLR_TFT     0x3F  // (TX_ABW-1):0
+#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT)
+#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT))
+
+// RXFLTR          0x1c        // Variable Length
+#define BIT_SHIFT_RXFTLR_RFT    0
+#define BIT_MASK_RXFTLR_RFT     0x3F  // (RX_ABW-1):0
+#define BIT_RXFTLR_RFT(x)(((x) & BIT_MASK_RXFTLR_RFT) << BIT_SHIFT_RXFTLR_RFT)
+#define BIT_INVC_RXFTLR_RFT (~(BIT_MASK_RXFTLR_RFT << BIT_SHIFT_RXFTLR_RFT))
+
+// TXFLR           0x20  // see     [READ ONLY]
+#define BIT_MASK_TXFLR_TXTFL    0x7F  // (TX_ABW):0
+
+// RXFLR           0x24  // see     [READ ONLY]
+#define BIT_MASK_RXFLR_RXTFL    0x7F  // (RX_ABW):0
+
+// SR              0x28  //  7 bits [READ ONLY]
+#define BIT_SR_BUSY  BIT0
+#define BIT_SR_TFNF  BIT1
+#define BIT_SR_TFE   BIT2
+#define BIT_SR_RFNE  BIT3
+#define BIT_SR_RFF   BIT4
+#define BIT_SR_TXE   BIT5
+#define BIT_SR_DCOL  BIT6
+
+// IMR             0x2c  // see
+#define BIT_SHIFT_IMR_TXEIM    0
+#define BIT_MASK_IMR_TXEIM     0x1
+// #define BIT_IMR_TXEIM(x)(((x) & BIT_MASK_IMR_TXEIM) << BIT_SHIFT_IMR_TXEIM)
+#define BIT_INVC_IMR_TXEIM (~(BIT_MASK_IMR_TXEIM << BIT_SHIFT_IMR_TXEIM))
+
+#define BIT_SHIFT_IMR_TXOIM    1
+#define BIT_MASK_IMR_TXOIM     0x1
+// #define BIT_IMR_TXOIM(x)(((x) & BIT_MASK_IMR_TXOIM) << BIT_SHIFT_IMR_TXOIM)
+#define BIT_INVC_IMR_TXOIM (~(BIT_MASK_IMR_TXOIM << BIT_SHIFT_IMR_TXOIM))
+
+#define BIT_SHIFT_IMR_RXUIM    2
+#define BIT_MASK_IMR_RXUIM     0x1
+// #define BIT_IMR_RXUIM(x)(((x) & BIT_MASK_IMR_RXUIM) << BIT_SHIFT_IMR_RXUIM)
+#define BIT_INVC_IMR_RXUIM (~(BIT_MASK_IMR_RXUIM << BIT_SHIFT_IMR_RXUIM))
+
+#define BIT_SHIFT_IMR_RXOIM    3
+#define BIT_MASK_IMR_RXOIM     0x1
+// #define BIT_IMR_RXOIM(x)(((x) & BIT_MASK_IMR_RXOIM) << BIT_SHIFT_IMR_RXOIM)
+#define BIT_INVC_IMR_RXOIM (~(BIT_MASK_IMR_RXOIM << BIT_SHIFT_IMR_RXOIM))
+
+#define BIT_SHIFT_IMR_RXFIM    4
+#define BIT_MASK_IMR_RXFIM     0x1
+// #define BIT_IMR_RXFIM(x)(((x) & BIT_MASK_IMR_RXFIM) << BIT_SHIFT_IMR_RXFIM)
+#define BIT_INVC_IMR_RXFIM (~(BIT_MASK_IMR_RXFIM << BIT_SHIFT_IMR_RXFIM))
+
+#define BIT_SHIFT_IMR_MSTIM    5
+#define BIT_MASK_IMR_MSTIM     0x1
+// #define BIT_IMR_MSTIM(x)(((x) & BIT_MASK_IMR_MSTIM) << BIT_SHIFT_IMR_MSTIM)
+#define BIT_INVC_IMR_MSTIM (~(BIT_MASK_IMR_MSTIM << BIT_SHIFT_IMR_MSTIM))
+
+#define BIT_IMR_TXEIM  BIT0
+#define BIT_IMR_TXOIM  BIT1
+#define BIT_IMR_RXUIM  BIT2
+#define BIT_IMR_RXOIM  BIT3
+#define BIT_IMR_RXFIM  BIT4
+#define BIT_IMR_MSTIM  BIT5
+
+// ISR             0x30  //  6 bits [READ ONLY]
+#define BIT_ISR_TXEIS  BIT0
+#define BIT_ISR_TXOIS  BIT1
+#define BIT_ISR_RXUIS  BIT2
+#define BIT_ISR_RXOIS  BIT3
+#define BIT_ISR_RXFIS  BIT4
+#define BIT_ISR_MSTIS  BIT5
+
+// RISR            0x34  //  6 bits [READ ONLY]
+#define BIT_RISR_TXEIR  BIT0
+#define BIT_RISR_TXOIR  BIT1
+#define BIT_RISR_RXUIR  BIT2
+#define BIT_RISR_RXOIR  BIT3
+#define BIT_RISR_RXFIR  BIT4
+#define BIT_RISR_MSTIR  BIT5
+
+// TXOICR          0x38  //  1 bits [READ ONLY]
+// RXOICR          0x3c  //  1 bits [READ ONLY]
+// RXUICR          0x40  //  1 bits [READ ONLY]
+// MSTICR          0x44  //  1 bits [READ ONLY]
+// ICR             0x48  //  1 bits [READ ONLY]
+
+// DMACR           0x4c  //  2 bits
+#define BIT_SHIFT_DMACR_RDMAE    0
+#define BIT_MASK_DMACR_RDMAE     0x1
+#define BIT_DMACR_RDMAE(x)(((x) & BIT_MASK_DMACR_RDMAE) << BIT_SHIFT_DMACR_RDMAE)
+#define BIT_INVC_DMACR_RDMAE (~(BIT_MASK_DMACR_RDMAE << BIT_SHIFT_DMACR_RDMAE))
+
+#define BIT_SHIFT_DMACR_TDMAE    1
+#define BIT_MASK_DMACR_TDMAE     0x1
+#define BIT_DMACR_TDMAE(x)(((x) & BIT_MASK_DMACR_TDMAE) << BIT_SHIFT_DMACR_TDMAE)
+#define BIT_INVC_DMACR_TDMAE (~(BIT_MASK_DMACR_TDMAE << BIT_SHIFT_DMACR_TDMAE))
+
+// DMATDLR         0x50
+#define BIT_SHIFT_DMATDLR_DMATDL    0
+#define BIT_MASK_DMATDLR_DMATDL     0x3F  // (TX_ABW-1):0
+#define BIT_DMATDLR_DMATDL(x)(((x) & BIT_MASK_DMATDLR_DMATDL) << BIT_SHIFT_DMATDLR_DMATDL)
+#define BIT_INVC_DMATDLR_DMATDL (~(BIT_MASK_DMATDLR_DMATDL << BIT_SHIFT_DMATDLR_DMATDL))
+
+// DMARDLR         0x54
+#define BIT_SHIFT_DMARDLR_DMARDL    0
+#define BIT_MASK_DMARDLR_DMARDL     0x3F  // (RX_ABW-1):0
+#define BIT_DMARDLR_DMARDL(x)(((x) & BIT_MASK_DMARDLR_DMARDL) << BIT_SHIFT_DMARDLR_DMARDL)
+#define BIT_INVC_DMARDLR_DMARDL (~(BIT_MASK_DMARDLR_DMARDL << BIT_SHIFT_DMARDLR_DMARDL))
+
+// IDR             0x58  // 32 bits [READ ONLY]
+// COMP_VERSION    0x5c  // 32 bits [READ ONLY]
+
+// DR              0x60  // 16 bits 0x60-0xEC
+#define BIT_SHIFT_DR_DR    0
+#define BIT_MASK_DR_DR     0xFFFF
+#define BIT_DR_DR(x)(((x) & BIT_MASK_DR_DR) << BIT_SHIFT_DR_DR)
+#define BIT_INVC_DR_DR (~(BIT_MASK_DR_DR << BIT_SHIFT_DR_DR))
+
+// RX_SAMPLE_DLY   0xF0  //  8 bits
+#define BIT_SHIFT_RX_SAMPLE_DLY_RSD    0
+#define BIT_MASK_RX_SAMPLE_DLY_RSD     0xFFFF
+#define BIT_RX_SAMPLE_DLY_RSD(x)(((x) & BIT_MASK_RX_SAMPLE_DLY_RSD) << BIT_SHIFT_RX_SAMPLE_DLY_RSD)
+#define BIT_INVC_RX_SAMPLE_DLY_RSD (~(BIT_MASK_RX_SAMPLE_DLY_RSD << BIT_SHIFT_RX_SAMPLE_DLY_RSD))
+
+// RSVD_0          0xF4  // 32 bits
+// RSVD_1          0xF8  // 32 bits
+// RSVD_2          0xFC  // 32 bits
+
+// SSI0 Pinmux
+#define BIT_SHIFT_SSI0_PIN_EN    0
+#define BIT_MASK_SSI0_PIN_EN     0x1
+#define BIT_SSI0_PIN_EN(x)(((x) & BIT_MASK_SSI0_PIN_EN) << BIT_SHIFT_SSI0_PIN_EN)
+#define BIT_INVC_SSI0_PIN_EN (~(BIT_MASK_SSI0_PIN_EN << BIT_SHIFT_SSI0_PIN_EN))
+
+#define BIT_SHIFT_SSI0_PIN_SEL    1
+#define BIT_MASK_SSI0_PIN_SEL     0x7
+#define BIT_SSI0_PIN_SEL(x)(((x) & BIT_MASK_SSI0_PIN_SEL) << BIT_SHIFT_SSI0_PIN_SEL)
+#define BIT_INVC_SSI0_PIN_SEL (~(BIT_MASK_SSI0_PIN_SEL << BIT_SHIFT_SSI0_PIN_SEL))
+
+// SSI1 Pinmux
+#define BIT_SHIFT_SSI1_PIN_EN    4
+#define BIT_MASK_SSI1_PIN_EN     0x1
+#define BIT_SSI1_PIN_EN(x)(((x) & BIT_MASK_SSI1_PIN_EN) << BIT_SHIFT_SSI1_PIN_EN)
+#define BIT_INVC_SSI1_PIN_EN (~(BIT_MASK_SSI1_PIN_EN << BIT_SHIFT_SSI1_PIN_EN))
+
+#define BIT_SHIFT_SSI1_PIN_SEL    5
+#define BIT_MASK_SSI1_PIN_SEL     0x7
+#define BIT_SSI1_PIN_SEL(x)(((x) & BIT_MASK_SSI1_PIN_SEL) << BIT_SHIFT_SSI1_PIN_SEL)
+#define BIT_INVC_SSI1_PIN_SEL (~(BIT_MASK_SSI1_PIN_SEL << BIT_SHIFT_SSI1_PIN_SEL))
+
+// SSI2 Pinmux
+#define BIT_SHIFT_SSI2_PIN_EN    8
+#define BIT_MASK_SSI2_PIN_EN     0x1
+#define BIT_SSI2_PIN_EN(x)(((x) & BIT_MASK_SSI2_PIN_EN) << BIT_SHIFT_SSI2_PIN_EN)
+#define BIT_INVC_SSI2_PIN_EN (~(BIT_MASK_SSI2_PIN_EN << BIT_SHIFT_SSI2_PIN_EN))
+
+#define BIT_SHIFT_SSI2_PIN_SEL    9
+#define BIT_MASK_SSI2_PIN_SEL     0x7
+#define BIT_SSI2_PIN_SEL(x)(((x) & BIT_MASK_SSI2_PIN_SEL) << BIT_SHIFT_SSI2_PIN_SEL)
+#define BIT_INVC_SSI2_PIN_SEL (~(BIT_MASK_SSI2_PIN_SEL << BIT_SHIFT_SSI2_PIN_SEL))
+
+// SSI0 Multiple Chip Selection (Pinmux Select is controlled by BIT_SSI0_PIN_SEL)
+#define BIT_SHIFT_SSI0_MULTI_CS_EN    28
+#define BIT_MASK_SSI0_MULTI_CS_EN     0x1
+#define BIT_SSI0_MULTI_CS_EN(x)(((x) & BIT_MASK_SSI0_MULTI_CS_EN) << BIT_SHIFT_SSI0_MULTI_CS_EN)
+#define BIT_INVC_SSI0_MULTI_CS_EN (~(BIT_MASK_SSI0_MULTI_CS_EN << BIT_SHIFT_SSI0_MULTI_CS_EN))
+
+
+#define HAL_SSI_READ32(SsiIndex, addr)         \
+    HAL_READ32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
+#define HAL_SSI_WRITE32(SsiIndex, addr, value) \
+    HAL_WRITE32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
+#define HAL_SSI_READ16(SsiIndex, addr)         \
+    HAL_READ16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
+#define HAL_SSI_WRITE16(SsiIndex, addr, value) \
+    HAL_WRITE16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
+#define HAL_SSI_READ8(SsiIndex, addr)          \
+    HAL_READ8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
+#define HAL_SSI_WRITE8(SsiIndex, addr, value)  \
+    HAL_WRITE8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
+
+
+// SSI Pinmux Select
+typedef enum _SSI0_PINMUX_SELECT_ {
+    SSI0_MUX_TO_GPIOE = S0,
+    SSI0_MUX_TO_GPIOC = S1
+}SSI0_PINMUX_SELECT, *PSSI0_PINMUX_SELECT;
+
+typedef enum _SSI1_PINMUX_SELECT_ {
+    SSI1_MUX_TO_GPIOA = S0,
+    SSI1_MUX_TO_GPIOB = S1,
+    SSI1_MUX_TO_GPIOD = S2
+}SSI1_PINMUX_SELECT, *PSSI1_PINMUX_SELECT;
+
+typedef enum _SSI2_PINMUX_SELECT_ {
+    SSI2_MUX_TO_GPIOG = S0,
+    SSI2_MUX_TO_GPIOE = S1,
+    SSI2_MUX_TO_GPIOD = S2
+}SSI2_PINMUX_SELECT, *PSSI2_PINMUX_SELECT;
+
+typedef enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
+    SSI0_CS_MUX_TO_GPIOE    = S0,
+    SSI0_CS_MUX_TO_GPIOC    = S1
+}SSI0_MULTI_CS_PINMUX_SELECT, *PSSI0_MULTI_CS_PINMUX_SELECT;
+
+typedef enum _SSI_CTRLR0_TMOD_ {
+    TMOD_TR       = 0,
+    TMOD_TO       = 1,
+    TMOD_RO       = 2,
+    TMOD_EEPROM_R = 3
+}SSI_CTRLR0_TMOD, *PSSI_CTRLR0_TMOD;
+
+typedef enum _SSI_CTRLR0_SCPOL_ {
+    SCPOL_INACTIVE_IS_LOW  = 0,
+    SCPOL_INACTIVE_IS_HIGH = 1
+}SSI_CTRLR0_SCPOL, *PSSI_CTRLR0_SCPOL;
+
+typedef enum _SSI_CTRLR0_SCPH_ {
+    SCPH_TOGGLES_IN_MIDDLE = 0,
+    SCPH_TOGGLES_AT_START  = 1
+}SSI_CTRLR0_SCPH, *PSSI_CTRLR0_SCPH;
+
+typedef enum _SSI_CTRLR0_DFS_ {
+    DFS_4_BITS   = 3,
+    DFS_5_BITS   = 4,
+    DFS_6_BITS   = 5,
+    DFS_7_BITS   = 6,
+    DFS_8_BITS   = 7,
+    DFS_9_BITS   = 8,
+    DFS_10_BITS  = 9,
+    DFS_11_BITS  = 10,
+    DFS_12_BITS  = 11,
+    DFS_13_BITS  = 12,
+    DFS_14_BITS  = 13,
+    DFS_15_BITS  = 14,
+    DFS_16_BITS  = 15,
+}SSI_CTRLR0_DFS, *PSSI_CTRLR0_DFS;
+
+typedef enum _SSI_CTRLR0_CFS_ {
+    CFS_1_BIT    = 0,
+    CFS_2_BITS   = 1,
+    CFS_3_BITS   = 2,
+    CFS_4_BITS   = 3,
+    CFS_5_BITS   = 4,
+    CFS_6_BITS   = 5,
+    CFS_7_BITS   = 6,
+    CFS_8_BITS   = 7,
+    CFS_9_BITS   = 8,
+    CFS_10_BITS  = 9,
+    CFS_11_BITS  = 10,
+    CFS_12_BITS  = 11,
+    CFS_13_BITS  = 12,
+    CFS_14_BITS  = 13,
+    CFS_15_BITS  = 14,
+    CFS_16_BITS  = 15
+}SSI_CTRLR0_CFS, *PSSI_CTRLR0_CFS;
+
+typedef enum _SSI_CTRLR0_SLV_OE_ {
+    SLV_TXD_ENABLE  = 0,
+    SLV_TXD_DISABLE = 1
+}SSI_CTRLR0_SLV_OE, *PSSI_CTRLR0_SLV_OE;
+
+typedef enum _SSI_ROLE_SELECT_ {
+    SSI_SLAVE  = 0,
+    SSI_MASTER = 1
+}SSI_ROLE_SELECT, *PSSI_ROLE_SELECT;
+
+typedef enum _SSI_FRAME_FORMAT_ {
+    FRF_MOTOROLA_SPI = 0,
+    FRF_TI_SSP       = 1,
+    FRF_NS_MICROWIRE = 2,
+    FRF_RSVD         = 3
+}SSI_FRAME_FORMAT, *PSSI_FRAME_FORMAT;
+
+typedef enum _SSI_DMACR_ENABLE_ {
+    SSI_NODMA        = 0,
+    SSI_RXDMA_ENABLE = 1,
+    SSI_TXDMA_ENABLE = 2,
+    SSI_TRDMA_ENABLE = 3
+}SSI_DMACR_ENABLE, *PSSI_DMACR_ENABLE;
+
+typedef enum _SSI_MWCR_HANDSHAKE_ {
+    MW_HANDSHAKE_DISABLE = 0,
+    MW_HANDSHAKE_ENABLE  = 1
+}SSI_MWCR_HANDSHAKE, *PSSI_MWCR_HANDSHAKE;
+
+typedef enum _SSI_MWCR_DIRECTION_ {
+    MW_DIRECTION_SLAVE_TO_MASTER = 0,
+    MW_DIRECTION_MASTER_TO_SLAVE = 1
+}SSI_MWCR_DIRECTION, *PSSI_MWCR_DIRECTION;
+
+typedef enum _SSI_MWCR_TMOD_ {
+    MW_TMOD_NONSEQUENTIAL = 0,
+    MW_TMOD_SEQUENTIAL    = 1
+}SSI_MWCR_TMOD, *PSSI_MWCR_TMOD;
+
+typedef enum _SSI_DATA_TRANSFER_MECHANISM_ {
+    SSI_DTM_BASIC,
+    SSI_DTM_INTERRUPT,
+    SSI_DTM_DMA
+}SSI_DATA_TRANSFER_MECHANISM, *PSSI_DATA_TRANSFER_MECHANISM;
+
+
+_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiEnableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiDisableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiSetSclkPolarityRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiSetSclkPhaseRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiWriteRtl8195a(VOID *Adaptor, u32 value);
+_LONG_CALL_ HAL_Status HalSsiLoadSettingRtl8195a(VOID *Adaptor, VOID *Setting);
+_LONG_CALL_ HAL_Status HalSsiSetInterruptMaskRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiSetDeviceRoleRtl8195a(VOID *Adaptor, u32 Role);
+_LONG_CALL_ HAL_Status HalSsiInterruptEnableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiInterruptDisableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiReadInterruptRtl8195a(VOID *Adaptor, VOID *RxData, u32 Length);
+_LONG_CALL_ HAL_Status HalSsiSetRxFifoThresholdLevelRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiSetTxFifoThresholdLevelRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiWriteInterruptRtl8195a(VOID *Adaptor, VOID *TxData, u32 Length);
+_LONG_CALL_ HAL_Status HalSsiSetSlaveEnableRegisterRtl8195a(VOID *Adaptor, u32 SlaveIndex);
+_LONG_CALL_ u32 HalSsiBusyRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiWriteableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiReadableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetInterruptMaskRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetRxFifoLevelRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetTxFifoLevelRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetStatusRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetInterruptStatusRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiReadRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetRawInterruptStatusRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetSlaveEnableRegisterRtl8195a(VOID *Adaptor);
+
+_LONG_CALL_ VOID _SsiReadInterrupt(VOID *Adaptor);
+_LONG_CALL_ VOID _SsiWriteInterrupt(VOID *Adaptor);
+_LONG_CALL_ u32  _SsiIrqHandle(VOID *Adaptor);
+
+// ROM code patch
+VOID _SsiReadInterruptRtl8195a(VOID *Adapter);
+VOID _SsiWriteInterruptRtl8195a(VOID *Adapter);
+HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
+HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
+HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
+VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
+HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
+HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
+#ifdef CONFIG_GDMA_EN
+VOID HalSsiTxGdmaLoadDefRtl8195a(VOID *Adapter);
+VOID HalSsiRxGdmaLoadDefRtl8195a(VOID *Adapter);
+VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
+HAL_Status HalSsiDmaSendRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
+HAL_Status HalSsiDmaRecvRtl8195a(VOID *Adapter, u8 *pRxData, u32 Length);
+#endif  // end of "#ifdef CONFIG_GDMA_EN"
+
+#endif

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h

@@ -0,0 +1,222 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL8195A_TIMER_H_
+#define _RTL8195A_TIMER_H_
+
+
+#define TIMER_TICK_US               31
+
+#define TIMER_LOAD_COUNT_OFF        0x00
+#define TIMER_CURRENT_VAL_OFF       0x04
+#define TIMER_CTL_REG_OFF           0x08
+#define TIMER_EOI_OFF               0x0c
+#define TIMER_INT_STATUS_OFF        0x10
+#define TIMER_INTERVAL              0x14
+#define TIMERS_INT_STATUS_OFF       0xa0
+#define TIMERS_EOI_OFF              0xa4
+#define TIMERS_RAW_INT_STATUS_OFF   0xa8
+#define TIMERS_COMP_VER_OFF         0xac
+
+#define MAX_TIMER_VECTOR_TABLE_NUM                  6
+
+#define HAL_TIMER_READ32(addr)            (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr)
+#define HAL_TIMER_WRITE32(addr, value)    ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value)
+#define HAL_TIMER_READ16(addr)            (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr)
+#define HAL_TIMER_WRITE16(addr, value)    ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value)
+#define HAL_TIMER_READ8(addr)             (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr)
+#define HAL_TIMER_WRITE8(addr, value)     ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value)
+
+_LONG_CALL_ u32
+HalGetTimerIdRtl8195a(
+    IN  u32     *TimerID
+);
+
+_LONG_CALL_ BOOL
+HalTimerInitRtl8195a(
+    IN  VOID    *Data
+);
+
+_LONG_CALL_ u32
+HalTimerReadCountRtl8195a(
+    IN  u32     TimerId
+);
+
+_LONG_CALL_ VOID
+HalTimerIrqClearRtl8195a(
+    IN  u32 TimerId
+);
+
+_LONG_CALL_ VOID
+HalTimerDisRtl8195a(
+    IN  u32 TimerId
+);
+
+_LONG_CALL_ VOID
+HalTimerEnRtl8195a(
+    IN  u32 TimerId
+);
+
+_LONG_CALL_ VOID
+HalTimerDumpRegRtl8195a(
+    IN  u32 TimerId
+);
+
+// ROM Code patch
+HAL_Status
+HalTimerInitRtl8195a_Patch(
+    IN  VOID    *Data
+);
+
+u32
+HalTimerReadCountRtl8195a_Patch(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerReLoadRtl8195a_Patch(
+    IN  u32 TimerId,
+    IN  u32 LoadUs
+);
+
+u32
+HalTimerReadCountRtl8195a_Patch(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerIrqEnRtl8195a(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerIrqDisRtl8195a(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerEnRtl8195a_Patch(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerDisRtl8195a_Patch(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerDeInitRtl8195a_Patch(
+    IN  VOID    *Data
+);
+
+#ifdef CONFIG_CHIP_C_CUT
+
+__weak _LONG_CALL_
+VOID
+HalTimerIrq2To7HandleV02(
+    IN  VOID    *Data
+);
+
+__weak _LONG_CALL_
+HAL_Status
+HalTimerIrqRegisterRtl8195aV02(
+    IN  VOID    *Data
+);
+
+__weak _LONG_CALL_
+HAL_Status
+HalTimerInitRtl8195aV02(
+    IN  VOID    *Data
+);
+
+__weak _LONG_CALL_
+u32
+HalTimerReadCountRtl8195aV02(
+    IN  u32 TimerId
+);
+
+__weak _LONG_CALL_
+VOID
+HalTimerReLoadRtl8195aV02(
+    IN  u32 TimerId,
+    IN  u32 LoadUs
+);
+
+__weak _LONG_CALL_
+HAL_Status
+HalTimerIrqUnRegisterRtl8195aV02(
+    IN  VOID    *Data
+);
+
+__weak _LONG_CALL_
+VOID
+HalTimerDeInitRtl8195aV02(
+    IN  VOID    *Data
+);
+
+#endif  // end of "#ifdef CONFIG_CHIP_C_CUT"
+
+// HAL functions wrapper
+static __inline HAL_Status
+HalTimerInit(
+    IN  VOID    *Data
+)
+{
+    return (HalTimerInitRtl8195a_Patch(Data));
+}
+
+static __inline VOID
+HalTimerEnable(
+    IN  u32 TimerId
+)
+{
+    HalTimerIrqEnRtl8195a(TimerId);
+    HalTimerEnRtl8195a_Patch(TimerId);
+}
+
+static __inline VOID
+HalTimerDisable(
+    IN  u32 TimerId
+)
+{
+    HalTimerDisRtl8195a_Patch(TimerId);
+}
+
+static __inline VOID
+HalTimerReLoad(
+    IN  u32 TimerId,
+    IN  u32 LoadUs
+)
+{
+    HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs);
+}
+
+#ifndef CONFIG_CHIP_C_CUT
+
+static __inline VOID
+HalTimerDeInit(
+    IN  VOID    *Data
+)
+{
+    HalTimerDeInitRtl8195a_Patch(Data);
+}
+
+#else
+
+static __inline VOID
+HalTimerDeInit(
+    IN  VOID    *Data
+)
+{
+    HalTimerDeInitRtl8195aV02(Data);
+}
+
+#endif      // end of "#ifndef CONFIG_CHIP_C_CUT"
+
+#endif //_RTL8195A_TIMER_H_

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h

@@ -0,0 +1,403 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_UART_H_
+#define _RTL8195A_UART_H_
+
+#define MAX_UART_INDEX      2
+
+#define RUART_DLL_OFF                   0x00
+#define RUART_DLM_OFF                   0x04    //RW, DLAB = 1
+#define RUART_INTERRUPT_EN_REG_OFF      0x04
+#define RUART_IER_ERBI                  0x01    //BIT0, Enable Received Data Available Interrupt (rx trigger)
+#define RUART_IER_ETBEI                 (1<<1)  //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty)
+#define RUART_IER_ELSI                  (1<<2)  //BIT2, Enable Receiver Line Status Interrupt (receiver line status)
+#define RUART_IER_EDSSI                 (1<<3)  //BIT3, Enable Modem Status Interrupt (modem status transition)
+
+#define RUART_INT_ID_REG_OFF            0x08    //[R]
+#define RUART_IIR_INT_PEND              0x01
+#define RUART_IIR_INT_ID                (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0)
+#define RUART_FIFO_CTL_REG_OFF          0x08    //[W]
+#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO (1<<1)  //BIT1, 0x02, Write 1 clear
+#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO (1<<2)  //BIT2, 0x04, Write 1 clear
+#define RUART_FIFO_CTL_REG_DMA_ENABLE   0x08    //BIT3
+
+#define FIFO_CTL_DEFAULT_WITH_FIFO_DMA  0xC9
+#define FIFO_CTL_DEFAULT_WITH_FIFO      0xC1
+
+#define RUART_MODEM_CTL_REG_OFF         0x10
+#define RUART_MCR_RTS                   BIT1
+#define RUART_MCL_AUTOFLOW_ENABLE       (1<<5)  //BIT5, 0x20
+
+#define RUART_LINE_CTL_REG_OFF          0x0C
+#define RUART_LINE_CTL_REG_DLAB_ENABLE  (1<<7)  //BIT7, 0x80
+
+#define RUART_LINE_STATUS_REG_OFF       0x14
+#define RUART_LINE_STATUS_REG_DR        0x01    //BIT0, Data Ready indicator
+#define RUART_LINE_STATUS_ERR_OVERRUN   (1<<1)  //BIT1, Over Run
+#define RUART_LINE_STATUS_ERR_PARITY    (1<<2)  //BIT2, Parity error
+#define RUART_LINE_STATUS_ERR_FRAMING   (1<<3)  //BIT3, Framing error
+#define RUART_LINE_STATUS_ERR_BREAK     (1<<4)  //BIT4, Break interrupt error
+#define RUART_LINE_STATUS_REG_THRE      (1<<5)  //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable
+#define RUART_LINE_STATUS_REG_TEMT      (1<<6)  //BIT6, 0x40, Transmitter Empty indicator(bit)
+#define RUART_LINE_STATUS_ERR_RXFIFO    (1<<7)  //BIT7, RX FIFO error
+#define RUART_LINE_STATUS_ERR           (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \
+                                        RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \
+                                        RUART_LINE_STATUS_ERR_RXFIFO)      //Line status error
+
+#define RUART_MODEM_STATUS_REG_OFF      0x18    //Modem Status Register
+#define RUART_SCRATCH_PAD_REG_OFF       0x1C    //Scratch Pad Register
+#define RUART_SP_REG_RXBREAK_INT_STATUS (1<<7)  //BIT7, 0x80, Write 1 clear
+#define RUART_SP_REG_DBG_SEL            0x0F<<8 //[11:8], Debug port selection
+#define RUART_SP_REG_XFACTOR_ADJ        0x7FF<<16  //[26:16]
+
+#define RUART_STS_REG_OFF               0x20
+#define RUART_STS_REG_RESET_RCV         (1<<3)  //BIT3, 0x08, Reset Uart Receiver
+#define RUART_STS_REG_XFACTOR           0xF<<4
+
+#define RUART_REV_BUF_REG_OFF           0x24  //Receiver Buffer Register
+#define RUART_TRAN_HOLD_REG_OFF         0x24  //Transmitter Holding Register
+
+#define RUART_MISC_CTL_REG_OFF          0x28
+#define RUART_TXDMA_BURSTSIZE_MASK      0xF8    //7:3
+#define RUART_RXDMA_BURSTSIZE_MASK      0x1F00  //12:8
+
+#define RUART_DEBUG_REG_OFF             0x3C
+
+// RUART_LINE_CTL_REG_OFF (0x0C)
+#define BIT_SHIFT_LCR_WLS             0     // word length select: 0: 7 bits, 1: 8bits
+#define BIT_MASK_LCR_WLS_8BITS        0x1
+#define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS)
+#define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS))
+
+#define BIT_SHIFT_LCR_STB             2     // Stop bit select: 0: no stop bit, 1: 1 stop bit
+#define BIT_MASK_LCR_STB_EN           0x1
+#define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB)
+#define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB))
+
+#define BIT_SHIFT_LCR_PARITY_EN       3
+#define BIT_MASK_LCR_PARITY_EN        0x1
+#define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN)
+#define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN))
+
+#define BIT_SHIFT_LCR_PARITY_TYPE       4
+#define BIT_MASK_LCR_PARITY_TYPE        0x1
+#define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE)
+#define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE))
+
+#define BIT_SHIFT_LCR_STICK_PARITY_EN       5
+#define BIT_MASK_LCR_STICK_PARITY_EN        0x1
+#define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN)
+#define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN))
+
+#define BIT_SHIFT_LCR_BREAK_CTRL       6
+#define BIT_MASK_LCR_BREAK_CTRL        0x1
+#define BIT_UART_LCR_BREAK_CTRL        ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL)
+
+#define RUART_BAUD_RATE_2400     2400
+#define RUART_BAUD_RATE_4800     4800
+#define RUART_BAUD_RATE_9600     9600
+#define RUART_BAUD_RATE_19200    19200
+#define RUART_BAUD_RATE_38400    38400
+#define RUART_BAUD_RATE_57600    57600
+#define RUART_BAUD_RATE_115200   115200
+#define RUART_BAUD_RATE_921600   921600
+#define RUART_BAUD_RATE_1152000  1152000
+
+#define HAL_RUART_READ32(UartIndex, addr)    \
+    HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
+#define HAL_RUART_WRITE32(UartIndex, addr, value)    \
+    HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
+#define HAL_RUART_READ16(UartIndex, addr)    \
+    HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
+#define HAL_RUART_WRITE16(UartIndex, addr, value)    \
+    HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
+#define HAL_RUART_READ8(UartIndex, addr)    \
+    HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
+#define HAL_RUART_WRITE8(UartIndex, addr, value)    \
+    HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
+
+typedef struct _RUART_SPEED_SETTING_ {
+    u32 BaudRate;
+    u32 Ovsr;
+    u32 Div;
+    u32 Ovsr_adj;
+}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING;
+
+typedef enum _UART_RXFIFO_TRIGGER_LEVEL_ {
+    OneByte       = 0x00,
+    FourBytes     = 0x01,
+    EightBytes    = 0x10,
+    FourteenBytes = 0x11
+}UART_RXFIFO_TRIGGER_LEVEL, *PUART_RXFIFO_TRIGGER_LEVEL;
+
+typedef enum _RUART0_PINMUX_SELECT_ {
+    RUART0_MUX_TO_GPIOC = S0,
+    RUART0_MUX_TO_GPIOE = S1,
+    RUART0_MUX_TO_GPIOA = S2
+}RUART0_PINMUX_SELECT, *PRUART0_PINMUX_SELECT;
+
+typedef enum _RUART1_PINMUX_SELECT_ {
+    RUART1_MUX_TO_GPIOD = S0,
+    RUART1_MUX_TO_GPIOE = S1,
+    RUART1_MUX_TO_GPIOB = S2
+}RUART1_PINMUX_SELECT, *PRUART1_PINMUX_SELECT;
+
+typedef enum _RUART2_PINMUX_SELECT_ {
+    RUART2_MUX_TO_GPIOA = S0,
+    RUART2_MUX_TO_GPIOC = S1,
+    RUART2_MUX_TO_GPIOD = S2
+}RUART2_PINMUX_SELECT, *PRUART2_PINMUX_SELECT;
+
+typedef enum _RUART_FLOW_CONTROL_ {
+    AUTOFLOW_DISABLE = 0,
+    AUTOFLOW_ENABLE  = 1
+}RUART_FLOW_CONTROL, *PRUART_FLOW_CONTROL;
+
+typedef enum _RUART_WORD_LEN_SEL_ {
+	RUART_WLS_7BITS = 0,
+    RUART_WLS_8BITS = 1
+}RUART_WORD_LEN_SEL, *PRUART_WORD_LEN_SEL;
+
+typedef enum _RUART_STOP_BITS_ {
+	RUART_NO_STOP_BIT = 0,
+    RUART_1_STOP_BIT = 1
+}RUART_STOP_BITS, *PRUART_STOP_BITS;
+
+typedef enum _RUART_PARITY_CONTROL_ {
+	RUART_PARITY_DISABLE = 0,
+	RUART_PARITY_ENABLE  = 1
+}RUART_PARITY_CONTROL, *PRUART_PARITY_CONTROL;
+
+typedef enum _RUART_PARITY_TYPE_ {
+	RUART_ODD_PARITY  = 0,
+	RUART_EVEN_PARITY = 1
+}RUART_PARITY_TYPE, *PRUART_PARITY_TYPE;
+
+typedef enum _RUART_STICK_PARITY_CONTROL_ {
+    RUART_STICK_PARITY_DISABLE = 0,
+    RUART_STICK_PARITY_ENABLE  = 1
+}RUART_STICK_PARITY_CONTROL, *PRUART_STICK_PARITY_CONTROL;
+
+typedef enum _UART_INT_ID_ {
+    ModemStatus           = 0,
+    TxFifoEmpty           = 1,
+    ReceiverDataAvailable = 2,
+    ReceivLineStatus      = 3,
+    TimeoutIndication     = 6
+}UART_INT_ID, *PUART_INT_ID;
+
+typedef enum _HAL_UART_State_
+{
+  HAL_UART_STATE_NULL              = 0x00,    // UART hardware not been initial yet
+  HAL_UART_STATE_READY             = 0x10,    // UART is initialed, ready to use
+  HAL_UART_STATE_BUSY              = 0x20,    // UART hardware is busy on configuration
+  HAL_UART_STATE_BUSY_TX           = 0x21,    // UART is buzy on TX
+  HAL_UART_STATE_BUSY_RX           = 0x22,    // UART is busy on RX
+  HAL_UART_STATE_BUSY_TX_RX        = 0x23,    // UART is busy on TX an RX
+  HAL_UART_STATE_TIMEOUT           = 0x30,    // Transfer timeout
+  HAL_UART_STATE_ERROR             = 0x40     // UART Error
+}HAL_UART_State, *PHAL_UART_State;
+
+typedef enum _HAL_UART_Status_
+{
+  HAL_UART_STATUS_OK               = 0x00,    // Transfer OK
+  HAL_UART_STATUS_TIMEOUT          = 0x01,    // Transfer Timeout
+  HAL_UART_STATUS_ERR_OVERRUN      = 0x02,    // RX Over run
+  HAL_UART_STATUS_ERR_PARITY       = 0x04,    // Parity error
+  HAL_UART_STATUS_ERR_FRAM         = 0x08,    // Framing Error
+  HAL_UART_STATUS_ERR_BREAK        = 0x10,    // Break Interrupt
+  HAL_UART_STATUS_ERR_PARA         = 0x20,    // Parameter error
+  HAL_UART_STATUS_ERR_RXFIFO       = 0x80,    // RX FIFO error
+}HAL_UART_Status, *PHAL_UART_Status;
+
+u32
+HalRuartGetDebugValueRtl8195a(
+        IN VOID* Data,
+        IN u32    DbgSel
+        );
+
+#if 0
+u32
+FindElementIndex(
+        u32 Element,
+        u32* Array
+        );
+#endif
+
+VOID
+RuartResetRxFifoRtl8195a(
+        IN u8 UartIndex
+        );
+#if 0
+VOID
+RuartBusDomainEnableRtl8195a(
+        IN u8 UartIndex
+        );
+#endif
+
+HAL_Status
+HalRuartResetRxFifoRtl8195a(
+        IN VOID *Data
+        );
+
+HAL_Status
+HalRuartInitRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalRuartDeInitRtl8195a(
+        IN VOID *Data  ///< RUART Adapter
+        );
+
+HAL_Status
+HalRuartPutCRtl8195a(
+        IN VOID *Data,
+        IN u8 TxData
+        );
+
+u32
+HalRuartSendRtl8195a(
+        IN VOID *Data,
+        IN u8 *pTxData,
+        IN u32 Length,
+        IN u32 Timeout
+        );
+
+HAL_Status
+HalRuartIntSendRtl8195a(
+        IN VOID *Data,      // PHAL_RUART_ADAPTER
+        IN u8 *pTxData,     // the Buffer to be send
+        IN u32 Length       // the length of data to be send
+        );
+
+HAL_Status
+HalRuartDmaSendRtl8195a(
+        IN VOID *Data,      // PHAL_RUART_ADAPTER
+        IN u8 *pTxData,     // the Buffer to be send
+        IN u32 Length      // the length of data to be send
+);
+
+HAL_Status
+HalRuartStopSendRtl8195a(
+        IN VOID *Data      // PHAL_RUART_ADAPTER
+);
+
+HAL_Status
+HalRuartGetCRtl8195a(
+        IN VOID *Data,
+        OUT u8  *pRxByte        
+        );
+
+u32
+HalRuartRecvRtl8195a(
+        IN VOID *Data,
+        IN u8  *pRxData,
+        IN u32 Length,
+        IN u32 Timeout
+        );
+
+HAL_Status
+HalRuartIntRecvRtl8195a(
+        IN VOID *Data,  ///< RUART Adapter
+        IN u8  *pRxData,  ///< Rx buffer
+        IN u32 Length      // buffer length
+        );
+
+HAL_Status
+HalRuartDmaRecvRtl8195a(
+        IN VOID *Data,  ///< RUART Adapter
+        IN u8  *pRxData,  ///< Rx buffer
+        IN u32 Length      // buffer length
+        );
+
+HAL_Status
+HalRuartStopRecvRtl8195a(
+        IN VOID *Data      // PHAL_RUART_ADAPTER
+);
+
+u8
+HalRuartGetIMRRtl8195a(
+        IN VOID *Data
+        );
+
+_LONG_CALL_ VOID
+HalRuartSetIMRRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalRuartDmaInitRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalRuartRTSCtrlRtl8195a(
+        IN VOID *Data,
+        IN BOOLEAN RtsCtrl
+        );
+
+VOID
+HalRuartRegIrqRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalRuartIntEnableRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalRuartIntDisableRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalRuartAdapterLoadDefRtl8195a(
+        IN VOID *pAdp,
+        IN u8 UartIdx
+);
+
+VOID
+HalRuartTxGdmaLoadDefRtl8195a(
+        IN VOID *pAdp,
+        IN VOID *pCfg
+);
+
+VOID
+HalRuartRxGdmaLoadDefRtl8195a(
+        IN VOID *pAdp,
+        IN VOID *pCfg
+);
+
+_LONG_CALL_  HAL_Status HalRuartIntSendRtl8195aV02(
+    IN VOID *Data,      // PHAL_RUART_ADAPTER
+    IN u8 *pTxData,     // the Buffer to be send
+    IN u32 Length      // the length of data to be send
+);
+
+_LONG_CALL_  HAL_Status
+HalRuartIntRecvRtl8195aV02(
+    IN VOID *Data,  ///< RUART Adapter
+    IN u8  *pRxData,  ///< Rx buffer
+    IN u32 Length      // buffer length
+);
+
+_LONG_CALL_ s32
+FindElementIndex_v02(
+        u32 Element,  ///< RUART Baudrate
+        u32* Array,    ///< Pre-defined Baudrate Array
+        u32 ElementNo
+);
+
+_LONG_CALL_ HAL_Status HalRuartInitRtl8195a_v02(IN VOID *Data);
+
+#endif

component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_wdt.h

@@ -0,0 +1,86 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2014 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL8195A_WDT_H_
+#define _RTL8195A_WDT_H_
+
+#define WDGTIMERELY  (10*1024)  //us
+
+typedef struct _WDG_REG_ {
+    u16     WdgScalar;
+    u8      WdgEnByte;
+    u8      WdgClear:1;
+    u8      WdgCunLimit:4;
+    u8      Rsvd:1;
+    u8      WdgMode:1;
+    u8      WdgToISR:1;
+}WDG_REG, *PWDG_REG;
+
+typedef struct _WDG_ADAPTER_ {
+
+    WDG_REG             Ctrl;
+    IRQ_HANDLE          IrqHandle;
+    TIMER_ADAPTER       WdgGTimer;
+    VOID (*UserCallback)(u32 callback_id);    // User callback function
+    u32                 callback_id;
+}WDG_ADAPTER, *PWDG_ADAPTER;
+
+typedef enum _WDG_CNTLMT_ {
+    CNT1H    = 0,
+    CNT3H    = 1,
+    CNT7H    = 2,
+    CNTFH    = 3,
+    CNT1FH   = 4,
+    CNT3FH   = 5,
+    CNT7FH   = 6,
+    CNTFFH   = 7,
+    CNT1FFH  = 8,
+    CNT3FFH  = 9,
+    CNT7FFH  = 10,
+    CNTFFFH  = 11
+}WDG_CNTLMT, *PWDG_CNTLMT;
+
+
+typedef enum _WDG_MODE_ {
+    INT_MODE    = 0,
+    RESET_MODE  = 1
+}WDG_MODE, *PWDG_MODE;
+
+extern VOID
+WDGInitial(
+    IN  u32 Period
+);
+
+extern VOID
+WDGIrqInitial(
+    VOID
+);
+
+extern VOID
+WDGIrqInitial(
+    VOID
+);
+
+extern VOID
+WDGStop(
+    VOID
+);
+
+extern VOID
+WDGRefresh(
+    VOID
+);
+
+extern VOID
+WDGIrqCallBackReg(
+    IN VOID *CallBack,
+    IN u32   Id
+);
+
+#endif //_RTL8195A_WDT_H_

component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_adc.c

@@ -0,0 +1,380 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "platform_autoconf.h" 
+#include "diag.h"
+#include "rtl8195a_adc.h"
+#include "hal_adc.h"
+
+//---------------------------------------------------------------------------------------------------
+//Function Name:
+//		HalI2CInit8195a
+//
+// Description:
+//		To initialize I2C module by using the given data.
+//
+// Arguments:
+//		[in] VOID    *Data -
+//			The I2C parameter data struct.
+//
+// Return:
+//		The status of the DeInit process.
+//          _EXIT_SUCCESS if the initialization succeeded.
+//          _EXIT_FAILURE if the initialization failed.
+//
+// Note:
+//		None
+//
+// See Also:
+//		NA
+//
+// Author:
+// 		By Jason Deng, 2014-04-02.
+//
+//---------------------------------------------------------------------------------------------------
+RTK_STATUS
+HalADCInit8195a(
+    IN  VOID    *Data
+)
+{
+    PHAL_ADC_INIT_DAT   pHalAdcInitData     =   (PHAL_ADC_INIT_DAT)Data;
+    u32 AdcTempDat;
+    u8  AdcTempIdx  =   pHalAdcInitData->ADCIdx;
+
+    /* Enable ADC power cut */
+/*
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_POWER);
+    AdcTempDat  |=  BIT_ADC_PWR_AUTO;
+    HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
+*/
+    
+    /* ADC Control register set-up*/
+    AdcTempDat  = 0;
+    AdcTempDat  |= (BIT_CTRL_ADC_COMP_ONLY(pHalAdcInitData->ADCCompOnly)    |
+                    BIT_CTRL_ADC_ONESHOT(pHalAdcInitData->ADCOneShotEn)     |
+                    BIT_CTRL_ADC_OVERWRITE(pHalAdcInitData->ADCOverWREn)    |
+                    BIT_CTRL_ADC_ENDIAN(pHalAdcInitData->ADCEndian)         |
+                    BIT_CTRL_ADC_BURST_SIZE(pHalAdcInitData->ADCBurstSz)    |
+                    BIT_CTRL_ADC_THRESHOLD(pHalAdcInitData->ADCOneShotTD)   |
+                    BIT_CTRL_ADC_DBG_SEL(pHalAdcInitData->ADCDbgSel));
+    HAL_ADC_WRITE32(REG_ADC_CONTROL,AdcTempDat);
+
+    DBG_8195A_ADC_LVL(HAL_ADC_LVL,"REG_ADC_CONTROL:%x\n", HAL_ADC_READ32(REG_ADC_CONTROL));
+    
+    /* ADC compare value and compare method setting*/    
+    switch (AdcTempIdx) {
+        case ADC0_SEL:
+            AdcTempDat  =   HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
+            AdcTempDat  &=  ~(BIT_ADC_COMP_TH_0(0xFFFF));
+            AdcTempDat  |=  BIT_CTRL_ADC_COMP_TH_0(pHalAdcInitData->ADCCompTD);
+            HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
+            break;
+            
+        case ADC1_SEL:
+            AdcTempDat  =   HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
+            AdcTempDat  &=  ~(BIT_ADC_COMP_TH_1(0xFFFF));
+            AdcTempDat  |=  BIT_CTRL_ADC_COMP_TH_1(pHalAdcInitData->ADCCompTD);
+            HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
+            break;
+            
+        case ADC2_SEL:
+            AdcTempDat  =   HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
+            AdcTempDat  &=  ~(BIT_ADC_COMP_TH_2(0xFFFF));
+            AdcTempDat  |=  BIT_CTRL_ADC_COMP_TH_2(pHalAdcInitData->ADCCompTD);
+            HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
+            break;
+            
+        case ADC3_SEL:
+            AdcTempDat  =   HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
+            AdcTempDat  &=  ~(BIT_ADC_COMP_TH_3(0xFFFF));
+            AdcTempDat  |=  BIT_CTRL_ADC_COMP_TH_3(pHalAdcInitData->ADCCompTD);
+            HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
+            break;
+        default:
+            return _EXIT_FAILURE;
+    }
+
+    /* ADC compare mode setting */
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_COMP_SET);
+    AdcTempDat  &=  (~(0x01 << pHalAdcInitData->ADCIdx));
+    AdcTempDat  |=  (BIT_CTRL_ADC_COMP_0_EN(pHalAdcInitData->ADCCompCtrl) << 
+                                                    pHalAdcInitData->ADCIdx);
+    HAL_ADC_WRITE32(REG_ADC_COMP_SET, AdcTempDat);
+
+    /* ADC audio mode set-up */
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
+    AdcTempDat  &=  ~(BIT_ADC_AUDIO_EN);
+    AdcTempDat  |=  BIT_CTRL_ADC_AUDIO_EN(pHalAdcInitData->ADCAudioEn);
+    HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
+
+    /* ADC enable manually setting */
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
+    AdcTempDat  &=  ~(BIT_ADC_EN_MANUAL);
+    AdcTempDat  |=  BIT_CTRL_ADC_EN_MANUAL(pHalAdcInitData->ADCEnManul);
+    HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
+
+
+    /* ADC analog parameter 0 */
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
+    DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
+    AdcTempDat  |= (BIT0);
+    if (pHalAdcInitData->ADCInInput == 1){
+        AdcTempDat  &= (~BIT14);
+    }
+    else {
+        AdcTempDat  |= (BIT14);
+    }
+    AdcTempDat  &= (~(BIT3|BIT2));
+        
+    /* Adjust VCM for C-Cut*/
+#ifdef CONFIG_CHIP_C_CUT
+    AdcTempDat  |= (BIT22);
+#endif
+    
+    HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
+    DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
+
+    /* ADC analog parameter 1 */
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
+    AdcTempDat  &= (~BIT1);
+    AdcTempDat  |= (BIT2|BIT0);
+    HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, AdcTempDat);
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
+    DBG_ADC_INFO("AD1:%x\n", AdcTempDat);
+        
+    /* ADC analog parameter 2 */
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
+    DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
+    AdcTempDat  = 0x67884400;
+    HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD2, AdcTempDat);
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
+    DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
+
+    /* ADC analog parameter 3 */
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
+    DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
+    AdcTempDat  =  0x77780039;
+    HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD3, AdcTempDat);
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
+    DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
+
+    /* ADC analog parameter 4 */
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
+    DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
+    AdcTempDat  =  0x0004d501;
+    HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD4, AdcTempDat);
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
+    DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
+
+    /* ADC analog parameter 5 */
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
+    DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
+    AdcTempDat  =  0x1E010800;
+    HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD5, AdcTempDat);
+    AdcTempDat  =   HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
+    DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
+
+    return _EXIT_SUCCESS;
+}
+
+//---------------------------------------------------------------------------------------------------
+//Function Name:
+//		HalI2CInit8195a
+//
+// Description:
+//		To initialize I2C module by using the given data.
+//
+// Arguments:
+//		[in] VOID    *Data -
+//			The I2C parameter data struct.
+//
+// Return:
+//		The status of the DeInit process.
+//          _EXIT_SUCCESS if the initialization succeeded.
+//          _EXIT_FAILURE if the initialization failed.
+//
+// Note:
+//		None
+//
+// See Also:
+//		NA
+//
+// Author:
+// 		By Jason Deng, 2014-04-02.
+//
+//---------------------------------------------------------------------------------------------------
+RTK_STATUS
+HalADCDeInit8195a(
+    IN  VOID    *Data
+)
+{
+    u32 AdcTempDat;
+
+    AdcTempDat      =   HAL_ADC_READ32(REG_ADC_POWER);
+    AdcTempDat      &=  ~(BIT_ADC_PWR_AUTO);
+    HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
+
+    return _EXIT_SUCCESS;
+}
+
+//---------------------------------------------------------------------------------------------------
+//Function Name:
+//		HalI2CIntrCtrl8195a
+//
+// Description:
+//		Modify the I2C interrupt mask according to the given value
+//
+// Arguments:
+//		[in] VOID    *Data -
+//			The I2C parameter data struct.
+//
+// Return:
+//		The status of the enable process.
+//          _EXIT_SUCCESS if the de-initialization succeeded.
+//          _EXIT_FAILURE if the de-initialization failed.
+//
+// Note:
+//		None
+//
+// See Also:
+//		NA
+//
+// Author:
+// 		By Jason Deng, 2014-02-18.
+//
+//---------------------------------------------------------------------------------------------------
+RTK_STATUS
+HalADCEnableRtl8195a(
+    IN  VOID    *Data
+){
+    PHAL_ADC_INIT_DAT   pHalAdcInitData     =   (PHAL_ADC_INIT_DAT)Data;
+    u32 AdcTempDat;
+
+    
+    AdcTempDat      =   HAL_ADC_READ32(REG_ADC_POWER);
+    AdcTempDat      &=  (~BIT_ADC_PWR_AUTO);
+    AdcTempDat      |=  BIT_CTRL_ADC_PWR_AUTO(pHalAdcInitData->ADCEn);
+    HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
+
+    return _EXIT_SUCCESS;
+}
+
+
+//---------------------------------------------------------------------------------------------------
+//Function Name:
+//		HalI2CIntrCtrl8195a
+//
+// Description:
+//		Modify the I2C interrupt mask according to the given value
+//
+// Arguments:
+//		[in] VOID    *Data -
+//			The I2C parameter data struct.
+//
+// Return:
+//		The status of the enable process.
+//          _EXIT_SUCCESS if the de-initialization succeeded.
+//          _EXIT_FAILURE if the de-initialization failed.
+//
+// Note:
+//		None
+//
+// See Also:
+//		NA
+//
+// Author:
+// 		By Jason Deng, 2014-02-18.
+//
+//---------------------------------------------------------------------------------------------------
+RTK_STATUS
+HalADCIntrCtrl8195a(
+    IN  VOID    *Data
+){
+    PHAL_ADC_INIT_DAT   pHalAdcInitData     =   (PHAL_ADC_INIT_DAT)Data;
+    
+    HAL_ADC_WRITE32(REG_ADC_INTR_EN, pHalAdcInitData->ADCIntrMSK);
+
+    return _EXIT_SUCCESS;
+}
+
+//---------------------------------------------------------------------------------------------------
+//Function Name:
+//		HalI2CReceiveRtl8195a
+//
+// Description:
+//		Directly read one data byte a I2C data fifo.
+//
+// Arguments:
+//		[in] VOID    *Data -
+//			The I2C parameter data struct.
+//
+// Return:
+//		The first data fifo content.
+//
+// Note:
+//		None
+//
+// See Also:
+//		NA
+//
+// Author:
+// 		By Jason Deng, 2014-02-18.
+//
+//---------------------------------------------------------------------------------------------------
+u32
+HalADCReceiveRtl8195a(
+    IN  VOID    *Data
+){
+    u32 AdcTempDat;
+
+    AdcTempDat = HAL_ADC_READ32(REG_ADC_FIFO_READ);
+    
+    return (AdcTempDat);
+}
+
+
+//---------------------------------------------------------------------------------------------------
+//Function Name:
+//		HalI2CReadRegRtl8195a
+//
+// Description:
+//		Directly read a I2C register according to the register offset.
+//
+// Arguments:
+//		[in] VOID    *Data -
+//			The I2C parameter data struct.
+//		[in] I2CReg -
+//			The I2C register offset.
+//
+// Return:
+//		The register content in u32 format.
+//
+// Note:
+//		None
+//
+// See Also:
+//		NA
+//
+// Author:
+// 		By Jason Deng, 2014-02-18.
+//
+//---------------------------------------------------------------------------------------------------
+u32
+HalADCReadRegRtl8195a(
+        IN  VOID    *Data,
+        IN  u8      I2CReg
+){
+    u32 AdcTempDat;
+
+    AdcTempDat  =   HAL_ADC_READ32(I2CReg);
+    return (AdcTempDat);
+}
+

component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_dac.c

@@ -0,0 +1,269 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h" 
+#include "rtl8195a_dac.h"
+#include "hal_dac.h"
+
+
+//---------------------------------------------------------------------------------------------------
+//Function Name:
+//		HalDACInit8195a
+//
+// Description:
+//		To initialize DAC module by using the given data.
+//
+// Arguments:
+//		[in] VOID    *Data -
+//			The DAC parameter data struct.
+//
+// Return:
+//		The status of the DeInit process.
+//          _EXIT_SUCCESS if the initialization succeeded.
+//          _EXIT_FAILURE if the initialization failed.
+//
+// Note:
+//		None
+//
+// See Also:
+//		NA
+//
+// Author:
+// 		By Jason Deng, 2014-04-15.
+//
+//---------------------------------------------------------------------------------------------------
+RTK_STATUS
+HalDACInit8195a(
+    IN  VOID    *Data
+){
+    PHAL_DAC_INIT_DAT   pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
+    u32 DacTempDat;
+    u8  DacTempIdx      = pHalDacInitData->DACIdx;
+    
+    /* Enable DAC power cut */
+    DacTempDat  = HAL_DAC_READ32(0, REG_DAC_PWR_CTRL);
+    DacTempDat  |= BIT_DAC_PWR_AUTO;
+    
+    HAL_DAC_WRITE32(0, REG_DAC_PWR_CTRL, DacTempDat);
+
+    /* Disable DAC module first */
+    HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, 0);
+
+    /* Setup DAC module */
+    DacTempDat  = 0;
+    DacTempDat  |= (BIT_CTRL_DAC_SPEED(pHalDacInitData->DACDataRate)            |
+                    BIT_CTRL_DAC_ENDIAN(pHalDacInitData->DACEndian)             |
+                    BIT_CTRL_DAC_FILTER_SETTLE(pHalDacInitData->DACFilterSet)   |
+                    BIT_CTRL_DAC_BURST_SIZE(pHalDacInitData->DACBurstSz)        |
+                    BIT_CTRL_DAC_DBG_SEL(pHalDacInitData->DACDbgSel)            |
+                    BIT_CTRL_DAC_DSC_DBG_SEL(pHalDacInitData->DACDscDbgSel)     |
+                    BIT_CTRL_DAC_BYPASS_DSC(pHalDacInitData->DACBPDsc)          |
+                    BIT_CTRL_DAC_DELTA_SIGMA(pHalDacInitData->DACDeltaSig));
+                    
+    HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
+    
+    return _EXIT_SUCCESS;
+}
+
+//---------------------------------------------------------------------------------------------------
+//Function Name:
+//		HalI2CInit8195a
+//
+// Description:
+//		To initialize I2C module by using the given data.
+//
+// Arguments:
+//		[in] VOID    *Data -
+//			The I2C parameter data struct.
+//
+// Return:
+//		The status of the DeInit process.
+//          _EXIT_SUCCESS if the initialization succeeded.
+//          _EXIT_FAILURE if the initialization failed.
+//
+// Note:
+//		None
+//
+// See Also:
+//		NA
+//
+// Author:
+// 		By Jason Deng, 2014-04-02.
+//
+//---------------------------------------------------------------------------------------------------
+RTK_STATUS
+HalDACDeInit8195a(
+    IN  VOID    *Data
+){
+    PHAL_DAC_INIT_DAT   pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
+    u32 DacTempDat;
+
+    DacTempDat = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL);
+    DacTempDat &= (~BIT_DAC_FIFO_EN);
+    HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL ,DacTempDat);
+    
+    return _EXIT_SUCCESS;
+}
+
+
+//---------------------------------------------------------------------------------------------------
+//Function Name:
+//		HalI2CIntrCtrl8195a
+//
+// Description:
+//		Modify the I2C interrupt mask according to the given value
+//
+// Arguments:
+//		[in] VOID    *Data -
+//			The I2C parameter data struct.
+//
+// Return:
+//		The status of the enable process.
+//          _EXIT_SUCCESS if the de-initialization succeeded.
+//          _EXIT_FAILURE if the de-initialization failed.
+//
+// Note:
+//		None
+//
+// See Also:
+//		NA
+//
+// Author:
+// 		By Jason Deng, 2014-02-18.
+//
+//---------------------------------------------------------------------------------------------------
+RTK_STATUS
+HalDACEnableRtl8195a(
+    IN  VOID    *Data
+){
+    PHAL_DAC_INIT_DAT   pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
+    u32 DacTempDat;
+    u8  DacTempIdx      = pHalDacInitData->DACIdx;
+    
+    DacTempDat  = HAL_DAC_READ32(DacTempIdx, REG_DAC_CTRL);
+    DacTempDat  &= (~BIT_DAC_FIFO_EN);
+
+    DacTempDat  |= BIT_CTRL_DAC_FIFO_EN(pHalDacInitData->DACEn);
+    HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
+
+    return _EXIT_SUCCESS;
+}
+
+
+//---------------------------------------------------------------------------------------------------
+//Function Name:
+//		HalI2CIntrCtrl8195a
+//
+// Description:
+//		Modify the I2C interrupt mask according to the given value
+//
+// Arguments:
+//		[in] VOID    *Data -
+//			The I2C parameter data struct.
+//
+// Return:
+//		The status of the enable process.
+//          _EXIT_SUCCESS if the de-initialization succeeded.
+//          _EXIT_FAILURE if the de-initialization failed.
+//
+// Note:
+//		None
+//
+// See Also:
+//		NA
+//
+// Author:
+// 		By Jason Deng, 2014-02-18.
+//
+//---------------------------------------------------------------------------------------------------
+RTK_STATUS
+HalDACIntrCtrl8195a(
+    IN  VOID    *Data
+){
+    PHAL_DAC_INIT_DAT   pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
+
+    HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL, pHalDacInitData->DACIntrMSK);
+    
+    return _EXIT_SUCCESS;
+}
+
+//---------------------------------------------------------------------------------------------------
+//Function Name:
+//		HalI2CReceiveRtl8195a
+//
+// Description:
+//		Directly read one data byte a I2C data fifo.
+//
+// Arguments:
+//		[in] VOID    *Data -
+//			The I2C parameter data struct.
+//
+// Return:
+//		The first data fifo content.
+//
+// Note:
+//		None
+//
+// See Also:
+//		NA
+//
+// Author:
+// 		By Jason Deng, 2014-02-18.
+//
+//---------------------------------------------------------------------------------------------------
+u8
+HalDACSendRtl8195a(
+    IN  VOID    *Data
+){
+
+
+    return (0);
+}
+
+
+//---------------------------------------------------------------------------------------------------
+//Function Name:
+//		HalDACReadRegRtl8195a
+//
+// Description:
+//		
+//
+// Arguments:
+//		[in] VOID    *Data -
+//			The DAC parameter data struct.
+//		[in] I2CReg -
+//			The DAC register offset.
+//
+// Return:
+//		The DAC register content in u32 format.
+//
+// Note:
+//		None
+//
+// See Also:
+//		NA
+//
+// Author:
+// 		By Jason Deng, 2014-04-15.
+//
+//---------------------------------------------------------------------------------------------------
+u32
+HalDACReadRegRtl8195a(
+        IN  VOID    *Data,
+        IN  u8      I2CReg
+){
+    PHAL_DAC_INIT_DAT   pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
+
+    //DBG_8195A_DAC("dac read reg idx:%x\n",pHalDacInitData->DACIdx);
+    //DBG_8195A_DAC("dac read reg offset:%x\n",I2CReg);
+
+    return (u32)HAL_DAC_READ32(pHalDacInitData->DACIdx, I2CReg);
+}
+

component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c

@@ -0,0 +1,243 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h" 
+#include "rtl8195a_gdma.h"
+#include "hal_gdma.h"
+
+#ifndef CONFIG_CHIP_D_CUT
+BOOL
+HalGdmaChBlockSetingRtl8195a(
+    IN  VOID     *Data
+)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
+    PGDMA_CH_LLI_ELE pLliEle;
+    struct GDMA_CH_LLI *pGdmaChLli;
+    struct BLOCK_SIZE_LIST *pGdmaChBkLi;
+    u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
+    u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
+    u8  GdmaIndex = pHalGdmaAdapter->GdmaIndex;
+    u8  ChNum = pHalGdmaAdapter->ChNum;
+    u32 ChEn = pHalGdmaAdapter->ChEn;
+    u8  GdmaChIsrBitmap = (ChEn & 0xFF);
+    u8  PendingIsrIndex;
+
+
+    pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
+    pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
+    pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
+
+
+    //4 1) Check chanel is avaliable
+    if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
+        //4 Disable Channel
+        DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
+
+        HalGdmaChDisRtl8195a(Data);
+
+    }
+
+    //4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran,  Error
+    for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
+
+        u32 PendRaw, PendStstus;
+        PendRaw = HAL_GDMAX_READ32(GdmaIndex, 
+                                        (REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
+        PendStstus = HAL_GDMAX_READ32(GdmaIndex, 
+                                        (REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
+
+        if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
+            //4 Clear Pending Isr
+            HAL_GDMAX_WRITE32(GdmaIndex,
+                              (REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8), 
+                              (PendStstus & (GdmaChIsrBitmap))
+                              );
+            
+        } 
+    }
+
+        //4 Fill in SARx register
+    HAL_GDMAX_WRITE32(GdmaIndex,
+                      (REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF), 
+                      (pHalGdmaAdapter->ChSar)
+                      );
+    
+    
+        //4 Fill in DARx register
+    HAL_GDMAX_WRITE32(GdmaIndex,
+                      (REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF), 
+                      (pHalGdmaAdapter->ChDar)
+                      );
+
+    
+
+    //4 3) Process CTLx
+    CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
+                               (REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
+
+        //4 Clear Config low register bits
+    CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
+                BIT_INVC_CTLX_LO_DST_TR_WIDTH &
+                BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
+                BIT_INVC_CTLX_LO_DINC &
+                BIT_INVC_CTLX_LO_SINC &
+                BIT_INVC_CTLX_LO_DEST_MSIZE &
+                BIT_INVC_CTLX_LO_SRC_MSIZE &
+                BIT_INVC_CTLX_LO_TT_FC &
+                BIT_INVC_CTLX_LO_LLP_DST_EN &
+                BIT_INVC_CTLX_LO_LLP_SRC_EN);
+
+    CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
+                               (REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
+
+        //4 Clear Config upper register bits
+    CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
+               BIT_INVC_CTLX_UP_DONE);
+
+
+    CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
+              BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
+              BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
+              BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
+              BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
+              BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
+              BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
+              BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
+              BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
+              BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
+              CtlxLow;
+    
+    CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
+             BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
+             CtlxUp;
+
+        //4 Fill in CTLx register
+    HAL_GDMAX_WRITE32(GdmaIndex,
+                      (REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF), 
+                      CtlxLow
+                      );
+    
+    HAL_GDMAX_WRITE32(GdmaIndex,
+                      (REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4), 
+                      CtlxUp
+                      );
+   
+    //4 4) Program CFGx
+    
+    CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
+                              (REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
+
+    CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
+                BIT_INVC_CFGX_LO_CH_SUSP &
+                BIT_INVC_CFGX_LO_HS_SEL_DST &
+                BIT_INVC_CFGX_LO_HS_SEL_SRC &
+                BIT_INVC_CFGX_LO_LOCK_CH_L &
+                BIT_INVC_CFGX_LO_LOCK_B_L &
+                BIT_INVC_CFGX_LO_LOCK_CH &
+                BIT_INVC_CFGX_LO_LOCK_B &
+                BIT_INVC_CFGX_LO_RELOAD_SRC &
+                BIT_INVC_CFGX_LO_RELOAD_DST);
+
+    CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
+                              (REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
+
+    CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
+               BIT_INVC_CFGX_UP_DS_UPD_EN &
+               BIT_INVC_CFGX_UP_SS_UPD_EN &
+               BIT_INVC_CFGX_UP_SRC_PER &
+               BIT_INVC_CFGX_UP_DEST_PER);
+
+    CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
+              BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
+              BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
+              BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
+              BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
+              BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
+              BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
+              BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
+              BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
+              BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
+              CfgxLow;
+
+    CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
+             BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
+             BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
+             BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
+             BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
+             CfgxUp;
+
+    HAL_GDMAX_WRITE32(GdmaIndex,
+                      (REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF), 
+                      CfgxLow
+                      );
+    
+    HAL_GDMAX_WRITE32(GdmaIndex,
+                      (REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4), 
+                      CfgxUp
+                      );
+    
+    
+
+    //4 Check 4 Bytes Alignment
+    if ((u32)(pLliEle) & 0x3) {
+        DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n", 
+                        pHalGdmaAdapter->pLli);
+        return _FALSE;
+    }
+    
+    HAL_GDMAX_WRITE32(GdmaIndex,
+                      (REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF), 
+                      pLliEle
+                      );
+
+    //4 Update the first llp0
+    pLliEle->CtlxLow = CtlxLow;
+    pLliEle->CtlxUp = CtlxUp;
+    pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
+    DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
+
+    pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
+
+    while (MultiBlockCount > 1) {
+        MultiBlockCount--;
+        DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
+        pLliEle = pGdmaChLli->pLliEle;
+
+        if (NULL == pLliEle) {
+            DBG_8195A("pLliEle Null Point!!!!!\n");
+            return _FALSE;
+        }
+
+        //4 Clear the last element llp enable bit
+        if (1 == MultiBlockCount) {
+            if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 0){
+                CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
+                       BIT_INVC_CTLX_LO_LLP_SRC_EN);
+            }            
+        }
+        //4 Update block size for transfer
+        CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
+        CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
+
+        //4 Update tje Lli and Block size list point to next llp
+        pGdmaChLli = pGdmaChLli->pNextLli;
+        pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
+
+        //4 Updatethe Llpx context
+        pLliEle->CtlxLow = CtlxLow;
+        pLliEle->CtlxUp = CtlxUp;        
+        pLliEle->Llpx = pGdmaChLli->pLliEle;
+        
+    }
+
+    return _TRUE;
+}
+#endif

component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gpio.c

@@ -0,0 +1,53 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#include "rtl8195a.h"
+#include "hal_gpio.h"
+#include "rtl8195a_gpio.h"
+#include "gpio_irq_api.h"
+
+extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
+
+/**
+  * @brief  Clear the pending interrupt of a specified pin
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @retval None
+  */
+HAL_Status
+HAL_GPIO_ClearISR_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    u8 port_num;
+    u8 pin_num;
+    HAL_GPIO_PIN_MODE pin_mode;
+
+    port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
+    pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
+    pin_mode = GPIO_Pin->pin_mode;
+
+    if ((pin_mode & HAL_GPIO_PIN_INT_MODE)==0 || (port_num != GPIO_PORT_A)) {
+        DBG_GPIO_ERR("HAL_GPIO_ClearISR_8195a: This pin(%x:%x) is'nt an interrupt pin\n", GPIO_Pin->pin_name, GPIO_Pin->pin_mode);
+        return HAL_ERR_PARA;
+    }
+
+    if (GPIO_Lock() != HAL_OK) {
+        return HAL_BUSY;
+    }
+
+    // Clear pending interrupt before unmask it
+    HAL_WRITE32(GPIO_REG_BASE, GPIO_PORTA_EOI, (1<<pin_num));
+
+    GPIO_UnLock();
+    return HAL_OK;
+    
+}
+

component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_i2s.c

@@ -0,0 +1,394 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h" 
+#include "rtl8195a_i2s.h"
+#include "hal_i2s.h"
+
+extern void *
+_memset( void *s, int c, SIZE_T n );
+
+RTK_STATUS
+HalI2SInitRtl8195a_Patch(
+    IN  VOID    *Data
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+
+    u8  I2SIdx;
+    u8  I2SEn;
+    u8  I2SMaster;
+    u8  I2SWordLen;
+    u8  I2SChNum;
+    u8  I2SPageNum;
+    u16 I2SPageSize;
+    u16 I2SRate;
+    u32 I2STxIntrMSK;
+    u32 I2SRxIntrMSK;
+    u8  I2STRxAct;
+    u8  *I2STxData;
+    u8  *I2SRxData;
+
+    u32 Tmp;
+
+    I2SIdx         = pHalI2SInitData->I2SIdx;
+    I2SEn          = pHalI2SInitData->I2SEn;
+    I2SMaster      = pHalI2SInitData->I2SMaster;
+    I2SWordLen     = pHalI2SInitData->I2SWordLen;
+    I2SChNum       = pHalI2SInitData->I2SChNum;
+    I2SPageNum     = pHalI2SInitData->I2SPageNum;
+    I2SPageSize    = pHalI2SInitData->I2SPageSize;
+    I2SRate        = pHalI2SInitData->I2SRate;
+    I2STRxAct      = pHalI2SInitData->I2STRxAct;
+    I2STxData      = pHalI2SInitData->I2STxData;
+    I2SRxData      = pHalI2SInitData->I2SRxData;
+
+
+    /* Disable the I2S first, and reset to default */
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) | 
+                                         BIT_CTRL_CTLX_I2S_SW_RSTN(1));
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) | 
+                                         BIT_CTRL_CTLX_I2S_SW_RSTN(0));
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) | 
+                                         BIT_CTRL_CTLX_I2S_SW_RSTN(1));
+
+    Tmp = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
+    Tmp |= BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(1);
+
+    if (I2SRate&0x10) 
+    {
+        Tmp |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
+    }
+
+    Tmp |= (BIT_CTRL_CTLX_I2S_WL(I2SWordLen) | BIT_CTRL_CTLX_I2S_CH_NUM(I2SChNum) |
+            BIT_CTRL_CTLX_I2S_SLAVE_MODE(I2SMaster) | BIT_CTRL_CTLX_I2S_TRX_ACT(I2STRxAct));
+    /* set 44.1khz clock source, word length, channel number, master or slave, trx act */
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, Tmp);
+
+    Tmp = BIT_CTRL_SETTING_I2S_PAGE_SZ(I2SPageSize) | BIT_CTRL_SETTING_I2S_PAGE_NUM(I2SPageNum) |
+          BIT_CTRL_SETTING_I2S_SAMPLE_RATE(I2SRate);
+    /* set page size, page number, sample rate */
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, Tmp);
+
+    /* need tx rx buffer? need rx page own bit */
+    if (I2STxData != NULL) {
+        HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (u32)I2STxData);
+    }
+
+    if (I2SRxData != NULL) {
+        HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (u32)I2SRxData);
+    }
+
+	pHalI2SInitData->I2STxIdx = 0;
+	pHalI2SInitData->I2SRxIdx = 0;
+    pHalI2SInitData->I2SHWTxIdx = 0;
+    pHalI2SInitData->I2SHWRxIdx = 0;
+    /* I2S Clear all interrupts first */
+    HalI2SClrAllIntrRtl8195a(pHalI2SInitData);
+
+    /* I2S Disable all interrupts first */
+    I2STxIntrMSK   = pHalI2SInitData->I2STxIntrMSK;
+    I2SRxIntrMSK   = pHalI2SInitData->I2SRxIntrMSK;
+    pHalI2SInitData->I2STxIntrMSK = 0;
+    pHalI2SInitData->I2SRxIntrMSK = 0;
+    HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
+    pHalI2SInitData->I2STxIntrMSK = I2STxIntrMSK;
+    pHalI2SInitData->I2SRxIntrMSK = I2SRxIntrMSK;
+
+    return _EXIT_SUCCESS;
+}
+
+RTK_STATUS
+HalI2SSetRateRtl8195a(
+    IN  VOID    *Data
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+    u8 I2SIdx;
+    u32 reg_value;
+
+    I2SIdx = pHalI2SInitData->I2SIdx;
+
+    reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);    
+    reg_value &= ~(BIT_MASK_CTLX_I2S_CLK_SRC << BIT_SHIFT_CTLX_I2S_CLK_SRC);
+    if (pHalI2SInitData->I2SRate&0x10) 
+    {
+        reg_value |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
+    }
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
+    
+    reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
+    reg_value &= ~(BIT_MASK_SETTING_I2S_SAMPLE_RATE << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE);
+    reg_value |= BIT_CTRL_SETTING_I2S_SAMPLE_RATE(pHalI2SInitData->I2SRate);
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
+    
+    return _EXIT_SUCCESS;
+}
+
+RTK_STATUS
+HalI2SSetWordLenRtl8195a(
+    IN  VOID    *Data
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+    u8 I2SIdx;
+    u32 reg_value;
+
+    I2SIdx = pHalI2SInitData->I2SIdx;
+    reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
+    reg_value &= ~(BIT_MASK_CTLX_I2S_WL << BIT_SHIFT_CTLX_I2S_WL);
+    reg_value |= BIT_CTRL_CTLX_I2S_WL(pHalI2SInitData->I2SWordLen);
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
+
+    return _EXIT_SUCCESS;
+}
+
+RTK_STATUS
+HalI2SSetChNumRtl8195a(
+    IN  VOID    *Data
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+    u8 I2SIdx;
+    u32 reg_value;
+
+    I2SIdx = pHalI2SInitData->I2SIdx;
+    reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
+    reg_value &= ~(BIT_MASK_CTLX_I2S_CH_NUM << BIT_SHIFT_CTLX_I2S_CH_NUM);
+    reg_value |= BIT_CTRL_CTLX_I2S_CH_NUM(pHalI2SInitData->I2SChNum);
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
+
+    return _EXIT_SUCCESS;
+}
+
+RTK_STATUS
+HalI2SSetPageNumRtl8195a(
+    IN  VOID    *Data
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+    u8 I2SIdx;
+    u32 reg_value;
+
+    I2SIdx = pHalI2SInitData->I2SIdx;
+
+    reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
+    reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
+    reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
+
+    return _EXIT_SUCCESS;
+}
+
+RTK_STATUS
+HalI2SSetPageSizeRtl8195a(
+    IN  VOID    *Data
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+    u8 I2SIdx;
+    u32 reg_value;
+
+    I2SIdx = pHalI2SInitData->I2SIdx;
+
+    reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
+    reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
+    reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
+
+    return _EXIT_SUCCESS;
+}
+
+RTK_STATUS
+HalI2SSetDirectionRtl8195a(
+    IN  VOID    *Data
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+    u8 I2SIdx;
+    u32 reg_value;
+
+    I2SIdx = pHalI2SInitData->I2SIdx;
+
+    reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
+    reg_value &= ~(BIT_MASK_CTLX_I2S_TRX_ACT << BIT_SHIFT_CTLX_I2S_TRX_ACT);
+    reg_value |= BIT_CTRL_CTLX_I2S_TRX_ACT(pHalI2SInitData->I2STRxAct);
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
+
+    return _EXIT_SUCCESS;
+}
+
+RTK_STATUS
+HalI2SSetDMABufRtl8195a(
+    IN  VOID    *Data
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+    u8 I2SIdx;
+    u32 reg_value;
+    u32 page_num;
+
+    I2SIdx = pHalI2SInitData->I2SIdx;
+
+    reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
+    reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
+    reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
+    reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
+    reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
+    HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
+
+    page_num = pHalI2SInitData->I2SPageNum + 1;
+    if (pHalI2SInitData->I2STxData) {
+        HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2STxData);
+        pHalI2SInitData->I2STxIntrMSK  = (1<<page_num) - 1;
+    } else {
+        pHalI2SInitData->I2STxIntrMSK = 0;
+    }
+
+    if (pHalI2SInitData->I2SRxData) {
+        HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2SRxData);
+        pHalI2SInitData->I2SRxIntrMSK  = (1<<page_num) - 1;
+    } else {
+        pHalI2SInitData->I2SRxIntrMSK  = 0;
+        
+    }
+
+    // According to the page number to modify the ISR mask
+    HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
+
+    return _EXIT_SUCCESS;
+}
+
+u8
+HalI2SGetTxPageRtl8195a(
+    IN  VOID    *Data
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+
+    u8  I2SIdx;
+	u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
+    u32 reg;
+    
+    I2SIdx = pHalI2SInitData->I2SIdx;
+    
+	reg = HAL_I2S_READ32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(I2STxIdx<<2));
+    if ((reg & (1<<31)) == 0) {
+        return I2STxIdx;
+    } else {
+        return 0xFF;
+    }
+}
+
+u8
+HalI2SGetRxPageRtl8195a(
+    IN  VOID    *Data
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+
+    u8  I2SIdx;
+	u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
+    u32 reg;
+    
+    I2SIdx = pHalI2SInitData->I2SIdx;
+    
+	reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
+    if ((reg & (1<<31)) == 0) {
+        return I2SRxIdx;
+    } else {
+        return 0xFF;
+    }
+}
+
+RTK_STATUS
+HalI2SPageSendRtl8195a(
+    IN  VOID    *Data,
+	IN  u8      PageIdx
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+	u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
+	u8  I2SPageNum = pHalI2SInitData->I2SPageNum;
+    u8  I2SIdx;
+
+    if (I2STxIdx != PageIdx) {
+        DBG_I2S_ERR("HalI2SPageSendRtl8195a: UnExpected Page Index. TxPage=%d, Expected:%d\r\n", 
+            PageIdx, I2STxIdx);
+    }
+    
+    I2SIdx = pHalI2SInitData->I2SIdx;
+    
+	HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+4*PageIdx, 1<<31);
+    I2STxIdx = PageIdx+1;
+    if (I2STxIdx > I2SPageNum) {
+        I2STxIdx = 0;
+    }
+    pHalI2SInitData->I2STxIdx = I2STxIdx;
+
+    return _EXIT_SUCCESS;
+}
+
+RTK_STATUS
+HalI2SPageRecvRtl8195a(
+    IN  VOID    *Data
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+	u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
+	u8  I2SPageNum = pHalI2SInitData->I2SPageNum;
+    u32 reg;
+    u8  I2SIdx;
+
+    I2SIdx = pHalI2SInitData->I2SIdx;
+	reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
+    if ((reg & (1<<31)) != 0) {
+        DBG_I2S_ERR("HalI2SPageRecvRtl8195a: No Idle Rx Page\r\n");
+        return _EXIT_FAILURE;
+    }
+
+	HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx<<2), 1<<31);
+    I2SRxIdx += 1;
+    if (I2SRxIdx > I2SPageNum) {
+        I2SRxIdx = 0;
+    }
+    pHalI2SInitData->I2SRxIdx = I2SRxIdx;
+
+    return _EXIT_SUCCESS;
+}
+
+RTK_STATUS
+HalI2SClearAllOwnBitRtl8195a(
+    IN  VOID    *Data
+)
+{
+    PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
+    u8  I2SIdx;
+    u32 i;
+    
+    I2SIdx = pHalI2SInitData->I2SIdx;
+
+    for (i=0;i<4;i++) {
+        HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(i<<2), 0);
+        HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(i<<2), 0);
+    }    
+	return _EXIT_SUCCESS;
+}
+
+RTK_STATUS
+HalI2SDMACtrlRtl8195a(
+    IN  VOID    *Data
+)
+{
+
+    return _EXIT_SUCCESS;
+}
+
+

component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_mii.c

@@ -0,0 +1,411 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+#include "rtl8195a_mii.h"
+#include "hal_mii.h"
+
+
+
+VOID MiiIrqHandle (IN VOID *Data);
+
+VOID MiiIrqHandle (IN VOID *Data) {
+    PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
+    PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
+    u32 RegValue = HalMiiGmacGetInterruptStatusRtl8195a();
+#ifdef CONFIG_MII_VERIFY
+	extern u8 isRxOK;
+	extern u8 isTxOK;
+	extern u8 RxIntCnt;
+	
+
+//	DBG_8195A("ISR = 0x%08X\n", RegValue);
+	if(RegValue & GMAC_ISR_ROK) {
+		HalMiiGmacClearInterruptStatusRtl8195a(0x00410001);
+		isRxOK = 1;
+		RxIntCnt++;
+	}
+
+	if(RegValue & GMAC_ISR_TOK_TI) {
+		HalMiiGmacClearInterruptStatusRtl8195a(0x00410040);
+		isTxOK = 1;
+    }
+#else
+
+#endif
+}
+
+
+VOID
+ConfigDebugPort_E4(u32 DebugSelect) {
+    u32 RegValue;
+    BOOL DebugMsg = _FALSE;
+
+    if (DebugMsg) {
+        LOGI(ANSI_COLOR_YELLOW"Debug Port Select (0xE4)\n"ANSI_COLOR_RESET);
+        LOGD2("[P] PERI_ON_010: %X\n", HAL_READ32(PERI_ON_BASE, REG_SOC_FUNC_EN));
+        LOGD2("[P] PERI_ON_014: %X\n", HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN));
+    }
+
+    RegValue = HAL_MII_READ32(REG_RTL_MII_CCR);
+    if (DebugMsg) {
+        LOGD2("[B] 0x00E4: %X\n", RegValue);
+    }
+
+    RegValue |= DebugSelect << 2;
+    if (DebugMsg) {
+        LOGD2("[B] RegValue: %X\n", RegValue);
+    }
+
+    HAL_MII_WRITE32(REG_RTL_MII_CCR, RegValue);
+    if (DebugMsg) {
+        LOGD2("[A] 0x00E4: %X\n", HAL_MII_READ32(REG_RTL_MII_CCR));
+    }
+}
+
+
+/**
+ * MII Initialize.
+ *
+ * MII Initialize.
+ *
+ * Initialization Steps:
+ *   I. Rtl8195A Board Configurations:
+ *     1. MII Function Enable & AHB mux
+ *
+ * @return runtime status value.
+ */
+BOOL
+HalMiiGmacInitRtl8195a(
+        IN VOID *Data
+        )
+{
+	PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
+	PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
+	u32 RegValue;
+
+
+	/* 1. enable MII Pinmux & disable SDIO Host/Device mode Pinmux */
+	RegValue = HAL_READ32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL);
+	RegValue |= BIT24;
+	RegValue &= ~(BIT0 | BIT1); // Important!
+	HAL_WRITE32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL, RegValue);
+
+	/* 2. enable MII IP block (214, 12) */
+	RegValue = HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN);
+	RegValue |= BIT12;
+	HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, RegValue);
+
+	/* 3. Lexra2AHB Function Enable (304, 11) */
+	RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL);
+	RegValue |= BIT11;
+	HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue);
+
+	/* 4. enable MII bus clock (240, 24|25) */
+	RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0);
+	RegValue |= (BIT24 | BIT25);
+	HAL_WRITE32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0, RegValue);
+
+	/* 5. */
+	RegValue = HAL_READ32(SYSTEM_CTRL_BASE, 0x74) & 0xFFFFC7FF;
+	HAL_WRITE32(SYSTEM_CTRL_BASE, 0x74, (RegValue | 0x00003000));
+
+	/* 6. AHB mux: select MII (214, 13) */
+    	RegValue = HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN);
+	RegValue |= BIT13;
+	HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, RegValue);
+
+	/* 7. Vendor Register Clock Enable (230, 6|7) */
+	RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_CTRL);
+	RegValue |= (BIT6 | BIT7);
+	HAL_WRITE32(PERI_ON_BASE, REG_PESOC_CLK_CTRL, RegValue);
+
+	/* 8. Enable GMAC Lexra Timeout (090, 16|17|18) */
+	RegValue = HAL_READ32(VENDOR_REG_BASE, 0x0090);
+	RegValue |= (BIT16 | BIT17 | BIT18);
+	HAL_WRITE32(VENDOR_REG_BASE, 0x0090, RegValue);
+
+	/* 9. Endian Swap Control (304, 12|13) */
+	RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL);
+	RegValue |= (BIT12 | BIT13);
+	HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue);
+
+	return _TRUE;
+}
+
+
+BOOL
+HalMiiInitRtl8195a(
+        IN VOID *Data
+        )
+{
+    DBG_ENTRANCE;
+    PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
+    PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
+    u32 RegValue;
+
+    return _TRUE;
+}
+
+
+BOOL
+HalMiiGmacResetRtl8195a(
+        IN VOID *Data
+        )
+{
+	HAL_MII_WRITE32(REG_RTL_MII_CR, (HAL_MII_READ32(REG_RTL_MII_CR) | BIT0));
+
+    return _TRUE;
+}
+
+
+BOOL
+HalMiiGmacEnablePhyModeRtl8195a(
+        IN VOID *Data
+        )
+{
+    return _TRUE;
+}
+
+
+u32
+HalMiiGmacXmitRtl8195a(
+        IN VOID *Data
+        )
+{
+    return 0;
+}
+
+
+VOID
+HalMiiGmacCleanTxRingRtl8195a(
+        IN VOID *Data
+        )
+{
+}
+
+
+VOID
+HalMiiGmacFillTxInfoRtl8195a(
+        IN VOID *Data
+        )
+{
+    DBG_ENTRANCE;
+    PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
+    PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
+    PTX_INFO pTx_Info = pMiiAdapter->pTx_Info;
+    VOID* TxBuffer  = pMiiAdapter->TxBuffer;
+    u32 RegValue;
+
+    LOGI(ANSI_COLOR_GREEN"==[ Tx Descriptor Configuration ]======\n"ANSI_COLOR_RESET);
+
+    pTx_Info->opts1.dw = 0xBC8001FE;
+    /* pTx_Info->opts1.dw = 0xBC800080; // size: 128 */
+
+    pTx_Info->addr     = (u32)TxBuffer;
+    pTx_Info->opts2.dw = 0x0400279F;
+    pTx_Info->opts3.dw = 0x00000000;
+    /* pTx_Info->opts4.dw = 0x57800000; */
+    pTx_Info->opts4.dw = 0x1FE00000;
+    LOGI("pTx_Info->addr: %X\n", pTx_Info->addr);
+
+    LOGI(ANSI_COLOR_YELLOW"TxFDP1 Register(0x%04X) (W: 0x%X)\n"ANSI_COLOR_RESET, REG_RTL_MII_TXFDP1, pTx_Info);
+    RegValue = HAL_MII_READ32(REG_RTL_MII_TXFDP1);
+    LOGD2("[B] REG_RTL_MII_TXFDP1: %X\n", RegValue);
+    HAL_MII_WRITE32(REG_RTL_MII_TXFDP1, pTx_Info);
+    LOGD2("[A] REG_RTL_MII_TXFDP1: %X\n", HAL_MII_READ32(REG_RTL_MII_TXFDP1));
+}
+
+
+VOID
+HalMiiGmacFillRxInfoRtl8195a(
+        IN VOID *Data
+        )
+{
+    DBG_ENTRANCE;
+    PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
+    PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
+    PRX_INFO pRx_Info = pMiiAdapter->pRx_Info;
+    VOID* RxBuffer    = pMiiAdapter->RxBuffer;
+    u32 RegValue;
+
+    LOGI(ANSI_COLOR_GREEN"==[ Rx Descriptor Configuration ]======\n"ANSI_COLOR_RESET);
+
+    /* pRx_Info->opts1.dw = 0x80000200; //Data Length: 4095(FFF), 512(200) */
+    pRx_Info->opts1.dw = 0x800001FC; //Data Length: 4095(FFF), 512(200)
+    /* pRx_Info->opts1.dw = 0x8000007F; */
+
+    pRx_Info->addr     = (u32)RxBuffer;
+    pRx_Info->opts2.dw = 0x00000000;
+    pRx_Info->opts3.dw = 0x00000000;
+
+    LOGI(ANSI_COLOR_YELLOW"RxFDP1 Register(0x%04X) (W: 0x%X)\n"ANSI_COLOR_RESET, REG_RTL_MII_RXFDP1, pRx_Info);
+    RegValue = HAL_MII_READ32(REG_RTL_MII_RXFDP1);
+    LOGD2("[B] REG_RTL_MII_RXFDP1: %X\n", RegValue);
+    HAL_MII_WRITE32(REG_RTL_MII_RXFDP1, pRx_Info);
+    LOGD2("[A] REG_RTL_MII_RXFDP1: %X\n", HAL_MII_READ32(REG_RTL_MII_RXFDP1));
+}
+
+
+VOID
+HalMiiGmacTxRtl8195a(
+        IN VOID *Data
+        )
+{
+    DBG_ENTRANCE;
+    PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
+    PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
+    PTX_INFO pTx_Info = pMiiAdapter->pTx_Info;
+    u32 RegValue;
+
+    LOGI(ANSI_COLOR_GREEN"==[ Tx ]===============================\n"ANSI_COLOR_RESET);
+
+    LOGI(ANSI_COLOR_YELLOW"REG_RTL_MII_IOCMD Register(0x%04X): Enable Tx (W: 0x10, BIT4)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD);
+    RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
+    LOGD2("[B] REG_RTL_MII_IOCMD: %X\n", RegValue);
+    RegValue |= BIT_IOCMD_TXENABLE(1);
+    HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue);
+    LOGD2("[A] REG_RTL_MII_IOCMD: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD));
+    LOGD4("--> Tx Descriptor opts1: %X\n", HAL_READ32(pTx_Info, 0));
+
+    LOGI(ANSI_COLOR_YELLOW"REG_RTL_MII_IOCMD Register(0x%04X): Enable 1st Tx (W: 0x1, BIT0)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD);
+    RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
+    LOGD2("[B] REG_RTL_MII_IOCMD: %X\n", RegValue);
+    RegValue |= BIT_IOCMD_FIRST_DMATX_ENABLE(1);
+    HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue);
+    LOGD2("[A] REG_RTL_MII_IOCMD: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD));
+    LOGD4("--> Tx Descriptor opts1: %X\n", HAL_READ32(pTx_Info, 0));
+}
+
+
+VOID
+HalMiiGmacRxRtl8195a(
+        IN VOID *Data
+        )
+{
+    DBG_ENTRANCE;
+    PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
+    PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
+    u32 RegValue;
+
+    LOGI(ANSI_COLOR_GREEN"==[ Rx ]===============================\n"ANSI_COLOR_RESET);
+    LOGI(ANSI_COLOR_YELLOW"Transmit (Tx) Configuration Register (0x%04X) (W: 0x00000C00)\n"ANSI_COLOR_RESET, REG_RTL_MII_TCR);
+    RegValue = HAL_MII_READ32(REG_RTL_MII_TCR);
+    LOGD2("[B] REG_RTL_MII_TCR: %X\n", RegValue);
+
+    HAL_MII_WRITE32(REG_RTL_MII_TCR, 0x00000D00);  // loopback R2T mode
+    LOGD2("[A] REG_RTL_MII_TCR: %X\n", HAL_MII_READ32(REG_RTL_MII_TCR));
+
+    LOGI(ANSI_COLOR_YELLOW"Receive (Rx) Configuration Register (0x%04X) (W: 0x0000007F)\n"ANSI_COLOR_RESET, REG_RTL_MII_RCR);
+    RegValue = HAL_MII_READ32(REG_RTL_MII_RCR);
+    LOGD2("[B] REG_RTL_MII_RCR: %X\n", RegValue);
+    HAL_MII_WRITE32(REG_RTL_MII_RCR, 0x0000007F);
+    LOGD2("[A] REG_RTL_MII_RCR: %X\n", HAL_MII_READ32(REG_RTL_MII_RCR));
+
+    LOGI(ANSI_COLOR_YELLOW"EhtrntRxCPU_Des_Num1 (0x%04X) (W: 0x1F0A0F00)\n"ANSI_COLOR_RESET, REG_RTL_MII_ETNRXCPU1);
+    RegValue = HAL_MII_READ32(REG_RTL_MII_ETNRXCPU1);
+    LOGD2("[B] REG_RTL_MII_ETNRXCPU1: %X\n", RegValue);
+    HAL_MII_WRITE32(REG_RTL_MII_ETNRXCPU1, 0x1F0A0F00);
+    LOGD2("[A] REG_RTL_MII_ETNRXCPU1: %X\n", HAL_MII_READ32(REG_RTL_MII_ETNRXCPU1));
+
+    LOGI(ANSI_COLOR_YELLOW"Rx_Pse_Des_Thres_1_h (0x%04X) (W: 0x00000022)\n"ANSI_COLOR_RESET, REG_RTL_MII_RX_PSE1);
+    RegValue = HAL_MII_READ32(REG_RTL_MII_RX_PSE1);
+    LOGD2("[B] REG_RTL_MII_RX_PSE1: %X\n", RegValue);
+    HAL_MII_WRITE32(REG_RTL_MII_RX_PSE1, 0x00000022);
+    LOGD2("[A] REG_RTL_MII_RX_PSE1: %X\n", HAL_MII_READ32(REG_RTL_MII_RX_PSE1));
+
+    LOGI(ANSI_COLOR_YELLOW"Ethernet_IO_CMD1 Register(0x%04X): Enable Rx Ring1 (W: 0x10000, BIT16)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD1);
+    RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1);
+    LOGD2("[B] REG_RTL_MII_IOCMD1: %X\n", RegValue);
+    RegValue |= BIT_IOCMD1_FIRST_DMARX_ENABLE(1);
+    HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, RegValue);
+    LOGD2("[A] REG_RTL_MII_IOCMD1: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD1));
+
+    LOGI(ANSI_COLOR_YELLOW"REG_RTL_MII_IOCMD Register(0x%04X): Enable Rx (W: 0x20, BIT5)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD);
+    RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
+    LOGD2("[B] REG_RTL_MII_IOCMD: %X\n", RegValue);
+    RegValue |= BIT_IOCMD_RXENABLE(1);
+    HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue);
+    LOGD2("[A] REG_RTL_MII_IOCMD: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD));
+}
+
+
+VOID
+HalMiiGmacSetDefaultEthIoCmdRtl8195a(
+        IN VOID *Data
+        )
+{
+    DBG_ENTRANCE;
+    PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
+    PHAL_MII_ADAPTER pHalMiiAdapter = pMiiAdapter->pHalMiiAdapter;
+    u32 RegValue;
+
+    LOGI(ANSI_COLOR_YELLOW"REG_RTL_MII_IOCMD Register(0x%04X) (W: CMD_CONFIG)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD);
+    RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
+    LOGD2("[B] REG_RTL_MII_IOCMD: %X\n", RegValue);
+    HAL_MII_WRITE32(REG_RTL_MII_IOCMD, CMD_CONFIG);
+    LOGD2("[A] REG_RTL_MII_IOCMD: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD));
+
+    LOGI(ANSI_COLOR_YELLOW"Ethernet_IO_CMD1 Register(0x%04X) (W: CMD1_CONFIG)\n"ANSI_COLOR_RESET, REG_RTL_MII_IOCMD1);
+    RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1);
+    LOGD2("[B] REG_RTL_MII_IOCMD1: %X\n", RegValue);
+    HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, CMD1_CONFIG);
+    LOGD2("[A] REG_RTL_MII_IOCMD1: %X\n", HAL_MII_READ32(REG_RTL_MII_IOCMD1));
+
+    //2014-04-29 yclin (disable 0x40051438[27] r_en_precise_dma) {
+    RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1);
+    RegValue = RegValue & 0xF7FFFFFF;
+    HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, RegValue);
+    // }
+}
+
+
+VOID
+HalMiiGmacInitIrqRtl8195a(
+		IN VOID *Data
+		)
+{
+	IRQ_HANDLE	MiiIrqHandle_Master;
+	PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
+
+
+	MiiIrqHandle_Master.Data	 = (u32) (pMiiAdapter);
+	MiiIrqHandle_Master.IrqNum	 = GMAC_IRQ;
+	MiiIrqHandle_Master.IrqFun	 = (IRQ_FUN) MiiIrqHandle;
+	MiiIrqHandle_Master.Priority = 0;
+	InterruptRegister(&MiiIrqHandle_Master);
+	InterruptEn(&MiiIrqHandle_Master);
+}
+
+
+u32
+HalMiiGmacGetInterruptStatusRtl8195a(
+        VOID
+        )
+{
+    DBG_ENTRANCE;
+    u32 RegValue;
+
+    RegValue = HAL_MII_READ32(REG_RTL_MII_IMRISR);
+    LOGD("REG_RTL_MII_IMRISR: %X\n", RegValue);
+    return RegValue;
+}
+
+
+VOID
+HalMiiGmacClearInterruptStatusRtl8195a(
+        u32 IsrStatus
+        )
+{
+    DBG_ENTRANCE;
+    HAL_MII_WRITE32(REG_RTL_MII_IMRISR, IsrStatus);
+}
+
+

component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c

@@ -0,0 +1,360 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "platform_autoconf.h" 
+#include "diag.h"
+#include "rtl8195a_pcm.h"
+#include "hal_pcm.h"
+
+extern void *
+_memset( void *s, int c, SIZE_T n );
+
+VOID
+HalPcmOnOffRtl8195a (
+    IN  VOID              *Data
+)
+{
+    PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
+    //todo on off pcm
+
+}
+
+//default sampling rate 8khz, linear,  10ms frame size, time slot 0 , tx+rx
+//          master mode, enable endian swap
+// Question: need local tx/rx page?
+BOOL
+HalPcmInitRtl8195a(
+    IN  VOID     *Data
+)
+{
+
+    PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
+    _memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER));
+
+    //4 1) Initial PcmChCNR03 Register
+    pHalPcmAdapter->PcmChCNR03.CH0MuA      = 0;
+    pHalPcmAdapter->PcmChCNR03.CH0Band     = 0;
+
+
+    //4 1) Initial PcmTSR03 Register
+    pHalPcmAdapter->PcmTSR03.CH0TSA      = 0; 
+
+    //4 1) Initial PcmBSize03 Register
+    pHalPcmAdapter->PcmBSize03.CH0BSize    = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte
+
+
+    //4 2) Initial Ctl Register
+
+    pHalPcmAdapter->PcmCtl.Pcm_En      = 1;
+    pHalPcmAdapter->PcmCtl.SlaveMode   = 0;
+    pHalPcmAdapter->PcmCtl.FsInv       = 0;
+    pHalPcmAdapter->PcmCtl.LinearMode  = 0;
+    pHalPcmAdapter->PcmCtl.LoopBack    = 0;
+    pHalPcmAdapter->PcmCtl.EndianSwap  = 1;
+
+    return _TRUE;        
+}
+
+
+BOOL
+HalPcmSettingRtl8195a(
+    IN  VOID     *Data
+)
+{
+
+    PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
+    u8  PcmIndex = pHalPcmAdapter->PcmIndex;
+    u8  PcmCh = pHalPcmAdapter->PcmCh;
+    u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03;
+    u32 Isr03;
+    
+    PcmCh=0;
+    //4 1) Check Pcm index is avaliable
+    if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) {
+        //4 Pcm index is running, stop first
+        DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
+
+        return _FALSE;
+    }
+
+    //4 2) Check if there are the pending isr
+
+
+        Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03);
+	Isr03 &= 0xff000000;
+            //4 Clear Pending Isr
+        HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03);
+        //} 
+
+
+    //4 3) Process RegCtl 
+    RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL);
+
+        //4 Clear Ctl register bits
+    RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL &
+                BIT_INV_CTLX_FSINV &
+                BIT_INV_CTLX_PCM_EN &
+                BIT_INV_CTLX_LINEARMODE &
+                BIT_INV_CTLX_LOOP_BACK &
+                BIT_INV_CTLX_ENDIAN_SWAP);
+
+    RegCtl =  BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) |
+              BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) |
+              BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) |
+              BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) |
+              BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) |
+              BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) |
+              RegCtl; 
+
+    HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl);
+        //4 4) Program ChCNR03 Register
+        
+        RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
+
+        RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE &
+                    BIT_INV_CHCNR03_CH0TE &
+                    BIT_INV_CHCNR03_CH0MUA &
+                    BIT_INV_CHCNR03_CH0BAND);
+
+        RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) |
+                     BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) |
+                     BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) |
+                     BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) |
+                     RegChCNR03;
+        
+        DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03);
+
+        HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03);
+        // time slot
+        RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03);
+
+        RegTSR03 &= (BIT_INV_TSR03_CH0TSA);
+        RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) |
+                     RegTSR03;
+        
+        DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03);
+
+        HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03);
+
+        // buffer size
+        RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03);
+
+        RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE);
+        RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) |
+                     RegBSize03;
+        
+        DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03);
+
+        HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03);
+
+
+
+
+    return _TRUE;
+}
+
+BOOL
+HalPcmEnRtl8195a(
+    IN  VOID     *Data
+)
+{
+
+    PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
+    u8  PcmIndex = pHalPcmAdapter->PcmIndex;
+    u8  PcmCh = pHalPcmAdapter->PcmCh;
+    u32 RegChCNR03;
+
+    PcmCh=0;
+    pHalPcmAdapter->Enable = 1;
+
+
+    //4 1) Check Pcm index is avaliable
+    RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
+    if (RegChCNR03 & (BIT24|BIT25)) {
+        //4 Pcm index is running, stop first
+        DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
+
+        return _FALSE;
+    }
+
+    HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25);
+    pHalPcmAdapter->PcmChCNR03.CH0RE = 1;
+    pHalPcmAdapter->PcmChCNR03.CH0TE = 1;
+
+    return _TRUE;
+}
+
+BOOL
+HalPcmDisRtl8195a(
+    IN  VOID     *Data
+)
+{
+
+    PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
+    u8  PcmIndex = pHalPcmAdapter->PcmIndex;
+    u8  PcmCh = pHalPcmAdapter->PcmCh;
+    u32 RegChCNR03;
+
+    PcmCh=0;
+    pHalPcmAdapter->Enable = 0;
+
+
+    RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
+
+    HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25)));
+    pHalPcmAdapter->PcmChCNR03.CH0RE = 0;
+    pHalPcmAdapter->PcmChCNR03.CH0TE = 0;
+
+    return _TRUE;
+}
+
+
+
+BOOL
+HalPcmIsrEnAndDisRtl8195a (
+    IN  VOID              *Data
+)
+{
+/*
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
+    u32 IsrMask, Addr, IsrCtrl;
+    u8  IsrTypeIndex = 0;
+
+    for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
+        
+        if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
+            Addr =  (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8);
+
+            IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr);
+
+            IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask):
+                                                 ((~pHalGdmaAdapter->ChEn) & IsrMask));
+
+            HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
+                              Addr, 
+                              IsrCtrl
+                              );
+                    
+        }   
+    }
+*/
+    return _TRUE;
+}
+
+
+
+BOOL
+HalPcmDumpRegRtl8195a (
+    IN  VOID              *Data
+)
+{
+/*    
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
+    HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex, 
+                      REG_GDMA_CH_EN, 
+                      (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)| 
+                        (pHalGdmaAdapter->ChEn))
+                      );    
+*/
+    return _TRUE;    
+}
+
+BOOL
+HalPcmRtl8195a (
+    IN  VOID              *Data
+)
+{
+/*    PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
+    HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex, 
+                      REG_GDMA_CH_EN, 
+                      (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)& 
+                        ~(pHalGdmaAdapter->ChEn))
+                      );    
+*/		      
+    return _TRUE;		      
+}
+/*
+u8
+HalGdmaChIsrCleanRtl8195a (
+    IN  VOID              *Data
+)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
+    u32 IsrStatus;
+    u8  IsrTypeIndex = 0, IsrActBitMap = 0;
+
+    for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
+
+        IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, 
+                                    (REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8));
+
+//        DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus);
+
+        IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF));
+        
+        if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
+            HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
+                              (REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)), 
+                              (IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF))
+                              );
+            IsrActBitMap |= BIT_(IsrTypeIndex);
+            
+        }
+        
+    }
+    return IsrActBitMap;
+     
+}
+
+
+VOID
+HalGdmaChCleanAutoSrcRtl8195a (
+    IN  VOID              *Data
+) 
+{
+    u32 CfgxLow;
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
+    CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
+                              (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
+
+    CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC;
+
+    HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
+                  (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF), 
+                  CfgxLow
+                  );
+    
+    DBG_8195A_DMA("CFG Low data:0x%x\n",
+    HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
+}
+
+VOID
+HalGdmaChCleanAutoDstRtl8195a (
+    IN  VOID              *Data
+) 
+{
+    u32 CfgxLow;
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
+    CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
+                              (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
+
+    CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST;
+
+    HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
+                  (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF), 
+                  CfgxLow
+                  );
+    DBG_8195A_DMA("CFG Low data:0x%x\n",
+    HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
+        
+}
+*/
+
+

component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pwm.c

@@ -0,0 +1,219 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+#include "hal_peri_on.h"
+
+#ifdef CONFIG_PWM_EN
+#include "rtl8195a_pwm.h"
+#include "hal_pwm.h"
+
+extern HAL_PWM_ADAPTER PWMPin[];
+
+extern HAL_TIMER_OP HalTimerOp;
+
+/**
+  * @brief  Configure a G-Timer to generate a tick with certain time.
+  *
+  * @param  pwm_id: the PWM pin index
+  * @param  tick_time: the time (micro-second) of a tick
+  *
+  * @retval None
+  */
+void 
+Pwm_SetTimerTick_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt,
+    u32 tick_time
+)
+{
+    TIMER_ADAPTER TimerAdapter;
+
+
+    if (tick_time <= MIN_GTIMER_TIMEOUT) {
+        tick_time = MIN_GTIMER_TIMEOUT;
+    }
+    else {
+        tick_time = (((tick_time-1)/TIMER_TICK_US)+1) * TIMER_TICK_US;
+    }
+    
+    // Initial a G-Timer for the PWM pin
+    if (pPwmAdapt->tick_time != tick_time) {
+        TimerAdapter.IrqDis = 1;    // Disable Irq
+        TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) NULL;
+        TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ;
+        TimerAdapter.IrqHandle.Priority = 0;
+        TimerAdapter.IrqHandle.Data = (u32)NULL;
+        TimerAdapter.TimerId = pPwmAdapt->gtimer_id;
+        TimerAdapter.TimerIrqPriority = 0;
+        TimerAdapter.TimerLoadValueUs = tick_time-1;
+        TimerAdapter.TimerMode = 1; // auto-reload with user defined value
+
+        HalTimerOp.HalTimerInit((VOID*) &TimerAdapter);
+        pPwmAdapt->tick_time = tick_time;
+        DBG_PWM_INFO("%s: Timer_Id=%d Count=%d\n", __FUNCTION__, pPwmAdapt->gtimer_id, tick_time);
+     }
+
+}
+
+
+/**
+  * @brief  Set the duty ratio of the PWM pin.
+  *
+  * @param  pwm_id: the PWM pin index
+  * @param  period: the period time, in micro-second.
+  * @param  pulse_width: the pulse width time, in micro-second.
+  *
+  * @retval None
+  */
+void
+HAL_Pwm_SetDuty_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt,
+    u32 period,
+    u32 pulse_width
+)
+{
+    u32 RegAddr;
+    u32 RegValue;
+    u32 period_tick;
+    u32 pulsewidth_tick;
+    u32 tick_time;
+    u8 timer_id;
+    u8 pwm_id;
+
+    pwm_id = pPwmAdapt->pwm_id;
+    // Adjust the tick time to a proper value
+    if (period < (MIN_GTIMER_TIMEOUT*2)) {
+        DBG_PWM_ERR ("HAL_Pwm_SetDuty_8195a: Invalid PWM period(%d), too short!!\n", period);
+        tick_time = MIN_GTIMER_TIMEOUT;
+        period = MIN_GTIMER_TIMEOUT*2;
+    }
+    else {
+        tick_time = period / 0x3fc;
+        if (tick_time < MIN_GTIMER_TIMEOUT) {
+            tick_time = MIN_GTIMER_TIMEOUT;
+        }
+    }
+
+    Pwm_SetTimerTick_8195a(pPwmAdapt, tick_time);
+    tick_time = pPwmAdapt->tick_time;
+#if 0    
+    // Check if current tick time needs adjustment
+    if ((pPwmAdapt->tick_time << 12) <= period) {
+        // need a longger tick time
+    }
+    else if ((pPwmAdapt->tick_time >> 2) >= period) {
+        // need a shorter tick time
+    }
+#endif
+    period_tick = period/tick_time;
+    if (period_tick == 0) {
+        period_tick = 1;
+    }
+
+    if (pulse_width >= period) {
+//        pulse_width = period-1;
+        pulse_width = period;
+    }
+    pulsewidth_tick = pulse_width/tick_time;
+    if (pulsewidth_tick == 0) {
+//        pulsewidth_tick = 1;
+    }
+    
+    timer_id = pPwmAdapt->gtimer_id;
+
+    pPwmAdapt->period = period_tick & 0x3ff;
+    pPwmAdapt->pulsewidth = pulsewidth_tick & 0x3ff;
+    
+    RegAddr = REG_PERI_PWM0_CTRL + (pwm_id*4);
+    RegValue = BIT31 | (timer_id<<24) | (pulsewidth_tick<<12) | period_tick;
+    
+    HAL_WRITE32(PERI_ON_BASE, RegAddr, RegValue);
+}
+
+/**
+  * @brief  Initializes and enable a PWM control pin.
+  *
+  * @param  pwm_id: the PWM pin index
+  * @param  sel: pin mux selection
+  * @param  timer_id: the G-timer index assigned to this PWM
+  *
+  * @retval HAL_Status
+  */
+HAL_Status 
+HAL_Pwm_Init_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt
+)
+{
+    u32 pwm_id;
+    u32 pin_sel;
+
+    pwm_id = pPwmAdapt->pwm_id;
+    pin_sel =  pPwmAdapt->sel;
+    // Initial a G-Timer for the PWM pin
+    Pwm_SetTimerTick_8195a(pPwmAdapt, MIN_GTIMER_TIMEOUT);
+
+    // Set default duty ration
+    HAL_Pwm_SetDuty_8195a(pPwmAdapt, 20000, 10000);
+
+    // Configure the Pin Mux
+    PinCtrl((PWM0+pwm_id), pin_sel, 1);
+
+    return HAL_OK;
+}
+
+
+/**
+  * @brief  Enable a PWM control pin.
+  *
+  * @param  pwm_id: the PWM pin index
+  *
+  * @retval None
+  */
+void 
+HAL_Pwm_Enable_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt
+)
+{
+    u32 pwm_id;
+    
+    pwm_id = pPwmAdapt->pwm_id;
+    // Configure the Pin Mux
+    if (!pPwmAdapt->enable) {
+        PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 1);
+        HalTimerOp.HalTimerEn(pPwmAdapt->gtimer_id);        
+        pPwmAdapt->enable = 1;
+    }
+}
+
+
+/**
+  * @brief  Disable a PWM control pin.
+  *
+  * @param  pwm_id: the PWM pin index
+  *
+  * @retval None
+  */
+void 
+HAL_Pwm_Disable_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt
+)
+{
+    u32 pwm_id;
+    
+    pwm_id = pPwmAdapt->pwm_id;
+    // Configure the Pin Mux
+    if (pPwmAdapt->enable) {
+        PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 0);
+        HalTimerOp.HalTimerDis(pPwmAdapt->gtimer_id);        
+        pPwmAdapt->enable = 0;
+    }
+}
+
+#endif  //CONFIG_PWM_EN

component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_timer.c

@@ -0,0 +1,317 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+#include "rtl8195a.h" 
+#include "rtl8195a_timer.h"
+
+extern u32 gTimerRecord;
+extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM];
+
+#ifdef CONFIG_CHIP_C_CUT
+extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
+#else
+u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
+#endif
+
+VOID
+HalTimerIrq2To7Handle_Patch(
+    IN  VOID    *Data
+)
+{
+    u32 TimerIrqStatus = 0, CheckIndex;
+    IRQ_FUN pHandler;
+
+    TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF);
+
+    DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus);
+    
+    for (CheckIndex = 2; CheckIndex<8; CheckIndex++) {
+
+        //3 Check IRQ status bit and Timer X IRQ enable bit
+        if ((TimerIrqStatus & BIT_(CheckIndex)) && 
+            (HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) {
+            //3 Execute Timer callback function
+            pHandler = Timer2To7VectorTable[CheckIndex-2];
+            if (pHandler != NULL) {
+                pHandler((void*)Timer2To7HandlerData[CheckIndex-2]);
+            }
+            //3 Clear Timer ISR
+            HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF);
+        }
+    }
+}
+
+HAL_Status
+HalTimerIrqRegisterRtl8195a_Patch(
+    IN  VOID    *Data
+)
+{
+    PTIMER_ADAPTER      pHalTimerAdap = (PTIMER_ADAPTER) Data;
+    IRQ_HANDLE          TimerIrqHandle;
+    IRQ_FUN             BackUpIrqFun = NULL;
+    
+    if (pHalTimerAdap->TimerId > 7) {
+        DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
+        return HAL_ERR_PARA;
+    }
+    else {
+        if (pHalTimerAdap->TimerId > 1) {
+
+            TimerIrqHandle.IrqNum = TIMER2_7_IRQ;
+            TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch;
+
+            Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = 
+                (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
+            Timer2To7HandlerData[pHalTimerAdap->TimerId-2] = 
+                (uint32_t) pHalTimerAdap->IrqHandle.Data;
+        }
+        else {
+            TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
+            TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
+        }
+        TimerIrqHandle.Data = (u32)pHalTimerAdap;
+        InterruptRegister(&TimerIrqHandle);
+    }
+    
+    return HAL_OK;
+}
+
+HAL_Status
+HalTimerInitRtl8195a_Patch(
+    IN  VOID    *Data
+)
+{
+    PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
+    HAL_Status ret=HAL_OK;
+    u32 ControlReg = 0, LoadCount = 0;
+    u32 LoadUsX4;
+
+    if ((gTimerRecord & (1<<pHalTimerAdap->TimerId)) != 0) {
+        DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
+        return HAL_BUSY;
+    }
+
+    ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2);
+
+    if (pHalTimerAdap->TimerMode) {
+        //User-defined Mode
+        LoadUsX4 = pHalTimerAdap->TimerLoadValueUs << 2;
+        if (LoadUsX4 < TIMER_TICK_US_X4) {
+            DBG_TIMER_WARN("%s : Timer Load Count = 1!\r\n", __FUNCTION__);
+            LoadCount = 1;
+        }
+        else {
+            LoadCount = (LoadUsX4-(TIMER_TICK_US_X4>>1))/TIMER_TICK_US_X4;  // to get the most closed integer
+            if (LoadCount == 0) {
+                LoadCount = 1;
+            }
+        }
+    } 
+    else {
+        LoadCount = 0xFFFFFFFF;
+    }
+
+    
+    //4 1) Config Timer Setting
+    /*
+        set TimerControlReg
+        0: Timer enable (0,disable; 1,enable)
+        1: Timer Mode (0, free-running mode; 1, user-defined count mode)
+        2: Timer Interrupt Mask (0, not masked; 1,masked)
+        */
+    HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF), 
+                        ControlReg);
+
+    // set TimerLoadCount Register
+    HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF),
+                        LoadCount);
+
+    //4  2) Setting Timer IRQ
+    if (!pHalTimerAdap->IrqDis) {
+        if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
+            //4 2.1) Initial TimerIRQHandle
+            ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap);
+            if (HAL_OK != ret) {
+                DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
+                return ret;
+            }
+            //4 2.2) Enable TimerIRQ for Platform
+            InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
+
+        }
+        else {
+            DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
+            return HAL_ERR_PARA;
+        }
+
+    }
+    
+    //4 4) Enable Timer
+//    HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF), 
+//                        (ControlReg|0x1));
+
+    gTimerRecord |= (1<<pHalTimerAdap->TimerId);
+
+    return ret;
+}
+
+
+HAL_Status
+HalTimerIrqUnRegisterRtl8195a_Patch(
+    IN  VOID    *Data
+)
+{
+    PTIMER_ADAPTER      pHalTimerAdap = (PTIMER_ADAPTER) Data;
+    PIRQ_HANDLE         pTimerIrqHandle;
+    u32 i;
+    
+    pTimerIrqHandle = &pHalTimerAdap->IrqHandle;
+
+    if (pHalTimerAdap->TimerId > 7) {
+        DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__);
+        return HAL_ERR_PARA;
+    }
+    else {
+        if (pHalTimerAdap->TimerId > 1) {
+            pTimerIrqHandle->IrqNum = TIMER2_7_IRQ;
+            Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL;
+            for (i=0;i<MAX_TIMER_VECTOR_TABLE_NUM;i++) {
+                if (Timer2To7VectorTable[i] != NULL) {
+                    break;
+                }
+            }
+            
+            if (i == MAX_TIMER_VECTOR_TABLE_NUM) {
+                // All timer UnRegister Interrupt
+                InterruptDis((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
+                InterruptUnRegister(pTimerIrqHandle);
+            }
+        }
+        else {
+            pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
+            InterruptUnRegister(pTimerIrqHandle);
+        }
+
+    }
+    
+    return HAL_OK;
+}
+
+
+VOID
+HalTimerDeInitRtl8195a_Patch(
+    IN  VOID    *Data
+)
+{
+    PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
+    u32 timer_id;
+
+    timer_id = pHalTimerAdap->TimerId;
+    HalTimerDisRtl8195a (timer_id);
+    if (!pHalTimerAdap->IrqDis) {
+        if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
+            HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap);
+        }
+    }
+
+    gTimerRecord &= ~(1<<pHalTimerAdap->TimerId);
+}
+
+VOID
+HalTimerReLoadRtl8195a_Patch(
+    IN  u32 TimerId,
+    IN  u32 LoadUs
+)
+{
+    u32 LoadCount = 0;
+    u32 LoadUsX4;
+
+    //User-defined Mode
+    LoadUsX4 = LoadUs << 2; // time 4
+    if (LoadUsX4 < TIMER_TICK_US_X4) {
+        DBG_TIMER_WARN("HalTimerReLoadRtl8195a Warning : Timer Load Count = 1!!!!!!!\n");
+        LoadCount = 1;
+    }
+    else {
+        LoadCount = (LoadUsX4-(TIMER_TICK_US_X4>>1))/TIMER_TICK_US_X4;  // to get the most closed integer
+        if (LoadCount == 0) {
+            LoadCount = 1;
+        }
+    }
+    
+    DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount);
+    // set TimerLoadCount Register
+    HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF),
+                        LoadCount);
+}
+
+u32
+HalTimerReadCountRtl8195a_Patch(
+    IN  u32 TimerId
+)
+{
+    u32 TimerCountOld;
+    u32 TimerCountNew;
+    u32 TimerRDCnt;
+    
+    TimerRDCnt = 0;
+    TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
+    while(1) {        
+        TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
+
+        if (TimerCountOld == TimerCountNew) {
+            return (u32)TimerCountOld;
+        }
+        else {
+            TimerRDCnt++;
+            TimerCountOld = TimerCountNew;
+
+            if (TimerRDCnt >= 2){
+                return (u32)TimerCountOld;
+            }
+        }
+    }    
+}
+
+VOID
+HalTimerIrqEnRtl8195a(
+    IN  u32 TimerId
+)
+{
+    HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF), 
+                        HAL_TIMER_READ32(TIMER_INTERVAL*TimerId  + TIMER_CTL_REG_OFF) & (~(BIT2)));
+}
+
+VOID
+HalTimerIrqDisRtl8195a(
+    IN  u32 TimerId
+)
+{
+    HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF), 
+                        HAL_TIMER_READ32(TIMER_INTERVAL*TimerId  + TIMER_CTL_REG_OFF) | (BIT2));
+}
+
+VOID
+HalTimerEnRtl8195a_Patch(
+    IN  u32 TimerId
+)
+{
+    HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF), 
+                        HAL_TIMER_READ32(TIMER_INTERVAL*TimerId  + TIMER_CTL_REG_OFF) | (BIT0));
+}
+
+VOID
+HalTimerDisRtl8195a_Patch(
+    IN  u32 TimerId
+)
+{
+    // Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer
+    HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF), 
+                        HAL_TIMER_READ32(TIMER_INTERVAL*TimerId  + TIMER_CTL_REG_OFF) & (~BIT0));    
+}
+

component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c

@@ -0,0 +1,399 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+#include "rtl8195a_uart.h"
+#include "hal_uart.h"
+#include "hal_gdma.h"
+
+#if (CONFIG_CHIP_A_CUT | CONFIG_CHIP_B_CUT)
+
+const u32 BAUDRATE_PATCH[] = {
+       1200,    2400,    4800,   9600,   
+      14400,   19200,   28800,   38400,   
+      57600,   76800,  115200,  128000,
+     153600,  230400,  460800,  500000,
+     921600, 1000000, 1382400, 1444400,
+    1500000, 1843200, 2000000, 2100000,
+    2764800, 3000000, 3250000, 3692300,
+    3750000, 4000000, 6000000,
+
+    // For UART to IR Carrier
+    66000, 72000, 73400, 76000, 
+    80000, 112000
+};
+
+#if 0
+const u32 OVSR_PATCH[] = {
+    11, 13, 19, 10,
+    20, 10, 20, 17, 
+    11, 10, 17, 10, 
+    10, 13, 18, 13, 
+    20, 19, 13, 15, 
+    13, 13, 15, 13, 
+    12, 11, 11, 20, 
+    13 
+};
+
+const u32 DIV_PATCH[] = {
+    6105, 643, 293, 434, 
+     142, 217,  71,  62, 
+      65,  62,  31,  34, 
+      17,  12,   5,   6, 
+       3,   3,   4,   3, 
+       3,   3,   2,   2, 
+       2,   2,   2,   1, 
+       1
+};
+
+const u32 OVSR_ADJ_PATCH[] = {
+    0x24A, 0x555, 0x3BB, 0x000,
+    0x24A, 0x000, 0x24A, 0x555,
+    0x008, 0x555, 0x555, 0x5AD,
+    0x5AD, 0x7EF, 0x020, 0x7EF,
+    0x020, 0x444, 0x7EF, 0x080,
+    0x7EF, 0x444, 0x080, 0x7EF,
+    0x6FB, 0x122, 0x010, 0x5F7,
+    0x7EF
+};
+#else
+const u8 OVSR_PATCH[] = {
+    10, 10, 10, 15,
+    10, 13, 15, 11,
+    12, 11, 12, 11,
+    11, 18, 11, 18,
+    11, 10, 11, 11,
+    18, 11, 10, 13,
+    14, 13, 12, 11,
+    10, 10, 13,
+
+    // For UART to IR Carrier
+    11, 18, 14, 10,
+    10, 11
+};
+
+const u16 DIV_PATCH[] = {
+    6516, 3258, 1629, 543,
+     543,  311,  181, 188,
+     114,  94,    57,  57,
+      47,  19,    15,   9,
+       8,   8,     5,   5,
+       3,   4,     4,   3,
+       2,   2,     2,   2,
+       2,   2,     1,     
+
+    // For UART to IR Carrier
+    111, 63, 79, 102,
+    98, 64
+};
+
+const u16 OVSR_ADJ_PATCH[] = {
+    0x555, 0x555, 0x555, 0x3BB,
+    0x555, 0x5DD, 0x3BB, 0x252,
+    0x555, 0x252, 0x555, 0x222,
+    0x252, 0x3BB, 0x7EF, 0x444,
+    0x008, 0x222, 0x7EF, 0x252,
+    0x444, 0x008, 0x222, 0x000,
+    0x5F7, 0x76D, 0x5AD, 0x010,
+    0x5FF, 0x222, 0x76D,
+
+    // For UART to IR Carrier
+    0x24A, 0x252, 0x252, 0x5DD,
+    0x5AD, 0x5AD    
+};
+#endif
+#if 0
+static s32
+FindElementIndex(
+        u32 Element,  ///< RUART Baudrate
+        u32* Array    ///< Pre-defined Baudrate Array
+        )
+{
+    /* DBG_ENTRANCE; */
+    u32 BaudRateNumber = 29;
+    s32 Result = -1;
+    u32 Index = 0;
+
+    for (Index = 0; Index < BaudRateNumber && Result == -1; Index++) {
+        if (Element == Array[Index])
+            Result = Index;
+    }
+    return Result;  //TODO: Error handling
+}
+#endif
+s32
+FindElementIndex_Patch(
+        u32 Element,  ///< RUART Baudrate
+        u32* Array,    ///< Pre-defined Baudrate Array
+        u32 ElementNo
+        )
+{
+    /* DBG_ENTRANCE; */
+    s32 Result = -1;
+    u32 Index = 0;
+
+    for (Index = 0; Index < ElementNo && Result == -1; Index++) {
+        if (Element == Array[Index])
+            Result = Index;
+    }
+    return Result;  //TODO: Error handling
+}
+
+HAL_Status 
+HalRuartInitRtl8195a_Patch(
+        IN VOID *Data  ///< RUART Adapter
+        )
+{
+    /* DBG_ENTRANCE; */
+    u32 RegValue;
+    u32 Divisor;
+    u32 Dll;
+    u32 Dlm;
+    u8 UartIndex;
+    s32 ElementIndex;
+    RUART_SPEED_SETTING RuartSpeedSetting;
+    u8 PinmuxSelect;
+
+    PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data;
+
+    UartIndex = pHalRuartAdapter->UartIndex;
+    PinmuxSelect = pHalRuartAdapter->PinmuxSelect;
+
+    if (UartIndex > 2) {
+        DBG_UART_ERR(ANSI_COLOR_MAGENTA"HalRuartInitRtl8195a: Invalid UART Index\n"ANSI_COLOR_RESET);
+        return HAL_ERR_PARA;
+    }
+
+    DBG_UART_INFO("%s==>\n", __FUNCTION__);
+    DBG_UART_INFO("HalRuartInitRtl8195a: [UART %d] PinSel=%d\n", UartIndex, PinmuxSelect);
+    if(( PinmuxSelect == RUART0_MUX_TO_GPIOE ) && ((UartIndex == 0) || (UartIndex == 1))) {
+        DBG_UART_WARN(ANSI_COLOR_MAGENTA"UART Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
+    }
+
+    // switch Pin from EEPROM to UART0
+    if(( PinmuxSelect == RUART0_MUX_TO_GPIOC ) && (UartIndex == 0)) {
+        RegValue = HAL_READ32(SYSTEM_CTRL_BASE, 0xa4);
+        if (RegValue & 0x10) {
+            DBG_UART_WARN("Disable EEPROM Pin for UART 0\n");
+            HAL_WRITE32(SYSTEM_CTRL_BASE, 0xa4, (RegValue & (~0x10)));
+        }
+    }
+
+    switch (UartIndex) {
+        case 0:
+            /* UART 0 */
+            ACTCK_UART0_CCTRL(ON);
+            SLPCK_UART0_CCTRL(ON);
+            PinCtrl(UART0, PinmuxSelect, ON);
+            UART0_FCTRL(ON);
+            UART0_BD_FCTRL(ON);
+            break;
+
+        case 1:
+            /* UART 1 */
+            ACTCK_UART1_CCTRL(ON);
+            SLPCK_UART1_CCTRL(ON);
+            PinCtrl(UART1, PinmuxSelect, ON);
+            UART1_FCTRL(ON);
+            UART1_BD_FCTRL(ON);
+            break;
+
+        case 2:
+            /* UART 1 */
+            ACTCK_UART2_CCTRL(ON);
+            SLPCK_UART2_CCTRL(ON);
+            PinCtrl(UART2, PinmuxSelect, ON);
+            UART2_FCTRL(ON);
+            UART2_BD_FCTRL(ON);
+            break;
+
+        default:
+            DBG_UART_ERR("Invalid UART Index(%d)\n", UartIndex);
+            return HAL_ERR_PARA;
+    }
+
+    /* Reset RX FIFO */
+    HalRuartResetRxFifoRtl8195a(Data);
+    DBG_UART_INFO(ANSI_COLOR_CYAN"HAL UART Init[UART %d]\n"ANSI_COLOR_RESET, UartIndex);
+
+    /* Disable all interrupts */
+    HAL_RUART_WRITE32(UartIndex, RUART_INTERRUPT_EN_REG_OFF, 0x00);
+
+    /* Set DLAB bit to 1 to access DLL/DLM */
+    RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF);
+    RegValue |= RUART_LINE_CTL_REG_DLAB_ENABLE;
+    HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue);
+    DBG_UART_INFO("[R] RUART_LINE_CTL_REG_OFF(0x0C) = %x\n", HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
+
+    /* Set Baudrate Division */
+#if 1
+    ElementIndex = FindElementIndex_Patch(pHalRuartAdapter->BaudRate, (uint32_t*)BAUDRATE_PATCH, sizeof(BAUDRATE_PATCH)/sizeof(u32));
+    if (ElementIndex < 0) {
+        ElementIndex = 5;
+        DBG_UART_ERR("Invalid BaudRate(%d), Force it as default(%d)\n", pHalRuartAdapter->BaudRate, BAUDRATE_PATCH[ElementIndex]);
+    }
+
+    RuartSpeedSetting.BaudRate = BAUDRATE_PATCH[ElementIndex];
+    RuartSpeedSetting.Ovsr     =     OVSR_PATCH[ElementIndex];
+    RuartSpeedSetting.Div      =      DIV_PATCH[ElementIndex];
+    RuartSpeedSetting.Ovsr_adj = OVSR_ADJ_PATCH[ElementIndex];
+#else
+    RuartSpeedSetting.BaudRate = 38400;
+    RuartSpeedSetting.Ovsr     = 10;
+    RuartSpeedSetting.Div      = 217;
+    RuartSpeedSetting.Ovsr_adj = 0x0;
+#endif
+
+    DBG_UART_INFO("Baud %d, Ovsr %d, Div %d, OvsrAdj 0x%X\n",
+            RuartSpeedSetting.BaudRate,
+            RuartSpeedSetting.Ovsr,
+            RuartSpeedSetting.Div,
+            RuartSpeedSetting.Ovsr_adj
+            );
+    /* Divisor = (SYSTEM_CLK / ((ovsr + 5 + ovsr_adj/11) * (UartAdapter.BaudRate))); */
+
+    /* Set Divisor */
+    Divisor = RuartSpeedSetting.Div;
+
+    Dll = Divisor & 0xFF;
+    Dlm = (Divisor & 0xFF00) >> 8;
+
+//    DBG_UART_INFO("Calculated Dll, Dlm = %02x, %02x\n", Dll, Dlm);
+//    DBG_UART_INFO("---- Before setting baud rate ----\n");
+//    DBG_UART_INFO("  [R] RUART_DLL_OFF(0x00) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLL_OFF));
+//    DBG_UART_INFO("  [R] RUART_DLM_OFF(0x04) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLM_OFF));
+
+    HAL_RUART_WRITE32(UartIndex, RUART_DLL_OFF, Dll);
+    HAL_RUART_WRITE32(UartIndex, RUART_DLM_OFF, Dlm);
+
+//    DBG_UART_INFO("---- After setting baud rate ----\n");
+//    DBG_UART_INFO("  [R] RUART_DLL_OFF(0x00) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLL_OFF));
+//    DBG_UART_INFO("  [R] RUART_DLM_OFF(0x04) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLM_OFF));
+
+//    DBG_UART_INFO(ANSI_COLOR_CYAN"---- Befor OVSR & OVSR_ADJ ----\n"ANSI_COLOR_RESET);
+//    RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
+//    DBG_UART_INFO("UART%d SPR(0x1C) = %X\n", UartIndex, RegValue);
+//    RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF);
+//    DBG_UART_INFO("UART%d SIS(0x20) = %X\n", UartIndex, RegValue);
+
+    /**
+      * Clean Rx break signal interrupt status at initial stage.
+      */
+    RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
+    RegValue |= RUART_SP_REG_RXBREAK_INT_STATUS;
+    HAL_RUART_WRITE32(UartIndex, RUART_SCRATCH_PAD_REG_OFF, RegValue);
+
+    /* Set OVSR(xfactor) */
+    RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF);
+    RegValue &= ~(RUART_STS_REG_XFACTOR);
+    RegValue |= (((RuartSpeedSetting.Ovsr - 5) << 4) & RUART_STS_REG_XFACTOR);
+    HAL_RUART_WRITE32(UartIndex, RUART_STS_REG_OFF, RegValue);
+
+    /* Set OVSR_ADJ[10:0] (xfactor_adj[26:16]) */
+    RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
+    RegValue &= ~(RUART_SP_REG_XFACTOR_ADJ);
+    RegValue |= ((RuartSpeedSetting.Ovsr_adj << 16) & RUART_SP_REG_XFACTOR_ADJ);
+    HAL_RUART_WRITE32(UartIndex, RUART_SCRATCH_PAD_REG_OFF, RegValue);
+
+//    DBG_UART_INFO(ANSI_COLOR_CYAN"---- After OVSR & OVSR_ADJ ----\n"ANSI_COLOR_RESET);
+//    RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
+//    DBG_UART_INFO("UART%d SPR(0x1C) = %X\n", UartIndex, RegValue);
+//    RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF);
+//    DBG_UART_INFO("UART%d SIS(0x20) = %X\n", UartIndex, RegValue);
+
+    /* clear DLAB bit */
+    RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF);
+    RegValue &= ~(RUART_LINE_CTL_REG_DLAB_ENABLE);
+    HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue);
+//    DBG_UART_INFO("[R] RUART_LINE_CTL_REG_OFF(0x0C) = %x\n", HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
+//    DBG_UART_INFO("[R] UART%d INT_EN(0x04) = %x\n", UartIndex, pHalRuartAdapter->Interrupts);
+    RegValue = ((pHalRuartAdapter->Interrupts) & 0xFF);
+    HAL_RUART_WRITE32(UartIndex, RUART_INTERRUPT_EN_REG_OFF, RegValue);
+//    DBG_UART_INFO("[W] UART%d INT_EN(0x04) = %x\n", UartIndex, RegValue);
+
+    /* Configure FlowControl */
+    if (pHalRuartAdapter->FlowControl == AUTOFLOW_ENABLE) {
+        RegValue = HAL_RUART_READ32(UartIndex, RUART_MODEM_CTL_REG_OFF);
+        RegValue |= RUART_MCL_AUTOFLOW_ENABLE;
+        HAL_RUART_WRITE32(UartIndex, RUART_MODEM_CTL_REG_OFF, RegValue);
+    }
+
+    /* RUART DMA Initialization */
+    HalRuartDmaInitRtl8195a(pHalRuartAdapter);
+
+    DBG_UART_INFO("[R] UART%d LCR(0x%02X): %X\n", UartIndex, RUART_LINE_CTL_REG_OFF, HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
+    RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF);
+
+    /* PARITY CONTROL */
+    RegValue &= BIT_CLR_LCR_WLS;
+    RegValue |= BIT_LCR_WLS(pHalRuartAdapter->WordLen);
+
+    RegValue &= BIT_INVC_LCR_STB_EN;
+    RegValue |= BIT_LCR_STB_EN(pHalRuartAdapter->StopBit);
+
+    RegValue &= BIT_INVC_LCR_PARITY_EN;
+    RegValue |= BIT_LCR_PARITY_EN(pHalRuartAdapter->Parity);
+
+    /* PARITY TYPE SELECT */
+    RegValue &= BIT_INVC_LCR_PARITY_TYPE;
+    RegValue |= BIT_LCR_PARITY_TYPE(pHalRuartAdapter->ParityType);
+
+    /* STICK PARITY CONTROL */
+    RegValue &= BIT_INVC_LCR_STICK_PARITY_EN;
+    RegValue |= BIT_LCR_STICK_PARITY_EN(pHalRuartAdapter->StickParity);
+
+    HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue);
+    DBG_UART_INFO("[W] UART%d LCR(0x%02X): %X\n", UartIndex, RUART_LINE_CTL_REG_OFF, HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
+
+    /* Need to assert RTS during initial stage. */
+    if (pHalRuartAdapter->FlowControl == AUTOFLOW_ENABLE) {
+        HalRuartRTSCtrlRtl8195a(Data, 1);
+    }
+    pHalRuartAdapter->State = HAL_UART_STATE_READY;
+
+	return HAL_OK;
+}
+
+#endif
+
+/**
+ * Reset RUART Tx FIFO.
+ *
+ * Reset RUART Receiver and Rx FIFO wrapper function.
+ * It will check LINE_STATUS_REG until reset action completion.
+ *
+ * @return BOOL
+ */
+HAL_Status
+HalRuartResetTxFifoRtl8195a(
+        IN VOID *Data  ///< RUART Adapter
+        )
+{
+    PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data;
+    u8 UartIndex = pHalRuartAdapter->UartIndex;
+    u32 rx_trigger_lv;
+    u32 RegValue;
+
+    // Backup the RX FIFO trigger Level setting
+    rx_trigger_lv = HAL_RUART_READ32(UartIndex, RUART_FIFO_CTL_REG_OFF);
+    rx_trigger_lv &= 0xC0;   // only keep the bit[7:6]
+
+    /* Step 2: Enable clear_txfifo */
+    RegValue = (FIFO_CTL_DEFAULT_WITH_FIFO_DMA | RUART_FIFO_CTL_REG_CLEAR_TXFIFO) & (~0xC0);
+    RegValue |= rx_trigger_lv;
+    HAL_RUART_WRITE32(UartIndex, RUART_FIFO_CTL_REG_OFF, RegValue);
+
+    //TODO: Check Defautl Value
+    RegValue = (FIFO_CTL_DEFAULT_WITH_FIFO_DMA & (~0xC0)) | rx_trigger_lv;
+    HAL_RUART_WRITE32(UartIndex, RUART_FIFO_CTL_REG_OFF, RegValue);
+
+    return HAL_OK;
+}
+

component/soc/realtek/8195a/fwlib/src/hal_32k.c

@@ -0,0 +1,293 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+
+#ifdef CONFIG_TIMER_MODULE
+
+VOID
+En32KCalibration(
+    VOID
+)
+{
+    u32 Rtemp;
+    u32 Ttemp = 0;
+
+    //DiagPrintf("32K clock source calibration\n");
+
+    //set parameter
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+    //offset 1 = 0x1500
+    Rtemp = 0x811500;
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+    HalDelayUs(40);
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+    //offset 2 = 0x01c0
+    Rtemp = 0x8201c0;
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+    HalDelayUs(40);
+        HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+    
+    //offset 4 = 0x0100
+    Rtemp = 0x840100;
+        HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+    HalDelayUs(40);
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+    //offset 0 = 0xf980
+    Rtemp = 0x80f980;
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+    HalDelayUs(40);
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+    while(1) {
+        //Polling LOCK
+        Rtemp = 0x110000;
+        HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+        //DiagPrintf("Polling lock\n");
+        HalDelayUs(40);
+
+        Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL1);
+        if ((Rtemp & 0x3000) != 0x0){
+            //DiagPrintf("32.768 Calibration Success\n", Ttemp);
+            break;
+        }
+        else {
+            Ttemp++;
+            HalDelayUs(30);
+            //DiagPrintf("Check lock: %d\n", Ttemp);
+            //DiagPrintf("0x278: %x\n", Rtemp);
+            if (Ttemp > 100000) { /*Delay 100ms*/            
+                DiagPrintf("32K Calibration Fail!!\n", Ttemp);
+                break;
+            }
+        }
+    }
+}
+
+#if CONFIG_WDG
+WDG_ADAPTER          WDGAdapter;
+extern HAL_TIMER_OP HalTimerOp;
+
+#ifdef CONFIG_WDG_NORMAL
+VOID
+WDGInitial(
+    IN  u32 Period
+)
+{
+    u8 CountId;
+    u16 DivFactor;
+    u32 CountTemp; 
+    u32 CountProcess = 0;
+    u32 DivFacProcess = 0;
+    u32 PeriodProcess = 100*Period;
+    u32 MinPeriodTemp = 0xFFFFFFFF;
+    u32 PeriodTemp = 0;
+    u32 *Reg = (u32*)&(WDGAdapter.Ctrl);
+    
+    DBG_8195A(" Period = 0x%08x\n", Period);
+
+    for (CountId = 0; CountId < 12; CountId++) {
+        CountTemp = ((0x00000001 << (CountId+1))-1);
+        DivFactor = (u16)((PeriodProcess)/(CountTemp*3));
+        
+        if (DivFactor > 0) {
+            PeriodTemp = 3*(DivFactor+1)*CountTemp;
+            if (PeriodProcess < PeriodTemp) {
+                if (MinPeriodTemp > PeriodTemp) {
+                    MinPeriodTemp = PeriodTemp;
+                    CountProcess = CountId;
+                    DivFacProcess = DivFactor;
+                }
+            }
+        }
+    }
+
+    DBG_8195A("WdgScalar = 0x%08x\n", DivFacProcess);
+    DBG_8195A("WdgCunLimit = 0x%08x\n", CountProcess);
+
+    WDGAdapter.Ctrl.WdgScalar   = DivFacProcess;
+    WDGAdapter.Ctrl.WdgEnByte   = 0;
+    WDGAdapter.Ctrl.WdgClear    = 1;
+    WDGAdapter.Ctrl.WdgCunLimit = CountProcess;
+    WDGAdapter.Ctrl.WdgMode     = RESET_MODE;
+    WDGAdapter.Ctrl.WdgToISR    = 0;
+
+    HAL_WRITE32(VENDOR_REG_BASE, 0, (*Reg));
+    
+}
+
+VOID
+WDGIrqHandle
+(
+    IN  VOID        *Data
+)
+{
+    u32 temp;
+    WDG_REG *CtrlReg;
+
+    if (NULL != WDGAdapter.UserCallback) {
+        WDGAdapter.UserCallback(WDGAdapter.callback_id);
+    }
+
+    // Clear ISR
+    temp = HAL_READ32(VENDOR_REG_BASE, 0);
+    CtrlReg = (WDG_REG*)&temp;
+    CtrlReg->WdgToISR    = 1;    // write 1 clear
+    HAL_WRITE32(VENDOR_REG_BASE, 0, (temp));
+}
+
+VOID
+WDGIrqInitial(
+    VOID
+)
+{
+    u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
+    
+    WDGAdapter.IrqHandle.Data = (u32)&WDGAdapter;
+    WDGAdapter.IrqHandle.IrqFun = (IRQ_FUN)WDGIrqHandle;
+    WDGAdapter.IrqHandle.IrqNum = WDG_IRQ;
+    WDGAdapter.IrqHandle.Priority = 0;
+         
+    InterruptRegister(&(WDGAdapter.IrqHandle));
+    InterruptEn(&(WDGAdapter.IrqHandle));
+
+    WDGAdapter.Ctrl.WdgToISR    = 1;    // clear ISR first
+    WDGAdapter.Ctrl.WdgMode     = INT_MODE;
+    HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
+    WDGAdapter.Ctrl.WdgToISR    = 0;
+}
+
+VOID
+WDGStart(
+    VOID
+)
+{
+    u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
+    WDGAdapter.Ctrl.WdgEnByte    = 0xA5;
+    HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
+}
+
+VOID
+WDGStop(
+    VOID
+)
+{
+    u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
+    WDGAdapter.Ctrl.WdgEnByte    = 0;
+    HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
+}
+
+VOID
+WDGRefresh(
+    VOID
+)
+{
+    u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
+    WDGAdapter.Ctrl.WdgClear    = 1;
+    HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
+} 
+
+VOID
+WDGIrqCallBackReg(
+    IN VOID *CallBack,
+    IN u32   Id
+)
+{
+    WDGAdapter.UserCallback = (VOID (*)(u32))CallBack;
+    WDGAdapter.callback_id = Id;
+} 
+
+#endif
+
+#ifdef CONFIG_GDMA_TEST
+VOID
+WDGIrqHandle
+(
+    IN  VOID        *Data
+)
+{
+}
+
+
+VOID
+WDGGtimerHandle
+(
+    IN  VOID        *Data
+)
+{
+    u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
+    WDGAdapter.Ctrl.WdgClear    = 1;
+    DBG_8195A("reset WDG\n");
+    if (HAL_READ32(SYSTEM_CTRL_BASE,REG_SYS_DSTBY_INFO2) == 0) {
+        HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
+    }
+}
+
+
+VOID
+InitWDGIRQ(VOID)
+{
+    u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
+    
+    WDGAdapter.Ctrl.WdgScalar   = 0x96;
+    WDGAdapter.Ctrl.WdgEnByte   = 0xA5;
+    WDGAdapter.Ctrl.WdgClear    = 1;
+    WDGAdapter.Ctrl.WdgCunLimit = CNTFFFH;
+    WDGAdapter.Ctrl.WdgMode     = RESET_MODE;
+    WDGAdapter.Ctrl.WdgToISR    = 0;
+
+    if (WDGAdapter.Ctrl.WdgMode == INT_MODE) {
+        
+        WDGAdapter.IrqHandle.Data = NULL;
+        WDGAdapter.IrqHandle.IrqFun = (IRQ_FUN)WDGIrqHandle;
+        WDGAdapter.IrqHandle.IrqNum = WDG_IRQ;
+        WDGAdapter.IrqHandle.Priority = 0;
+             
+        InterruptRegister(&(WDGAdapter.IrqHandle));
+        InterruptEn(&(WDGAdapter.IrqHandle));
+    }
+    else {
+        
+        WDGAdapter.WdgGTimer.TimerIrqPriority   = 0;
+        WDGAdapter.WdgGTimer.TimerMode          = USER_DEFINED;
+        WDGAdapter.WdgGTimer.IrqDis             = OFF;
+        WDGAdapter.WdgGTimer.TimerId            = 2;//
+        WDGAdapter.WdgGTimer.IrqHandle.IrqFun   = (IRQ_FUN)WDGGtimerHandle;
+        WDGAdapter.WdgGTimer.IrqHandle.IrqNum   = TIMER2_7_IRQ;
+        WDGAdapter.WdgGTimer.IrqHandle.Priority = 0;
+        WDGAdapter.WdgGTimer.IrqHandle.Data     = NULL;
+        
+        if ((WDGAdapter.Ctrl.WdgCunLimit == CNTFFFH)&&(WDGAdapter.Ctrl.WdgScalar >= 0x8429)){
+            WDGAdapter.WdgGTimer.TimerLoadValueUs = 0xFFFFFFFF - WDGTIMERELY;
+        }
+        else {
+            WDGAdapter.WdgGTimer.TimerLoadValueUs   = (BIT0 << (WDGAdapter.Ctrl.WdgCunLimit+1))
+                *WDGAdapter.Ctrl.WdgScalar*TIMER_TICK_US - WDGTIMERELY;
+        }
+
+        HalTimerOp.HalTimerInit((VOID*) &(WDGAdapter.WdgGTimer));
+    }
+    //fill reg
+    HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
+}
+
+
+//WDG
+VOID HalWdgInit(
+    VOID
+)
+{
+        
+}
+#endif  //WDG_Verify_Mode
+#endif  //CONFIG_WDG
+#endif  //#ifdef CONFIG_TIMER_MODULE

component/soc/realtek/8195a/fwlib/src/hal_common.c

@@ -0,0 +1,23 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#include "rtl8195a.h"
+#include "hal_common.h"
+
+extern HAL_TIMER_OP        HalTimerOp;
+
+HAL_Status 
+HalCommonInit(void){
+
+#ifdef CONFIG_TIMER_MODULE
+    HalTimerOpInit_Patch((VOID*)(&HalTimerOp));
+#endif
+
+    return HAL_OK;
+}

component/soc/realtek/8195a/fwlib/src/hal_gdma.c

@@ -0,0 +1,358 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+#include "hal_gdma.h"
+
+#define MAX_GDMA_INDX       1
+#define MAX_GDMA_CHNL       6
+
+static u8 HalGdmaReg[MAX_GDMA_INDX+1];
+
+const HAL_GDMA_CHNL GDMA_Chnl_Option[] = { 
+        {0,0,GDMA0_CHANNEL0_IRQ,0},
+        {1,0,GDMA1_CHANNEL0_IRQ,0},
+        {0,1,GDMA0_CHANNEL1_IRQ,0},
+        {1,1,GDMA1_CHANNEL1_IRQ,0},
+        {0,2,GDMA0_CHANNEL2_IRQ,0},
+        {1,2,GDMA1_CHANNEL2_IRQ,0},
+        {0,3,GDMA0_CHANNEL3_IRQ,0},
+        {1,3,GDMA1_CHANNEL3_IRQ,0},
+        {0,4,GDMA0_CHANNEL4_IRQ,0},
+        {1,4,GDMA1_CHANNEL4_IRQ,0},
+        {0,5,GDMA0_CHANNEL5_IRQ,0},
+        {1,5,GDMA1_CHANNEL5_IRQ,0},
+        
+        {0xff,0,0,0}    // end
+};
+
+const u16 HalGdmaChnlEn[6] = {
+    GdmaCh0, GdmaCh1, GdmaCh2, GdmaCh3,
+    GdmaCh4, GdmaCh5
+};
+    
+VOID HalGdmaOpInit(
+    IN  VOID *Data
+)
+{
+    PHAL_GDMA_OP pHalGdmaOp = (PHAL_GDMA_OP) Data;
+
+    pHalGdmaOp->HalGdmaOnOff = HalGdmaOnOffRtl8195a;
+    pHalGdmaOp->HalGdamChInit = HalGdamChInitRtl8195a;
+    pHalGdmaOp->HalGdmaChDis = HalGdmaChDisRtl8195a;
+    pHalGdmaOp->HalGdmaChEn = HalGdmaChEnRtl8195a;
+    pHalGdmaOp->HalGdmaChSeting = HalGdmaChSetingRtl8195a;
+    pHalGdmaOp->HalGdmaChBlockSeting = HalGdmaChBlockSetingRtl8195a;
+    pHalGdmaOp->HalGdmaChIsrEnAndDis = HalGdmaChIsrEnAndDisRtl8195a;
+    pHalGdmaOp->HalGdmaChIsrClean = HalGdmaChIsrCleanRtl8195a;
+    pHalGdmaOp->HalGdmaChCleanAutoSrc = HalGdmaChCleanAutoSrcRtl8195a;
+    pHalGdmaOp->HalGdmaChCleanAutoDst = HalGdmaChCleanAutoDstRtl8195a;
+}
+
+VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    pHalGdmaAdapter->GdmaOnOff = ON;
+    HalGdmaOnOffRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    pHalGdmaAdapter->GdmaOnOff = OFF;
+    HalGdmaOnOffRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    return (HalGdamChInitRtl8195a((VOID*)pHalGdmaAdapter));
+}
+
+VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    HalGdmaChDisRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    HalGdmaChEnRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    return (HalGdmaChSetingRtl8195a((VOID*)pHalGdmaAdapter));
+}
+
+BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    return (HalGdmaChBlockSetingRtl8195a((VOID*)pHalGdmaAdapter));
+}
+
+VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    pHalGdmaAdapter->IsrCtrl = ENABLE;
+    HalGdmaChIsrEnAndDisRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    pHalGdmaAdapter->IsrCtrl = DISABLE;
+    HalGdmaChIsrEnAndDisRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    return (HalGdmaChIsrCleanRtl8195a((VOID*)pHalGdmaAdapter));
+}
+
+VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    HalGdmaChCleanAutoSrcRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    HalGdmaChCleanAutoDstRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum)
+{
+    u32 mask;
+
+    if ((GdmaIdx > MAX_GDMA_INDX) || (ChnlNum > MAX_GDMA_CHNL)) {
+        // Invalid GDMA Index or Channel Number
+        return HAL_ERR_PARA;
+    }
+
+    mask = 1 << ChnlNum;
+
+    if ((HalGdmaReg[GdmaIdx] & mask) != 0) {
+        return HAL_BUSY;
+    }
+    else {
+#if 1
+        if (HalGdmaReg[GdmaIdx] == 0) {
+            if (GdmaIdx == 0) {
+                ACTCK_GDMA0_CCTRL(ON);
+                GDMA0_FCTRL(ON);
+            }
+            else {
+                ACTCK_GDMA1_CCTRL(ON);
+                GDMA1_FCTRL(ON);
+            }
+        }
+#endif    
+        HalGdmaReg[GdmaIdx] |= mask;
+        return HAL_OK;
+    }
+}
+
+VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum)
+{
+    u32 mask;
+
+    if ((GdmaIdx > MAX_GDMA_INDX) || (ChnlNum > MAX_GDMA_CHNL)) {
+        // Invalid GDMA Index or Channel Number
+        return;
+    }
+    
+    mask = 1 << ChnlNum;
+
+    HalGdmaReg[GdmaIdx] &= ~mask;
+#if 1
+    if (HalGdmaReg[GdmaIdx] == 0) {
+        if (GdmaIdx == 0) {
+            ACTCK_GDMA0_CCTRL(OFF);
+            GDMA0_FCTRL(OFF);
+        }
+        else {
+            ACTCK_GDMA1_CCTRL(OFF);
+            GDMA1_FCTRL(OFF);
+        }
+    }
+#endif    
+}
+
+PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption)
+{
+    HAL_GDMA_CHNL *pgdma_chnl;
+
+    pgdma_chnl = pChnlOption;
+    if (pChnlOption == NULL) {
+        // Use default GDMA Channel Option table
+        pgdma_chnl = (HAL_GDMA_CHNL*)&GDMA_Chnl_Option[0];
+    }
+
+    while (pgdma_chnl->GdmaIndx <= MAX_GDMA_INDX) {
+        if (HalGdmaChnlRegister(pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl) == HAL_OK) {
+            // This GDMA Channel is available
+            break;
+        }
+        pgdma_chnl += 1;
+    }
+
+    if (pgdma_chnl->GdmaIndx > MAX_GDMA_INDX) {
+        pgdma_chnl = NULL;
+    }
+    
+    return pgdma_chnl;
+}
+
+VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl)
+{
+    IRQ_HANDLE IrqHandle;
+
+    IrqHandle.IrqNum = pChnl->IrqNum;
+    InterruptDis(&IrqHandle);
+    InterruptUnRegister(&IrqHandle);
+    HalGdmaChnlUnRegister(pChnl->GdmaIndx, pChnl->GdmaChnl);
+}
+
+VOID HalGdmaMemIrqHandler(VOID *pData)
+{
+    PHAL_GDMA_OBJ pHalGdmaObj=(PHAL_GDMA_OBJ)pData;
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PIRQ_HANDLE pGdmaIrqHandle;
+    u8 IsrTypeMap;
+    
+    pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
+    pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
+    // Clean Auto Reload Bit
+    HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter);
+
+    // Clear Pending ISR
+    IsrTypeMap = HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
+
+    HalGdmaChDis((VOID*)(pHalGdmaAdapter));
+    pHalGdmaObj->Busy = 0;
+
+    if (pGdmaIrqHandle->IrqFun != NULL) {
+        pGdmaIrqHandle->IrqFun((VOID*)pGdmaIrqHandle->Data);
+    }
+}
+
+BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj)
+{
+    HAL_GDMA_CHNL *pgdma_chnl;
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PIRQ_HANDLE pGdmaIrqHandle;
+    IRQ_HANDLE IrqHandle;
+
+    pgdma_chnl = HalGdmaChnlAlloc(NULL);    // get a whatever GDMA channel
+    if (NULL == pgdma_chnl) {        
+        DBG_GDMA_ERR("%s: Cannot allocate a GDMA Channel\n", __FUNCTION__);
+        return _FALSE;
+    }
+
+    pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
+    pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
+    
+    DBG_GDMA_INFO("%s: Use GDMA%d CH%d\n", __FUNCTION__, pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl);
+#if 0
+    if (pgdma_chnl->GdmaIndx == 0) {
+        ACTCK_GDMA0_CCTRL(ON);
+        GDMA0_FCTRL(ON);
+    }
+    else if (pgdma_chnl->GdmaIndx == 1) {
+        ACTCK_GDMA1_CCTRL(ON);
+        GDMA1_FCTRL(ON);
+    }
+#endif    
+    _memset((void *)pHalGdmaAdapter, 0, sizeof(HAL_GDMA_ADAPTER));
+
+//    pHalGdmaAdapter->GdmaCtl.TtFc = TTFCMemToMem;
+    pHalGdmaAdapter->GdmaCtl.Done = 1;
+//    pHalGdmaAdapter->MuliBlockCunt = 0;
+//    pHalGdmaAdapter->MaxMuliBlock = 1;
+    pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
+    pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
+    pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
+    pHalGdmaAdapter->GdmaIsrType = (TransferType|ErrType);
+    pHalGdmaAdapter->IsrCtrl = ENABLE;
+    pHalGdmaAdapter->GdmaOnOff = ON;
+
+    pHalGdmaAdapter->GdmaCtl.IntEn      = 1;
+//    pHalGdmaAdapter->GdmaCtl.SrcMsize   = MsizeEight;
+//    pHalGdmaAdapter->GdmaCtl.DestMsize  = MsizeEight;
+//    pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
+//    pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
+//    pHalGdmaAdapter->GdmaCtl.Dinc = IncType;
+//    pHalGdmaAdapter->GdmaCtl.Sinc = IncType;
+
+    pGdmaIrqHandle->IrqNum = pgdma_chnl->IrqNum;
+    pGdmaIrqHandle->Priority = 10;
+
+    IrqHandle.IrqFun = (IRQ_FUN) HalGdmaMemIrqHandler;
+    IrqHandle.Data = (u32) pHalGdmaObj;
+    IrqHandle.IrqNum = pGdmaIrqHandle->IrqNum;
+    IrqHandle.Priority = pGdmaIrqHandle->Priority;
+
+    InterruptRegister(&IrqHandle);
+    InterruptEn(&IrqHandle);
+    pHalGdmaObj->Busy = 0;
+    
+    return _TRUE;
+}
+
+VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj)
+{
+    HAL_GDMA_CHNL GdmaChnl;
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PIRQ_HANDLE pGdmaIrqHandle;
+
+    pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
+    pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
+
+    GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
+    GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
+    GdmaChnl.IrqNum = pGdmaIrqHandle->IrqNum;
+    HalGdmaChnlFree(&GdmaChnl);
+}
+
+// If multi-task using the same GDMA Object, then it needs a mutex to protect this procedure
+VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+
+    if (pHalGdmaObj->Busy) {
+        DBG_GDMA_ERR("%s: ==> GDMA is Busy\r\n", __FUNCTION__);
+        return 0;
+    }
+    pHalGdmaObj->Busy = 1;
+    pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
+
+    DBG_GDMA_INFO("%s: ==> Src=0x%x Dst=0x%x Len=%d\r\n", __FUNCTION__, pSrc, pDest, len);
+    if ((((u32)pSrc & 0x03)==0) &&
+        (((u32)pDest & 0x03)==0) &&        
+        ((len & 0x03)== 0)) {
+        // 4-bytes aligned, move 4 bytes each transfer
+        pHalGdmaAdapter->GdmaCtl.SrcMsize   = MsizeEight;
+        pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
+        pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
+        pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
+        pHalGdmaAdapter->GdmaCtl.BlockSize = len >> 2;
+    }
+    else {
+        pHalGdmaAdapter->GdmaCtl.SrcMsize   = MsizeEight;
+        pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte;
+        pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
+        pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte;
+        pHalGdmaAdapter->GdmaCtl.BlockSize = len;
+    }
+
+    pHalGdmaAdapter->ChSar = (u32)pSrc;
+    pHalGdmaAdapter->ChDar = (u32)pDest;                
+    pHalGdmaAdapter->PacketLen = len;
+
+    HalGdmaOn((pHalGdmaAdapter));
+    HalGdmaChIsrEn((pHalGdmaAdapter));
+    HalGdmaChSeting((pHalGdmaAdapter));
+    HalGdmaChEn((pHalGdmaAdapter));
+
+    return (pDest);
+}

component/soc/realtek/8195a/fwlib/src/hal_gpio.c

@@ -0,0 +1,144 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#include "rtl8195a.h"
+
+#ifdef CONFIG_GPIO_EN
+
+HAL_GPIO_DATA_SECTION HAL_GPIO_ADAPTER gHAL_Gpio_Adapter;
+extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
+
+extern VOID GPIO_PullCtrl_8195a(u32 chip_pin, u8 pull_type);
+
+/**
+  * @brief  To get the GPIO IP Pin name for the given chip pin name
+  *
+  * @param  chip_pin: The chip pin name.
+  *
+  * @retval The gotten GPIO IP pin name
+  */
+HAL_GPIO_TEXT_SECTION u32 
+HAL_GPIO_GetPinName(
+    u32 chip_pin
+)
+{
+    return HAL_GPIO_GetIPPinName_8195a((u32)chip_pin);
+}
+
+/**
+  * @brief  Set the GPIO pad Pull type
+  *
+  *  @param    pin: The pin for pull type control.
+  *  @param    mode: the pull type for the pin.
+  *  @return   None
+  */
+VOID 
+HAL_GPIO_PullCtrl(
+    u32 pin,
+    u32 mode    
+)
+{
+    u8 pull_type;
+
+    DBG_GPIO_INFO("%s: pin=0x%x mode=%d\n ", __FUNCTION__, (u32)pin, (u32)mode);
+
+    switch (mode) {
+        case hal_PullNone:
+            pull_type = DIN_PULL_NONE;
+            break;
+            
+        case hal_PullDown:
+            pull_type = DIN_PULL_LOW;
+            break;
+            
+        case hal_PullUp:
+            pull_type = DIN_PULL_HIGH;
+            break;
+            
+        case hal_OpenDrain:
+        default:
+            pull_type = DIN_PULL_NONE;
+            break;
+    }
+
+//    HAL_GPIO_PullCtrl_8195a (pin, pull_type);
+    GPIO_PullCtrl_8195a (pin, pull_type);
+}
+
+
+/**
+  * @brief  Initializes a GPIO Pin by the GPIO_Pin parameters.
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
+  *
+  * @retval HAL_Status
+  */
+HAL_GPIO_TEXT_SECTION VOID 
+HAL_GPIO_Init(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    if (_pHAL_Gpio_Adapter == NULL) {
+        _pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter;
+        DBG_GPIO_INFO("%s: Initial GPIO Adapter\n ", __FUNCTION__);
+    }
+
+    HAL_GPIO_Init_8195a(GPIO_Pin);
+}
+
+/**
+  * @brief  Initializes a GPIO Pin as a interrupt signal
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
+  *
+  * @retval HAL_Status
+  */
+VOID 
+HAL_GPIO_Irq_Init(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    if (_pHAL_Gpio_Adapter == NULL) {
+        _pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter;
+        DBG_GPIO_INFO("%s: Initial GPIO Adapter\n ", __FUNCTION__);
+    }
+
+    if (_pHAL_Gpio_Adapter->IrqHandle.IrqFun == NULL) {
+        _pHAL_Gpio_Adapter->IrqHandle.IrqFun = HAL_GPIO_MbedIrqHandler_8195a;
+        _pHAL_Gpio_Adapter->IrqHandle.Priority = 0x10;
+        HAL_GPIO_RegIrq_8195a(&_pHAL_Gpio_Adapter->IrqHandle);        
+        InterruptEn(&_pHAL_Gpio_Adapter->IrqHandle);
+        DBG_GPIO_INFO("%s: Initial GPIO IRQ Adapter\n ", __FUNCTION__);
+    }
+
+    DBG_GPIO_INFO("%s: GPIO(name=0x%x)(mode=%d)\n ", __FUNCTION__, GPIO_Pin->pin_name, 
+        GPIO_Pin->pin_mode);
+    HAL_GPIO_Init_8195a(GPIO_Pin);
+}
+
+/**
+  * @brief  UnInitial GPIO Adapter
+  *
+  *
+  * @retval HAL_Status
+  */
+VOID
+HAL_GPIO_IP_DeInit(
+    VOID
+)
+{
+    if (_pHAL_Gpio_Adapter != NULL) {
+        InterruptDis(&_pHAL_Gpio_Adapter->IrqHandle);
+        HAL_GPIO_UnRegIrq_8195a(&_pHAL_Gpio_Adapter->IrqHandle);                
+        _pHAL_Gpio_Adapter = NULL;
+    }
+    
+}
+
+#endif // CONFIG_GPIO_EN

component/soc/realtek/8195a/fwlib/src/hal_i2s.c

@@ -0,0 +1,415 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+#include "hal_i2s.h"
+#include "rand.h"
+#include "rtl_utility.h"
+
+
+//1 need to be modified 
+
+
+/*======================================================
+    Local used variables
+*/
+SRAM_BF_DATA_SECTION
+HAL_I2S_OP HalI2SOpSAL={0};
+
+
+VOID
+I2SISRHandle(
+    IN  VOID *Data
+)
+{
+    PHAL_I2S_ADAPTER pI2SAdp = (PHAL_I2S_ADAPTER) Data;
+    PHAL_I2S_OP     pHalI2SOP = &HalI2SOpSAL;
+    PHAL_I2S_INIT_DAT pI2SCfg = pI2SAdp->pInitDat;
+    u8  I2SIrqIdx = pI2SCfg->I2SIdx;
+    u32 I2STxIsr, I2SRxIsr;
+    u8  I2SPageNum = pI2SCfg->I2SPageNum+1;
+//    u32 I2SPageSize = (pI2SAdp->I2SPageSize+1)<<2;
+    u32 i;
+    u32 pbuf;
+
+    I2STxIsr = pHalI2SOP->HalI2SReadReg(pI2SCfg, REG_I2S_TX_STATUS_INT);
+    I2SRxIsr = pHalI2SOP->HalI2SReadReg(pI2SCfg, REG_I2S_RX_STATUS_INT);
+
+    pI2SCfg->I2STxIntrClr = I2STxIsr;
+    pI2SCfg->I2SRxIntrClr = I2SRxIsr;
+    pHalI2SOP->HalI2SClrIntr(pI2SCfg);
+
+    for (i=0 ; i<I2SPageNum ; i++) { // page 0, 1, 2, 3
+        if (I2STxIsr & (1<<pI2SCfg->I2SHWTxIdx)) {
+//            pbuf = ((u32)(pI2SCfg->I2STxData)) + (I2SPageSize*pI2SCfg->I2SHWTxIdx);
+            pbuf = (u32)pI2SAdp->TxPageList[pI2SCfg->I2SHWTxIdx];
+            pI2SAdp->UserCB.TxCCB(pI2SAdp->UserCB.TxCBId, (char*)pbuf);
+            I2STxIsr &= ~(1<<pI2SCfg->I2SHWTxIdx);
+            pI2SCfg->I2SHWTxIdx += 1;
+            if (pI2SCfg->I2SHWTxIdx == I2SPageNum) {
+                pI2SCfg->I2SHWTxIdx = 0;
+            }
+        }
+        
+        if (I2SRxIsr & (1<<pI2SCfg->I2SHWRxIdx)) {
+//            pbuf = ((u32)(pI2SCfg->I2SRxData)) + (I2SPageSize*pI2SCfg->I2SHWRxIdx);
+            pbuf = (u32)pI2SAdp->RxPageList[pI2SCfg->I2SHWRxIdx];
+            pI2SAdp->UserCB.RxCCB(pI2SAdp->UserCB.RxCBId, (char*)pbuf);
+            I2SRxIsr &= ~(1<<pI2SCfg->I2SHWRxIdx);
+            pI2SCfg->I2SHWRxIdx += 1;
+            if (pI2SCfg->I2SHWRxIdx == I2SPageNum) {
+                pI2SCfg->I2SHWRxIdx = 0;
+            }
+        }
+    }
+}
+
+
+static HAL_Status
+RtkI2SIrqInit(
+    IN  PHAL_I2S_ADAPTER pI2SAdapter
+)
+{
+    PIRQ_HANDLE pIrqHandle;
+
+    if (pI2SAdapter->DevNum > I2S_MAX_ID) {
+        DBG_I2S_ERR("RtkI2SIrqInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
+        return HAL_ERR_PARA;
+    }
+    
+    pIrqHandle = &pI2SAdapter->IrqHandle;
+    
+    switch (pI2SAdapter->DevNum){
+        case I2S0_SEL:
+            pIrqHandle->IrqNum = I2S0_PCM0_IRQ;
+            break;
+            
+        case I2S1_SEL:
+            pIrqHandle->IrqNum = I2S1_PCM1_IRQ;
+            break;
+            
+        default:
+            return HAL_ERR_PARA;
+    }
+
+    pIrqHandle->Data = (u32) (pI2SAdapter);
+    pIrqHandle->IrqFun = (IRQ_FUN) I2SISRHandle;
+    pIrqHandle->Priority = 3;
+    InterruptRegister(pIrqHandle);
+    InterruptEn(pIrqHandle);
+    
+    return HAL_OK;
+}
+
+static HAL_Status
+RtkI2SIrqDeInit(
+    IN  PHAL_I2S_ADAPTER pI2SAdapter
+)
+{
+    if (pI2SAdapter->DevNum > I2S_MAX_ID) {
+        DBG_I2S_ERR("RtkI2SIrqDeInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
+        return HAL_ERR_PARA;
+    }
+
+    InterruptDis(&pI2SAdapter->IrqHandle);
+    InterruptUnRegister(&pI2SAdapter->IrqHandle);  
+
+    return HAL_OK;
+}
+
+static HAL_Status
+RtkI2SPinMuxInit(
+    IN  PHAL_I2S_ADAPTER pI2SAdapter
+)
+{
+    u32 I2Stemp;
+
+    if (pI2SAdapter->DevNum > I2S_MAX_ID) {
+        DBG_I2S_ERR("RtkI2SPinMuxInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
+        return HAL_ERR_PARA;
+    }
+
+    // enable system pll
+    I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) | (1<<9) | (1<<10);
+    HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
+
+    switch (pI2SAdapter->DevNum){
+        case I2S0_SEL:
+            ACTCK_I2S_CCTRL(ON);
+            LXBUS_FCTRL(ON); // enable lx bus for i2s
+            
+            /*I2S0 Pin Mux Setting*/
+            PinCtrl(I2S0, pI2SAdapter->PinMux, ON);
+            if (pI2SAdapter->PinMux == I2S_S0) {
+                DBG_I2S_WARN(ANSI_COLOR_MAGENTA"I2S0 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
+            }
+            I2S0_MCK_CTRL(ON);
+            I2S0_PIN_CTRL(ON);
+            I2S0_FCTRL(ON);
+            
+            break;
+        case I2S1_SEL:
+            ACTCK_I2S_CCTRL(ON);
+            LXBUS_FCTRL(ON); // enable lx bus for i2s
+            
+            /*I2S1 Pin Mux Setting*/
+            PinCtrl(I2S1, pI2SAdapter->PinMux, ON);
+            if (pI2SAdapter->PinMux == I2S_S2) {
+                DBG_I2S_WARN(ANSI_COLOR_MAGENTA"I2S1 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
+            }
+            I2S1_MCK_CTRL(ON);
+            I2S1_PIN_CTRL(ON);
+            I2S0_FCTRL(ON); //i2s 1 is control by bit 24 BIT_PERI_I2S0_EN
+            I2S1_FCTRL(ON);
+            break;
+        default:
+            return HAL_ERR_PARA;
+    }
+    
+    return HAL_OK;
+}
+
+
+static HAL_Status
+RtkI2SPinMuxDeInit(
+    IN  PHAL_I2S_ADAPTER pI2SAdapter
+)
+{
+    if (pI2SAdapter->DevNum > I2S_MAX_ID) {
+        DBG_I2S_ERR("RtkI2SPinMuxDeInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
+        return HAL_ERR_PARA;
+    }
+
+    switch (pI2SAdapter->DevNum){
+        case I2S0_SEL:
+            /*I2S0 Pin Mux Setting*/
+            //ACTCK_I2C0_CCTRL(OFF);
+            PinCtrl(I2S0, pI2SAdapter->PinMux, OFF);
+            I2S0_MCK_CTRL(OFF);
+            I2S0_PIN_CTRL(OFF);
+            //I2S0_FCTRL(OFF);
+            
+            break;
+        case I2S1_SEL:
+            /*I2S1 Pin Mux Setting*/
+            //ACTCK_I2C1_CCTRL(OFF);
+            PinCtrl(I2S1, pI2SAdapter->PinMux, OFF);
+            I2S1_MCK_CTRL(OFF);
+            I2S1_PIN_CTRL(OFF);
+            //I2S1_FCTRL(OFF);
+            break;
+        default:
+            return HAL_ERR_PARA;
+    }
+    
+    return HAL_OK;
+}
+
+
+HAL_Status
+RtkI2SInit(
+    IN  VOID *Data
+)
+{
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
+    PHAL_I2S_OP     pHalI2SOP  = &HalI2SOpSAL;
+    PHAL_I2S_INIT_DAT pI2SCfg;
+
+    if (pI2SAdapter == 0) {
+        DBG_I2S_ERR("RtkI2SInit: Null Pointer\r\n");
+        return HAL_ERR_PARA;
+    }
+    
+    if (pI2SAdapter->DevNum > I2S_MAX_ID) {
+        DBG_I2S_ERR("RtkI2SInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
+        return HAL_ERR_PARA;
+    }
+
+    pI2SCfg = pI2SAdapter->pInitDat;
+
+    /*I2S Initialize HAL Operations*/
+    HalI2SOpInit(pHalI2SOP);
+    
+    /*I2S Interrupt Initialization*/
+    RtkI2SIrqInit(pI2SAdapter);
+
+    /*I2S Pin Mux Initialization*/
+    RtkI2SPinMuxInit(pI2SAdapter);
+
+    /*I2S Load User Setting*/
+    pI2SCfg->I2SIdx = pI2SAdapter->DevNum;
+
+    /*I2S HAL Initialization*/
+    pHalI2SOP->HalI2SInit(pI2SCfg);
+
+    /*I2S Device Status Update*/
+    pI2SAdapter->DevSts  = I2S_STS_INITIALIZED;
+    
+    /*I2S Enable Module*/
+    pI2SCfg->I2SEn = I2S_ENABLE;
+    pHalI2SOP->HalI2SEnable(pI2SCfg);
+
+    /*I2S Device Status Update*/
+    pI2SAdapter->DevSts  = I2S_STS_IDLE;    
+    
+    return HAL_OK;
+}
+
+HAL_Status
+RtkI2SDeInit(
+    IN  VOID *Data
+)
+{
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
+    PHAL_I2S_OP     pHalI2SOP  = &HalI2SOpSAL;
+    PHAL_I2S_INIT_DAT pI2SCfg;
+
+    if (pI2SAdapter == 0) {
+        DBG_I2S_ERR("RtkI2SDeInit: Null Pointer\r\n");
+        return HAL_ERR_PARA;
+    }
+
+    pI2SCfg = pI2SAdapter->pInitDat;
+
+    /*I2S Disable Module*/
+    pI2SCfg->I2SEn = I2S_DISABLE;
+    pHalI2SOP->HalI2SEnable(pI2SCfg);
+
+    /*I2C HAL DeInitialization*/
+    //pHalI2SOP->HalI2SDeInit(pI2SCfg);
+    
+    /*I2S Interrupt DeInitialization*/
+    RtkI2SIrqDeInit(pI2SAdapter);
+
+    /*I2S Pin Mux DeInitialization*/
+    RtkI2SPinMuxDeInit(pI2SAdapter);
+    
+    /*I2S HAL DeInitialization*/
+    pHalI2SOP->HalI2SDeInit(pI2SCfg);
+
+    /*I2S Device Status Update*/
+    pI2SAdapter->DevSts  = I2S_STS_UNINITIAL;
+    
+    return HAL_OK;
+}
+
+HAL_Status
+RtkI2SEnable(
+    IN  VOID *Data
+)
+{
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
+    PHAL_I2S_OP     pHalI2SOP  = &HalI2SOpSAL;
+    PHAL_I2S_INIT_DAT pI2SCfg;
+
+    pI2SCfg = pI2SAdapter->pInitDat;
+    pI2SCfg->I2SEn = I2S_ENABLE;
+    pHalI2SOP->HalI2SEnable(pI2SCfg);
+
+    return HAL_OK;
+}
+
+HAL_Status
+RtkI2SDisable(
+    IN  VOID *Data
+)
+{
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
+    PHAL_I2S_OP     pHalI2SOP  = &HalI2SOpSAL;
+    PHAL_I2S_INIT_DAT pI2SCfg;
+
+    pI2SCfg = pI2SAdapter->pInitDat;
+    pI2SCfg->I2SEn = I2S_DISABLE;
+    pHalI2SOP->HalI2SEnable(pI2SCfg);
+
+    HalI2SClearAllOwnBit((VOID*)pI2SCfg);
+
+    return HAL_OK;
+}
+
+RTK_STATUS
+RtkI2SIoCtrl(
+    IN  VOID *Data
+)
+{
+    return _EXIT_SUCCESS;
+}
+
+RTK_STATUS
+RtkI2SPowerCtrl(
+    IN  VOID *Data
+)
+{
+    return _EXIT_SUCCESS;
+}
+
+HAL_Status
+RtkI2SLoadDefault( 
+    IN  VOID *Adapter,
+    IN  VOID *Setting
+)
+{
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Adapter;
+    PHAL_I2S_INIT_DAT pI2SCfg = pI2SAdapter->pInitDat;
+    PHAL_I2S_DEF_SETTING pLoadSetting = (PHAL_I2S_DEF_SETTING)Setting;
+
+    if (pI2SAdapter == 0) {
+        DBG_I2S_ERR("RtkI2SLoadDefault: Null Pointer\r\n");
+        return HAL_ERR_PARA;
+    }
+
+    if (pI2SAdapter->pInitDat == NULL) {
+        DBG_I2S_ERR("RtkI2SLoadDefault: pInitDat is NULL!\r\n", pI2SAdapter->DevNum);
+        return HAL_ERR_PARA;
+    }
+
+    pI2SAdapter->DevSts          = pLoadSetting->DevSts;
+    pI2SAdapter->ErrType         = 0;
+    pI2SAdapter->TimeOut         = 0;
+    
+    pI2SCfg->I2SIdx        = pI2SAdapter->DevNum;
+    pI2SCfg->I2SEn         = I2S_DISABLE;
+    pI2SCfg->I2SMaster     = pLoadSetting->I2SMaster;
+    pI2SCfg->I2SWordLen    = pLoadSetting->I2SWordLen;
+    pI2SCfg->I2SChNum      = pLoadSetting->I2SChNum;
+    pI2SCfg->I2SPageNum    = pLoadSetting->I2SPageNum;
+    pI2SCfg->I2SPageSize   = pLoadSetting->I2SPageSize;
+    pI2SCfg->I2SRate       = pLoadSetting->I2SRate;
+    pI2SCfg->I2STRxAct     = pLoadSetting->I2STRxAct;
+    pI2SCfg->I2STxIntrMSK  = pLoadSetting->I2STxIntrMSK;
+    pI2SCfg->I2SRxIntrMSK  = pLoadSetting->I2SRxIntrMSK;
+
+    return HAL_OK;
+}
+
+VOID HalI2SOpInit(
+    IN  VOID *Data
+)
+{
+    PHAL_I2S_OP pHalI2SOp = (PHAL_I2S_OP) Data;
+
+    pHalI2SOp->HalI2SInit        = HalI2SInitRtl8195a_Patch;
+    pHalI2SOp->HalI2SDeInit      = HalI2SDeInitRtl8195a;
+    pHalI2SOp->HalI2STx          = HalI2STxRtl8195a;
+    pHalI2SOp->HalI2SRx          = HalI2SRxRtl8195a;
+    pHalI2SOp->HalI2SEnable      = HalI2SEnableRtl8195a;
+    pHalI2SOp->HalI2SIntrCtrl    = HalI2SIntrCtrlRtl8195a;
+    pHalI2SOp->HalI2SReadReg     = HalI2SReadRegRtl8195a;
+    pHalI2SOp->HalI2SSetRate     = HalI2SSetRateRtl8195a;
+    pHalI2SOp->HalI2SSetWordLen  = HalI2SSetWordLenRtl8195a;
+    pHalI2SOp->HalI2SSetChNum    = HalI2SSetChNumRtl8195a;
+    pHalI2SOp->HalI2SSetPageNum  = HalI2SSetPageNumRtl8195a;
+    pHalI2SOp->HalI2SSetPageSize = HalI2SSetPageSizeRtl8195a;
+    pHalI2SOp->HalI2SClrIntr     = HalI2SClrIntrRtl8195a;
+    pHalI2SOp->HalI2SClrAllIntr  = HalI2SClrAllIntrRtl8195a;
+    pHalI2SOp->HalI2SDMACtrl     = HalI2SDMACtrlRtl8195a;
+}
+
+

component/soc/realtek/8195a/fwlib/src/hal_mii.c

@@ -0,0 +1,43 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "hal_mii.h"
+
+VOID
+HalMiiOpInit(
+    IN VOID *Data
+    )
+{
+    DBG_ENTRANCE;
+    PHAL_MII_OP pHalMiiOp = (PHAL_MII_OP) Data;
+
+    pHalMiiOp->HalMiiGmacInit          = HalMiiGmacInitRtl8195a;
+    pHalMiiOp->HalMiiInit              = HalMiiInitRtl8195a;
+    pHalMiiOp->HalMiiGmacReset         = HalMiiGmacResetRtl8195a;
+    pHalMiiOp->HalMiiGmacEnablePhyMode = HalMiiGmacEnablePhyModeRtl8195a;
+    pHalMiiOp->HalMiiGmacXmit          = HalMiiGmacXmitRtl8195a;
+    pHalMiiOp->HalMiiGmacCleanTxRing   = HalMiiGmacCleanTxRingRtl8195a;
+    pHalMiiOp->HalMiiGmacFillTxInfo    = HalMiiGmacFillTxInfoRtl8195a;
+    pHalMiiOp->HalMiiGmacFillRxInfo    = HalMiiGmacFillRxInfoRtl8195a;
+    pHalMiiOp->HalMiiGmacTx            = HalMiiGmacTxRtl8195a;
+    pHalMiiOp->HalMiiGmacRx            = HalMiiGmacRxRtl8195a;
+    pHalMiiOp->HalMiiGmacSetDefaultEthIoCmd   = HalMiiGmacSetDefaultEthIoCmdRtl8195a;
+    pHalMiiOp->HalMiiGmacInitIrq       = HalMiiGmacInitIrqRtl8195a;
+    pHalMiiOp->HalMiiGmacGetInterruptStatus   = HalMiiGmacGetInterruptStatusRtl8195a;
+    pHalMiiOp->HalMiiGmacClearInterruptStatus = HalMiiGmacClearInterruptStatusRtl8195a;
+#if 0
+    pHalMiiOp-> = Rtl8195a;
+    pHalMiiOp-> = Rtl8195a;
+    pHalMiiOp-> = Rtl8195a;
+    pHalMiiOp-> = Rtl8195a;
+    pHalMiiOp-> = Rtl8195a;
+#endif
+}
+

component/soc/realtek/8195a/fwlib/src/hal_nfc.c

@@ -0,0 +1,20 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+#include "hal_nfc.h"
+
+VOID HalNFCOpInit(
+    IN  VOID *Data
+)
+{
+
+}
+

component/soc/realtek/8195a/fwlib/src/hal_pcm.c

@@ -0,0 +1,28 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "hal_pcm.h"
+
+VOID HalPcmOpInit(
+    IN  VOID *Data
+)
+{
+    PHAL_PCM_OP pHalPcmOp = (PHAL_PCM_OP) Data;
+
+    pHalPcmOp->HalPcmOnOff = HalPcmOnOffRtl8195a;
+    pHalPcmOp->HalPcmInit = HalPcmInitRtl8195a;
+    pHalPcmOp->HalPcmSetting = HalPcmSettingRtl8195a;
+    pHalPcmOp->HalPcmEn = HalPcmEnRtl8195a;
+    pHalPcmOp->HalPcmIsrEnAndDis= HalPcmIsrEnAndDisRtl8195a;
+    pHalPcmOp->HalPcmDumpReg= HalPcmDumpRegRtl8195a;
+    pHalPcmOp->HalPcm= HalPcmRtl8195a;
+}
+
+

component/soc/realtek/8195a/fwlib/src/hal_pwm.c

@@ -0,0 +1,131 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+ 
+
+#include "rtl8195a.h"
+
+#ifdef CONFIG_PWM_EN
+#include "hal_pwm.h"
+#include "hal_timer.h"
+
+HAL_PWM_ADAPTER PWMPin[MAX_PWM_CTRL_PIN];
+const u8 PWMTimerIdx[MAX_PWM_CTRL_PIN]= {3,4,5,6};  // the G-timer ID used for PWM pin 0~3
+
+/**
+  * @brief  Initializes and enable a PWM control pin.
+  *
+  * @param  pwm_id: the PWM pin index
+  * @param  sel: pin mux selection
+  *
+  * @retval HAL_Status
+  */
+HAL_Status 
+HAL_Pwm_Init(
+    u32 pwm_id,
+    u32 sel
+)
+{
+    HAL_PWM_ADAPTER *pPwmAdapt;
+    u32 timer_id;
+
+    DBG_PWM_INFO("%s: Init PWM for PWM %d, Sel %d\n", __FUNCTION__, pwm_id, sel);
+
+    if ((pwm_id >= MAX_PWM_CTRL_PIN) || (sel > 3)) {
+        DBG_PWM_ERR ("HAL_Pwm_Init: Invalid PWM index(%d), sel(%d)\n", pwm_id, sel);
+        return HAL_ERR_PARA;
+    }
+    
+    pPwmAdapt = &PWMPin[pwm_id];
+    pPwmAdapt->pwm_id = pwm_id;
+    pPwmAdapt->sel = sel;
+    timer_id = PWMTimerIdx[pwm_id];
+    pPwmAdapt->gtimer_id = timer_id;
+    
+    return HAL_Pwm_Init_8195a (pPwmAdapt);
+}
+
+
+/**
+  * @brief  Disable a PWM control pin.
+  *
+  * @param  pwm_id: the PWM pin index
+  *
+  * @retval None
+  */
+void 
+HAL_Pwm_Enable(
+    u32 pwm_id
+)
+{
+    HAL_PWM_ADAPTER *pPwmAdapt;
+        
+    if (pwm_id >= MAX_PWM_CTRL_PIN) {
+        DBG_PWM_ERR ("HAL_Pwm_Enable: Invalid PWM index(%d)\n", pwm_id);
+        return;
+    }
+    pPwmAdapt = &PWMPin[pwm_id];
+    
+    HAL_Pwm_Enable_8195a(pPwmAdapt);
+}
+
+
+/**
+  * @brief  Disable a PWM control pin.
+  *
+  * @param  pwm_id: the PWM pin index
+  *
+  * @retval None
+  */
+void 
+HAL_Pwm_Disable(
+    u32 pwm_id
+)
+{
+    HAL_PWM_ADAPTER *pPwmAdapt;
+        
+    if (pwm_id >= MAX_PWM_CTRL_PIN) {
+        DBG_PWM_ERR ("HAL_Pwm_Disable: Invalid PWM index(%d)\n", pwm_id);
+        return;
+    }
+    pPwmAdapt = &PWMPin[pwm_id];
+    
+    HAL_Pwm_Disable_8195a(pPwmAdapt);
+}
+
+/**
+  * @brief  Set the duty ratio of the PWM pin.
+  *
+  * @param  pwm_id: the PWM pin index
+  * @param  period: the period time, in micro-second.
+  * @param  pulse_width: the pulse width time, in micro-second.
+  *
+  * @retval None
+  */
+void
+HAL_Pwm_SetDuty(
+    u32 pwm_id,
+    u32 period,
+    u32 pulse_width
+)
+{
+    HAL_PWM_ADAPTER *pPwmAdapt;
+
+    if (pwm_id >= MAX_PWM_CTRL_PIN) {
+        DBG_PWM_ERR ("HAL_Pwm_SetDuty: Invalid PWM index(%d)\n", pwm_id);
+        return;
+    }
+
+//    DBG_PWM_INFO("%s: Period%d Pulse%d\n", __FUNCTION__, period, pulse_width);
+    pPwmAdapt = &PWMPin[pwm_id];
+
+    HAL_Pwm_SetDuty_8195a(pPwmAdapt, period, pulse_width);
+}
+
+
+#endif  // end of "#ifdef CONFIG_PWM_EN"

component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c

@@ -0,0 +1,962 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+#include "rtl8195a.h"
+#include "hal_sdr_controller.h"
+#include "rtl8195a_sdr.h"
+#if 0
+#define HAL_SDR_WRITE32(addr, value32)  HAL_WRITE32(SDR_CTRL_BASE, addr, value32)
+#define HAL_SDR_WRITE16(addr, value16)  HAL_WRITE16(SDR_CTRL_BASE, addr, value16)
+#define HAL_SDR_WRITE8(addr, value8)    HAL_WRITE8(SDR_CTRL_BASE, addr, value8)
+#define HAL_SDR_READ32(addr)            HAL_READ32(SDR_CTRL_BASE, addr)
+#define HAL_SDR_READ16(addr)            HAL_READ16(SDR_CTRL_BASE, addr)
+#define HAL_SDR_READ8(addr)             HAL_READ8(SDR_CTRL_BASE, addr)
+
+#define HAL_SDRAM_WRITE32(addr, value32)  HAL_WRITE32(SDR_SDRAM_BASE, addr, value32)
+#define HAL_SDRAM_WRITE16(addr, value16)  HAL_WRITE16(SDR_SDRAM_BASE, addr, value16)
+#define HAL_SDRAM_WRITE8(addr, value8)    HAL_WRITE8(SDR_SDRAM_BASE, addr, value8)
+#define HAL_SDRAM_READ32(addr)            HAL_READ32(SDR_SDRAM_BASE, addr)
+#define HAL_SDRAM_READ16(addr)            HAL_READ16(SDR_SDRAM_BASE, addr)
+#define HAL_SDRAM_READ8(addr)             HAL_READ8(SDR_SDRAM_BASE, addr)
+#endif
+
+
+
+HAL_CUT_B_RAM_DATA_SECTION
+DRAM_INFO SdrDramDev = {
+  DRAM_INFO_TYPE,
+  DRAM_INFO_COL_ADDR_WTH, 
+  DRAM_INFO_BANK_SZ, 
+  DRAM_INFO_DQ_WTH
+};
+
+
+HAL_CUT_B_RAM_DATA_SECTION
+DRAM_MODE_REG_INFO SdrDramModeReg = {
+  BST_LEN_4, 
+  SENQUENTIAL,
+  0x3, // Mode0Cas: 3 
+  0x0, // Mode0Wr 
+  0,   // Mode1DllEnN  
+  0,   // Mode1AllLat  
+  0    // Mode2Cwl   
+};
+
+HAL_CUT_B_RAM_DATA_SECTION
+DRAM_TIMING_INFO SdrDramTiming = {
+  DRAM_TIMING_TRFC,         // TrfcPs;
+  DRAM_TIMING_TREFI,        // TrefiPs;
+  DRAM_TIMING_TWRMAXTCK,    // WrMaxTck;
+  DRAM_TIMING_TRCD,         // TrcdPs; 
+  DRAM_TIMING_TRP,          // TrpPs;
+  DRAM_TIMING_TRAS,         // TrasPs;
+  DRAM_TIMING_TRRD,         // TrrdTck;
+  DRAM_TIMING_TWR,          // TwrPs;
+  DRAM_TIMING_TWTR,         // TwtrTck; 
+  //13090,      // TrtpPs;
+  DRAM_TIMING_TMRD,         // TmrdTck;
+  DRAM_TIMING_TRTP,         // TrtpTck;
+  DRAM_TIMING_TCCD,         // TccdTck;
+  DRAM_TIMING_TRC           // TrcPs;
+};
+
+HAL_CUT_B_RAM_DATA_SECTION
+DRAM_DEVICE_INFO SdrDramInfo = {
+  &SdrDramDev,
+  &SdrDramModeReg,
+  &SdrDramTiming,
+  DRAM_TIMING_TCK,
+  DFI_RATIO_1
+};
+
+
+#define FPGA
+#define FPGA_TEMP
+#define SDR_CLK_DLY_CTRL 0x40000300
+#define MIN_RD_PIPE 0x0
+#define MAX_RD_PIPE 0x7
+
+#define SUPPORT_DRAM_KED
+
+
+#ifdef FPGA
+#ifdef FPGA_TEMP
+#define MAX_TAP_DLY 0xC
+#else
+#define MAX_TAP_DLY 0x7F
+#define SPEC_MAX_TAP 0xFF
+#endif
+#else
+#define MAX_TAP_DLY 99		// 0~99
+#define SPEC_MAX_TAP 99
+#define WINDOW_COMBIN		// combine window [0~a] and [b~99] (for asic mode)
+#endif
+ 
+#define TAP_DLY 0x1
+#define REC_NUM 512
+ 
+ 
+u32 SdrControllerInit(VOID);
+VOID DramInit(DRAM_DEVICE_INFO *);
+s32 MemTest(u32 loop_cnt);
+u32 SdrCalibration(VOID);
+u32 Sdr_Rand2(VOID);
+
+//3 Note: stack overfloat if the arrary is declared in the task
+HAL_CUT_B_RAM_DATA_SECTION
+u32  AvaWds[2][REC_NUM];
+
+HAL_CUT_B_RAM_DATA_SECTION
+unsigned int rand_x = 123456789;
+
+#ifdef CONFIG_SDR_EN
+
+#ifdef CONFIG_SDR_VERIFY
+enum{
+	LLT,
+    TXRPT,
+    RXBUFF,
+	TXBUFF,	
+};
+#define REPORT_OFFSET   0x8000
+#define RAMASK_OFFSET   0x8800
+#define LLT_H_ADDR      0x650
+#define TXREPORT_H_ADDR 0x660
+#define RXBUFF_H_ADDR   0x670
+#define TXBUFF_H_ADDR   0x680
+
+#define REG_PKTBUF_DBG_CTRL_8723B		0x0140
+
+int
+rt_rpt_h_addr(u8 rpt)
+{
+    u32 r_val, offset;
+    
+    if (rpt == LLT){
+        offset = LLT_H_ADDR;
+    }
+    else if (rpt == TXRPT){
+        offset = TXREPORT_H_ADDR;
+    }
+    else if (rpt == RXBUFF){
+        offset = RXBUFF_H_ADDR;
+    }
+    else if (rpt == TXBUFF){
+        offset = TXBUFF_H_ADDR;
+    }
+    else {
+    }
+
+    r_val = ((HAL_READ32(WIFI_REG_BASE, REG_PKTBUF_DBG_CTRL_8723B)&0xFFFFF000)|offset);
+    HAL_WRITE32(WIFI_REG_BASE, REG_PKTBUF_DBG_CTRL_8723B, r_val);
+}
+
+
+
+int
+rt_txrpt_read32(u8 macid, u8 offset)
+{
+    u32 r_val;
+    
+    rt_rpt_h_addr(TXRPT);
+    r_val = HAL_READ32(WIFI_REG_BASE, (REPORT_OFFSET + macid*4 + offset));
+    
+    return r_val;
+}
+
+int
+rt_txrpt_read16(u8 macid, u8 offset)
+{
+    u16 r_val;
+    
+    rt_rpt_h_addr(TXRPT);
+    r_val = HAL_READ16(WIFI_REG_BASE, (REPORT_OFFSET + macid*8 + offset));
+    
+    return r_val;
+}
+
+int
+rt_txrpt_read8(u8 macid, u8 offset)
+{
+    u8 r_val;
+    
+    rt_rpt_h_addr(TXRPT);
+    r_val = HAL_READ8(WIFI_REG_BASE, (REPORT_OFFSET + macid*16 + offset));
+    
+    return r_val;
+}
+
+int
+rt_txrpt_read_1b(u8 macid, u8 offset, u8 bit_offset)
+{
+    u8 r_val = ((rt_txrpt_read8(macid, offset) & BIT(bit_offset))?1:0);
+
+    return r_val;
+}
+
+
+int
+rt_txrpt_write32(u8 macid, u8 offset, u32 val)
+{
+    rt_rpt_h_addr(TXRPT);
+    HAL_WRITE32(WIFI_REG_BASE, (REPORT_OFFSET + macid*4 + offset), val);
+}
+
+int
+rt_txrpt_write16(u8 macid, u8 offset, u16 val)
+{
+    rt_rpt_h_addr(TXRPT);
+    HAL_WRITE16(WIFI_REG_BASE, (REPORT_OFFSET + macid*8 + offset), val);
+}
+
+int
+rt_txrpt_write8(u8 macid, u8 offset, u8 val)
+{
+    rt_rpt_h_addr(TXRPT);
+    DBG_8195A("Write addr %x %x\n", (REPORT_OFFSET + macid*16 + offset), val);
+    HAL_WRITE8(WIFI_REG_BASE, (REPORT_OFFSET + macid*16 + offset), val);
+}
+
+int
+rt_txrpt_write_1b(u8 macid, u8 offset, u8 bit_offset, u8 val)
+{
+    u8 r_val = rt_txrpt_read8(macid, offset);
+
+    if (val){
+        r_val |= BIT(bit_offset);
+    }
+    else {
+        r_val &= (~BIT(bit_offset));
+    }
+    
+    HAL_WRITE8(WIFI_REG_BASE, (REPORT_OFFSET + macid*16 + offset), r_val);
+}
+
+
+u8
+ReadTxrptsdr8(
+    IN u8 Macid,
+    IN u8 Offset)
+{
+    u8 r_val;
+    
+    r_val = rt_txrpt_read8(Macid, Offset);
+    return r_val;
+}
+
+VOID
+WriteTxrptsdr8(
+    IN u8 Macid,
+    IN u8 Offset,
+    IN u8 Val)
+{
+    rt_txrpt_write8(Macid, Offset, Val);
+}
+
+VOID 
+SdrTestApp(
+    IN  VOID *Data
+)
+{
+    u32 *Cmd =(u32*)Data;
+    u32 Loop, LoopIndex, Value32, Addr, Loop1, LoopIndex1;
+
+    switch (Cmd[0]) {
+        case 1:
+                DBG_8195A("Initial SDR\n");
+
+                //1 "SdrControllerInit" is located in Image1, so we shouldn't call it in Image2 
+                if (!SdrControllerInit()) {
+                    DBG_8195A("SDR Calibartion Fail!!!!\n");
+                }
+            break;
+        case 2:
+                Loop = Cmd[1];
+                Loop1 = Cmd[2];
+                DBG_8195A("Verify SDR: Loop = 0x%08x Loop1 = 0x%08x\n",Loop, Loop1);
+                
+                for (LoopIndex1=0; LoopIndex1 < Loop1; LoopIndex1++) {
+                
+                for (LoopIndex=0; LoopIndex < Loop; LoopIndex++) {
+                    Value32 = Rand2();
+                    Addr = Rand2();
+                    Addr &= 0x1FFFFF;
+                    Addr &= (~0x3);
+
+                        if (!(LoopIndex & 0xFFFFF)) {
+                            DBG_8195A("Alive: LOOP = 0x%08x, LOOP = 0x%08x\n",LoopIndex1, LoopIndex);
+                    }
+
+                    //        DBG_8195A("Value: 0x%x; Addr: 0x%x\n", Value32, Addr+SDR_SDRAM_BASE);        
+                    HAL_SDRAM_WRITE32(Addr, Value32);
+
+                    if (Value32 != HAL_SDRAM_READ32(Addr)) {
+                        DBG_8195A("Loop:%d; Addr: 0x%08x => CheckData error: W: 0x%08x /R:0x%x\n"
+                            ,LoopIndex
+                            ,Addr
+                            ,Value32
+                            ,HAL_SDRAM_READ32(Addr));
+
+                            HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO2, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO2)+1);
+                        break;
+                    }        
+                }            
+                }
+                DBG_8195A("Verify SDR Success\n");
+            break;
+
+        case 3:
+            DBG_8195A("WL read RPT MACID %x\n", Cmd[1]);
+            {
+                u8 i =0;
+                for(i=0;i<16;i++) {
+                    DBG_8195A("WL RPT offset %d = %x\n", i, ReadTxrptsdr8(Cmd[1],i));
+                }
+            }
+            break;
+        case 4:
+            DBG_8195A("WL write RPT MACID %x\n", Cmd[1]);
+            {
+                u8 i =0;
+                for(i=0;i<16;i++) {
+                    WriteTxrptsdr8(Cmd[1],i,Cmd[2]);
+                    //DBG_8195A("WL RPT offset %d = %x\n", i, ReadTxrptsdr8(Cmd[1],i));
+                }
+            }
+            break;
+        default:
+            break;
+    }
+    
+}
+    
+#endif
+
+HAL_SDRC_TEXT_SECTION  
+u32 
+SdrControllerInit(
+VOID
+)
+{
+    DBG_8195A("SDR Controller Init\n");
+
+    SRAM_MUX_CFG(0x2);
+
+    SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE);
+
+    HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4,0);
+
+    ACTCK_SDR_CCTRL(ON);
+
+    SLPCK_SDR_CCTRL(ON);
+
+    PinCtrl(SDR, 0, ON);
+
+    HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4,0);
+
+    //MEM_CTRL_FCTRL(OFF);
+
+    MEM_CTRL_FCTRL(ON);
+     
+    LDO25M_CTRL(ON);
+
+    HalDelayUs(3000);
+     
+    // sdr initialization
+    DramInit(&SdrDramInfo);
+
+    // sdr calibration
+    if(!SdrCalibration()) {
+        return 0;
+    }
+    else {
+        return 1;
+    }
+}
+
+
+HAL_SDRC_TEXT_SECTION 
+VOID
+DramInit (
+    IN  DRAM_DEVICE_INFO *DramInfo
+)
+{
+    u32 CsBstLen = 0;            // 0:bst_4, 1:bst_8
+    u32 CasWr = 0;//, CasWrT;       // cas write latency
+    u32 CasRd = 0, CasRdT = 0, CrlSrt = 0;  // cas read latency
+    u32 AddLat;
+    u32 DramEmr2 = 0, DramMr0 = 0;
+    u32 CrTwr, DramMaxWr, DramWr;
+    u32 CrTrtw = 0, CrTrtwT = 0;
+    u32 DrmaPeriod; 
+    DRAM_TYPE         DdrType;
+    DRAM_DQ_WIDTH     DqWidth;
+    DRAM_COLADDR_WTH    Page;
+    u32 DfiRate;
+    volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
+    ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
+    ms_ctrl_0_map = ms_ctrl_0_map;
+
+    DfiRate = 1 << (u32) (DramInfo->DfiRate);
+    DrmaPeriod = (DramInfo->DdrPeriodPs)*(DfiRate); // according DFI_RATE to setting
+
+    // In PHY, write latency == 3
+    DramMaxWr= (DramInfo->Timing->WrMaxTck)/(DfiRate) +1;
+    DramWr = ((DramInfo->Timing->TwrPs) / DrmaPeriod)+1;
+    CrTwr = ((DramInfo->Timing->TwrPs) / DrmaPeriod) + 3;
+
+    if (CrTwr < DramMaxWr) {
+        CrTwr = CrTwr;
+    }
+    else {
+        CrTwr = DramMaxWr;
+    }
+
+    if ((DramInfo->Dev->DeviceType) == DRAM_DDR_2) {
+        DdrType = DRAM_DDR_2;
+        if (DramInfo->ModeReg->BstLen == BST_LEN_4) {
+            CsBstLen = 0; //bst_4
+            CrTrtwT = 2+2;    //4/2+2
+            DramMr0 = 0x2;
+        }
+        else { // BST_LEN_8
+            CsBstLen = 1; // bst_8
+            CrTrtwT = 4+2;    // 8/2+2
+            DramMr0 = 0x3;
+        }
+        CasRd = DramInfo->ModeReg->Mode0Cas;
+        AddLat = DramInfo->ModeReg ->Mode1AllLat;
+        CasWr = CasRd + AddLat -1;
+        DramEmr2 = 0;
+     
+        DramMr0  =(((DramWr%6)-1)                  << (PCTL_MR_OP_BFO+1)) | // write_recovery
+                   (0                                << PCTL_MR_OP_BFO    ) | // dll
+                   (DramInfo->ModeReg->Mode0Cas << PCTL_MR_CAS_BFO   ) |
+                   (DramInfo->ModeReg->BstType  << PCTL_MR_BT_BFO    ) |
+                   DramMr0;
+    }
+    else if ((DramInfo->Dev->DeviceType) == DRAM_DDR_3) {
+        DdrType = DRAM_DDR_3;
+        if (DramInfo->ModeReg->BstLen == BST_LEN_4) {
+            CsBstLen = 0; //bst_4
+            DramMr0 = 0x2;
+        }
+        else { // BST_LEN_8
+            CsBstLen = 1; // bst_8
+            DramMr0 = 0x0;
+        }
+
+        CrlSrt = (DramInfo->ModeReg->Mode0Cas >> 1);
+        if (((DramInfo->ModeReg->Mode0Cas) & 0x1) ) {
+            CasRdT = CrlSrt+ 12;
+        }
+        else {
+            CasRdT = CrlSrt+ 4;
+        }
+
+        if (DramInfo->ModeReg->Mode1AllLat == 1) { // CL-1
+            AddLat = CasRd -1;
+        }
+        else if (DramInfo->ModeReg->Mode1AllLat == 2){ // CL-2
+            AddLat = CasRd -2;
+        }
+        else {
+            AddLat = 0;
+        }
+
+        CasRd = CasRdT + AddLat;
+
+        CasWr =  DramInfo->ModeReg->Mode2Cwl + 5 + AddLat;
+
+        DramEmr2 = DramInfo->ModeReg->Mode2Cwl << 3;
+
+        if (DramWr == 16) {
+            DramWr = 0;
+        }
+        else if (DramWr <= 9) {  // 5< wr <= 9
+            DramWr = DramWr - 4;
+        }
+        else {
+            DramWr = (DramWr + 1) / 2;
+        }
+
+        DramMr0  =(DramWr                            << (PCTL_MR_OP_BFO+1) ) | // write_recovery
+                (0                                   << PCTL_MR_OP_BFO     ) | // dll
+                ((DramInfo->ModeReg->Mode0Cas >>1 )  << PCTL_MR_CAS_BFO    ) |
+                (DramInfo->ModeReg->BstType          << PCTL_MR_BT_BFO     ) |
+                ((DramInfo->ModeReg->Mode0Cas & 0x1) << 2                  ) |
+                DramMr0;
+
+        CrTrtwT = (CasRdT + 6) - CasWr;
+
+    }  // ddr2/ddr3
+    else if ((DramInfo->Dev->DeviceType) == DRAM_SDR) {
+            DdrType = DRAM_SDR;
+        if (DramInfo->ModeReg->BstLen == BST_LEN_4) {
+            DramMr0 = 2; // bst_4
+            CsBstLen = 0; //bst_4
+            CasRd = 0x2;
+        }
+        else { // BST_LEN_8
+            DramMr0 = 3; // bst_8
+            CsBstLen = 1; // bst_8
+            CasRd  = 0x3;
+        }
+
+        CasWr = 0;
+
+        DramMr0  =(CasRd                    << PCTL_MR_CAS_BFO) |
+                (DramInfo->ModeReg->BstType << PCTL_MR_BT_BFO ) |
+                DramMr0;
+
+        CrTrtwT = 0; // tic: CasRd + rd_rtw + rd_pipe
+    } // SDR
+
+
+     // countting tRTW
+    if ((CrTrtwT & 0x1)) {
+        CrTrtw = (CrTrtwT+1) /(DfiRate);
+    }
+    else {
+        CrTrtw = CrTrtwT /(DfiRate);
+    }
+
+    DqWidth = (DramInfo->Dev->DqWidth); 
+    Page = DramInfo->Dev->ColAddrWth +1; // DQ16 -> memory:byte_unit *2
+    if (DqWidth == DRAM_DQ_32) { // paralle dq_16 => Page + 1
+        Page = Page +1;
+    }
+#if 1
+    
+    // WRAP_MISC setting
+    HAL_SDR_WRITE32(REG_SDR_MISC,(
+                           (Page                 << WRAP_MISC_PAGE_SIZE_BFO) |  
+                           (DramInfo->Dev->Bank  << WRAP_MISC_BANK_SIZE_BFO) |
+                           (CsBstLen             << WRAP_MISC_BST_SIZE_BFO ) |
+                           (DqWidth              << WRAP_MISC_DDR_PARAL_BFO)
+                          ));
+    // PCTL setting
+    HAL_SDR_WRITE32(REG_SDR_DCR,(
+                          (0x2      << PCTL_DCR_DFI_RATE_BFO) |
+                          (DqWidth << PCTL_DCR_DQ32_BFO    ) |
+                          (DdrType << PCTL_DCR_DDR3_BFO    )
+                         ));
+
+    HAL_SDR_WRITE32(REG_SDR_IOCR,(
+                           ((CasRd -4)/(DfiRate)  << PCTL_IOCR_TPHY_RD_EN_BFO ) |
+                           (0                        << PCTL_IOCR_TPHY_WL_BFO   ) |
+                           (((CasWr -3)/(DfiRate)) << PCTL_IOCR_TPHY_WD_BFO   ) |
+                           (0                        << PCTL_IOCR_RD_PIPE_BFO   )
+                          ));
+
+    if ((DramInfo->Dev->DeviceType) != SDR) { // DDR2/3 
+        HAL_SDR_WRITE32(REG_SDR_EMR2,DramEmr2);
+        HAL_SDR_WRITE32(REG_SDR_EMR1,(
+                                (1               << 2 ) | //RTT
+                                (1               << 1 ) | //D.I.C
+                                (DramInfo->ModeReg->Mode1DllEnN )
+                                ));
+     } // DDR2/3
+
+    HAL_SDR_WRITE32(REG_SDR_MR,DramMr0);
+
+    HAL_SDR_WRITE32(REG_SDR_DRR, (
+                      (0                                             << PCTL_DRR_REF_DIS_BFO) |
+                      (9                                             << PCTL_DRR_REF_NUM_BFO) |
+                      ((((DramInfo->Timing->TrefiPs)/DrmaPeriod)+1) << PCTL_DRR_TREF_BFO   ) |
+                      ((((DramInfo->Timing->TrfcPs)/DrmaPeriod)+1)  << PCTL_DRR_TRFC_BFO   )
+                     ));
+
+    HAL_SDR_WRITE32(REG_SDR_TPR0,(
+                      ((((DramInfo->Timing->TrtpTck)/DfiRate)+1)   << PCTL_TPR0_TRTP_BFO) |
+                      (CrTwr                                        << PCTL_TPR0_TWR_BFO ) |
+                      ((((DramInfo->Timing->TrasPs)/DrmaPeriod)+1) << PCTL_TPR0_TRAS_BFO) |
+                      ((((DramInfo->Timing->TrpPs)/DrmaPeriod)+1)  << PCTL_TPR0_TRP_BFO )
+                     ));
+
+    HAL_SDR_WRITE32(REG_SDR_TPR1, (
+                    (CrTrtw                                       << PCTL_TPR1_TRTW_BFO) |
+                    ((((DramInfo->Timing->TwtrTck)/DfiRate)+3)   << PCTL_TPR1_TWTR_BFO) |
+                    ((((DramInfo->Timing->TccdTck)/DfiRate)+1)   << PCTL_TPR1_TCCD_BFO) |
+                    ((((DramInfo->Timing->TrcdPs)/DrmaPeriod)+1) << PCTL_TPR1_TRCD_BFO) |
+                    ((((DramInfo->Timing->TrcPs)/DrmaPeriod)+1)  << PCTL_TPR1_TRC_BFO ) |
+                    (((DramInfo->Timing->TrrdTck/DfiRate)+1)     << PCTL_TPR1_TRRD_BFO)
+                    ));
+
+    HAL_SDR_WRITE32(REG_SDR_TPR2, (
+                        (DramInfo->Timing->TmrdTck << PCTL_TPR2_TMRD_BFO ) |
+                        (0                         << PCTL_TPR2_INIT_NS_EN_BFO  ) |
+                        (2                         << PCTL_TPR2_INIT_REF_NUM_BFO)
+                        ));
+
+    // set all_mode _idle
+    HAL_SDR_WRITE32(REG_SDR_CSR,0x700);
+
+    // start to init
+    HAL_SDR_WRITE32(REG_SDR_CCR,0x01);
+    while ((HAL_SDR_READ32(REG_SDR_CCR)& 0x1) == 0x0);
+
+    // enter mem_mode
+    HAL_SDR_WRITE32(REG_SDR_CSR,0x600);
+#else
+    // WRAP_MISC setting
+    ms_ctrl_0_map->misc = //0x12;
+                          (
+                           (Page                   << WRAP_MISC_PAGE_SIZE_BFO) |  
+                           (DramInfo->Dev->Bank << WRAP_MISC_BANK_SIZE_BFO) |
+                           (CsBstLen             << WRAP_MISC_BST_SIZE_BFO ) |
+                           (DqWidth               << WRAP_MISC_DDR_PARAL_BFO)
+                          );
+    // PCTL setting
+    ms_ctrl_0_map->dcr = //0x208;
+                         (
+                          (0x2      << PCTL_DCR_DFI_RATE_BFO) |
+                          (DqWidth << PCTL_DCR_DQ32_BFO    ) |
+                          (DdrType << PCTL_DCR_DDR3_BFO    )
+                         );
+
+    ms_ctrl_0_map->iocr = (
+                           ((CasRd -4)/(DfiRate)  << PCTL_IOCR_TPHY_RD_EN_BFO ) |
+                           (0                        << PCTL_IOCR_TPHY_WL_BFO   ) |
+                           (((CasWr -3)/(DfiRate)) << PCTL_IOCR_TPHY_WD_BFO   ) |
+                           (0                        << PCTL_IOCR_RD_PIPE_BFO   )
+                          );
+
+    if ((DramInfo->Dev->DeviceType) != SDR) { // DDR2/3 
+        ms_ctrl_0_map->emr2 = DramEmr2;
+
+        ms_ctrl_0_map->emr1 = (
+                                (1               << 2 ) | //RTT
+                                (1               << 1 ) | //D.I.C
+                                (DramInfo->ModeReg->Mode1DllEnN )
+                                );
+    } // DDR2/3
+
+    ms_ctrl_0_map->mr = DramMr0;
+
+    ms_ctrl_0_map->drr = (
+                      (0                                                 << PCTL_DRR_REF_DIS_BFO) |
+                      (9                                                 << PCTL_DRR_REF_NUM_BFO) |
+                      ((((DramInfo->Timing->TrefiPs)/DrmaPeriod)+1)<< PCTL_DRR_TREF_BFO   ) |
+                      ((((DramInfo->Timing->TrfcPs)/DrmaPeriod)+1) << PCTL_DRR_TRFC_BFO   )
+                     );
+
+    ms_ctrl_0_map->tpr0= (
+                      ((((DramInfo->Timing->TrtpTck)/DfiRate)+1)   << PCTL_TPR0_TRTP_BFO) |
+                      (CrTwr                                            << PCTL_TPR0_TWR_BFO ) |
+                      ((((DramInfo->Timing->TrasPs)/DrmaPeriod)+1) << PCTL_TPR0_TRAS_BFO) |
+                      ((((DramInfo->Timing->TrpPs)/DrmaPeriod)+1)  << PCTL_TPR0_TRP_BFO )
+                     );
+
+    ms_ctrl_0_map->tpr1= (
+                    (CrTrtw                                           << PCTL_TPR1_TRTW_BFO) |
+                    ((((DramInfo->Timing->TwtrTck)/DfiRate)+3)   << PCTL_TPR1_TWTR_BFO) |
+                    ((((DramInfo->Timing->TccdTck)/DfiRate)+1)   << PCTL_TPR1_TCCD_BFO) |
+                    ((((DramInfo->Timing->TrcdPs)/DrmaPeriod)+1) << PCTL_TPR1_TRCD_BFO) |
+                    ((((DramInfo->Timing->TrcPs)/DrmaPeriod)+1)  << PCTL_TPR1_TRC_BFO ) |
+                    (((DramInfo->Timing->TrrdTck/DfiRate)+1)     << PCTL_TPR1_TRRD_BFO)
+                    );
+
+    ms_ctrl_0_map->tpr2= (
+                        (DramInfo->Timing->TmrdTck << PCTL_TPR2_TMRD_BFO ) |
+                        (0                         << PCTL_TPR2_INIT_NS_EN_BFO  ) |
+                        (2                         << PCTL_TPR2_INIT_REF_NUM_BFO)
+                        );
+    // set all_mode _idle
+    ms_ctrl_0_map->csr = 0x700;
+
+    // start to init
+    ms_ctrl_0_map->ccr = 0x1;
+    while (((ms_ctrl_0_map->ccr)& 0x1) == 0x0);
+
+    // enter mem_mode
+    ms_ctrl_0_map->csr= 0x600;
+#endif
+} // DramInit
+
+ //3 
+extern void *
+_memset( void *s, int c, SIZE_T n );
+
+HAL_SDRC_TEXT_SECTION
+u32 
+SdrCalibration(
+    VOID
+)
+{
+#ifdef FPGA
+#ifdef FPGA_TEMP
+//    u32 Value32;
+#endif
+#else
+//    u32 Value32;
+#endif
+    u32 RdPipe = 0, TapCnt = 0, Pass = 0, AvaWdsCnt = 0;
+    u32 RdPipeCounter, RecNum[2], RecRdPipe[2];//, AvaWds[2][REC_NUM];
+    BOOL RdPipeFlag, PassFlag = 0, Result; 
+    
+    Result = _FALSE;
+
+#ifdef SUPPORT_DRAM_KED
+	// read calibration data from system data 0x5d~0x6c
+	SPIC_INIT_PARA SpicInitPara;	
+	u32 valid;
+	union { u8 b[4]; u32 l;} value;
+	u32 CpuType = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4);
+	
+	valid = RdPipe = TapCnt = 0xFFFFFFFF;
+	value.l	= HAL_READ32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType);
+	if((value.b[0]^value.b[1])==0xFF)
+		valid = value.b[0];
+	//DiagPrintf("dump1 %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
+	value.l	= HAL_READ32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType+4);
+	if((value.b[0]^value.b[1])==0xFF)
+		RdPipe = value.b[0];
+	if((value.b[2]^value.b[3])==0xFF)
+		TapCnt = value.b[2];	
+	//DiagPrintf("dump2 %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
+		
+	if((valid==1)&&(RdPipe!=0xFFFFFFFF)&&(TapCnt!=0xFFFFFFFF)){
+		// wait DRAM settle down
+		HalDelayUs(10);
+		// load previous dram Ked data
+		HAL_SDR_WRITE32(REG_SDR_IOCR, ((HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | (RdPipe << PCTL_IOCR_RD_PIPE_BFO)));
+		SDR_DDL_FCTRL(TapCnt);
+		if(MemTest(3))
+			return _TRUE;
+	}	
+#endif	
+
+    _memset((u8*)AvaWds, 0, sizeof(u32)*REC_NUM*2);
+
+    volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
+    ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
+    ms_ctrl_0_map = ms_ctrl_0_map;
+    PassFlag = PassFlag;
+    RdPipeCounter =0;
+
+//    DBG_8195A("%d\n",__LINE__);
+ 
+    for(RdPipe=MIN_RD_PIPE; RdPipe<=MAX_RD_PIPE; RdPipe++) {
+//        ms_ctrl_0_map->iocr = (ms_ctrl_0_map->iocr & 0xff) | (RdPipe << PCTL_IOCR_RD_PIPE_BFO);
+        HAL_SDR_WRITE32(REG_SDR_IOCR, ((HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | (RdPipe << PCTL_IOCR_RD_PIPE_BFO)));
+
+        DBG_SDR_INFO("IOCR: 0x%x; Write: 0x%x\n",HAL_SDR_READ32(REG_SDR_IOCR), (RdPipe << PCTL_IOCR_RD_PIPE_BFO));        
+//        DBG_8195A("IOCR: 0x%x; Write: 0x%x\n",ms_ctrl_0_map->iocr, (RdPipe << PCTL_IOCR_RD_PIPE_BFO));
+
+        RdPipeFlag = _FALSE;
+        PassFlag = _FALSE;
+        AvaWdsCnt = 0;
+
+        for(TapCnt=0; TapCnt < (MAX_TAP_DLY+1); TapCnt++) {
+            // Modify clk delay
+#ifdef FPGA
+#ifdef FPGA_TEMP
+            SDR_DDL_FCTRL(TapCnt);
+//            Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF);
+//            Value32 = (Value32 | (TapCnt << 16));
+//            WR_DATA(SDR_CLK_DLY_CTRL, Value32);
+#else
+            HAL_SDR_WRITE32(REG_SDR_DLY0, TapCnt);
+//            ms_ctrl_0_map->phy_dly0 = TapCnt;
+#endif
+            DBG_SDR_INFO("DLY: 0x%x; Write: 0x%x\n",HAL_PERI_ON_READ32(REG_PESOC_MEM_CTRL), TapCnt);
+#else
+            SDR_DDL_FCTRL(TapCnt);
+//            Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF);
+//            Value32 = (Value32 | (TapCnt << 16));
+//            WR_DATA(SDR_CLK_DLY_CTRL, Value32);
+#endif
+
+            Pass = MemTest(10000);
+            PassFlag = _FALSE;
+
+            if(Pass==_TRUE) {   // PASS
+
+                if (!RdPipeFlag) {
+                    DBG_SDR_INFO("%d Time Pass\n", RdPipeCounter);
+                    RdPipeCounter++;
+                    RdPipeFlag = _TRUE;
+                    RecRdPipe[RdPipeCounter - 1] = RdPipe;
+                }
+
+                AvaWds[RdPipeCounter-1][AvaWdsCnt] = TapCnt;
+                AvaWdsCnt++;
+
+                RecNum[RdPipeCounter-1] = AvaWdsCnt;
+
+                if((TapCnt+TAP_DLY)>=MAX_TAP_DLY) {
+                    break;
+                }
+
+                PassFlag = _TRUE;
+                
+                DBG_SDR_INFO("Verify Pass => RdPipe:%d; TapCnt: %d\n", RdPipe, TapCnt);
+
+            }
+            else {      // FAIL
+//                if(PassFlag==_TRUE) {   
+//                    break;
+//                }
+//                else {
+                    if (RdPipeCounter > 0) {
+                        RdPipeCounter++;
+                        if (RdPipeCounter < 3) {
+                            RecNum[RdPipeCounter-1] = 0;
+                            RecRdPipe[RdPipeCounter - 1] = RdPipe;
+                        }
+                        break;
+                    }
+//                }
+            }
+        }
+
+
+        if (RdPipeCounter > 2) {
+            u8 BestRangeIndex, BestIndex;
+            u32 i;
+            
+            #ifdef CONFIG_SDR_VERIFY //to reduce log
+            DBG_SDR_INFO("Avaliable RdPipe 0\n");                
+            
+            for (i=0;i<256;i++) {
+                DBG_SDR_INFO("%d\n", AvaWds[0][i]);                
+            }
+            DBG_SDR_INFO("Avaliable RdPipe 1\n");                
+            for (i=0;i<256;i++) {
+                DBG_SDR_INFO("%d\n", AvaWds[1][i]);                
+            }
+            #endif
+            
+            DBG_SDR_INFO("Rec 0 => total counter %d; RdPipe:%d;\n", RecNum[0], RecRdPipe[0]);
+            DBG_SDR_INFO("Rec 1 => total counter %d; RdPipe:%d;\n", RecNum[1], RecRdPipe[1]);
+
+            BestRangeIndex = (RecNum[0] > RecNum[1]) ? 0 : 1;
+
+            BestIndex = RecNum[BestRangeIndex]>>1;
+            
+            DBG_SDR_INFO("The Finial RdPipe: %d; TpCnt: 0x%x\n", RecRdPipe[BestRangeIndex], AvaWds[BestRangeIndex][BestIndex]);
+
+            // set RdPipe and tap_dly
+//            ms_ctrl_0_map->iocr = (ms_ctrl_0_map->iocr & 0xff) | (RecRdPipe[BestRangeIndex] << PCTL_IOCR_RD_PIPE_BFO);
+            HAL_SDR_WRITE32(REG_SDR_IOCR, ((HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | (RecRdPipe[BestRangeIndex] << PCTL_IOCR_RD_PIPE_BFO)));
+            
+#ifdef FPGA
+#ifdef FPGA_TEMP
+            SDR_DDL_FCTRL(AvaWds[BestRangeIndex][BestIndex]);
+    
+//            Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF);
+//            Value32 = Value32 | (AvaWds[BestRangeIndex][BestIndex] << 16);
+//            WR_DATA(SDR_CLK_DLY_CTRL, Value32);
+#else
+            HAL_SDR_WRITE32(REG_SDR_DLY0, AvaWds[BestRangeIndex][BestIndex]);
+//            ms_ctrl_0_map->phy_dly0 = AvaWds[BestRangeIndex][BestIndex];
+#endif
+#else
+            SDR_DDL_FCTRL(AvaWds[BestRangeIndex][BestIndex]);
+//            Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF);
+//            Value32 = Value32 | (AvaWds[BestRangeIndex][BestIndex] << 16);
+//            WR_DATA(SDR_CLK_DLY_CTRL, Value32);
+#endif            
+		#ifdef SUPPORT_DRAM_KED
+			RdPipe = RecRdPipe[BestRangeIndex];
+			TapCnt = AvaWds[BestRangeIndex][BestIndex];
+			
+			value.b[0] = (u8)RdPipe;
+			value.b[1] = ~value.b[0];
+			value.b[2] = (u8)TapCnt;
+			value.b[3] = ~value.b[2];
+			//DiagPrintf("dump1w %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
+			HAL_WRITE32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType+4, value.l);
+			SpicWaitWipDoneRefinedRtl8195A(SpicInitPara);
+			
+			valid = 1;
+			value.b[0] = (u8)valid;
+			value.b[1] = ~value.b[0];
+			value.b[2] = 0xFF;
+			value.b[3] = 0xFF;
+			//DiagPrintf("dump1w %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
+			HAL_WRITE32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType, value.l);
+			SpicWaitWipDoneRefinedRtl8195A(SpicInitPara);
+		#endif				
+            Result = _TRUE;
+            break;
+        }
+
+        if (RdPipeCounter == 0) {
+
+            DBG_SDR_INFO("NOT Find RdPipe\n"); 
+        }
+    }
+
+    return Result;
+} // SdrCalibration
+ 
+ 
+
+ 
+HAL_SDRC_TEXT_SECTION 
+VOID
+ChangeRandSeed(
+    IN  u32 Seed
+)
+{
+    rand_x = Seed;
+}
+ 
+HAL_SDRC_TEXT_SECTION 
+u32 
+Sdr_Rand2(
+    VOID
+)
+{
+    HAL_RAM_DATA_SECTION static unsigned int y = 362436;
+
+    HAL_RAM_DATA_SECTION static unsigned int z = 521288629;
+
+    HAL_RAM_DATA_SECTION static unsigned int c = 7654321;
+
+    unsigned long long t, a= 698769069;
+
+    rand_x = 69069 * rand_x + 12345;
+    y ^= (y << 13); y ^= (y >> 17); y ^= (y << 5);
+    t = a * z + c; c = (t >> 32); z = t;
+
+    return rand_x + y + z;
+}
+ 
+HAL_SDRC_TEXT_SECTION 
+s32 
+MemTest(
+    u32 LoopCnt
+)
+{
+    u32 LoopIndex = 0;
+    u32 Value32, Addr;
+    for (LoopIndex = 0; LoopIndex<LoopCnt; LoopIndex++) {
+        Value32 = Sdr_Rand2();
+        Addr = Sdr_Rand2();
+        Addr &= 0x1FFFFF;
+        Addr &= (~0x3);
+        
+        HAL_SDRAM_WRITE32(Addr, Value32);
+
+        if (HAL_SDRAM_READ32(Addr) != Value32) {
+            DBG_8195A("Test %d: No match addr 0x%x => 0x%x != 0x%x\n",LoopIndex,
+                Addr, Value32, HAL_SDRAM_READ32(Addr));
+            return _FALSE;
+        }
+        else {
+    //            HAL_SDRAM_WRITE32(Addr, 0);        
+        }
+    }
+    return _TRUE;
+
+} // MemTest
+
+#endif  // end of "#ifdef CONFIG_SDR_EN"

component/soc/realtek/8195a/fwlib/src/hal_ssi.c

@@ -0,0 +1,281 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#include "rtl8195a.h"
+#include "hal_ssi.h"
+
+const HAL_GDMA_CHNL Ssi2_TX_GDMA_Chnl_Option[] = { 
+    {0,4,GDMA0_CHANNEL4_IRQ,0},
+    {0,5,GDMA0_CHANNEL5_IRQ,0},
+    {0,3,GDMA0_CHANNEL3_IRQ,0},
+    {0,0,GDMA0_CHANNEL0_IRQ,0},
+    {0,1,GDMA0_CHANNEL1_IRQ,0},
+    {0,2,GDMA0_CHANNEL2_IRQ,0},
+    
+    {0xff,0,0,0}    // end
+};
+
+const HAL_GDMA_CHNL Ssi2_RX_GDMA_Chnl_Option[] = { 
+    {1,4,GDMA1_CHANNEL4_IRQ,0},
+    {1,5,GDMA1_CHANNEL5_IRQ,0},
+    {1,3,GDMA1_CHANNEL3_IRQ,0},
+    {1,0,GDMA1_CHANNEL0_IRQ,0},
+    {1,1,GDMA1_CHANNEL1_IRQ,0},
+    {1,2,GDMA1_CHANNEL2_IRQ,0},
+    
+    {0xff,0,0,0}    // end
+};
+
+//TODO: Load default Setting: It should be loaded from external setting file.
+const DW_SSI_DEFAULT_SETTING SpiDefaultSetting =
+{
+    .RxCompCallback    = NULL,
+    .RxCompCbPara      = NULL,
+    .RxData            = NULL,
+    .TxCompCallback    = NULL,
+    .TxCompCbPara      = NULL,
+    .TxData            = NULL,
+    .DmaRxDataLevel    =    7,  // RX FIFO stored bytes > (DMARDLR(7) + 1) then trigger DMA transfer
+    .DmaTxDataLevel    =   48,  // TX FIFO free space > (FIFO_SPACE(64)-DMATDLR(48)) then trigger DMA transfer
+    .InterruptPriority = 0x20,
+    .RxLength          =    0,
+    .RxLengthRemainder =    0,
+    .RxThresholdLevel  =    7,  // if number of entries in th RX FIFO >= (RxThresholdLevel+1), RX interrupt asserted
+    .TxLength          =    0,
+    .TxThresholdLevel  =    8,  // if number of entries in th TX FIFO <= TxThresholdLevel, TX interrupt asserted
+    .SlaveSelectEnable =    0,
+    .ClockDivider      = SSI_CLK_SPI0_2/1000000,    // SCLK=1M
+    .DataFrameNumber   =    0,
+    .ControlFrameSize  = CFS_1_BIT,
+    .DataFrameFormat   = FRF_MOTOROLA_SPI,
+    .DataFrameSize     = DFS_8_BITS,
+    .DmaControl        = 0, // default DMA is disable
+    .InterruptMask     =  0x0,
+    .MicrowireDirection    = MW_DIRECTION_MASTER_TO_SLAVE,
+    .MicrowireHandshaking  = MW_HANDSHAKE_DISABLE,
+    .MicrowireTransferMode = MW_TMOD_NONSEQUENTIAL,
+    .SclkPhase             = SCPH_TOGGLES_AT_START,
+    .SclkPolarity          = SCPOL_INACTIVE_IS_HIGH,
+    .SlaveOutputEnable     = SLV_TXD_ENABLE,  // Slave
+    .TransferMode          = TMOD_TR,
+    .TransferMechanism     = SSI_DTM_INTERRUPT
+};
+
+extern HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
+extern HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
+extern HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
+extern HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
+extern HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
+extern VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
+#ifdef CONFIG_GDMA_EN
+extern VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
+#endif
+
+VOID HalSsiOpInit(VOID *Adaptor)
+{
+    PHAL_SSI_OP pHalSsiOp = (PHAL_SSI_OP) Adaptor;
+
+//    pHalSsiOp->HalSsiPinmuxEnable            = HalSsiPinmuxEnableRtl8195a;
+    pHalSsiOp->HalSsiPinmuxEnable            = HalSsiPinmuxEnableRtl8195a_Patch;
+    pHalSsiOp->HalSsiPinmuxDisable           = HalSsiPinmuxDisableRtl8195a;
+    pHalSsiOp->HalSsiEnable                  = HalSsiEnableRtl8195a;
+    pHalSsiOp->HalSsiDisable                 = HalSsiDisableRtl8195a;
+//    pHalSsiOp->HalSsiInit                    = HalSsiInitRtl8195a;
+    pHalSsiOp->HalSsiInit                    = HalSsiInitRtl8195a_Patch;
+    pHalSsiOp->HalSsiSetSclkPolarity         = HalSsiSetSclkPolarityRtl8195a;
+    pHalSsiOp->HalSsiSetSclkPhase            = HalSsiSetSclkPhaseRtl8195a;
+    pHalSsiOp->HalSsiWrite                   = HalSsiWriteRtl8195a;
+    pHalSsiOp->HalSsiRead                    = HalSsiReadRtl8195a;
+    pHalSsiOp->HalSsiGetRxFifoLevel          = HalSsiGetRxFifoLevelRtl8195a;
+    pHalSsiOp->HalSsiGetTxFifoLevel          = HalSsiGetTxFifoLevelRtl8195a;
+    pHalSsiOp->HalSsiGetStatus               = HalSsiGetStatusRtl8195a;
+    pHalSsiOp->HalSsiGetInterruptStatus      = HalSsiGetInterruptStatusRtl8195a;
+    pHalSsiOp->HalSsiLoadSetting             = HalSsiLoadSettingRtl8195a;
+    pHalSsiOp->HalSsiSetInterruptMask        = HalSsiSetInterruptMaskRtl8195a;
+    pHalSsiOp->HalSsiGetInterruptMask        = HalSsiGetInterruptMaskRtl8195a;
+    pHalSsiOp->HalSsiSetDeviceRole           = HalSsiSetDeviceRoleRtl8195a;
+    pHalSsiOp->HalSsiWriteable               = HalSsiWriteableRtl8195a;
+    pHalSsiOp->HalSsiReadable                = HalSsiReadableRtl8195a;
+    pHalSsiOp->HalSsiBusy                    = HalSsiBusyRtl8195a;
+    pHalSsiOp->HalSsiInterruptEnable         = HalSsiInterruptEnableRtl8195a;
+    pHalSsiOp->HalSsiInterruptDisable        = HalSsiInterruptDisableRtl8195a;
+//    pHalSsiOp->HalSsiReadInterrupt           = HalSsiReadInterruptRtl8195a;
+    pHalSsiOp->HalSsiReadInterrupt           = HalSsiIntReadRtl8195a;
+    pHalSsiOp->HalSsiSetRxFifoThresholdLevel = HalSsiSetRxFifoThresholdLevelRtl8195a;
+    pHalSsiOp->HalSsiSetTxFifoThresholdLevel = HalSsiSetTxFifoThresholdLevelRtl8195a;
+//    pHalSsiOp->HalSsiWriteInterrupt          = HalSsiWriteInterruptRtl8195a;
+    pHalSsiOp->HalSsiWriteInterrupt          = HalSsiIntWriteRtl8195a;
+    pHalSsiOp->HalSsiGetRawInterruptStatus   = HalSsiGetRawInterruptStatusRtl8195a;
+    pHalSsiOp->HalSsiGetSlaveEnableRegister  = HalSsiGetSlaveEnableRegisterRtl8195a;
+    pHalSsiOp->HalSsiSetSlaveEnableRegister  = HalSsiSetSlaveEnableRegisterRtl8195a;
+}
+
+
+#ifdef CONFIG_GDMA_EN    
+
+HAL_Status
+HalSsiTxGdmaInit(
+    IN PHAL_SSI_OP pHalSsiOp,
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PSSI_DMA_CONFIG pDmaConfig;    
+    u8 gdma_idx;
+    u8 gdma_chnum;
+    HAL_GDMA_CHNL *pgdma_chnl;
+    PHAL_GDMA_OP pHalGdmaOp;
+    
+    if ((NULL == pHalSsiOp) || (NULL == pHalSsiAdapter)) {
+        return HAL_ERR_PARA;
+    }
+
+    pDmaConfig = &pHalSsiAdapter->DmaConfig;
+
+    // Load default setting
+    HalSsiTxGdmaLoadDefRtl8195a((void*)pHalSsiAdapter);
+
+    // Start to patch the default setting
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter;
+    if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) {
+        // The default GDMA Channel is not available, try others
+        if (pHalSsiAdapter->Index == 2) {
+            // SSI2 TX Only can use GDMA 0
+            pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Ssi2_TX_GDMA_Chnl_Option);
+        }
+        else {
+            pgdma_chnl = HalGdmaChnlAlloc(NULL);
+        }
+
+        if (pgdma_chnl == NULL) {
+            // No Available DMA channel
+            return HAL_BUSY;
+        }
+        else {
+            pHalGdmaAdapter->GdmaIndex   = pgdma_chnl->GdmaIndx;
+            pHalGdmaAdapter->ChNum       = pgdma_chnl->GdmaChnl;
+            pHalGdmaAdapter->ChEn        = 0x0101 << pgdma_chnl->GdmaChnl;
+            pDmaConfig->TxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum;            
+        }
+    }
+
+    DBG_SSI_INFO("HalSsiTxGdmaInit: GdmaIndex=%d ChNum=%d \r\n", pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum);
+    pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp;
+    pHalGdmaOp->HalGdmaOnOff((VOID*)(pHalGdmaAdapter));
+    pHalGdmaOp->HalGdmaChIsrEnAndDis((VOID*)(pHalGdmaAdapter));
+
+    HalSsiDmaInit(pHalSsiAdapter);
+    InterruptRegister(&pDmaConfig->TxGdmaIrqHandle);
+    InterruptEn(&pDmaConfig->TxGdmaIrqHandle);
+
+    return HAL_OK;
+}
+
+VOID
+HalSsiTxGdmaDeInit(
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    PSSI_DMA_CONFIG pDmaConfig;    
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    HAL_GDMA_CHNL GdmaChnl;
+    
+    if (NULL == pHalSsiAdapter) {
+        return;
+    }
+
+    pDmaConfig = &pHalSsiAdapter->DmaConfig;
+
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter;
+    GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
+    GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
+    GdmaChnl.IrqNum = pDmaConfig->TxGdmaIrqHandle.IrqNum;
+    HalGdmaChnlFree(&GdmaChnl);
+}
+
+
+HAL_Status
+HalSsiRxGdmaInit(
+    IN PHAL_SSI_OP pHalSsiOp,
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PSSI_DMA_CONFIG pDmaConfig;    
+    HAL_GDMA_CHNL *pgdma_chnl;
+    PHAL_GDMA_OP pHalGdmaOp;
+    
+    if ((NULL == pHalSsiOp) || (NULL == pHalSsiAdapter)) {
+        return HAL_ERR_PARA;
+    }
+
+    pDmaConfig = &pHalSsiAdapter->DmaConfig;
+    // Load default setting
+    HalSsiRxGdmaLoadDefRtl8195a((void*)pHalSsiAdapter);
+
+    // Start to patch the default setting
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter;
+    if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) {
+        // The default GDMA Channel is not available, try others
+        if (pHalSsiAdapter->Index == 2) {
+            // SSI2 RX Only can use GDMA 1
+            pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Ssi2_RX_GDMA_Chnl_Option);
+        }
+        else {
+            pgdma_chnl = HalGdmaChnlAlloc(NULL);
+        }
+
+        if (pgdma_chnl == NULL) {
+            // No Available DMA channel
+            return HAL_BUSY;
+        }
+        else {
+            pHalGdmaAdapter->GdmaIndex   = pgdma_chnl->GdmaIndx;
+            pHalGdmaAdapter->ChNum       = pgdma_chnl->GdmaChnl;
+            pHalGdmaAdapter->ChEn        = 0x0101 << pgdma_chnl->GdmaChnl;
+            pDmaConfig->RxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum;            
+        }
+    }
+
+    DBG_SSI_INFO("HalSsiRxGdmaInit: GdmaIndex=%d ChNum=%d \r\n", pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum);
+    pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp;
+    pHalGdmaOp->HalGdmaOnOff((VOID*)(pHalGdmaAdapter));
+    pHalGdmaOp->HalGdmaChIsrEnAndDis((VOID*)(pHalGdmaAdapter));
+
+    HalSsiDmaInit(pHalSsiAdapter);
+    InterruptRegister(&pDmaConfig->RxGdmaIrqHandle);
+    InterruptEn(&pDmaConfig->RxGdmaIrqHandle);
+
+    return HAL_OK;
+}
+
+VOID
+HalSsiRxGdmaDeInit(
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    PSSI_DMA_CONFIG pDmaConfig;    
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    HAL_GDMA_CHNL GdmaChnl;
+    
+    if (NULL == pHalSsiAdapter) {
+        return;
+    }
+
+    pDmaConfig = &pHalSsiAdapter->DmaConfig;
+
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter;
+    GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
+    GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
+    GdmaChnl.IrqNum = pDmaConfig->RxGdmaIrqHandle.IrqNum;
+    HalGdmaChnlFree(&GdmaChnl);
+}
+
+#endif  // end of "#ifdef CONFIG_GDMA_EN"
+

component/soc/realtek/8195a/fwlib/src/hal_timer.c

@@ -0,0 +1,32 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+
+VOID 
+HalTimerOpInit_Patch(
+    IN  VOID *Data
+)
+{
+    PHAL_TIMER_OP pHalTimerOp = (PHAL_TIMER_OP) Data;
+
+    pHalTimerOp->HalGetTimerId = HalGetTimerIdRtl8195a;    
+    pHalTimerOp->HalTimerInit = (BOOL (*)(void*))HalTimerInitRtl8195a_Patch;   
+#ifdef CONFIG_CHIP_C_CUT
+    pHalTimerOp->HalTimerReadCount = HalTimerReadCountRtl8195aV02;    
+#else
+    pHalTimerOp->HalTimerReadCount = HalTimerReadCountRtl8195a_Patch;    
+#endif
+    pHalTimerOp->HalTimerIrqClear = HalTimerIrqClearRtl8195a;
+    pHalTimerOp->HalTimerDis = HalTimerDisRtl8195a_Patch;
+    pHalTimerOp->HalTimerEn = HalTimerEnRtl8195a_Patch;
+    pHalTimerOp->HalTimerDumpReg = HalTimerDumpRegRtl8195a;
+}
+

component/soc/realtek/8195a/fwlib/src/hal_uart.c

@@ -0,0 +1,332 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+#include "rtl8195a_uart.h"
+#include "hal_uart.h"
+#include "hal_gdma.h"
+
+extern u32 _UartIrqHandle(VOID *Data);
+
+#if (CONFIG_CHIP_A_CUT | CONFIG_CHIP_B_CUT)
+HAL_Status 
+HalRuartInitRtl8195a_Patch(
+        IN VOID *Data  ///< RUART Adapter
+        );
+#else
+extern _LONG_CALL_ HAL_Status
+HalRuartInitRtl8195aV02(
+        IN VOID *Data  ///< RUART Adapter
+        );
+#endif
+
+const HAL_GDMA_CHNL Uart2_TX_GDMA_Chnl_Option[] = { 
+    {0,0,GDMA0_CHANNEL0_IRQ,0},
+    {0,1,GDMA0_CHANNEL1_IRQ,0},
+    {0,2,GDMA0_CHANNEL2_IRQ,0},
+    {0,3,GDMA0_CHANNEL3_IRQ,0},
+    {0,4,GDMA0_CHANNEL4_IRQ,0},
+    {0,5,GDMA0_CHANNEL5_IRQ,0},
+    
+    {0xff,0,0,0}    // end
+};
+
+const HAL_GDMA_CHNL Uart2_RX_GDMA_Chnl_Option[] = { 
+    {1,0,GDMA1_CHANNEL0_IRQ,0},
+    {1,1,GDMA1_CHANNEL1_IRQ,0},
+    {1,2,GDMA1_CHANNEL2_IRQ,0},
+    {1,3,GDMA1_CHANNEL3_IRQ,0},
+    {1,4,GDMA1_CHANNEL4_IRQ,0},
+    {1,5,GDMA1_CHANNEL5_IRQ,0},
+    
+    {0xff,0,0,0}    // end
+};
+
+VOID
+HalRuartOpInit(
+        IN VOID *Data
+)
+{
+    PHAL_RUART_OP pHalRuartOp = (PHAL_RUART_OP) Data;
+
+    pHalRuartOp->HalRuartAdapterLoadDef     = HalRuartAdapterLoadDefRtl8195a;
+    pHalRuartOp->HalRuartTxGdmaLoadDef      = HalRuartTxGdmaLoadDefRtl8195a;
+    pHalRuartOp->HalRuartRxGdmaLoadDef      = HalRuartRxGdmaLoadDefRtl8195a;
+    pHalRuartOp->HalRuartResetRxFifo        = HalRuartResetRxFifoRtl8195a;
+#if (CONFIG_CHIP_A_CUT | CONFIG_CHIP_B_CUT)
+    pHalRuartOp->HalRuartInit               = HalRuartInitRtl8195a_Patch;         // Hardware Init ROM code patch 
+#else
+    pHalRuartOp->HalRuartInit               = HalRuartInitRtl8195aV02;         // Hardware Init
+#endif
+    pHalRuartOp->HalRuartDeInit             = HalRuartDeInitRtl8195a;         // Hardware Init
+    pHalRuartOp->HalRuartPutC               = HalRuartPutCRtl8195a;         // Send a byte
+    pHalRuartOp->HalRuartSend               = HalRuartSendRtl8195a;         // Polling mode Tx
+    pHalRuartOp->HalRuartIntSend            = HalRuartIntSendRtl8195a;      // Interrupt mode Tx
+    pHalRuartOp->HalRuartDmaSend            = HalRuartDmaSendRtl8195a;      // DMA mode Tx
+    pHalRuartOp->HalRuartStopSend           = HalRuartStopSendRtl8195a;     // Stop non-blocking TX
+    pHalRuartOp->HalRuartGetC               = HalRuartGetCRtl8195a;           // get a byte
+    pHalRuartOp->HalRuartRecv               = HalRuartRecvRtl8195a;         // Polling mode Rx
+    pHalRuartOp->HalRuartIntRecv            = HalRuartIntRecvRtl8195a;      // Interrupt mode Rx
+    pHalRuartOp->HalRuartDmaRecv            = HalRuartDmaRecvRtl8195a;      // DMA mode Rx
+    pHalRuartOp->HalRuartStopRecv           = HalRuartStopRecvRtl8195a;     // Stop non-blocking Rx
+    pHalRuartOp->HalRuartGetIMR             = HalRuartGetIMRRtl8195a;
+    pHalRuartOp->HalRuartSetIMR             = HalRuartSetIMRRtl8195a;
+    pHalRuartOp->HalRuartGetDebugValue      = HalRuartGetDebugValueRtl8195a;
+    pHalRuartOp->HalRuartDmaInit            = HalRuartDmaInitRtl8195a;
+    pHalRuartOp->HalRuartRTSCtrl            = HalRuartRTSCtrlRtl8195a;
+    pHalRuartOp->HalRuartRegIrq             = HalRuartRegIrqRtl8195a;
+    pHalRuartOp->HalRuartIntEnable          = HalRuartIntEnableRtl8195a;
+    pHalRuartOp->HalRuartIntDisable         = HalRuartIntDisableRtl8195a;
+}
+
+
+
+/**
+ * Load UART HAL default setting
+ *
+ * Call this function to load the default setting for UART HAL adapter
+ *
+ *
+ */
+VOID
+HalRuartAdapterInit(
+    PRUART_ADAPTER pRuartAdapter,
+    u8 UartIdx
+)
+{
+    PHAL_RUART_OP pHalRuartOp;
+    PHAL_RUART_ADAPTER pHalRuartAdapter;
+    
+    if (NULL == pRuartAdapter) {
+        return;
+    }
+    
+    pHalRuartOp = pRuartAdapter->pHalRuartOp;
+    pHalRuartAdapter = pRuartAdapter->pHalRuartAdapter;
+
+    if ((NULL == pHalRuartOp) || (NULL == pHalRuartAdapter)) {
+        return;
+    }
+
+    // Load default setting
+    if (pHalRuartOp->HalRuartAdapterLoadDef != NULL) {
+        pHalRuartOp->HalRuartAdapterLoadDef (pHalRuartAdapter, UartIdx);
+    }
+    else {
+        // Initial your UART HAL adapter here
+    }
+
+    // Start to modify the defualt setting
+    pHalRuartAdapter->PinmuxSelect = RUART0_MUX_TO_GPIOC;
+    pHalRuartAdapter->BaudRate = 38400;
+
+//    pHalRuartAdapter->IrqHandle.IrqFun = (IRQ_FUN)_UartIrqHandle;
+//    pHalRuartAdapter->IrqHandle.Data = (void *)pHalRuartAdapter;
+//    pHalRuartAdapter->IrqHandle.Priority = 0x20;
+
+    // Register IRQ
+    InterruptRegister(&pHalRuartAdapter->IrqHandle);
+    
+}
+
+/**
+ * Load UART HAL GDMA default setting
+ *
+ * Call this function to load the default setting for UART GDMA
+ *
+ *
+ */
+HAL_Status
+HalRuartTxGdmaInit(
+    PHAL_RUART_OP pHalRuartOp,
+    PHAL_RUART_ADAPTER pHalRuartAdapter,
+    PUART_DMA_CONFIG pUartGdmaConfig
+)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    u8 gdma_idx;
+    u8 gdma_chnum;
+    HAL_GDMA_CHNL *pgdma_chnl;
+    
+    if ((NULL == pHalRuartOp) || (NULL == pHalRuartAdapter) || (NULL == pUartGdmaConfig)) {
+        return HAL_ERR_PARA;
+    }
+
+    // Load default setting
+    if (pHalRuartOp->HalRuartTxGdmaLoadDef != NULL) {
+        pHalRuartOp->HalRuartTxGdmaLoadDef (pHalRuartAdapter, pUartGdmaConfig);
+    }
+    else {
+        // Initial your GDMA setting here
+    }
+
+    // Start to patch the default setting
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter;
+    if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) {
+        // The default GDMA Channel is not available, try others
+        if (pHalRuartAdapter->UartIndex == 2) {
+            // UART2 TX Only can use GDMA 0
+            pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Uart2_TX_GDMA_Chnl_Option);
+        }
+        else {
+            pgdma_chnl = HalGdmaChnlAlloc(NULL);
+        }
+
+        if (pgdma_chnl == NULL) {
+            // No Available DMA channel
+            return HAL_BUSY;
+        }
+        else {
+            pHalGdmaAdapter->GdmaIndex   = pgdma_chnl->GdmaIndx;
+            pHalGdmaAdapter->ChNum       = pgdma_chnl->GdmaChnl;
+            pHalGdmaAdapter->ChEn        = 0x0101 << pgdma_chnl->GdmaChnl;
+            pUartGdmaConfig->TxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum;            
+        }
+    }
+
+    // User can assign a Interrupt Handler here
+//    pUartGdmaConfig->TxGdmaIrqHandle.Data = pHalRuartAdapter;
+//    pUartGdmaConfig->TxGdmaIrqHandle.IrqFun = (IRQ_FUN)_UartTxDmaIrqHandle
+//    pUartGdmaConfig->TxGdmaIrqHandle.Priority = 0x20;
+
+    pHalRuartOp->HalRuartDmaInit (pHalRuartAdapter);
+    InterruptRegister(&pUartGdmaConfig->TxGdmaIrqHandle);
+    InterruptEn(&pUartGdmaConfig->TxGdmaIrqHandle);
+
+    return HAL_OK;
+}
+
+VOID
+HalRuartTxGdmaDeInit(
+    PUART_DMA_CONFIG pUartGdmaConfig
+)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    HAL_GDMA_CHNL GdmaChnl;
+
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter;
+    GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
+    GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
+    GdmaChnl.IrqNum = pUartGdmaConfig->TxGdmaIrqHandle.IrqNum;
+    HalGdmaChnlFree(&GdmaChnl);
+}
+
+/**
+ * Load UART HAL GDMA default setting
+ *
+ * Call this function to load the default setting for UART GDMA
+ *
+ *
+ */
+HAL_Status
+HalRuartRxGdmaInit(
+    PHAL_RUART_OP pHalRuartOp,
+    PHAL_RUART_ADAPTER pHalRuartAdapter,
+    PUART_DMA_CONFIG pUartGdmaConfig
+)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    HAL_GDMA_CHNL *pgdma_chnl;
+    
+    if ((NULL == pHalRuartOp) || (NULL == pHalRuartAdapter) || (NULL == pUartGdmaConfig)) {
+        return HAL_ERR_PARA;
+    }
+
+    // Load default setting
+    if (pHalRuartOp->HalRuartRxGdmaLoadDef != NULL) {
+        pHalRuartOp->HalRuartRxGdmaLoadDef (pHalRuartAdapter, pUartGdmaConfig);
+    }
+    else {
+        // Initial your GDMA setting here
+    }
+
+    // Start to patch the default setting
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter;
+    if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) {
+        // The default GDMA Channel is not available, try others
+        if (pHalRuartAdapter->UartIndex == 2) {
+            // UART2 RX Only can use GDMA 1
+            pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Uart2_RX_GDMA_Chnl_Option);
+        }
+        else {
+            pgdma_chnl = HalGdmaChnlAlloc(NULL);
+        }
+
+        if (pgdma_chnl == NULL) {
+            // No Available DMA channel
+            return HAL_BUSY;
+        }
+        else {
+            pHalGdmaAdapter->GdmaIndex   = pgdma_chnl->GdmaIndx;
+            pHalGdmaAdapter->ChNum       = pgdma_chnl->GdmaChnl;
+            pHalGdmaAdapter->ChEn        = 0x0101 << pgdma_chnl->GdmaChnl;
+            pUartGdmaConfig->RxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum;            
+        }
+    }
+
+//    pUartGdmaConfig->RxGdmaIrqHandle.Data = pHalRuartAdapter;
+//    pUartGdmaConfig->RxGdmaIrqHandle.IrqFun = (IRQ_FUN)_UartTxDmaIrqHandle;
+//    pUartGdmaConfig->RxGdmaIrqHandle.Priority = 0x20;
+
+    pHalRuartOp->HalRuartDmaInit (pHalRuartAdapter);
+    InterruptRegister(&pUartGdmaConfig->RxGdmaIrqHandle);
+    InterruptEn(&pUartGdmaConfig->RxGdmaIrqHandle);
+
+    return HAL_OK;
+}
+
+VOID
+HalRuartRxGdmaDeInit(
+    PUART_DMA_CONFIG pUartGdmaConfig
+)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    HAL_GDMA_CHNL GdmaChnl;
+
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter;
+    GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
+    GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
+    GdmaChnl.IrqNum = pUartGdmaConfig->RxGdmaIrqHandle.IrqNum;
+    HalGdmaChnlFree(&GdmaChnl);
+}
+
+/**
+ * Hook a RX indication callback
+ *
+ * To hook a callback function which will be called when a got a RX byte
+ *
+ *
+ */
+VOID
+HalRuartRxIndHook(
+    PRUART_ADAPTER pRuartAdapter,
+    VOID *pCallback,
+    VOID *pPara
+)
+{
+    PHAL_RUART_ADAPTER pHalRuartAdapter = pRuartAdapter->pHalRuartAdapter;
+
+    pHalRuartAdapter->RxDRCallback = (void (*)(void*))pCallback;
+    pHalRuartAdapter->RxDRCbPara = pPara;
+
+    // enable RX data ready interrupt
+    pHalRuartAdapter->Interrupts |= RUART_IER_ERBI | RUART_IER_ELSI;
+    pRuartAdapter->pHalRuartOp->HalRuartSetIMR(pHalRuartAdapter);    
+}
+
+
+HAL_Status
+HalRuartResetTxFifo(
+    IN VOID *Data
+)
+{
+    return (HalRuartResetTxFifoRtl8195a(Data));
+}
+