mirror of
https://github.com/cwyark/ameba-sdk-gcc-make.git
synced 2025-01-16 18:25:19 +00:00
382 lines
No EOL
13 KiB
Text
Executable file
382 lines
No EOL
13 KiB
Text
Executable file
//DRAM_INFO
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__var DeviceType;
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__var Page;
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__var Bank;
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__var DqWidth;
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//DRAM_MODE_REG_INFO
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__var BstLen;
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__var BstType;
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__var Mode0Cas;
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__var Mode0Wr;
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__var Mode1DllEnN;
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__var Mode1AllLat;
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__var Mode2Cwl;
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//DRAM_TIMING_INFO, additional parameter, to config DRAM_TIMING INFO
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__var DramTimingTref;
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__var DramRowNum;
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__var Tck;
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//DRAM_TIMING_INFO
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__var TrfcPs;
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__var TrefiPs;
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__var WrMaxTck;
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__var TrcdPs;
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__var TrpPs;
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__var TrasPs;
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__var TrrdTck;
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__var TwrPs;
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__var TwtrTck;
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__var TmrdTck;
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__var TrtpTck;
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__var TccdTck;
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__var TrcPs;
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//DRAM_DEVICE_INFO
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__var DdrPeriodPs;
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__var DfiRate;
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__config_dram_param(){
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__var CsBstLen;
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__var CasWr;
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__var CasRd;
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__var CasRdT;
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__var ClrSrt;
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__var AddLat;
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__var DramEmr2;
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__var DramMr0;
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__var CrTwr;
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__var DramMaxWr;
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__var DramWr;
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__var CrTrtw;
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__var CrTrtwT;
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__var DramPeriod;
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__var DdrType;
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//__var paDqWidth;
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//__var paPage;
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//__var paDfiRate
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__var tmp;
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// Register dram common.mac
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//__registerMacroFile("$PROJ_DIR$\\..\\..\\..\\component\\soc\\realtek\\8195a\\misc\\iar_utility\\common\\dram\\common.mac");
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__load_dram_common();
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// Load parameter
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__load_dram_param();
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DfiRate = 1<<DfiRate;
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DramPeriod = DdrPeriodPs*DfiRate;
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DramMaxWr= (WrMaxTck)/(DfiRate) +1;
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DramWr = ((TwrPs) / DramPeriod)+1;
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CrTwr = ((TwrPs) / DramPeriod) + 3;
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if (CrTwr < DramMaxWr) {
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CrTwr = CrTwr;
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}else {
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CrTwr = DramMaxWr;
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}
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if(DeviceType==2){ // Case DDR2
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DdrType = 2;
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if (BstLen == 0){
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CsBstLen = 0;
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CrTrtwT = 4;
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DramMr0 = 2;
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}else{
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CsBstLen = 1;
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CrTrtwT = 6;
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DramMr0 = 3;
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}
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CasRd = Mode0Cas;
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AddLat = Mode1AllLat;
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CasWr = CasRd + AddLat -1;
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DramEmr2 = 0;
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DramMr0 =(((DramWr%6)-1)<<(8+1))|(0<<8)|(Mode0Cas<<4)|(BstType<<3)|DramMr0;
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}
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if(DeviceType==3){ // Case DDR3
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DdrType = 3;
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if (BstLen==0){
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CsBstLen = 0; //bst_4
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DramMr0 = 2;
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}else{
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CsBstLen = 1; // bst_8
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DramMr0 = 0;
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}
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CrlSrt = (Mode0Cas >> 1);
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if (((Mode0Cas) & 0x1) ) {
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CasRdT = CrlSrt+ 12;
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}else{
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CasRdT = CrlSrt+ 4;
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}
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AddLat = 0;
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if (Mode1AllLat == 1) { // CL-1
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AddLat = CasRd -1;
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}
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if (Mode1AllLat == 2){ // CL-2
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AddLat = CasRd -2;
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}
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CasRd = CasRdT + AddLat;
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CasWr = Mode2Cwl + 5 + AddLat;
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DramEmr2 = Mode2Cwl << 3;
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DramWr = (DramWr + 1) / 2;
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if (DramWr == 16) {
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DramWr = 0;
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}
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if (DramWr <= 9) { // 5< wr <= 9
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DramWr = DramWr - 4;
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}
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DramMr0 =(DramWr<<(8+1))|(0<<8)|((Mode0Cas>>1)<<4)|(BstType<<3)|((Mode0Cas&0x1)<<2)|DramMr0;
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CrTrtwT = (CasRdT + 6) - CasWr;
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}
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if (DeviceType == 8){
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DdrType = 8;
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if (BstLen == 0) {
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DramMr0 = 2; // bst_4
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CsBstLen = 0; //bst_4
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CasRd = 0x2;
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} else {
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DramMr0 = 3; // bst_8
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CsBstLen = 1; // bst_8
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CasRd = 0x3;
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}
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CasWr = 0;
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DramMr0 =(CasRd<<4)|(BstType<<3)|DramMr0;
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CrTrtwT = 0; // tic: CasRd + rd_rtw + rd_pipe
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}
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// countting tRTW
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if ((CrTrtwT & 0x1)) {
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CrTrtw = (CrTrtwT+1) /(DfiRate);
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} else {
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CrTrtw = CrTrtwT /(DfiRate);
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}
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DqWidth = DqWidth;
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Page = Page +1; // DQ16 -> memory:byte_unit *2
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if (DqWidth == 1) { // paralle dq_16 => Page + 1
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Page = Page +1;
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}
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// REG_SDR_MISC
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tmp =(Page<<0)|(Bank<<4)|(CsBstLen<<6)|(DqWidth<<8);
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__writeMemory32(tmp, 0x40005224, "Memory"); __delay(10);
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// REG_SDR_DCR
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tmp =(0x2<<8)|(DqWidth<<4)|(DdrType<<0);
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__writeMemory32(tmp, 0x40005004, "Memory"); __delay(10);
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// REG_SDR_IOCR
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tmp =((CasRd-4)/(DfiRate)<<20)|(0<<17)|(((CasWr-3)/(DfiRate))<<12)|(0<<8);
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__writeMemory32(tmp, 0x40005008, "Memory"); __delay(10);
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if(DeviceType != 8){
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tmp =DramEmr2;
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__writeMemory32(tmp, 0x40005028, "Memory"); __delay(10);
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tmp =(1<<2)|(1<<1)|(Mode1DllEnN);
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__writeMemory32(tmp, 0x40005024, "Memory"); __delay(10);
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}
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tmp =DramMr0;
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__writeMemory32(tmp, 0x40005020, "Memory"); __delay(10);
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tmp =(0<<28)|(9<<24)|((((TrefiPs)/DramPeriod)+1)<<8)|((((TrfcPs)/DramPeriod)+1)<<0);
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__writeMemory32(tmp, 0x40005010, "Memory"); __delay(10);
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tmp =((((TrtpTck)/DfiRate)+1)<<13)|(CrTwr<<9)|((((TrasPs)/DramPeriod)+1)<<4)|((((TrpPs)/DramPeriod)+1)<<0);
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__writeMemory32(tmp, 0x40005014, "Memory"); __delay(10);
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tmp =(CrTrtw << 20) |
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((((TwtrTck)/DfiRate)+3) << 17) |
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((((TccdTck)/DfiRate)+1) << 14) |
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((((TrcdPs)/DramPeriod)+1) << 10) |
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((((TrcPs)/DramPeriod)+1) << 4 ) |
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(((TrrdTck/DfiRate)+1) << 0);
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__writeMemory32(tmp, 0x40005018, "Memory"); __delay(10);
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tmp =(TmrdTck<<5)|(0<<4)|(2<<0);
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__writeMemory32(tmp, 0x4000501c, "Memory"); __delay(10);
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// Set Idle
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__writeMemory32(0x700, 0x4000500c, "Memory"); __delay(10);
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// start init
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__writeMemory32(0x1, 0x40005000, "Memory"); __delay(100);
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tmp = __readMemory32(0x40005000,"Memory"); __delay(10);
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// enter memory mode
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__writeMemory32(0x600, 0x4000500c, "Memory"); __delay(10);
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}
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__config_dram_param_fixed(){
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__var tmp;
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// Dram Attribute
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__writeMemory32(0x1, 0x40005224, "Memory"); __delay(10);
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__writeMemory32(0x2c8, 0x40005004, "Memory"); __delay(10);
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__writeMemory32(0xffffd000, 0x40005008, "Memory"); __delay(10);
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__delay(3);
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__writeMemory32(0x22, 0x40005020, "Memory"); __delay(10);
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__delay(3);
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__writeMemory32(0x09032001, 0x40005010, "Memory"); __delay(10);
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__delay(3);
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__writeMemory32(0x2611, 0x40005014, "Memory"); __delay(10);
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__delay(3);
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__writeMemory32(0x68413, 0x40005018, "Memory"); __delay(10);
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__delay(3);
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__writeMemory32(0x42, 0x4000501c, "Memory"); __delay(10);
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__delay(3);
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// Enable
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__writeMemory32(0x700, 0x4000500c, "Memory"); __delay(10);
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__delay(20);
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__writeMemory32(0x1, 0x40005000, "Memory"); __delay(10);
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__delay(100);
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tmp = __readMemory32(0x40005000,"Memory"); __delay(10);
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__writeMemory32(0x600, 0x4000500c, "Memory"); __delay(10);
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__delay(30);
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}
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__mem_test(){
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__var i;
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__var vaddr;
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__var tmp;
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i=0;
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while(i<10){
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vaddr = 0x30000000+((i*23)&0x1FFFFC);
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__writeMemory32(0x55AA55AA, vaddr, "Memory");
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tmp = __readMemory32(vaddr,"Memory");
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if(tmp!=0x55AA55AA)
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return 1;
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i=i+1;
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}
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return 0;
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}
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__var ok_pipe_id0;
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__var ok_pipe_id1;
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__var ok_tpc_min0;
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__var ok_tpc_max0;
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__var ok_tpc_min1;
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__var ok_tpc_max1;
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__var tpc0_cnt;
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__var tpc1_cnt;
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// calibration result
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__var isCalibrationDone;
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__dram_calibration(){
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__var rdp;
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__var tpc;
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__var rdp_reg;
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__var tpc_reg;
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__var err_cnt;
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__var ok_cnt;
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ok_cnt=0;
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ok_pipe_id0 = 15;
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ok_tpc_min0 = 12;
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ok_tpc_max0 = 0;
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rdp_reg = __readMemory32(0x40005008,"Memory")&0xFFFF00FF;
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tpc_reg = __readMemory32(0x40000300,"Memory")&0xFF00FFFF;
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for(rdp=0;(rdp<=7)&&(err_cnt==0||ok_cnt==0);rdp++){
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err_cnt=0;
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// try pipe
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__writeMemory32(rdp_reg|rdp<<8,0x40005008, "Memory");__delay(10);
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for(tpc=0;(tpc<=12)&&(err_cnt<2);tpc++){
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// try tpc
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__writeMemory32(tpc_reg|tpc<<16,0x40000300, "Memory");__delay(10);
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if(__mem_test()==0){
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if(ok_pipe_id0==15) {ok_pipe_id0 = rdp; ok_cnt++;}
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if(ok_tpc_min0>tpc) ok_tpc_min0 = tpc;
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if(ok_tpc_max0<tpc) ok_tpc_max0 = tpc;
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}else{
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err_cnt++;
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}
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}
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if(ok_pipe_id0!=15){
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ok_pipe_id1 = ok_pipe_id0;
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ok_tpc_min1 = ok_tpc_min0;
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ok_tpc_max1 = ok_tpc_max0;
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ok_pipe_id0 = 15;
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ok_tpc_min0 = 12;
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ok_tpc_max0 = 0;
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}
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}
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tpc0_cnt = ok_tpc_max0-ok_tpc_min0;
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if(tpc0_cnt<0) tpc0_cnt = 0;
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tpc1_cnt = ok_tpc_max1-ok_tpc_min1;
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if(tpc1_cnt<0) tpc1_cnt = 0;
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if(tpc1_cnt>tpc0_cnt){
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__writeMemory32(rdp_reg|ok_pipe_id1<<8,0x40005008, "Memory");__delay(10);
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__writeMemory32(tpc_reg|(tpc1_cnt/2)<<16,0x40000300, "Memory");__delay(10);
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}else{
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__writeMemory32(rdp_reg|ok_pipe_id0<<8,0x40005008, "Memory");__delay(10);
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__writeMemory32(tpc_reg|(tpc0_cnt/2)<<16,0x40000300, "Memory");__delay(10);
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}
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}
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__setup_system()
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{
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__var tmp;
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__hwReset(1);
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__writeMemory32(0x21, 0x40000014, "Memory"); __delay(10);
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__writeMemory32(0x1FC00002, 0x40000304, "Memory"); __delay(10);
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__writeMemory32(0x400, 0x40000250, "Memory"); __delay(10);
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__writeMemory32(0x0, 0x40000340, "Memory"); __delay(10);
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__writeMemory32(0xdcc4, 0x40000230, "Memory"); __delay(10);
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__writeMemory32(0x11117, 0x40000210, "Memory"); __delay(10);
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__writeMemory32(0x11157, 0x40000210, "Memory"); __delay(10);
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__writeMemory32(0x110011, 0x400002c0, "Memory"); __delay(10);
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__writeMemory32(0xffffffff, 0x40000320, "Memory"); __delay(10);
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__config_dram_param();
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if(isCalibrationDone){
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__var rdp_reg;
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__var tpc_reg;
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rdp_reg = __readMemory32(0x40005008,"Memory")&0xFFFF00FF;
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tpc_reg = __readMemory32(0x40000300,"Memory")&0xFF00FFFF;
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if(tpc1_cnt>tpc0_cnt){
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__writeMemory32(rdp_reg|ok_pipe_id1<<8,0x40005008, "Memory");__delay(10);
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__writeMemory32(tpc_reg|(tpc1_cnt/2)<<16,0x40000300, "Memory");__delay(10);
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}else{
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__writeMemory32(rdp_reg|ok_pipe_id0<<8,0x40005008, "Memory");__delay(10);
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__writeMemory32(tpc_reg|(tpc0_cnt/2)<<16,0x40000300, "Memory");__delay(10);
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}
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}else{
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// Calibration
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__dram_calibration();
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isCalibrationDone = 1;
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}
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}
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execUserPreload()
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{
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// Register dram common.mac
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__registerMacroFile("$PROJ_DIR$\\..\\..\\..\\component\\soc\\realtek\\8195a\\misc\\iar_utility\\common\\dram\\common.mac");
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__message "User Preload....";
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if(__driverType("jlink")){
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__message "driver type J-LINK";
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isCalibrationDone = 0;
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}else if(__driverType("cmsisdap") || __driverType("ijet")){
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__message "driver type CMSIS-DAP or I-JET";
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}
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__setup_system();
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}
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execUserSetup()
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{
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__var tmp;
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__message "User Setup....";
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// if use normal reset, please unmark those 2 lines
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//execUserPreload();
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__setup_system();
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if(__driverType("jlink")){
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__loadImage("$TARGET_PATH$ ", 0, 0);
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tmp = __readMemory32(0x40000210, "Memory")|(1<<27);
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}else if(__driverType("cmsisdap") || __driverType("ijet")){
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tmp = __readMemory32(0x40000210, "Memory")|(1<<21);
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}else{
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__message "Not support drive type";
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}
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__writeMemory32(tmp, 0x40000210, "Memory");
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} |