mirror of
https://github.com/cwyark/ameba-sdk-gcc-make.git
synced 2024-11-24 15:04:19 +00:00
698 lines
20 KiB
C
Executable file
698 lines
20 KiB
C
Executable file
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#include "objects.h"
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#include "spi_api.h"
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#include "spi_ex_api.h"
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#include "PinNames.h"
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#include "pinmap.h"
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#include "hal_ssi.h"
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extern u32 SystemGetCpuClk(VOID);
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extern VOID HAL_GPIO_PullCtrl(u32 pin, u32 mode);
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void spi_tx_done_callback(VOID *obj);
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void spi_rx_done_callback(VOID *obj);
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#ifdef CONFIG_GDMA_EN
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HAL_GDMA_OP SpiGdmaOp;
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#endif
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uint8_t SPI0_IS_AS_SLAVE = 0;
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//TODO: Load default Setting: It should be loaded from external setting file.
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extern const DW_SSI_DEFAULT_SETTING SpiDefaultSetting;
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static const PinMap PinMap_SSI_MOSI[] = {
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{PE_2, RTL_PIN_PERI(SPI0, 0, S0), RTL_PIN_FUNC(SPI0, S0)},
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{PC_2, RTL_PIN_PERI(SPI0, 0, S1), RTL_PIN_FUNC(SPI0, S1)},
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{PA_1, RTL_PIN_PERI(SPI1, 1, S0), RTL_PIN_FUNC(SPI1, S0)},
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{PB_6, RTL_PIN_PERI(SPI1, 1, S1), RTL_PIN_FUNC(SPI1, S1)},
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{PD_6, RTL_PIN_PERI(SPI1, 1, S2), RTL_PIN_FUNC(SPI1, S2)},
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{PG_2, RTL_PIN_PERI(SPI2, 2, S0), RTL_PIN_FUNC(SPI2, S0)},
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{PE_6, RTL_PIN_PERI(SPI2, 2, S1), RTL_PIN_FUNC(SPI2, S1)},
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{PD_2, RTL_PIN_PERI(SPI2, 2, S2), RTL_PIN_FUNC(SPI2, S2)},
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{NC, NC, 0}
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};
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static const PinMap PinMap_SSI_MISO[] = {
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{PE_3, RTL_PIN_PERI(SPI0, 0, S0), RTL_PIN_FUNC(SPI0, S0)},
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{PC_3, RTL_PIN_PERI(SPI0, 0, S1), RTL_PIN_FUNC(SPI0, S1)},
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{PA_0, RTL_PIN_PERI(SPI1, 1, S0), RTL_PIN_FUNC(SPI1, S0)},
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{PB_7, RTL_PIN_PERI(SPI1, 1, S1), RTL_PIN_FUNC(SPI1, S1)},
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{PD_7, RTL_PIN_PERI(SPI1, 1, S2), RTL_PIN_FUNC(SPI1, S2)},
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{PG_3, RTL_PIN_PERI(SPI2, 2, S0), RTL_PIN_FUNC(SPI2, S0)},
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{PE_7, RTL_PIN_PERI(SPI2, 2, S1), RTL_PIN_FUNC(SPI2, S1)},
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{PD_3, RTL_PIN_PERI(SPI2, 2, S2), RTL_PIN_FUNC(SPI2, S2)},
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{NC, NC, 0}
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};
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void spi_init (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
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{
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SSI_DBG_ENTRANCE("spi_init()\n");
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uint32_t ssi_mosi, ssi_miso, ssi_peri;
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uint8_t ssi_idx, ssi_pinmux;
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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PHAL_SSI_OP pHalSsiOp;
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obj->state = 0;
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uint32_t SystemClock = SystemGetCpuClk();
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uint32_t MaxSsiFreq = (SystemClock >> 2) >> 1;
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/* SsiClockDivider doesn't support odd number */
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DBG_SSI_INFO("SystemClock: %d\n", SystemClock);
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DBG_SSI_INFO("MaxSsiFreq : %d\n", MaxSsiFreq);
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ssi_mosi = pinmap_peripheral(mosi, PinMap_SSI_MOSI);
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ssi_miso = pinmap_peripheral(miso, PinMap_SSI_MISO);
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//DBG_SSI_INFO("ssi_mosi: %d, ssi_miso: %d\n", ssi_mosi, ssi_miso);
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ssi_peri = pinmap_merge(ssi_mosi, ssi_miso);
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if (unlikely(ssi_peri == NC)) {
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DBG_SSI_ERR("spi_init(): Cannot find matched SSI index.\n");
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return;
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}
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obj->sclk = (u8)sclk;
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ssi_idx = RTL_GET_PERI_IDX(ssi_peri);
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ssi_pinmux = RTL_GET_PERI_SEL(ssi_peri);
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DBG_SSI_INFO("ssi_peri: %d, ssi_idx: %d, ssi_pinmux: %d\n", ssi_peri, ssi_idx, ssi_pinmux);
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pHalSsiAdaptor = &obj->spi_adp;
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pHalSsiOp = &obj->spi_op;
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pHalSsiAdaptor->Index = ssi_idx;
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pHalSsiAdaptor->PinmuxSelect = ssi_pinmux;
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#if 0
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// XXX: Only for test
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if ((ssi_idx == 0) && (SPI0_IS_AS_SLAVE == 1)) {
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//DBG_SSI_INFO("SSI%d will be as slave. (spi0_is_slave: %d)\n", index, spi0_is_slave);
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pHalSsiAdaptor->Role = SSI_SLAVE;
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}
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else
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#endif
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{
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//DBG_SSI_INFO("SSI%d will be as master. (spi0_is_slave: %d)\n", index, spi0_is_slave);
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pHalSsiAdaptor->Role = SSI_MASTER;
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}
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HalSsiOpInit((VOID*)pHalSsiOp);
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pHalSsiOp->HalSsiSetDeviceRole(pHalSsiAdaptor, pHalSsiAdaptor->Role);
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/* Pinmux workaround */
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if ((ssi_idx == 0) && (ssi_pinmux == SSI0_MUX_TO_GPIOC)) {
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EEPROM_PIN_CTRL(OFF);
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}
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if ((ssi_idx == 0) && (ssi_pinmux == SSI0_MUX_TO_GPIOE)) {
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DBG_SSI_WARN(ANSI_COLOR_MAGENTA"SPI0 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
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}
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//pHalSsiOp->HalSsiPinmuxEnable(pHalSsiAdaptor);
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//TODO: Implement default setting structure.
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pHalSsiOp->HalSsiLoadSetting(pHalSsiAdaptor, (void*)&SpiDefaultSetting);
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pHalSsiAdaptor->DefaultRxThresholdLevel = SpiDefaultSetting.RxThresholdLevel;
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//pHalSsiOp->HalSsiInit(pHalSsiAdaptor);
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HalSsiInit(pHalSsiAdaptor);
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pHalSsiAdaptor->TxCompCallback = spi_tx_done_callback;
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pHalSsiAdaptor->TxCompCbPara = (void*)obj;
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pHalSsiAdaptor->RxCompCallback = spi_rx_done_callback;
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pHalSsiAdaptor->RxCompCbPara = (void*)obj;
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#ifdef CONFIG_GDMA_EN
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HalGdmaOpInit((VOID*)&SpiGdmaOp);
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pHalSsiAdaptor->DmaConfig.pHalGdmaOp = &SpiGdmaOp;
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pHalSsiAdaptor->DmaConfig.pRxHalGdmaAdapter = &obj->spi_gdma_adp_rx;
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pHalSsiAdaptor->DmaConfig.pTxHalGdmaAdapter = &obj->spi_gdma_adp_tx;
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obj->dma_en = 0;
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#endif
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}
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void spi_free (spi_t *obj)
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{
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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//PHAL_SSI_OP pHalSsiOp;
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pHalSsiAdaptor = &obj->spi_adp;
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//pHalSsiOp = &obj->spi_op;
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//pHalSsiOp->HalSsiInterruptDisable(pHalSsiAdaptor);
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//pHalSsiOp->HalSsiDisable(pHalSsiAdaptor);
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//pHalSsiOp->HalSsiPinmuxDisable(pHalSsiAdaptor);
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HalSsiDeInit(pHalSsiAdaptor);
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SPI0_MULTI_CS_CTRL(OFF);
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#ifdef CONFIG_GDMA_EN
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if (obj->dma_en & SPI_DMA_RX_EN) {
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HalSsiRxGdmaDeInit(pHalSsiAdaptor);
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}
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if (obj->dma_en & SPI_DMA_TX_EN) {
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HalSsiTxGdmaDeInit(pHalSsiAdaptor);
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}
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obj->dma_en = 0;
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#endif
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}
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void spi_format (spi_t *obj, int bits, int mode, int slave)
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{
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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PHAL_SSI_OP pHalSsiOp;
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pHalSsiAdaptor = &obj->spi_adp;
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pHalSsiOp = &obj->spi_op;
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pHalSsiAdaptor->DataFrameSize = (bits - 1);
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/*
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* mode | POL PHA
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* -----+--------
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* 0 | 0 0
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* 1 | 0 1
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* 2 | 1 0
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* 3 | 1 1
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*
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* SCPOL_INACTIVE_IS_LOW = 0,
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* SCPOL_INACTIVE_IS_HIGH = 1
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*
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* SCPH_TOGGLES_IN_MIDDLE = 0,
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* SCPH_TOGGLES_AT_START = 1
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*/
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switch (mode)
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{
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case 0:
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pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_LOW;
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pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_IN_MIDDLE;
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break;
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case 1:
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pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_LOW;
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pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_AT_START;
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break;
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case 2:
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pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_HIGH;
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pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_IN_MIDDLE;
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break;
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case 3:
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pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_HIGH;
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pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_AT_START;
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break;
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default: // same as 3
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pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_HIGH;
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pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_AT_START;
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break;
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}
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if (slave == 1) {
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if (pHalSsiAdaptor->Index == 0) {
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pHalSsiAdaptor->Role = SSI_SLAVE;
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pHalSsiAdaptor->SlaveOutputEnable = SLV_TXD_ENABLE; // <-- Slave only
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SPI0_IS_AS_SLAVE = 1;
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DBG_SSI_INFO("SPI0 is as slave\n");
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}
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else {
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DBG_SSI_ERR("The SPI%d cannot work as Slave mode, only SPI0 does.\r\n", pHalSsiAdaptor->Index);
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pHalSsiAdaptor->Role = SSI_MASTER;
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}
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}
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else {
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pHalSsiAdaptor->Role = SSI_MASTER;
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}
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pHalSsiOp->HalSsiSetDeviceRole(pHalSsiAdaptor, pHalSsiAdaptor->Role);
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#ifdef CONFIG_GPIO_EN
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if (pHalSsiAdaptor->Role == SSI_SLAVE) {
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if (pHalSsiAdaptor->SclkPolarity == SCPOL_INACTIVE_IS_LOW) {
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HAL_GPIO_PullCtrl((u32)obj->sclk, hal_PullDown);
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}
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else {
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HAL_GPIO_PullCtrl((u32)obj->sclk, hal_PullUp);
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}
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}
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#endif
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pHalSsiOp->HalSsiInit(pHalSsiAdaptor);
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}
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void spi_frequency (spi_t *obj, int hz)
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{
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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pHalSsiAdaptor = &obj->spi_adp;
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HalSsiSetSclk(pHalSsiAdaptor, (u32)hz);
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}
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void spi_slave_select(spi_t *obj, ChipSelect slaveindex)
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{
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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PHAL_SSI_OP pHalSsiOp;
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u8 Index;
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pHalSsiAdaptor = &obj->spi_adp;
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pHalSsiOp = &obj->spi_op;
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Index = pHalSsiAdaptor->Index;
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if((pHalSsiAdaptor->Role == SSI_MASTER) && (Index == 0)){
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pHalSsiOp->HalSsiSetSlaveEnableRegister((VOID*)pHalSsiAdaptor,slaveindex);
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if(slaveindex != CS_0){
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SPI0_MULTI_CS_CTRL(ON);
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}
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}
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else{
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DBG_SSI_ERR("Only SPI 0 master mode supports slave selection.\n");
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}
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}
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static inline void ssi_write (spi_t *obj, int value)
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{
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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PHAL_SSI_OP pHalSsiOp;
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pHalSsiAdaptor = &obj->spi_adp;
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pHalSsiOp = &obj->spi_op;
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while (!pHalSsiOp->HalSsiWriteable(pHalSsiAdaptor));
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pHalSsiOp->HalSsiWrite((VOID*)pHalSsiAdaptor, value);
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}
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static inline int ssi_read(spi_t *obj)
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{
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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PHAL_SSI_OP pHalSsiOp;
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pHalSsiAdaptor = &obj->spi_adp;
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pHalSsiOp = &obj->spi_op;
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while (!pHalSsiOp->HalSsiReadable(pHalSsiAdaptor));
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return (int)pHalSsiOp->HalSsiRead(pHalSsiAdaptor);
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}
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int spi_master_write (spi_t *obj, int value)
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{
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ssi_write(obj, value);
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return ssi_read(obj);
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}
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int spi_slave_receive (spi_t *obj)
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{
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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PHAL_SSI_OP pHalSsiOp;
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int Readable;
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int Busy;
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pHalSsiAdaptor = &obj->spi_adp;
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pHalSsiOp = &obj->spi_op;
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Readable = pHalSsiOp->HalSsiReadable(pHalSsiAdaptor);
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Busy = (int)pHalSsiOp->HalSsiBusy(pHalSsiAdaptor);
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return ((Readable && !Busy) ? 1 : 0);
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}
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int spi_slave_read (spi_t *obj)
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{
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return ssi_read(obj);
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}
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void spi_slave_write (spi_t *obj, int value)
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{
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ssi_write(obj, value);
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}
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int spi_busy (spi_t *obj)
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{
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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PHAL_SSI_OP pHalSsiOp;
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pHalSsiAdaptor = &obj->spi_adp;
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pHalSsiOp = &obj->spi_op;
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return (int)pHalSsiOp->HalSsiBusy(pHalSsiAdaptor);
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}
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void spi_flush_rx_fifo (spi_t *obj)
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{
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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PHAL_SSI_OP pHalSsiOp;
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u32 rx_fifo_level;
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u32 i;
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pHalSsiAdaptor = &obj->spi_adp;
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pHalSsiOp = &obj->spi_op;
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while(pHalSsiOp->HalSsiReadable(pHalSsiAdaptor)){
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rx_fifo_level = pHalSsiOp->HalSsiGetRxFifoLevel(pHalSsiAdaptor);
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for(i=0;i<rx_fifo_level;i++) {
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pHalSsiOp->HalSsiRead(pHalSsiAdaptor);
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}
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}
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}
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// Slave mode read a sequence of data by interrupt mode
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int32_t spi_slave_read_stream(spi_t *obj, char *rx_buffer, uint32_t length)
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{
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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PHAL_SSI_OP pHalSsiOp;
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int32_t ret;
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if (obj->state & SPI_STATE_RX_BUSY) {
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DBG_SSI_WARN("spi_slave_read_stream: state(0x%x) is not ready\r\n",
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obj->state);
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return HAL_BUSY;
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}
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pHalSsiAdaptor = &obj->spi_adp;
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pHalSsiOp = &obj->spi_op;
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//DBG_SSI_INFO("rx_buffer addr: %X, length: %d\n", rx_buffer, length);
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obj->state |= SPI_STATE_RX_BUSY;
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if ((ret=pHalSsiOp->HalSsiReadInterrupt(pHalSsiAdaptor, rx_buffer, length)) != HAL_OK) {
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obj->state &= ~SPI_STATE_RX_BUSY;
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}
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return ret;
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}
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// Slave mode write a sequence of data by interrupt mode
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int32_t spi_slave_write_stream(spi_t *obj, char *tx_buffer, uint32_t length)
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{
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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PHAL_SSI_OP pHalSsiOp;
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int32_t ret;
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if (obj->state & SPI_STATE_TX_BUSY) {
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DBG_SSI_WARN("spi_slave_write_stream: state(0x%x) is not ready\r\n",
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obj->state);
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return HAL_BUSY;
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}
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pHalSsiAdaptor = &obj->spi_adp;
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pHalSsiOp = &obj->spi_op;
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obj->state |= SPI_STATE_TX_BUSY;
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if ((ret=pHalSsiOp->HalSsiWriteInterrupt(pHalSsiAdaptor, (u8 *) tx_buffer, length)) != HAL_OK) {
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obj->state &= ~SPI_STATE_TX_BUSY;
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}
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return ret;
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}
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// Master mode read a sequence of data by interrupt mode
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// The length unit is byte, for both 16-bits and 8-bits mode
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int32_t spi_master_read_stream(spi_t *obj, char *rx_buffer, uint32_t length)
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{
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PHAL_SSI_ADAPTOR pHalSsiAdaptor;
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PHAL_SSI_OP pHalSsiOp;
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int32_t ret;
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if (obj->state & SPI_STATE_RX_BUSY) {
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DBG_SSI_WARN("spi_master_read_stream: state(0x%x) is not ready\r\n",
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obj->state);
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return HAL_BUSY;
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}
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pHalSsiAdaptor = &obj->spi_adp;
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pHalSsiOp = &obj->spi_op;
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// wait bus idle
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while(pHalSsiOp->HalSsiBusy(pHalSsiAdaptor));
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obj->state |= SPI_STATE_RX_BUSY;
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if ((ret=pHalSsiOp->HalSsiReadInterrupt(pHalSsiAdaptor, rx_buffer, length)) == HAL_OK) {
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/* as Master mode, it need to push data to TX FIFO to generate clock out
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then the slave can transmit data out */
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// send some dummy data out
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if ((ret=pHalSsiOp->HalSsiWriteInterrupt(pHalSsiAdaptor, NULL, length)) != HAL_OK) {
|
|
obj->state &= ~SPI_STATE_RX_BUSY;
|
|
}
|
|
}
|
|
else {
|
|
obj->state &= ~SPI_STATE_RX_BUSY;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
// Master mode write a sequence of data by interrupt mode
|
|
// The length unit is byte, for both 16-bits and 8-bits mode
|
|
int32_t spi_master_write_stream(spi_t *obj, char *tx_buffer, uint32_t length)
|
|
{
|
|
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
|
|
PHAL_SSI_OP pHalSsiOp;
|
|
int32_t ret;
|
|
|
|
if (obj->state & SPI_STATE_TX_BUSY) {
|
|
DBG_SSI_WARN("spi_master_write_stream: state(0x%x) is not ready\r\n",
|
|
obj->state);
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
pHalSsiAdaptor = &obj->spi_adp;
|
|
pHalSsiOp = &obj->spi_op;
|
|
|
|
obj->state |= SPI_STATE_TX_BUSY;
|
|
/* as Master mode, sending data will receive data at sametime, so we need to
|
|
drop those received dummy data */
|
|
if ((ret=pHalSsiOp->HalSsiWriteInterrupt(pHalSsiAdaptor, (u8 *) tx_buffer, length)) != HAL_OK) {
|
|
obj->state &= ~SPI_STATE_TX_BUSY;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
// Master mode write a sequence of data by interrupt mode
|
|
// The length unit is byte, for both 16-bits and 8-bits mode
|
|
int32_t spi_master_write_read_stream(spi_t *obj, char *tx_buffer,
|
|
char *rx_buffer, uint32_t length)
|
|
{
|
|
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
|
|
PHAL_SSI_OP pHalSsiOp;
|
|
int32_t ret;
|
|
|
|
if (obj->state & (SPI_STATE_RX_BUSY|SPI_STATE_TX_BUSY)) {
|
|
DBG_SSI_WARN("spi_master_write_and_read_stream: state(0x%x) is not ready\r\n",
|
|
obj->state);
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
pHalSsiAdaptor = &obj->spi_adp;
|
|
pHalSsiOp = &obj->spi_op;
|
|
// wait bus idle
|
|
while(pHalSsiOp->HalSsiBusy(pHalSsiAdaptor));
|
|
|
|
obj->state |= SPI_STATE_RX_BUSY;
|
|
/* as Master mode, sending data will receive data at sametime */
|
|
if ((ret=pHalSsiOp->HalSsiReadInterrupt(pHalSsiAdaptor, rx_buffer, length)) == HAL_OK) {
|
|
obj->state |= SPI_STATE_TX_BUSY;
|
|
if ((ret=pHalSsiOp->HalSsiWriteInterrupt(pHalSsiAdaptor, (u8 *) tx_buffer, length)) != HAL_OK) {
|
|
obj->state &= ~(SPI_STATE_RX_BUSY|SPI_STATE_TX_BUSY);
|
|
// Disable RX IRQ
|
|
pHalSsiAdaptor->InterruptMask &= ~(BIT_IMR_RXFIM | BIT_IMR_RXOIM | BIT_IMR_RXUIM);
|
|
pHalSsiOp->HalSsiSetInterruptMask((VOID*)pHalSsiAdaptor);
|
|
}
|
|
}
|
|
else {
|
|
obj->state &= ~(SPI_STATE_RX_BUSY);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
void spi_tx_done_callback(VOID *obj)
|
|
{
|
|
spi_t *spi_obj = (spi_t *)obj;
|
|
spi_irq_handler handler;
|
|
|
|
if (spi_obj->state & SPI_STATE_TX_BUSY) {
|
|
spi_obj->state &= ~SPI_STATE_TX_BUSY;
|
|
if (spi_obj->irq_handler) {
|
|
handler = (spi_irq_handler)spi_obj->irq_handler;
|
|
handler(spi_obj->irq_id, SpiTxIrq);
|
|
}
|
|
}
|
|
}
|
|
|
|
void spi_rx_done_callback(VOID *obj)
|
|
{
|
|
spi_t *spi_obj = (spi_t *)obj;
|
|
spi_irq_handler handler;
|
|
|
|
spi_obj->state &= ~SPI_STATE_RX_BUSY;
|
|
if (spi_obj->irq_handler) {
|
|
handler = (spi_irq_handler)spi_obj->irq_handler;
|
|
handler(spi_obj->irq_id, SpiRxIrq);
|
|
}
|
|
}
|
|
|
|
void spi_irq_hook(spi_t *obj, spi_irq_handler handler, uint32_t id)
|
|
{
|
|
obj->irq_handler = (u32)handler;
|
|
obj->irq_id = (u32)id;
|
|
}
|
|
|
|
void spi_enable(spi_t *obj)
|
|
{
|
|
PHAL_SSI_ADAPTOR pHalSsiAdapter;
|
|
pHalSsiAdapter = &obj->spi_adp;
|
|
|
|
HalSsiEnable((VOID*)pHalSsiAdapter);
|
|
}
|
|
|
|
void spi_disable(spi_t *obj)
|
|
{
|
|
PHAL_SSI_ADAPTOR pHalSsiAdapter;
|
|
pHalSsiAdapter = &obj->spi_adp;
|
|
|
|
HalSsiDisable((VOID*)pHalSsiAdapter);
|
|
|
|
}
|
|
#ifdef CONFIG_GDMA_EN
|
|
int32_t spi_slave_read_stream_dma(spi_t *obj, char *rx_buffer, uint32_t length)
|
|
{
|
|
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
|
|
PHAL_SSI_OP pHalSsiOp;
|
|
int32_t ret;
|
|
|
|
if (obj->state & SPI_STATE_RX_BUSY) {
|
|
DBG_SSI_WARN("spi_slave_read_stream_dma: state(0x%x) is not ready\r\n",
|
|
obj->state);
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
pHalSsiAdaptor = &obj->spi_adp;
|
|
pHalSsiOp = &obj->spi_op;
|
|
|
|
if ((obj->dma_en & SPI_DMA_RX_EN)==0) {
|
|
if (HAL_OK == HalSsiRxGdmaInit(pHalSsiOp, pHalSsiAdaptor)) {
|
|
obj->dma_en |= SPI_DMA_RX_EN;
|
|
}
|
|
else {
|
|
return HAL_BUSY;
|
|
}
|
|
}
|
|
|
|
obj->state |= SPI_STATE_RX_BUSY;
|
|
ret = HalSsiDmaRecv(pHalSsiAdaptor, (u8 *) rx_buffer, length);
|
|
if (ret != HAL_OK) {
|
|
obj->state &= ~SPI_STATE_RX_BUSY;
|
|
}
|
|
return (ret);
|
|
}
|
|
|
|
int32_t spi_slave_write_stream_dma(spi_t *obj, char *tx_buffer, uint32_t length)
|
|
{
|
|
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
|
|
PHAL_SSI_OP pHalSsiOp;
|
|
int32_t ret;
|
|
|
|
if (obj->state & SPI_STATE_TX_BUSY) {
|
|
DBG_SSI_WARN("spi_slave_write_stream_dma: state(0x%x) is not ready\r\n",
|
|
obj->state);
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
pHalSsiAdaptor = &obj->spi_adp;
|
|
pHalSsiOp = &obj->spi_op;
|
|
|
|
if ((obj->dma_en & SPI_DMA_TX_EN)==0) {
|
|
if (HAL_OK == HalSsiTxGdmaInit(pHalSsiOp, pHalSsiAdaptor)) {
|
|
obj->dma_en |= SPI_DMA_TX_EN;
|
|
}
|
|
else {
|
|
return HAL_BUSY;
|
|
}
|
|
}
|
|
obj->state |= SPI_STATE_TX_BUSY;
|
|
ret = HalSsiDmaSend(pHalSsiAdaptor, (u8 *) tx_buffer, length);
|
|
if (ret != HAL_OK) {
|
|
obj->state &= ~SPI_STATE_TX_BUSY;
|
|
}
|
|
return (ret);
|
|
}
|
|
|
|
int32_t spi_master_read_stream_dma(spi_t *obj, char *rx_buffer, uint32_t length)
|
|
{
|
|
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
|
|
PHAL_SSI_OP pHalSsiOp;
|
|
int32_t ret;
|
|
|
|
if (obj->state & SPI_STATE_RX_BUSY) {
|
|
DBG_SSI_WARN("spi_master_read_stream_dma: state(0x%x) is not ready\r\n",
|
|
obj->state);
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
pHalSsiAdaptor = &obj->spi_adp;
|
|
pHalSsiOp = &obj->spi_op;
|
|
|
|
if ((obj->dma_en & SPI_DMA_RX_EN)==0) {
|
|
if (HAL_OK == HalSsiRxGdmaInit(pHalSsiOp, pHalSsiAdaptor)) {
|
|
obj->dma_en |= SPI_DMA_RX_EN;
|
|
}
|
|
else {
|
|
return HAL_BUSY;
|
|
}
|
|
}
|
|
|
|
obj->state |= SPI_STATE_RX_BUSY;
|
|
ret = HalSsiDmaRecv(pHalSsiAdaptor, (u8 *) rx_buffer, length);
|
|
if (ret != HAL_OK) {
|
|
obj->state &= ~SPI_STATE_RX_BUSY;
|
|
}
|
|
|
|
// for master mode, we need to send data to generate clock out
|
|
if (obj->dma_en & SPI_DMA_TX_EN) {
|
|
// TX DMA is on already, so use DMA to TX data
|
|
// Make the GDMA to use the rx_buffer too
|
|
ret = HalSsiDmaSend(pHalSsiAdaptor, (u8 *) rx_buffer, length);
|
|
if (ret != HAL_OK) {
|
|
obj->state &= ~SPI_STATE_RX_BUSY;
|
|
}
|
|
}
|
|
else {
|
|
// TX DMA isn't enabled, so we just use Interrupt mode to TX dummy data
|
|
if ((ret=pHalSsiOp->HalSsiWriteInterrupt(pHalSsiAdaptor, NULL, length)) != HAL_OK) {
|
|
obj->state &= ~SPI_STATE_RX_BUSY;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int32_t spi_master_write_stream_dma(spi_t *obj, char *tx_buffer, uint32_t length)
|
|
{
|
|
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
|
|
PHAL_SSI_OP pHalSsiOp;
|
|
int32_t ret;
|
|
|
|
if (obj->state & SPI_STATE_TX_BUSY) {
|
|
DBG_SSI_WARN("spi_master_write_stream_dma: state(0x%x) is not ready\r\n",
|
|
obj->state);
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
pHalSsiAdaptor = &obj->spi_adp;
|
|
pHalSsiOp = &obj->spi_op;
|
|
|
|
if ((obj->dma_en & SPI_DMA_TX_EN)==0) {
|
|
if (HAL_OK == HalSsiTxGdmaInit(pHalSsiOp, pHalSsiAdaptor)) {
|
|
obj->dma_en |= SPI_DMA_TX_EN;
|
|
}
|
|
else {
|
|
return HAL_BUSY;
|
|
}
|
|
}
|
|
|
|
obj->state |= SPI_STATE_TX_BUSY;
|
|
ret = HalSsiDmaSend(pHalSsiAdaptor, (u8 *) tx_buffer, length);
|
|
if (ret != HAL_OK) {
|
|
obj->state &= ~SPI_STATE_TX_BUSY;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
#endif // end of "#ifdef CONFIG_GDMA_EN"
|