mirror of
https://github.com/cwyark/ameba-sdk-gcc-make.git
synced 2024-11-25 23:44:19 +00:00
204 lines
11 KiB
Text
204 lines
11 KiB
Text
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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/*-Specials-*/
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//define symbol __ICFEDIT_intvec_start__ = 0x00000000;
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF;
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define symbol __ICFEDIT_region_TCM_start__ = 0x1FFF0000;
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define symbol __ICFEDIT_region_TCM_end__ = 0x1FFFFFFF;
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define symbol __ICFEDIT_region_ROM_USED_RAM_start__ = 0x10000000;
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define symbol __ICFEDIT_region_ROM_USED_RAM_end__ = 0x10005FFF;
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//define symbol __ICFEDIT_region_RECY_RAM_start__ = 0x10002090;
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//define symbol __ICFEDIT_region_RECY_RAM_end__ = 0x100037FF;
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define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10006000;
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define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1006FFFF;
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define symbol __ICFEDIT_region_SDRAM_RAM_start__ = 0x30000000;
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define symbol __ICFEDIT_region_SDRAM_RAM_end__ = 0x301FFFFF;
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/*-Sizes-*/
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/*define symbol __ICFEDIT_size_cstack__ = 0x400;*/
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/*define symbol __ICFEDIT_size_heap__ = 0x800;*/
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
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define region ROM_USED_RAM_region = mem:[from __ICFEDIT_region_ROM_USED_RAM_start__ to __ICFEDIT_region_ROM_USED_RAM_end__];
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//define region RECY_RAM_region = mem:[from __ICFEDIT_region_RECY_RAM_start__ to __ICFEDIT_region_RECY_RAM_end__];
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define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__];
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define region SDRAM_RAM_region = mem:[from __ICFEDIT_region_SDRAM_RAM_start__ to __ICFEDIT_region_SDRAM_RAM_end__];
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/*define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };*/
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/*define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };*/
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//initialize by copy { readwrite };
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//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
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//do not initialize { section * };
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//place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors_table };
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/*place in RAM_region { readwrite, block CSTACK, block HEAP };*/
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place in TCM_region { readwrite };
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/****************************************
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* ROM Section config *
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****************************************/
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keep { section .rom };
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place at start of ROM_region { readonly, section .rom };
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/****************************************
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* BD RAM Section config *
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****************************************/
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keep { section .ram_dedecated_vector_table* };
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define block .vector_table with fixed order{section .ram_dedecated_vector_table*};
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keep { section .ram_user_define_irq_table* };
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define block .user_vector_table with fixed order{section .ram_user_define_irq_table*};
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keep { section .ram_user_define_data_table* };
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define block .user_data_table with fixed order{section .ram_user_define_data_table*};
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define block .rom.bss with fixed order{ section .hal.ram.bss* object hal_misc.o,
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section .hal.ram.bss* object hal_pinmux.o,
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section .hal.ram.bss* object diag.o,
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section .hal.ram.bss* object rtl8195a_ssi_rom.o,
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section .hal.ram.bss* object rtl8195a_gpio.o,
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section .hal.ram.bss*,
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section .timer2_7_vector_table.data*,
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section .infra.ram.bss*,
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section .mon.ram.bss*,
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section .wlan_ram_map* object rom_wlan_ram_map.o,
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section .wlan_ram_map*,
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section .libc.ram.bss*,
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};
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keep { section .start.ram.data* };
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define block .ram.start.table with fixed order{ section .start.ram.data* };
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keep { section .image1.validate.rodata* };
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keep { section .infra.ram.data* };
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keep { section .timer.ram.data* };
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keep { section .hal.ram.data* };
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define block .ram_image1.data with fixed order{ section .image1.validate.rodata*,
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section .infra.ram.data*,
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section .timer.ram.data*,
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section .cutb.ram.data*,
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section .hal.ram.data* object rom.o, // for standard libaray __impure_data_ptr
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section .cutc.ram.data*,
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section .hal.ram.data*
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};
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define block .ram_image1.bss with fixed order{ //section .hal.flash.data*,
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section .hal.sdrc.data*
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};
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define block .ram_image1.text with fixed order{ section .hal.ram.text*,
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section .hal.sdrc.text*,
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//section .text* object startup.o,
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section .infra.ram.text*,
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};
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define block IMAGE1 with fixed order { section LOADER };
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define block IMAGE1_DBG with fixed order { block .ram.start.table, block .ram_image1.data, block .ram_image1.bss, block .ram_image1.text };
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place at start of ROM_USED_RAM_region { readwrite,
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block .vector_table,
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block .user_vector_table,
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block .user_data_table,
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block .rom.bss,
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block IMAGE1
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};
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keep { section .image2.ram.data* };
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define block .image2.start.table1 with fixed order{ section .image2.ram.data* };
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keep { section .image2.validate.rodata*, section .custom.validate.rodata* };
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define block .image2.start.table2 with fixed order{ section .image2.validate.rodata*, section .custom.validate.rodata* };
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define block SHT$$PREINIT_ARRAY { preinit_array };
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define block SHT$$INIT_ARRAY { init_array };
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define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY,
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block SHT$$INIT_ARRAY };
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define block .ram_image2.text with fixed order{ section .infra.ram.start*,
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section .rodata*,
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block CPP_INIT,
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section .mon.ram.text*,
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section .hal.flash.text*,
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section .hal.gpio.text*,
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section .text* object main.o,
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section .text*,
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section CODE,
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section .otg.rom.text,
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section Veneer object startup.o,
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section __DLIB_PERTHREAD,
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//section .mdns.text
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};
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define block .ram.data with fixed order{ section .data*,
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section DATA,
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section .ram.otg.data.a,
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section .iar.init_table,
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//section .mdns.data
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};
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define block IMAGE2 with fixed order { block .image2.start.table1, block .image2.start.table2, block .ram_image2.text, block .ram.data };
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define block .ram.bss with fixed order{ section .bss*,
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section .ssl_ram_map,
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section .hal.flash.data*,
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section .hal.gpio.data*,
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section COMMON,
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section .bdsram.data*,
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section .bss* object heap_4.o
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};
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define block .bf_data with fixed order{ section .bfsram.data* };
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define block .heap with fixed order{ section .heap* };
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define block .stack_dummy with fixed order { section .stack };
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place at start of BD_RAM_region { readwrite,
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block IMAGE2,
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//block IMAGE1_DBG,
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block .ram.bss,
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//block .bf_data,
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};
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//place at address mem:0x10052b00 { readwrite,
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place at end of BD_RAM_region { readwrite,
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block .bf_data,
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};
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define block SDRAM with fixed order{ section .sdram.text*,
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section .sdram.data*,
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section .mdns.text*,
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section .mdns.data*
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};
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place at start of SDRAM_RAM_region { readwrite,
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block SDRAM,
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//block IMAGE1_DBG
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};
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/* TCM placement */
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define overlay TCM_overlay { section .tcm.heap,
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section .bss object mem.o,
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section .bss object memp.o,
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block .heap,
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block .stack_dummy
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};
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/* dummy code placement */
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define overlay TCM_overlay { block IMAGE1_DBG };
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place at start of TCM_region { readwrite,
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overlay TCM_overlay
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};
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define exported symbol __rom_bss_start__ = 0x10000300; // use in rom
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define exported symbol __rom_bss_end__ = 0x10000bc8; // use in rom
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define exported symbol __ram_start_table_start__= 0x10000bc8; // use in rom
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define exported symbol __image1_validate_code__= 0x10000bdc; // needed by ram code
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define exported symbol _rtl_impure_ptr = 0x10001c60; // for standard library
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