mirror of
https://github.com/eggman/ameba-gcc-sample-rtos.git
synced 2024-11-22 20:04:15 +00:00
210 lines
4.4 KiB
Text
210 lines
4.4 KiB
Text
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ENTRY(Reset_Handler)
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INCLUDE "export-rom_v03.txt"
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__stack_size__ = 512K; /* interrupts are handled within this stack */
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__min_heap_size__ = 128K;
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MEMORY
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{
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TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 65536
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ROM_USED_RAM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x5FFF
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BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 434176
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SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
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}
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SECTIONS
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{
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__rom_bss_start__ = 0x10000300;
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__rom_bss_end__ = 0x10000bc8;
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.ram.start.table :
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{
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__ram_image1_text_start__ = .;
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__ram_start_table_start__ = .;
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KEEP(*(SORT(.start.ram.data*)))
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__ram_start_table_end__ = .;
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} > ROM_USED_RAM
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/* Add . to assign the start address of the section, *
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* to prevent the change of the start address by ld doing section alignment */
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.ram_image1.text . :
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{
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/* these 4 sections is used by ROM global variable */
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/* Don't move them and never add RAM code variable to these sections */
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__image1_validate_code__ = .;
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KEEP(*(.image1.validate.rodata*))
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KEEP(*(.infra.ram.data*))
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KEEP(*(.timer.ram.data*))
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KEEP(*(.cutb.ram.data*))
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KEEP(*(.cutc.ram.data*))
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KEEP(*(.hal.ram.data*))
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.ram_image1.bss$$Base = .;
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__image1_bss_start__ = .;
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.ram_image1.bss$$Limit = .;
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__image1_bss_end__ = .;
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__ram_image1_data_end__ = .;
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*(.hal.ram.text*)
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*(.infra.ram.text*)
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__ram_image1_text_end__ = .;
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} > ROM_USED_RAM
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.tcm :
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{
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__tcm_start__ = .;
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*(.tcm.heap)
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*mem.o (.bss)
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*memp.o (.bss)
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__tcm_end__ = .;
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} > TCM
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.sdr_data :
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{
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__sdram_data_start__ = .;
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*(.mon.ram.text*)
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INCLUDE "sdram_obj_list.txt"
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*(.sdram.text*)
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*(.sdram.data*)
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__sdram_data_end__ = .;
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} > SDRAM_RAM
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.mp_data :
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{
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/* define micropython heap start and end */
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_mp_heap_head = .;
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. = . + __min_heap_size__;
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. = . + (ORIGIN(SDRAM_RAM) + LENGTH(SDRAM_RAM) - __stack_size__ - ABSOLUTE(.));
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_mp_heap_end = .;
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} > SDRAM_RAM
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.sdr_otg_bf_data :
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{
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__sdram_otg_buffer_data_start__ = .;
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*(.ram.otg.bfdata*)
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__sdram_otg_buffer_data_end__ = .;
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} > SDRAM_RAM
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.sdr_bf_data :
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{
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__sdram_buffer_data_start__ = .;
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*(.ossdram.heap*)
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__sdram_buffer_data_end__ = .;
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} > SDRAM_RAM
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.image2.start.table :
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{
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.image2.start.table1$$Base = .;
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__ram_image2_text_start__ = .;
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__image2_entry_func__ = .;
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KEEP(*(SORT(.image2.ram.data*)))
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__image2_validate_code__ = .;
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KEEP(*(.image2.validate.rodata*))
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} > BD_RAM
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.ram_image2.text :
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{
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KEEP(*(.infra.ram.start*))
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PROVIDE (_init = .);
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. = ALIGN(4);
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KEEP(*(.init))
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/* init data */
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. = ALIGN(4);
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PROVIDE (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE (__init_array_end = .);
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. = ALIGN(4);
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KEEP(*(.fini))
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. = ALIGN(4);
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PROVIDE (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE (__fini_array_end = .);
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*(.rodata*)
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*(.hal.flash.text*)
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*(.hal.sdrc.text*)
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*(.hal.gpio.text*)
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*(.fwu.rodata*)
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*(.fwu.text*)
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*(.otg.rom.text*)
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*(.text*)
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} > BD_RAM
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.ram.data :
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{
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__data_start__ = .;
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*(.data*)
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__data_end__ = .;
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__ram_image2_text_end__ = .;
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} > BD_RAM
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.ram.bss :
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{
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.ram.bss$$Base = .;
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__bss_start__ = .;
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*(.hal.flash.data*)
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*(.hal.sdrc.data*)
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*(.hal.gpio.data*)
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*(.fwu.data*)
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*(.ram.otg.data.a*)
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*(.ram.otg.data.b*)
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*(.bss*)
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*(.mon.ram.bss*)
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*(COMMON)
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*(.bdsram.data*)
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*(.bfsram.data*)
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__bss_end__ = .;
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.ram.bss$$Limit = .;
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} > BD_RAM
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.bf_data :
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{
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__buffer_data_start__ = .;
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*(.ossram.heap*)
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__buffer_data_end__ = .;
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} > BD_RAM
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.heap :
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{
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__end__ = .;
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end = __end__;
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*(.heap*)
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__HeapLimit = .;
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} > BD_RAM
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/* .stack_dummy section doesn't contains any symbols. It is only
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* used for linker to calculate size of stack sections, and assign
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* values to stack symbols later */
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.stack_dummy :
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{
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*(.stack)
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} > BD_RAM
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/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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__StackTop = ORIGIN(BD_RAM) + LENGTH(BD_RAM);
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__StackLimit = __StackTop - SIZEOF(.stack_dummy);
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PROVIDE(__stack = __StackTop);
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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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}
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