mirror of
https://github.com/rtlduino/RTL8710AF_GCC.git
synced 2024-11-23 09:44:15 +00:00
404 lines
13 KiB
C
404 lines
13 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*******************************************************************************/
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#ifndef __RTL8195A_GSPI_H__
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#define __RTL8195A_GSPI_H__
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#define SPI_LOCAL_DOMAIN 0x0
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#define SPI_TXFIFO_DOMAIN 0xc
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#define SPI_RXFIFO_DOMAIN 0x1f
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//IO Bus domain address mapping
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#define DEFUALT_OFFSET 0x0
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#define SPI_LOCAL_OFFSET 0x10250000
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#define SPI_TX_FIFO_OFFSET 0x10310000
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#define SPI_RX_FIFO_OFFSET 0x10340000
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#define SPI_LOCAL_DEVICE_ID 0
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#define SPI_TXQ_FIFO_DEVICE_ID 3
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#define SPI_RXQ_FIFO_DEVICE_ID 7
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#define SPI_UNDEFINED_DEVICE_ID (-1)
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//SPI Local registers
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#define SPI_REG_INT_CTRL 0x0004 // 4 bytes, SPI INT Control
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#define SPI_REG_INT_TIMEOUT 0x0006 // 2 bytes, SPI 32us INT timout
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#define SPI_REG_HIMR 0x0014 // 4 bytes, SPI Host Interrupt Mask
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#define SPI_REG_HISR 0x0018 // 4 bytes, SPI Host Interrupt Service Routine
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#define SPI_REG_RX0_REQ_LEN 0x001C // 4 bytes, RXDMA Request Length
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#define SPI_REG_FREE_TX_SPACE 0x0020 // 4 bytes, Free Tx Buffer Page
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#define SPI_REG_TX_SEQNUM 0x0024 // 1 byte, TX Sequence Number Definition
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#define SPI_REG_HCPWM 0x0038 // 1 byte, HCI Current Power Mode
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#define SPI_REG_HCPWM2 0x003A // 2 bytes, HCI Current Power Mode 2
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#define SPI_REG_AVAI_PATH_L 0x0040 // 4 bytes, SPI TX Available Low Size reg
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#define SPI_REG_AVAI_PATH_H 0x0044 // 4 bytes, SPI TX Available High Size reg
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#define SPI_REG_RX_AGG_CTL 0x0048 // 4 bytes, SPI RX AGG control
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#define SPI_REG_H2C_MSG 0x004C // 4 bytes, SPI_REG_H2C_MSG
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#define SPI_REG_C2H_MSG 0x0050 // 4 bytes, SPI_REG_C2H_MSG
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#define SPI_REG_HRPWM 0x0080 // 1 byte, SPI_REG_HRPWM
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#define SPI_REG_HPS_CLKR 0x0084 // 1 byte, not uesd
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#define SPI_REG_CPU_IND 0x0087 // 1 byte, firmware indication to host
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#define SPI_REG_32K_TRANS_CTL 0x0088 // 1 byte, 32K transparent control, BIT0 EN32K_TRANS
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#define SPI_REG_32K_IDLE_TIME 0x008B // 1 byte, 32K idle time,
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#define SPI_REG_DELY_LINE_SEL 0x008C // 1 byte, Delay line selection,
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#define SPI_REG_SPI_CFG 0x00F0 // 1 byte, SPI configuration,
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#define LOCAL_REG_FREE_TX_SPACE (SPI_LOCAL_OFFSET | SPI_REG_FREE_TX_SPACE)
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// Register SPI_REG_CPU_IND
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#define SPI_CPU_RDY_IND (BIT0)
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/************************************************/
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// SPI_REG_HISR: SDIO Host Interrupt Service Routine
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#define SPI_HISR_RX_REQUEST (BIT0)
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#define SPI_HISR_AVAL_INT (BIT1)
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#define SPI_HISR_TXPKT_OVER_BUFF (BIT2)
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#define SPI_HISR_TX_AGG_SIZE_MISMATCH (BIT3)
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#define SPI_HISR_TXBD_OVF (BIT4)
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//BIT5~16 not used
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#define SPI_HISR_C2H_MSG_INT (BIT17)
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#define SPI_HISR_CPWM1_INT (BIT18)
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#define SPI_HISR_CPWM2_INT (BIT19)
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//BIT20~31 not used
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#define SPI_HISR_CPU_NOT_RDY (BIT22)
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#define MASK_SPI_HISR_CLEAR (SPI_HISR_RX_REQUEST |\
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SPI_HISR_AVAL_INT |\
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SPI_HISR_TXPKT_OVER_BUFF |\
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SPI_HISR_TX_AGG_SIZE_MISMATCH |\
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SPI_HISR_TXBD_OVF |\
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SPI_HISR_C2H_MSG_INT |\
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SPI_HISR_CPWM1_INT |\
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SPI_HISR_CPWM2_INT)
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// RTL8195A SPI Host Interrupt Mask Register
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#define SPI_HIMR_RX_REQUEST_MSK (BIT0)
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#define SPI_HIMR_AVAL_MSK (BIT1)
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#define SPI_HIMR_TXPKT_SIZE_OVER_BUFF_MSK (BIT2)
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#define SPI_HIMR_AGG_SIZE_MISMATCH_MSK (BIT3)
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#define SPI_HIMR_TXBD_OVF_MSK (BIT4)
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//BIT5~16 not used
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#define SPI_HIMR_C2H_MSG_INT_MSK (BIT17)
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#define SPI_HIMR_CPWM1_INT_MSK (BIT18)
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#define SPI_HIMR_CPWM2_INT_MSK (BIT19)
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//BIT20~31 not used
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#define SPI_HIMR_DISABLED 0
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// Register SPI_REG_HCPWM
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#define SPI_HCPWM_WLAN_TRX (BIT1)
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enum{
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SPI_LITTLE_ENDIAN = 2,
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SPI_BIG_ENDIAN = 0
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};
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enum{
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SPI_WORD_LEN_16 = 0,
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SPI_WORD_LEN_32 = 1
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};
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typedef enum{
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SPI_LITTLE_ENDIAN_16 = SPI_LITTLE_ENDIAN|SPI_WORD_LEN_16,
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SPI_LITTLE_ENDIAN_32 = SPI_LITTLE_ENDIAN|SPI_WORD_LEN_32, // default configure
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SPI_BIG_ENDIAN_16 = SPI_BIG_ENDIAN|SPI_WORD_LEN_16,
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SPI_BIG_ENDIAN_32 = SPI_BIG_ENDIAN|SPI_WORD_LEN_32
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}_gspi_conf_t;
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#define GSPI_CMD_LEN 4
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#define GSPI_STATUS_LEN 8
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#define FILL_SPI_CMD(byte_en, addr, domain_id, fun, write_flag) ((byte_en & 0xff) | ((addr & 0xffff) << 8) \
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| ((domain_id & 0x1f) << 24) | ((fun & 0x3) << 29) | ((write_flag & 0x1) << 31))
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#define GET_STATUS_HISR(status) ((((*(u32*)status)) & 0x3) |((((*(u32*)status) >> 2) & 0x7) << 17))
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#define GET_STATUS_FREE_TX(status) ((((*(u32*)status) >> 5) & 0x7ffffff) << 2)
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#define GET_STATUS_RXQ_REQ_LEN(status) (((*(u32*)((u8 *)status + 4))) & 0xffffff)
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#define GET_STATUS_TX_SEQ(status) (((*(u32*)((u8 *)status + 4)) >> 24) & 0xff)
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#define GSPI_CMD_TX 0x83 //
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#define GSPI_CMD_RX 0X82
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// define transmit packat type
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#define GPSI_TX_PACKET_802_3 (0x83)
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#define GSPI_TX_PACKET_802_11 (0x81)
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#define GSPI_TX_H2C_CMD (0x11)
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#define GSPI_TX_MEM_READ (0x51)
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#define GSPI_TX_MEM_WRITE (0x53)
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#define GSPI_TX_MEM_SET (0x55)
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#define GSPI_TX_FM_FREETOGO (0x61)
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//define receive packet type
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#define GSPI_RX_PACKET_802_3 (0x82)
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#define GSPI_RX_PACKET_802_11 (0x80)
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#define GSPI_RX_C2H_CMD (0x10)
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#define GSPI_RX_MEM_READ (0x50)
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#define GSPI_RX_MEM_WRITE (0x52)
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#define GSPI_RX_MEM_SET (0x54)
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#define GSPI_RX_FM_FREETOGO (0x60)
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typedef struct _GSPI_TX_DESC{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 txpktsize:16; // bit[15:0]
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u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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#else
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
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u32 txpktsize:16; // bit[15:0]
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the packet type
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u32 rsvd0:24;
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#else
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u32 rsvd0:24;
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u32 type:8; // bit[7:0], the packet type
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#endif
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// u4Byte 2
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u32 rsvd1;
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// u4Byte 3
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u32 rsvd2;
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// u4Byte 4
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u32 rsvd3;
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// u4Byte 5
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u32 rsvd4;
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} GSPI_TX_DESC, *PGSPI_TX_DESC;
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typedef struct _GSPI_RX_DESC{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 pkt_len:16; // bit[15:0], the packet size
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u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
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u32 rsvd0:6; // bit[29:24]
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u32 icv:1; // bit[30], ICV error
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u32 crc:1; // bit[31], CRC error
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#else
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u32 crc:1; // bit[31], CRC error
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u32 icv:1; // bit[30], ICV error
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u32 rsvd0:6; // bit[29:24]
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u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
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u32 pkt_len:16; // bit[15:0], the packet size
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the type of this packet
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u32 rsvd1:24; // bit[31:8]
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#else
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u32 rsvd1:24; // bit[31:8]
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u32 type:8; // bit[7:0], the type of this packet
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#endif
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// u4Byte 2
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u32 rsvd2;
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// u4Byte 3
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u32 rsvd3;
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// u4Byte 4
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u32 rsvd4;
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// u4Byte 5
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u32 rsvd5;
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} GSPI_RX_DESC, *PGSPI_RX_DESC;
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#define SIZE_TX_DESC (sizeof(GSPI_TX_DESC))
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#define SIZE_RX_DESC (sizeof(GSPI_RX_DESC))
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// For memory read command
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typedef struct _GSPI_DESC_MR{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 pkt_len:16; // bit[15:0], the packet size
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u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
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u32 rsvd0:8; // bit[31:24]
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#else
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u32 rsvd0:8; // bit[31:24]
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u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
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u32 pkt_len:16; // bit[15:0], the packet size
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the type of this packet
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u32 rsvd1:24; // bit[31:8]
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#else
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u32 rsvd1:24; // bit[31:8]
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u32 type:8; // bit[7:0], the type of this packet
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#endif
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// u4Byte 2
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u32 start_addr;
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// u4Byte 3
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u32 rsvd2;
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// u4Byte 4
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u32 rsvd3;
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// u4Byte 5
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u32 rsvd4;
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} GSPI_DESC_MR, *PGSPI_DESC_MR;
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// For memory write reply command
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typedef struct _GSPI_DESC_MW{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 txpktsize:16; // bit[15:0]
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u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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#else
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
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u32 txpktsize:16; // bit[15:0]
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the packet type
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u32 reply:1; // bit[8], request to send a reply message
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u32 rsvd0:23;
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#else
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u32 rsvd0:23;
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u32 reply:1; // bit[8], request to send a reply message
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u32 type:8; // bit[7:0], the packet type
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#endif
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// u4Byte 2
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u32 start_addr; // memory write start address
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// u4Byte 3
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 write_len:16; // bit[15:0], the length to write
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u32 rsvd2:16; // bit[31:16]
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#else
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u32 rsvd2:16; // bit[31:16]
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u32 write_len:16; // bit[15:0], the length to write
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#endif
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// u4Byte 4
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u32 rsvd3;
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// u4Byte 5
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u32 rsvd4;
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} GSPI_DESC_MW, *PGSPI_DESC_MW;
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// For memory set command
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typedef struct _GSPI_DESC_MS{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 txpktsize:16; // bit[15:0]
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u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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#else
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
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u32 txpktsize:16; // bit[15:0]
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the packet type
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u32 data:8; // bit[8:15], the value to be written to the memory
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u32 reply:1; // bit[16], request to send a reply message
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u32 rsvd0:15;
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#else
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u32 rsvd0:15;
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u32 reply:1; // bit[16], request to send a reply message
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u32 data:8; // bit[8:15], the value to be written to the memory
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u32 type:8; // bit[7:0], the packet type
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#endif
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// u4Byte 2
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u32 start_addr; // memory write start address
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// u4Byte 3
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 write_len:16; // bit[15:0], the length to write
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u32 rsvd2:16; // bit[31:16]
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#else
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u32 rsvd2:16; // bit[31:16]
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u32 write_len:16; // bit[15:0], the length to write
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#endif
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// u4Byte 4
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u32 rsvd3;
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// u4Byte 5
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u32 rsvd4;
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} GSPI_DESC_MS, *PGSPI_DESC_MS;
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// TX Desc for Jump to Start command
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typedef struct _GSPI_DESC_JS{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 txpktsize:16; // bit[15:0]
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u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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#else
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
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u32 txpktsize:16; // bit[15:0]
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the packet type
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u32 rsvd0:24;
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#else
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u32 rsvd0:24;
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u32 type:8; // bit[7:0], the packet type
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#endif
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// u4Byte 2
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u32 start_fun; // the pointer of the startup function
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// u4Byte 3
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u32 rsvd2;
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// u4Byte 4
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u32 rsvd3;
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// u4Byte 5
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u32 rsvd4;
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} GSPI_DESC_JS, *PGSPI_DESC_JS;
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// CCPWM2 bit map definition for Firmware download
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#define GSPI_INIT_DONE (BIT0)
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#define GSPI_MEM_WR_DONE (BIT1)
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#define GSPI_MEM_RD_DONE (BIT2)
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#define GSPI_MEM_ST_DONE (BIT3)
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#define GSPI_CPWM2_TOGGLE (BIT15)
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// Register REG_SPDIO_CPU_IND
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#define GPSI_SYSTEM_TRX_RDY_IND (BIT0)
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#endif //__GSPI_REG_H__
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