mirror of
https://github.com/rtlduino/RTL8710AF_GCC.git
synced 2024-11-28 09:10:28 +00:00
150 lines
5.7 KiB
C
150 lines
5.7 KiB
C
/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _HAL_LOG_UART_H_
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#define _HAL_LOG_UART_H_
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#include "hal_diag.h"
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#define LOG_UART_WAIT_FOREVER 0xffffffff
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// Define Line Control Register Bits
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typedef enum {
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LCR_DLS_5B = 0, // Data Length: 5 bits
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LCR_DLS_6B = BIT(0), // Data Length: 6 bits
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LCR_DLS_7B = BIT(1), // Data Length: 7 bits
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LCR_DLS_8B = (BIT(1)|BIT(0)), // Data Length: 7 bits
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LCR_STOP_1B = 0, // Number of stop bits: 1
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LCR_STOP_2B = BIT(2), // Number of stop bits: 1.5(data len=5) or 2
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LCR_PARITY_NONE = 0, // Parity Enable: 0
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LCR_PARITY_ODD = BIT(3), // Parity Enable: 1, Even Parity: 0
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LCR_PARITY_EVEN = (BIT(4)|BIT(3)), // Parity Enable: 1, Even Parity: 1
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LCR_BC = BIT(6), // Break Control Bit
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LCR_DLAB = BIT(7) // Divisor Latch Access Bit
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} LOG_UART_LINE_CTRL;
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// define Log UART Interrupt Indication ID
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/*
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IIR[3:0]:
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0000 = modem status
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0001 = no interrupt pending
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0010 = THR empty
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0100 = received data available
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0110 = receiver line status
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0111 = busy detect
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1100 = character timeout
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*/
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typedef enum {
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IIR_MODEM_STATUS = 0, //Clear to send or data set ready or ring indicator or data carrier detect.
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IIR_NO_PENDING = 1,
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IIR_THR_EMPTY = 2, // TX FIFO level lower than threshold or FIFO empty
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IIR_RX_RDY = 4, // RX data ready
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IIR_RX_LINE_STATUS = 6, // Overrun/parity/framing errors or break interrupt
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IIR_BUSY = 7,
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IIR_CHAR_TIMEOUT = 12 // timeout: Rx dara ready but no read
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} LOG_UART_INT_ID;
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// Define Interrupt Enable Bit
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typedef enum {
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IER_ERBFI = BIT(0), // Enable Received Data Available Interrupt
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IER_ETBEI = BIT(1), // Enable Transmit Holding Register Empty Interrupt
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IER_ELSI = BIT(2), // Enable Receiver Line Status Interrupt
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IER_EDSSI = BIT(3), // Enable Modem Status Interrupt
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IER_PTIME = BIT(7) // Programmable THRE Interrupt Mode Enable
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} LOG_UART_INT_EN;
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// Define Line Status Bit
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typedef enum {
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LSR_DR = BIT(0), // Data Ready bit
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LSR_OE = BIT(1), // Overrun error bit
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LSR_PE = BIT(2), // Parity Error bit
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LSR_FE = BIT(3), // Framing Error bit
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LSR_BI = BIT(4), // Break Interrupt bit
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LSR_THRE = BIT(5), // Transmit Holding Register Empty bit(IER_PTIME=0)
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LSR_FIFOF = BIT(5), // Transmit FIFO Full bit(IER_PTIME=1)
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LSR_TEMT = BIT(6), // Transmitter Empty bit
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LSR_RFE = BIT(7) // Receiver FIFO Error bit
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} LOG_UART_LINE_STATUS;
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enum {
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LOG_UART_RST_TX_FIFO = 0x01,
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LOG_UART_RST_RX_FIFO = 0x02
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};
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#define LOG_UART_TX_FIFO_DEPTH 16
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#define LOG_UART_RX_FIFO_DEPTH 16
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// Define FIFO Control Register Bits
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typedef enum {
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FCR_FIFO_EN = BIT(0), // FIFO Enable.
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FCR_RST_RX = BIT(1), // RCVR FIFO Reset, self clear
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FCR_RST_TX = BIT(2), // XMIT FIFO Reset, self clear
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FCR_TX_TRIG_EMP = 0, // TX Empty Trigger: FIFO empty
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FCR_TX_TRIG_2CH = BIT(4), // TX Empty Trigger: 2 characters in the FIFO
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FCR_TX_TRIG_QF = BIT(5), // TX Empty Trigger: FIFO 1/4 full
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FCR_TX_TRIG_HF = (BIT(5)|BIT(4)), // TX Empty Trigger: FIFO 1/2 full
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FCR_TX_TRIG_MASK = (BIT(5)|BIT(4)), // TX Empty Trigger Bit Mask
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FCR_RX_TRIG_1CH = 0, // RCVR Trigger: 1 character in the FIFO
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FCR_RX_TRIG_QF = BIT(6), // RCVR Trigger: FIFO 1/4 full
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FCR_RX_TRIG_HF = BIT(7), // RCVR Trigger: FIFO 1/2 full
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FCR_RX_TRIG_AF = (BIT(7)|BIT(6)), // RCVR Trigger: FIFO 2 less than full
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FCR_RX_TRIG_MASK = (BIT(7)|BIT(6)) // RCVR Trigger bits Mask
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} LOG_UART_FIFO_CTRL;
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typedef struct _HAL_LOG_UART_ADAPTER_ {
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u32 BaudRate;
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u32 FIFOControl;
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u32 IntEnReg;
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u8 Parity;
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u8 Stop;
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u8 DataLength;
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u8 LineStatus;
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volatile u32 TxCount; // how many byte to TX
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volatile u32 RxCount; // how many bytes to RX
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volatile u8 *pTxBuf;
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volatile u8 *pRxBuf;
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u8 *pTxStartAddr;
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u8 *pRxStartAddr;
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IRQ_HANDLE IrqHandle;
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VOID (*LineStatusCallback)(VOID *para, u8 status); // User Line Status interrupt callback
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VOID (*TxCompCallback)(VOID *para); // User Tx complete callback
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VOID (*RxCompCallback)(VOID *para); // User Rx complete callback
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VOID *LineStatusCbPara; // the argument for LineStatusCallback
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VOID *TxCompCbPara; // the argument for TxCompCallback
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VOID *RxCompCbPara; // the argument for RxCompCallback
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void (*api_irq_handler)(u32 id, LOG_UART_INT_ID event);
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u32 api_irq_id;
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}HAL_LOG_UART_ADAPTER, *PHAL_LOG_UART_ADAPTER;
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VOID HalLogUartIrqHandle(VOID * Data);
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VOID HalLogUartSetBaudRate(HAL_LOG_UART_ADAPTER *pUartAdapter);
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VOID HalLogUartSetLineCtrl(HAL_LOG_UART_ADAPTER *pUartAdapter);
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VOID HalLogUartSetIntEn(HAL_LOG_UART_ADAPTER *pUartAdapter);
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u32 HalLogUartInitSetting(HAL_LOG_UART_ADAPTER *pUartAdapter);
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u32 HalLogUartRecv(HAL_LOG_UART_ADAPTER *pUartAdapter,
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u8 *pRxData, u32 Length, u32 TimeoutMS);
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u32 HalLogUartSend(HAL_LOG_UART_ADAPTER *pUartAdapter,
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u8 *pTxData, u32 Length, u32 TimeoutMS);
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HAL_Status HalLogUartIntSend(HAL_LOG_UART_ADAPTER *pUartAdapter,
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u8 *pTxData, u32 Length);
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HAL_Status HalLogUartIntRecv(HAL_LOG_UART_ADAPTER *pUartAdapter,
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u8 *pRxData, u32 Length);
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VOID HalLogUartAbortIntSend(HAL_LOG_UART_ADAPTER *pUartAdapter);
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VOID HalLogUartAbortIntRecv(HAL_LOG_UART_ADAPTER *pUartAdapter);
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HAL_Status HalLogUartRstFIFO(HAL_LOG_UART_ADAPTER *pUartAdapter, u8 RstCtrl);
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VOID HalLogUartEnable(HAL_LOG_UART_ADAPTER *pUartAdapter);
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VOID HalLogUartDisable(HAL_LOG_UART_ADAPTER *pUartAdapter);
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#endif
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