mirror of
https://github.com/rtlduino/RTL8710AF_GCC.git
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188 lines
5.7 KiB
C
188 lines
5.7 KiB
C
/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _HAL_SDR_CONTROLLER_H_
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#define _HAL_SDR_CONTROLLER_H_
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typedef enum _DRAM_TYPE_ {
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DRAM_DDR_1 = 1,
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DRAM_DDR_2 = 2,
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DRAM_DDR_3 = 3,
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DRAM_DDR_4 = 4,
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DRAM_SDR = 8
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}DRAM_TYPE;
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typedef enum _DRAM_COLADDR_WTH_ {
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DRAM_COLADDR_8B = 0,
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DRAM_COLADDR_9B = 1,
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DRAM_COLADDR_10B = 2,
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DRAM_COLADDR_11B = 3,
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DRAM_COLADDR_12B = 4,
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DRAM_COLADDR_13B = 5,
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DRAM_COLADDR_14B = 6,
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DRAM_COLADDR_15B = 7,
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DRAM_COLADDR_16B = 8
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}DRAM_COLADDR_WTH;
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typedef enum _DRAM_BANK_SIZE_ {
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DRAM_BANK_2 = 0,
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DRAM_BANK_4 = 1,
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DRAM_BANK_8 = 2
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}DRAM_BANK_SIZE;
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typedef enum _DRAM_DQ_WIDTH_ {
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DRAM_DQ_16 = 0,
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DRAM_DQ_32 = 1,
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DRAM_HALF_DQ32 = 2
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}DRAM_DQ_WIDTH;
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typedef enum _MODE0_BST_LEN_ {
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BST_LEN_4 = 0,
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BST_LEN_FLY = 1,
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BST_LEN_8 = 2
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}MODE0_BST_LEN;
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typedef enum _MODE0_BST_TYPE_ {
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SENQUENTIAL = 0,
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INTERLEAVE = 1
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}MODE0_BST_TYPE;
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typedef enum _DFI_RATIO_TYPE_ {
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DFI_RATIO_1 = 0, // DFI= 1:1, or SDR
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DFI_RATIO_2 = 1,
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DFI_RATIO_4 = 2
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}DFI_RATIO_TYPE;
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typedef struct _DRAM_INFO_ {
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DRAM_TYPE DeviceType;
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DRAM_COLADDR_WTH ColAddrWth;
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DRAM_BANK_SIZE Bank;
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DRAM_DQ_WIDTH DqWidth;
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}DRAM_INFO;
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typedef struct _DRAM_MODE_REG_INFO_ {
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MODE0_BST_LEN BstLen;
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MODE0_BST_TYPE BstType;
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//enum mode0_cas rd_cas;
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u32 Mode0Cas;
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u32 Mode0Wr;
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u32 Mode1DllEnN;
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u32 Mode1AllLat;
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u32 Mode2Cwl;
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}DRAM_MODE_REG_INFO;
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typedef struct _DRAM_TIMING_INFO_ {
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u32 TrfcPs;
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u32 TrefiPs;
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u32 WrMaxTck;
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u32 TrcdPs;
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u32 TrpPs;
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u32 TrasPs;
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u32 TrrdTck;
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u32 TwrPs;
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u32 TwtrTck;
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//u32 TrtpPs;
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u32 TmrdTck;
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u32 TrtpTck;
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u32 TccdTck;
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u32 TrcPs;
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}DRAM_TIMING_INFO;
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typedef struct _DRAM_DEVICE_INFO_ {
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DRAM_INFO *Dev;
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DRAM_MODE_REG_INFO *ModeReg;
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DRAM_TIMING_INFO *Timing;
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u32 DdrPeriodPs;
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DFI_RATIO_TYPE *DfiRate;
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}DRAM_DEVICE_INFO;
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//======================================================
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//DRAM Info
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#ifdef CONFIG_FPGA
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#define DRAM_INFO_TYPE DRAM_SDR
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#define DRAM_INFO_COL_ADDR_WTH DRAM_COLADDR_9B
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#define DRAM_INFO_BANK_SZ DRAM_BANK_4
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#define DRAM_INFO_DQ_WTH DRAM_DQ_16
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#else
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#define DRAM_INFO_TYPE DRAM_SDR
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#define DRAM_INFO_COL_ADDR_WTH DRAM_COLADDR_8B
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#define DRAM_INFO_BANK_SZ DRAM_BANK_2
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#define DRAM_INFO_DQ_WTH DRAM_DQ_16
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#endif
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//======================================================
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//DRAM Timing
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#ifdef CONFIG_SDR_100MHZ
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#define DRAM_TIMING_TCK 10000 //ps
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#endif
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#ifdef CONFIG_SDR_50MHZ
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#define DRAM_TIMING_TCK 20000 //ps
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#endif
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#ifdef CONFIG_SDR_25MHZ
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#define DRAM_TIMING_TCK 40000 //ps
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#endif
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#ifdef CONFIG_SDR_12_5MHZ
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#define DRAM_TIMING_TCK 80000 //ps
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#endif
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#if 1
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#define DRAM_TIMING_TREF 64000 //us
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#define DRAM_ROW_NUM 8192 //depends on row bit number
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#define DRAM_TIMING_TRFC 60000 //ps
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#define DRAM_TIMING_TREFI ((u32)((DRAM_TIMING_TREF*1000)/DRAM_ROW_NUM)*1000) //ps
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#define DRAM_TIMING_TWRMAXTCK 2 //tck
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#define DRAM_TIMING_TRCD 15000 //ps
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#define DRAM_TIMING_TRP 15000 //ps
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#define DRAM_TIMING_TRAS 42000 //ps
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#define DRAM_TIMING_TRRD 2 //tck
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#define DRAM_TIMING_TWR ((u32)(DRAM_TIMING_TCK*2))
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#define DRAM_TIMING_TWTR 0 //tck
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#define DRAM_TIMING_TMRD 2 //tck
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#define DRAM_TIMING_TRTP 0 //tck
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#define DRAM_TIMING_TCCD 1 //tck
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#define DRAM_TIMING_TRC 60000 //ps
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#else
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#define DRAM_TIMING_TREF 66000 //us
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#define DRAM_ROW_NUM 8192 //depends on row bit number
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#define DRAM_TIMING_TRFC 66000 //ps
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#define DRAM_TIMING_TREFI 63999800
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#define DRAM_TIMING_TWRMAXTCK 2 //tck
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#define DRAM_TIMING_TRCD 15000 //ps
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#define DRAM_TIMING_TRP 15000 //ps
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#define DRAM_TIMING_TRAS 37000 //ps
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#define DRAM_TIMING_TRRD 2 //tck
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#define DRAM_TIMING_TWR 7000
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#define DRAM_TIMING_TWTR 0 //tck
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#define DRAM_TIMING_TMRD 2 //tck
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#define DRAM_TIMING_TRTP 0 //tck
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#define DRAM_TIMING_TCCD 1 //tck
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#define DRAM_TIMING_TRC 60000 //ps
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#endif
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#define HAL_SDR_WRITE32(addr, value32) HAL_WRITE32(SDR_CTRL_BASE, addr, value32)
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#define HAL_SDR_WRITE16(addr, value16) HAL_WRITE16(SDR_CTRL_BASE, addr, value16)
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#define HAL_SDR_WRITE8(addr, value8) HAL_WRITE8(SDR_CTRL_BASE, addr, value8)
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#define HAL_SDR_READ32(addr) HAL_READ32(SDR_CTRL_BASE, addr)
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#define HAL_SDR_READ16(addr) HAL_READ16(SDR_CTRL_BASE, addr)
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#define HAL_SDR_READ8(addr) HAL_READ8(SDR_CTRL_BASE, addr)
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#define HAL_SDRAM_WRITE32(addr, value32) HAL_WRITE32(SDR_SDRAM_BASE, addr, value32)
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#define HAL_SDRAM_WRITE16(addr, value16) HAL_WRITE16(SDR_SDRAM_BASE, addr, value16)
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#define HAL_SDRAM_WRITE8(addr, value8) HAL_WRITE8(SDR_SDRAM_BASE, addr, value8)
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#define HAL_SDRAM_READ32(addr) HAL_READ32(SDR_SDRAM_BASE, addr)
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#define HAL_SDRAM_READ16(addr) HAL_READ16(SDR_SDRAM_BASE, addr)
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#define HAL_SDRAM_READ8(addr) HAL_READ8(SDR_SDRAM_BASE, addr)
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#endif // end of "#ifndef _HAL_SDR_CONTROLLER_H_"
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