motify compile link error

motify compile link error
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<h1 class="settitle">GDB's Obsolete Annotations</h1>
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<p>
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<h2 class="chapter">1 What is an Annotation?</h2>
<p><a name="index-annotations-1"></a>
To produce obsolete level two annotations, start <span class="sc">gdb</span> with the
<code>--annotate=2</code> option.
<p>Annotations start with a newline character, two &lsquo;<samp><span class="samp">control-z</span></samp>&rsquo;
characters, and the name of the annotation. If there is no additional
information associated with this annotation, the name of the annotation
is followed immediately by a newline. If there is additional
information, the name of the annotation is followed by a space, the
additional information, and a newline. The additional information
cannot contain newline characters.
<p>Any output not beginning with a newline and two &lsquo;<samp><span class="samp">control-z</span></samp>&rsquo;
characters denotes literal output from <span class="sc">gdb</span>. Currently there is
no need for <span class="sc">gdb</span> to output a newline followed by two
&lsquo;<samp><span class="samp">control-z</span></samp>&rsquo; characters, but if there was such a need, the
annotations could be extended with an &lsquo;<samp><span class="samp">escape</span></samp>&rsquo; annotation which
means those three characters as output.
<p>A simple example of starting up <span class="sc">gdb</span> with annotations is:
<pre class="smallexample"> $ gdb --annotate=2
GNU GDB 5.0
Copyright 2000 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License,
and you are welcome to change it and/or distribute copies of it
under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB. Type "show warranty"
for details.
This GDB was configured as "sparc-sun-sunos4.1.3"
^Z^Zpre-prompt
(gdb)
^Z^Zprompt
quit
^Z^Zpost-prompt
$
</pre>
<p>Here &lsquo;<samp><span class="samp">quit</span></samp>&rsquo; is input to <span class="sc">gdb</span>; the rest is output from
<span class="sc">gdb</span>. The three lines beginning &lsquo;<samp><span class="samp">^Z^Z</span></samp>&rsquo; (where &lsquo;<samp><span class="samp">^Z</span></samp>&rsquo;
denotes a &lsquo;<samp><span class="samp">control-z</span></samp>&rsquo; character) are annotations; the rest is
output from <span class="sc">gdb</span>.
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<a name="Annotations-for-Running"></a>
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Previous:&nbsp;<a rel="previous" accesskey="p" href="Invalidation.html#Invalidation">Invalidation</a>,
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<h2 class="chapter">12 Running the Program</h2>
<p><a name="index-annotations-for-running-programs-73"></a>
<a name="index-starting-74"></a><a name="index-stopping-75"></a>When the program starts executing due to a <span class="sc">gdb</span> command such as
<code>step</code> or <code>continue</code>,
<pre class="smallexample"> ^Z^Zstarting
</pre>
<p>is output. When the program stops,
<pre class="smallexample"> ^Z^Zstopped
</pre>
<p>is output. Before the <code>stopped</code> annotation, a variety of
annotations describe how the program stopped.
<a name="index-exited-76"></a>
<dl><dt><code>^Z^Zexited </code><var>exit-status</var><dd>The program exited, and <var>exit-status</var> is the exit status (zero for
successful exit, otherwise nonzero).
<p><a name="index-signalled-77"></a><a name="index-signal_002dname-78"></a><a name="index-signal_002dname_002dend-79"></a><a name="index-signal_002dstring-80"></a><a name="index-signal_002dstring_002dend-81"></a><br><dt><code>^Z^Zsignalled</code><dd>The program exited with a signal. After the <code>^Z^Zsignalled</code>, the
annotation continues:
<pre class="smallexample"> <var>intro-text</var>
^Z^Zsignal-name
<var>name</var>
^Z^Zsignal-name-end
<var>middle-text</var>
^Z^Zsignal-string
<var>string</var>
^Z^Zsignal-string-end
<var>end-text</var>
</pre>
<p class="noindent">where <var>name</var> is the name of the signal, such as <code>SIGILL</code> or
<code>SIGSEGV</code>, and <var>string</var> is the explanation of the signal, such
as <code>Illegal Instruction</code> or <code>Segmentation fault</code>.
<var>intro-text</var>, <var>middle-text</var>, and <var>end-text</var> are for the
user's benefit and have no particular format.
<p><a name="index-signal-82"></a><br><dt><code>^Z^Zsignal</code><dd>The syntax of this annotation is just like <code>signalled</code>, but <span class="sc">gdb</span> is
just saying that the program received the signal, not that it was
terminated with it.
<p><a name="index-breakpoint-83"></a><br><dt><code>^Z^Zbreakpoint </code><var>number</var><dd>The program hit breakpoint number <var>number</var>.
<p><a name="index-watchpoint-84"></a><br><dt><code>^Z^Zwatchpoint </code><var>number</var><dd>The program hit watchpoint number <var>number</var>.
</dl>
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<h2 class="chapter">10 Information on Breakpoints</h2>
<p><em>Breakpoint Annotations have been removed. </em><span class="sc">gdb/mi</span><em> instead
provides breakpoint commands.</em>
<p><a name="index-annotations-for-breakpoints-64"></a>The output from the <code>info breakpoints</code> command is annotated as follows:
<p><a name="index-breakpoints_002dheaders-65"></a><a name="index-breakpoints_002dtable-66"></a>
<pre class="smallexample"> ^Z^Zbreakpoints-headers
<var>header-entry</var>
^Z^Zbreakpoints-table
</pre>
<p class="noindent">where <var>header-entry</var> has the same syntax as an entry (see below) but
instead of containing data, it contains strings which are intended to
convey the meaning of each field to the user. This is followed by any
number of entries. If a field does not apply for this entry, it is
omitted. Fields may contain trailing whitespace. Each entry consists
of:
<p><a name="index-record-67"></a><a name="index-field-68"></a>
<pre class="smallexample"> ^Z^Zrecord
^Z^Zfield 0
<var>number</var>
^Z^Zfield 1
<var>type</var>
^Z^Zfield 2
<var>disposition</var>
^Z^Zfield 3
<var>enable</var>
^Z^Zfield 4
<var>address</var>
^Z^Zfield 5
<var>what</var>
^Z^Zfield 6
<var>frame</var>
^Z^Zfield 7
<var>condition</var>
^Z^Zfield 8
<var>ignore-count</var>
^Z^Zfield 9
<var>commands</var>
</pre>
<p>Note that <var>address</var> is intended for user consumption&mdash;the syntax
varies depending on the language.
<p>The output ends with
<p><a name="index-breakpoints_002dtable_002dend-69"></a>
<pre class="smallexample"> ^Z^Zbreakpoints-table-end
</pre>
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<h2 class="chapter">7 Displays</h2>
<p><em>Display Annotations have been removed. </em><span class="sc">gdb/mi</span><em> instead
provides Variable Objects.</em>
<p><a name="index-display_002dbegin-36"></a><a name="index-display_002dnumber_002dend-37"></a><a name="index-display_002dformat-38"></a><a name="index-display_002dexpression-39"></a><a name="index-display_002dexpression_002dend-40"></a><a name="index-display_002dvalue-41"></a><a name="index-display_002dend-42"></a><a name="index-annotations-for-display-43"></a>When <span class="sc">gdb</span> is told to display something using the <code>display</code> command,
the results of the display are annotated:
<pre class="smallexample"> ^Z^Zdisplay-begin
<var>number</var>
^Z^Zdisplay-number-end
<var>number-separator</var>
^Z^Zdisplay-format
<var>format</var>
^Z^Zdisplay-expression
<var>expression</var>
^Z^Zdisplay-expression-end
<var>expression-separator</var>
^Z^Zdisplay-value
<var>value</var>
^Z^Zdisplay-end
</pre>
<p class="noindent">where <var>number</var> is the number of the display, <var>number-separator</var>
is intended to separate the number from what follows for the user,
<var>format</var> includes information such as the size, format, or other
information about how the value is being displayed, <var>expression</var> is
the expression being displayed, <var>expression-separator</var> is intended
to separate the expression from the text that follows for the user,
and <var>value</var> is the actual value being displayed.
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<h2 class="chapter">9 Errors</h2>
<p><a name="index-annotations-for-errors_002c-warnings-and-interrupts-60"></a>
<a name="index-quit-61"></a>
<pre class="smallexample"> ^Z^Zquit
</pre>
<p>This annotation occurs right before <span class="sc">gdb</span> responds to an interrupt.
<p><a name="index-error-62"></a>
<pre class="smallexample"> ^Z^Zerror
</pre>
<p>This annotation occurs right before <span class="sc">gdb</span> responds to an error.
<p>Quit and error annotations indicate that any annotations which <span class="sc">gdb</span> was
in the middle of may end abruptly. For example, if a
<code>value-history-begin</code> annotation is followed by a <code>error</code>, one
cannot expect to receive the matching <code>value-history-end</code>. One
cannot expect not to receive it either, however; an error annotation
does not necessarily mean that <span class="sc">gdb</span> is immediately returning all the way
to the top level.
<p><a name="index-error_002dbegin-63"></a>A quit or error annotation may be preceded by
<pre class="smallexample"> ^Z^Zerror-begin
</pre>
<p>Any output between that and the quit or error annotation is the error
message.
<p>Warning messages are not yet annotated.
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<h2 class="chapter">6 Frames</h2>
<p><em>Value Annotations have been removed. </em><span class="sc">gdb/mi</span><em> instead provides
a number of frame commands.</em>
<p><em>Frame annotations are no longer available. The </em><span class="sc">gdb/mi</span><em>
provides &lsquo;</em><samp><span class="samp">-stack-list-arguments</span></samp><em>&rsquo;, &lsquo;</em><samp><span class="samp">-stack-list-locals</span></samp><em>&rsquo;, and
&lsquo;</em><samp><span class="samp">-stack-list-frames</span></samp><em>&rsquo; commands.</em>
<p><a name="index-annotations-for-frames-21"></a>Whenever <span class="sc">gdb</span> prints a frame, it annotates it. For example, this applies
to frames printed when <span class="sc">gdb</span> stops, output from commands such as
<code>backtrace</code> or <code>up</code>, etc.
<p><a name="index-frame_002dbegin-22"></a>The frame annotation begins with
<pre class="smallexample"> ^Z^Zframe-begin <var>level</var> <var>address</var>
<var>level-string</var>
</pre>
<p class="noindent">where <var>level</var> is the number of the frame (0 is the innermost frame,
and other frames have positive numbers), <var>address</var> is the address of
the code executing in that frame, and <var>level-string</var> is a string
designed to convey the level to the user. <var>address</var> is in the form
&lsquo;<samp><span class="samp">0x</span></samp>&rsquo; followed by one or more lowercase hex digits (note that this
does not depend on the language). The frame ends with
<p><a name="index-frame_002dend-23"></a>
<pre class="smallexample"> ^Z^Zframe-end
</pre>
<p>Between these annotations is the main body of the frame, which can
consist of
<ul>
<li><a name="index-function_002dcall-24"></a>
<pre class="smallexample"> ^Z^Zfunction-call
<var>function-call-string</var>
</pre>
<p>where <var>function-call-string</var> is text designed to convey to the user
that this frame is associated with a function call made by <span class="sc">gdb</span> to a
function in the program being debugged.
<li><a name="index-signal_002dhandler_002dcaller-25"></a>
<pre class="smallexample"> ^Z^Zsignal-handler-caller
<var>signal-handler-caller-string</var>
</pre>
<p>where <var>signal-handler-caller-string</var> is text designed to convey to
the user that this frame is associated with whatever mechanism is used
by this operating system to call a signal handler (it is the frame which
calls the signal handler, not the frame for the signal handler itself).
<li>A normal frame.
<p><a name="index-frame_002daddress-26"></a><a name="index-frame_002daddress_002dend-27"></a>This can optionally (depending on whether this is thought of as
interesting information for the user to see) begin with
<pre class="smallexample"> ^Z^Zframe-address
<var>address</var>
^Z^Zframe-address-end
<var>separator-string</var>
</pre>
<p>where <var>address</var> is the address executing in the frame (the same
address as in the <code>frame-begin</code> annotation, but printed in a form
which is intended for user consumption&mdash;in particular, the syntax varies
depending on the language), and <var>separator-string</var> is a string
intended to separate this address from what follows for the user's
benefit.
<p><a name="index-frame_002dfunction_002dname-28"></a><a name="index-frame_002dargs-29"></a>Then comes
<pre class="smallexample"> ^Z^Zframe-function-name
<var>function-name</var>
^Z^Zframe-args
<var>arguments</var>
</pre>
<p>where <var>function-name</var> is the name of the function executing in the
frame, or &lsquo;<samp><span class="samp">??</span></samp>&rsquo; if not known, and <var>arguments</var> are the arguments
to the frame, with parentheses around them (each argument is annotated
individually as well, see <a href="Value-Annotations.html#Value-Annotations">Value Annotations</a>).
<p><a name="index-frame_002dsource_002dbegin-30"></a><a name="index-frame_002dsource_002dfile-31"></a><a name="index-frame_002dsource_002dfile_002dend-32"></a><a name="index-frame_002dsource_002dline-33"></a><a name="index-frame_002dsource_002dend-34"></a>If source information is available, a reference to it is then printed:
<pre class="smallexample"> ^Z^Zframe-source-begin
<var>source-intro-string</var>
^Z^Zframe-source-file
<var>filename</var>
^Z^Zframe-source-file-end
:
^Z^Zframe-source-line
<var>line-number</var>
^Z^Zframe-source-end
</pre>
<p>where <var>source-intro-string</var> separates for the user's benefit the
reference from the text which precedes it, <var>filename</var> is the name of
the source file, and <var>line-number</var> is the line number within that
file (the first line is line 1).
<p><a name="index-frame_002dwhere-35"></a>If <span class="sc">gdb</span> prints some information about where the frame is from (which
library, which load segment, etc.; currently only done on the RS/6000),
it is annotated with
<pre class="smallexample"> ^Z^Zframe-where
<var>information</var>
</pre>
<p>Then, if source is to actually be displayed for this frame (for example,
this is not true for output from the <code>backtrace</code> command), then a
<code>source</code> annotation (see <a href="Source-Annotations.html#Source-Annotations">Source Annotations</a>) is displayed. Unlike
most annotations, this is output instead of the normal text which would be
output, not in addition.
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<h2 class="appendix">Appendix A GNU Free Documentation License</h2>
<!-- The GNU Free Documentation License. -->
<div align="center">Version 1.3, 3 November 2008</div>
<!-- This file is intended to be included within another document, -->
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<pre class="display"> Copyright &copy; 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc.
<a href="http://fsf.org/">http://fsf.org/</a>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
</pre>
<ol type=1 start=0>
<li>PREAMBLE
<p>The purpose of this License is to make a manual, textbook, or other
functional and useful document <dfn>free</dfn> in the sense of freedom: to
assure everyone the effective freedom to copy and redistribute it,
with or without modifying it, either commercially or noncommercially.
Secondarily, this License preserves for the author and publisher a way
to get credit for their work, while not being considered responsible
for modifications made by others.
<p>This License is a kind of &ldquo;copyleft&rdquo;, which means that derivative
works of the document must themselves be free in the same sense. It
complements the GNU General Public License, which is a copyleft
license designed for free software.
<p>We have designed this License in order to use it for manuals for free
software, because free software needs free documentation: a free
program should come with manuals providing the same freedoms that the
software does. But this License is not limited to software manuals;
it can be used for any textual work, regardless of subject matter or
whether it is published as a printed book. We recommend this License
principally for works whose purpose is instruction or reference.
<li>APPLICABILITY AND DEFINITIONS
<p>This License applies to any manual or other work, in any medium, that
contains a notice placed by the copyright holder saying it can be
distributed under the terms of this License. Such a notice grants a
world-wide, royalty-free license, unlimited in duration, to use that
work under the conditions stated herein. The &ldquo;Document&rdquo;, below,
refers to any such manual or work. Any member of the public is a
licensee, and is addressed as &ldquo;you&rdquo;. You accept the license if you
copy, modify or distribute the work in a way requiring permission
under copyright law.
<p>A &ldquo;Modified Version&rdquo; of the Document means any work containing the
Document or a portion of it, either copied verbatim, or with
modifications and/or translated into another language.
<p>A &ldquo;Secondary Section&rdquo; is a named appendix or a front-matter section
of the Document that deals exclusively with the relationship of the
publishers or authors of the Document to the Document's overall
subject (or to related matters) and contains nothing that could fall
directly within that overall subject. (Thus, if the Document is in
part a textbook of mathematics, a Secondary Section may not explain
any mathematics.) The relationship could be a matter of historical
connection with the subject or with related matters, or of legal,
commercial, philosophical, ethical or political position regarding
them.
<p>The &ldquo;Invariant Sections&rdquo; are certain Secondary Sections whose titles
are designated, as being those of Invariant Sections, in the notice
that says that the Document is released under this License. If a
section does not fit the above definition of Secondary then it is not
allowed to be designated as Invariant. The Document may contain zero
Invariant Sections. If the Document does not identify any Invariant
Sections then there are none.
<p>The &ldquo;Cover Texts&rdquo; are certain short passages of text that are listed,
as Front-Cover Texts or Back-Cover Texts, in the notice that says that
the Document is released under this License. A Front-Cover Text may
be at most 5 words, and a Back-Cover Text may be at most 25 words.
<p>A &ldquo;Transparent&rdquo; copy of the Document means a machine-readable copy,
represented in a format whose specification is available to the
general public, that is suitable for revising the document
straightforwardly with generic text editors or (for images composed of
pixels) generic paint programs or (for drawings) some widely available
drawing editor, and that is suitable for input to text formatters or
for automatic translation to a variety of formats suitable for input
to text formatters. A copy made in an otherwise Transparent file
format whose markup, or absence of markup, has been arranged to thwart
or discourage subsequent modification by readers is not Transparent.
An image format is not Transparent if used for any substantial amount
of text. A copy that is not &ldquo;Transparent&rdquo; is called &ldquo;Opaque&rdquo;.
<p>Examples of suitable formats for Transparent copies include plain
<span class="sc">ascii</span> without markup, Texinfo input format, LaTeX input
format, <acronym>SGML</acronym> or <acronym>XML</acronym> using a publicly available
<acronym>DTD</acronym>, and standard-conforming simple <acronym>HTML</acronym>,
PostScript or <acronym>PDF</acronym> designed for human modification. Examples
of transparent image formats include <acronym>PNG</acronym>, <acronym>XCF</acronym> and
<acronym>JPG</acronym>. Opaque formats include proprietary formats that can be
read and edited only by proprietary word processors, <acronym>SGML</acronym> or
<acronym>XML</acronym> for which the <acronym>DTD</acronym> and/or processing tools are
not generally available, and the machine-generated <acronym>HTML</acronym>,
PostScript or <acronym>PDF</acronym> produced by some word processors for
output purposes only.
<p>The &ldquo;Title Page&rdquo; means, for a printed book, the title page itself,
plus such following pages as are needed to hold, legibly, the material
this License requires to appear in the title page. For works in
formats which do not have any title page as such, &ldquo;Title Page&rdquo; means
the text near the most prominent appearance of the work's title,
preceding the beginning of the body of the text.
<p>The &ldquo;publisher&rdquo; means any person or entity that distributes copies
of the Document to the public.
<p>A section &ldquo;Entitled XYZ&rdquo; means a named subunit of the Document whose
title either is precisely XYZ or contains XYZ in parentheses following
text that translates XYZ in another language. (Here XYZ stands for a
specific section name mentioned below, such as &ldquo;Acknowledgements&rdquo;,
&ldquo;Dedications&rdquo;, &ldquo;Endorsements&rdquo;, or &ldquo;History&rdquo;.) To &ldquo;Preserve the Title&rdquo;
of such a section when you modify the Document means that it remains a
section &ldquo;Entitled XYZ&rdquo; according to this definition.
<p>The Document may include Warranty Disclaimers next to the notice which
states that this License applies to the Document. These Warranty
Disclaimers are considered to be included by reference in this
License, but only as regards disclaiming warranties: any other
implication that these Warranty Disclaimers may have is void and has
no effect on the meaning of this License.
<li>VERBATIM COPYING
<p>You may copy and distribute the Document in any medium, either
commercially or noncommercially, provided that this License, the
copyright notices, and the license notice saying this License applies
to the Document are reproduced in all copies, and that you add no other
conditions whatsoever to those of this License. You may not use
technical measures to obstruct or control the reading or further
copying of the copies you make or distribute. However, you may accept
compensation in exchange for copies. If you distribute a large enough
number of copies you must also follow the conditions in section 3.
<p>You may also lend copies, under the same conditions stated above, and
you may publicly display copies.
<li>COPYING IN QUANTITY
<p>If you publish printed copies (or copies in media that commonly have
printed covers) of the Document, numbering more than 100, and the
Document's license notice requires Cover Texts, you must enclose the
copies in covers that carry, clearly and legibly, all these Cover
Texts: Front-Cover Texts on the front cover, and Back-Cover Texts on
the back cover. Both covers must also clearly and legibly identify
you as the publisher of these copies. The front cover must present
the full title with all words of the title equally prominent and
visible. You may add other material on the covers in addition.
Copying with changes limited to the covers, as long as they preserve
the title of the Document and satisfy these conditions, can be treated
as verbatim copying in other respects.
<p>If the required texts for either cover are too voluminous to fit
legibly, you should put the first ones listed (as many as fit
reasonably) on the actual cover, and continue the rest onto adjacent
pages.
<p>If you publish or distribute Opaque copies of the Document numbering
more than 100, you must either include a machine-readable Transparent
copy along with each Opaque copy, or state in or with each Opaque copy
a computer-network location from which the general network-using
public has access to download using public-standard network protocols
a complete Transparent copy of the Document, free of added material.
If you use the latter option, you must take reasonably prudent steps,
when you begin distribution of Opaque copies in quantity, to ensure
that this Transparent copy will remain thus accessible at the stated
location until at least one year after the last time you distribute an
Opaque copy (directly or through your agents or retailers) of that
edition to the public.
<p>It is requested, but not required, that you contact the authors of the
Document well before redistributing any large number of copies, to give
them a chance to provide you with an updated version of the Document.
<li>MODIFICATIONS
<p>You may copy and distribute a Modified Version of the Document under
the conditions of sections 2 and 3 above, provided that you release
the Modified Version under precisely this License, with the Modified
Version filling the role of the Document, thus licensing distribution
and modification of the Modified Version to whoever possesses a copy
of it. In addition, you must do these things in the Modified Version:
<ol type=A start=1>
<li>Use in the Title Page (and on the covers, if any) a title distinct
from that of the Document, and from those of previous versions
(which should, if there were any, be listed in the History section
of the Document). You may use the same title as a previous version
if the original publisher of that version gives permission.
<li>List on the Title Page, as authors, one or more persons or entities
responsible for authorship of the modifications in the Modified
Version, together with at least five of the principal authors of the
Document (all of its principal authors, if it has fewer than five),
unless they release you from this requirement.
<li>State on the Title page the name of the publisher of the
Modified Version, as the publisher.
<li>Preserve all the copyright notices of the Document.
<li>Add an appropriate copyright notice for your modifications
adjacent to the other copyright notices.
<li>Include, immediately after the copyright notices, a license notice
giving the public permission to use the Modified Version under the
terms of this License, in the form shown in the Addendum below.
<li>Preserve in that license notice the full lists of Invariant Sections
and required Cover Texts given in the Document's license notice.
<li>Include an unaltered copy of this License.
<li>Preserve the section Entitled &ldquo;History&rdquo;, Preserve its Title, and add
to it an item stating at least the title, year, new authors, and
publisher of the Modified Version as given on the Title Page. If
there is no section Entitled &ldquo;History&rdquo; in the Document, create one
stating the title, year, authors, and publisher of the Document as
given on its Title Page, then add an item describing the Modified
Version as stated in the previous sentence.
<li>Preserve the network location, if any, given in the Document for
public access to a Transparent copy of the Document, and likewise
the network locations given in the Document for previous versions
it was based on. These may be placed in the &ldquo;History&rdquo; section.
You may omit a network location for a work that was published at
least four years before the Document itself, or if the original
publisher of the version it refers to gives permission.
<li>For any section Entitled &ldquo;Acknowledgements&rdquo; or &ldquo;Dedications&rdquo;, Preserve
the Title of the section, and preserve in the section all the
substance and tone of each of the contributor acknowledgements and/or
dedications given therein.
<li>Preserve all the Invariant Sections of the Document,
unaltered in their text and in their titles. Section numbers
or the equivalent are not considered part of the section titles.
<li>Delete any section Entitled &ldquo;Endorsements&rdquo;. Such a section
may not be included in the Modified Version.
<li>Do not retitle any existing section to be Entitled &ldquo;Endorsements&rdquo; or
to conflict in title with any Invariant Section.
<li>Preserve any Warranty Disclaimers.
</ol>
<p>If the Modified Version includes new front-matter sections or
appendices that qualify as Secondary Sections and contain no material
copied from the Document, you may at your option designate some or all
of these sections as invariant. To do this, add their titles to the
list of Invariant Sections in the Modified Version's license notice.
These titles must be distinct from any other section titles.
<p>You may add a section Entitled &ldquo;Endorsements&rdquo;, provided it contains
nothing but endorsements of your Modified Version by various
parties&mdash;for example, statements of peer review or that the text has
been approved by an organization as the authoritative definition of a
standard.
<p>You may add a passage of up to five words as a Front-Cover Text, and a
passage of up to 25 words as a Back-Cover Text, to the end of the list
of Cover Texts in the Modified Version. Only one passage of
Front-Cover Text and one of Back-Cover Text may be added by (or
through arrangements made by) any one entity. If the Document already
includes a cover text for the same cover, previously added by you or
by arrangement made by the same entity you are acting on behalf of,
you may not add another; but you may replace the old one, on explicit
permission from the previous publisher that added the old one.
<p>The author(s) and publisher(s) of the Document do not by this License
give permission to use their names for publicity for or to assert or
imply endorsement of any Modified Version.
<li>COMBINING DOCUMENTS
<p>You may combine the Document with other documents released under this
License, under the terms defined in section 4 above for modified
versions, provided that you include in the combination all of the
Invariant Sections of all of the original documents, unmodified, and
list them all as Invariant Sections of your combined work in its
license notice, and that you preserve all their Warranty Disclaimers.
<p>The combined work need only contain one copy of this License, and
multiple identical Invariant Sections may be replaced with a single
copy. If there are multiple Invariant Sections with the same name but
different contents, make the title of each such section unique by
adding at the end of it, in parentheses, the name of the original
author or publisher of that section if known, or else a unique number.
Make the same adjustment to the section titles in the list of
Invariant Sections in the license notice of the combined work.
<p>In the combination, you must combine any sections Entitled &ldquo;History&rdquo;
in the various original documents, forming one section Entitled
&ldquo;History&rdquo;; likewise combine any sections Entitled &ldquo;Acknowledgements&rdquo;,
and any sections Entitled &ldquo;Dedications&rdquo;. You must delete all
sections Entitled &ldquo;Endorsements.&rdquo;
<li>COLLECTIONS OF DOCUMENTS
<p>You may make a collection consisting of the Document and other documents
released under this License, and replace the individual copies of this
License in the various documents with a single copy that is included in
the collection, provided that you follow the rules of this License for
verbatim copying of each of the documents in all other respects.
<p>You may extract a single document from such a collection, and distribute
it individually under this License, provided you insert a copy of this
License into the extracted document, and follow this License in all
other respects regarding verbatim copying of that document.
<li>AGGREGATION WITH INDEPENDENT WORKS
<p>A compilation of the Document or its derivatives with other separate
and independent documents or works, in or on a volume of a storage or
distribution medium, is called an &ldquo;aggregate&rdquo; if the copyright
resulting from the compilation is not used to limit the legal rights
of the compilation's users beyond what the individual works permit.
When the Document is included in an aggregate, this License does not
apply to the other works in the aggregate which are not themselves
derivative works of the Document.
<p>If the Cover Text requirement of section 3 is applicable to these
copies of the Document, then if the Document is less than one half of
the entire aggregate, the Document's Cover Texts may be placed on
covers that bracket the Document within the aggregate, or the
electronic equivalent of covers if the Document is in electronic form.
Otherwise they must appear on printed covers that bracket the whole
aggregate.
<li>TRANSLATION
<p>Translation is considered a kind of modification, so you may
distribute translations of the Document under the terms of section 4.
Replacing Invariant Sections with translations requires special
permission from their copyright holders, but you may include
translations of some or all Invariant Sections in addition to the
original versions of these Invariant Sections. You may include a
translation of this License, and all the license notices in the
Document, and any Warranty Disclaimers, provided that you also include
the original English version of this License and the original versions
of those notices and disclaimers. In case of a disagreement between
the translation and the original version of this License or a notice
or disclaimer, the original version will prevail.
<p>If a section in the Document is Entitled &ldquo;Acknowledgements&rdquo;,
&ldquo;Dedications&rdquo;, or &ldquo;History&rdquo;, the requirement (section 4) to Preserve
its Title (section 1) will typically require changing the actual
title.
<li>TERMINATION
<p>You may not copy, modify, sublicense, or distribute the Document
except as expressly provided under this License. Any attempt
otherwise to copy, modify, sublicense, or distribute it is void, and
will automatically terminate your rights under this License.
<p>However, if you cease all violation of this License, then your license
from a particular copyright holder is reinstated (a) provisionally,
unless and until the copyright holder explicitly and finally
terminates your license, and (b) permanently, if the copyright holder
fails to notify you of the violation by some reasonable means prior to
60 days after the cessation.
<p>Moreover, your license from a particular copyright holder is
reinstated permanently if the copyright holder notifies you of the
violation by some reasonable means, this is the first time you have
received notice of violation of this License (for any work) from that
copyright holder, and you cure the violation prior to 30 days after
your receipt of the notice.
<p>Termination of your rights under this section does not terminate the
licenses of parties who have received copies or rights from you under
this License. If your rights have been terminated and not permanently
reinstated, receipt of a copy of some or all of the same material does
not give you any rights to use it.
<li>FUTURE REVISIONS OF THIS LICENSE
<p>The Free Software Foundation may publish new, revised versions
of the GNU Free Documentation License from time to time. Such new
versions will be similar in spirit to the present version, but may
differ in detail to address new problems or concerns. See
<a href="http://www.gnu.org/copyleft/">http://www.gnu.org/copyleft/</a>.
<p>Each version of the License is given a distinguishing version number.
If the Document specifies that a particular numbered version of this
License &ldquo;or any later version&rdquo; applies to it, you have the option of
following the terms and conditions either of that specified version or
of any later version that has been published (not as a draft) by the
Free Software Foundation. If the Document does not specify a version
number of this License, you may choose any version ever published (not
as a draft) by the Free Software Foundation. If the Document
specifies that a proxy can decide which future versions of this
License can be used, that proxy's public statement of acceptance of a
version permanently authorizes you to choose that version for the
Document.
<li>RELICENSING
<p>&ldquo;Massive Multiauthor Collaboration Site&rdquo; (or &ldquo;MMC Site&rdquo;) means any
World Wide Web server that publishes copyrightable works and also
provides prominent facilities for anybody to edit those works. A
public wiki that anybody can edit is an example of such a server. A
&ldquo;Massive Multiauthor Collaboration&rdquo; (or &ldquo;MMC&rdquo;) contained in the
site means any set of copyrightable works thus published on the MMC
site.
<p>&ldquo;CC-BY-SA&rdquo; means the Creative Commons Attribution-Share Alike 3.0
license published by Creative Commons Corporation, a not-for-profit
corporation with a principal place of business in San Francisco,
California, as well as future copyleft versions of that license
published by that same organization.
<p>&ldquo;Incorporate&rdquo; means to publish or republish a Document, in whole or
in part, as part of another Document.
<p>An MMC is &ldquo;eligible for relicensing&rdquo; if it is licensed under this
License, and if all works that were first published under this License
somewhere other than this MMC, and subsequently incorporated in whole
or in part into the MMC, (1) had no cover texts or invariant sections,
and (2) were thus incorporated prior to November 1, 2008.
<p>The operator of an MMC Site may republish an MMC contained in the site
under CC-BY-SA on the same site at any time before August 1, 2009,
provided the MMC is eligible for relicensing.
</ol>
<h3 class="heading">ADDENDUM: How to use this License for your documents</h3>
<p>To use this License in a document you have written, include a copy of
the License in the document and put the following copyright and
license notices just after the title page:
<pre class="smallexample"> Copyright (C) <var>year</var> <var>your name</var>.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
or any later version published by the Free Software Foundation;
with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
Texts. A copy of the license is included in the section entitled ``GNU
Free Documentation License''.
</pre>
<p>If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
replace the &ldquo;with<small class="dots">...</small>Texts.&rdquo; line with this:
<pre class="smallexample"> with the Invariant Sections being <var>list their titles</var>, with
the Front-Cover Texts being <var>list</var>, and with the Back-Cover Texts
being <var>list</var>.
</pre>
<p>If you have Invariant Sections without Cover Texts, or some other
combination of the three, merge those two alternatives to suit the
situation.
<p>If your document contains nontrivial examples of program code, we
recommend releasing these examples in parallel under your choice of
free software license, such as the GNU General Public License,
to permit their use in free software.
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<h2 class="chapter">11 Invalidation Notices</h2>
<p><a name="index-annotations-for-invalidation-messages-70"></a>The following annotations say that certain pieces of state may have
changed.
<a name="index-frames_002dinvalid-71"></a>
<dl><dt><code>^Z^Zframes-invalid</code><dd>
The frames (for example, output from the <code>backtrace</code> command) may
have changed.
<p><a name="index-breakpoints_002dinvalid-72"></a><br><dt><code>^Z^Zbreakpoints-invalid</code><dd>
The breakpoints may have changed. For example, the user just added or
deleted a breakpoint.
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<h2 class="chapter">2 Limitations of the Annotation Interface</h2>
<p>The level two annotations mechanism is known to have a number of
technical and architectural limitations. As a consequence, in 2001,
with the release of <span class="sc">gdb</span> 5.1 and the addition of <span class="sc">gdb/mi</span>,
the annotation interface was marked as deprecated.
<p>This chapter discusses the known problems.
<h3 class="section">2.1 Dependant on <span class="sc">cli</span> output</h3>
<p>The annotation interface works by interspersing markups with
<span class="sc">gdb</span> normal command-line interpreter output. Unfortunately, this
makes the annotation client dependant on not just the annotations, but
also the <span class="sc">cli</span> output. This is because the client is forced to
assume that specific <span class="sc">gdb</span> commands provide specific information.
Any change to <span class="sc">gdb</span>'s <span class="sc">cli</span> output modifies or removes that
information and, consequently, likely breaks the client.
<p>Since the <span class="sc">gdb/mi</span> output is independent of the <span class="sc">cli</span>, it does not
have this problem.
<h3 class="section">2.2 Scalability</h3>
<p>The annotation interface relies on value annotations (see <a href="Value-Annotations.html#Value-Annotations">Value Annotations</a>) and the display mechanism as a way of obtaining up-to-date
value information. These mechanisms are not scalable.
<p>In a graphical environment, where many values can be displayed
simultaneously, a serious performance problem occurs when the client
tries to first extract from <span class="sc">gdb</span>, and then re-display, all those
values. The client should instead only request and update the values
that changed.
<p>The <span class="sc">gdb/mi</span> Variable Objects provide just that mechanism.
<h3 class="section">2.3 Correctness</h3>
<p>The annotation interface assumes that a variable's value can only be
changed when the target is running. This assumption is not correct. A
single assignment to a single variable can result in the entire target,
and all displayed values, needing an update.
<p>The <span class="sc">gdb/mi</span> Variable Objects include a mechanism for efficiently
reporting such changes.
<h3 class="section">2.4 Reliability</h3>
<p>The <span class="sc">gdb/mi</span> interface includes a dedicated test directory
(<samp><span class="file">gdb/gdb.mi</span></samp>), and any addition or fix to <span class="sc">gdb/mi</span> must include
testsuite changes.
<h3 class="section">2.5 Maintainability</h3>
<p>The annotation mechanism was implemented by interspersing <span class="sc">cli</span> print
statements with various annotations. As a consequence, any <span class="sc">cli</span>
output change can alter the annotation output.
<p>Since the <span class="sc">gdb/mi</span> output is independent of the <span class="sc">cli</span>, and the
<span class="sc">gdb/mi</span> is increasingly implemented independent of the <span class="sc">cli</span>
code, its long term maintenance is much easier.
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<h2 class="chapter">3 Migrating to <span class="sc">gdb/mi</span></h2>
<p>By using the &lsquo;<samp><span class="samp">interp mi</span></samp>&rsquo; command, it is possible for annotation
clients to invoke <span class="sc">gdb/mi</span> commands, and hence access the
<span class="sc">gdb/mi</span>. By doing this, existing annotation clients have a
migration path from this obsolete interface to <span class="sc">gdb/mi</span>.
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<h2 class="chapter">14 Multi-threaded Applications</h2>
<p><a name="index-annotations-for-multi_002dthreaded-apps-87"></a>
The following annotations report thread related changes of state.
<a name="index-new_002dthread_0040r_007b_002c-annotation_007d-88"></a>
<dl><dt><code>^Z^Znew-thread</code><dd>
This annotation is issued once for each thread that is created apart from
the main thread, which is not reported.
<p><a name="index-thread_002dchanged_0040r_007b_002c-annotation_007d-89"></a><br><dt><code>^Z^Zthread-changed</code><dd>
The selected thread has changed. This may occur at the request of the
user with the <code>thread</code> command, or as a result of execution,
e.g., another thread hits a breakpoint.
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<h2 class="chapter">8 Annotation for <span class="sc">gdb</span> Input</h2>
<p><a name="index-annotations-for-prompts-44"></a>When <span class="sc">gdb</span> prompts for input, it annotates this fact so it is possible
to know when to send output, when the output from a given command is
over, etc.
<p>Different kinds of input each have a different <dfn>input type</dfn>. Each
input type has three annotations: a <code>pre-</code> annotation, which
denotes the beginning of any prompt which is being output, a plain
annotation, which denotes the end of the prompt, and then a <code>post-</code>
annotation which denotes the end of any echo which may (or may not) be
associated with the input. For example, the <code>prompt</code> input type
features the following annotations:
<pre class="smallexample"> ^Z^Zpre-prompt
^Z^Zprompt
^Z^Zpost-prompt
</pre>
<p>The input types are
<a name="index-pre_002dprompt-45"></a>
<a name="index-prompt-46"></a>
<a name="index-post_002dprompt-47"></a>
<dl><dt><code>prompt</code><dd>When <span class="sc">gdb</span> is prompting for a command (the main <span class="sc">gdb</span> prompt).
<p><a name="index-pre_002dcommands-48"></a><a name="index-commands-49"></a><a name="index-post_002dcommands-50"></a><br><dt><code>commands</code><dd>When <span class="sc">gdb</span> prompts for a set of commands, like in the <code>commands</code>
command. The annotations are repeated for each command which is input.
<p><a name="index-pre_002doverload_002dchoice-51"></a><a name="index-overload_002dchoice-52"></a><a name="index-post_002doverload_002dchoice-53"></a><br><dt><code>overload-choice</code><dd>When <span class="sc">gdb</span> wants the user to select between various overloaded functions.
<p><a name="index-pre_002dquery-54"></a><a name="index-query-55"></a><a name="index-post_002dquery-56"></a><br><dt><code>query</code><dd>When <span class="sc">gdb</span> wants the user to confirm a potentially dangerous operation.
<p><a name="index-pre_002dprompt_002dfor_002dcontinue-57"></a><a name="index-prompt_002dfor_002dcontinue-58"></a><a name="index-post_002dprompt_002dfor_002dcontinue-59"></a><br><dt><code>prompt-for-continue</code><dd>When <span class="sc">gdb</span> is asking the user to press return to continue. Note: Don't
expect this to work well; instead use <code>set height 0</code> to disable
prompting. This is because the counting of lines is buggy in the
presence of annotations.
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<h2 class="chapter">4 The Server Prefix</h2>
<p><a name="index-server-prefix-for-annotations-2"></a>
To issue a command to <span class="sc">gdb</span> without affecting certain aspects of
the state which is seen by users, prefix it with &lsquo;<samp><span class="samp">server </span></samp>&rsquo;. This
means that this command will not affect the command history, nor will it
affect <span class="sc">gdb</span>'s notion of which command to repeat if &lt;RET&gt; is
pressed on a line by itself.
<p>The server prefix does not affect the recording of values into the value
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<h2 class="chapter">13 Displaying Source</h2>
<p><a name="index-annotations-for-source-display-85"></a>
<a name="index-source-86"></a>The following annotation is used instead of displaying source code:
<pre class="smallexample"> ^Z^Zsource <var>filename</var>:<var>line</var>:<var>character</var>:<var>middle</var>:<var>addr</var>
</pre>
<p>where <var>filename</var> is an absolute file name indicating which source
file, <var>line</var> is the line number within that file (where 1 is the
first line in the file), <var>character</var> is the character position
within the file (where 0 is the first character in the file) (for most
debug formats this will necessarily point to the beginning of a line),
<var>middle</var> is &lsquo;<samp><span class="samp">middle</span></samp>&rsquo; if <var>addr</var> is in the middle of the
line, or &lsquo;<samp><span class="samp">beg</span></samp>&rsquo; if <var>addr</var> is at the beginning of the line, and
<var>addr</var> is the address in the target program associated with the
source which is being displayed. <var>addr</var> is in the form &lsquo;<samp><span class="samp">0x</span></samp>&rsquo;
followed by one or more lowercase hex digits (note that this does not
depend on the language).
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<h2 class="chapter">5 Values</h2>
<p><em>Value Annotations have been removed. </em><span class="sc">gdb/mi</span><em> instead provides
Variable Objects.</em>
<p><a name="index-annotations-for-values-3"></a>When a value is printed in various contexts, <span class="sc">gdb</span> uses
annotations to delimit the value from the surrounding text.
<p><a name="index-value_002dhistory_002dbegin-4"></a><a name="index-value_002dhistory_002dvalue-5"></a><a name="index-value_002dhistory_002dend-6"></a>If a value is printed using <code>print</code> and added to the value history,
the annotation looks like
<pre class="smallexample"> ^Z^Zvalue-history-begin <var>history-number</var> <var>value-flags</var>
<var>history-string</var>
^Z^Zvalue-history-value
<var>the-value</var>
^Z^Zvalue-history-end
</pre>
<p class="noindent">where <var>history-number</var> is the number it is getting in the value
history, <var>history-string</var> is a string, such as &lsquo;<samp><span class="samp">$5 = </span></samp>&rsquo;, which
introduces the value to the user, <var>the-value</var> is the output
corresponding to the value itself, and <var>value-flags</var> is &lsquo;<samp><span class="samp">*</span></samp>&rsquo; for
a value which can be dereferenced and &lsquo;<samp><span class="samp">-</span></samp>&rsquo; for a value which cannot.
<p><a name="index-value_002dbegin-7"></a><a name="index-value_002dend-8"></a>If the value is not added to the value history (it is an invalid float
or it is printed with the <code>output</code> command), the annotation is similar:
<pre class="smallexample"> ^Z^Zvalue-begin <var>value-flags</var>
<var>the-value</var>
^Z^Zvalue-end
</pre>
<p><a name="index-arg_002dbegin-9"></a><a name="index-arg_002dname_002dend-10"></a><a name="index-arg_002dvalue-11"></a><a name="index-arg_002dend-12"></a>When <span class="sc">gdb</span> prints an argument to a function (for example, in the output
from the <code>backtrace</code> command), it annotates it as follows:
<pre class="smallexample"> ^Z^Zarg-begin
<var>argument-name</var>
^Z^Zarg-name-end
<var>separator-string</var>
^Z^Zarg-value <var>value-flags</var>
<var>the-value</var>
^Z^Zarg-end
</pre>
<p class="noindent">where <var>argument-name</var> is the name of the argument,
<var>separator-string</var> is text which separates the name from the value
for the user's benefit (such as &lsquo;<samp><span class="samp">=</span></samp>&rsquo;), and <var>value-flags</var> and
<var>the-value</var> have the same meanings as in a
<code>value-history-begin</code> annotation.
<p><a name="index-field_002dbegin-13"></a><a name="index-field_002dname_002dend-14"></a><a name="index-field_002dvalue-15"></a><a name="index-field_002dend-16"></a>When printing a structure, <span class="sc">gdb</span> annotates it as follows:
<pre class="smallexample"> ^Z^Zfield-begin <var>value-flags</var>
<var>field-name</var>
^Z^Zfield-name-end
<var>separator-string</var>
^Z^Zfield-value
<var>the-value</var>
^Z^Zfield-end
</pre>
<p class="noindent">where <var>field-name</var> is the name of the field, <var>separator-string</var>
is text which separates the name from the value for the user's benefit
(such as &lsquo;<samp><span class="samp">=</span></samp>&rsquo;), and <var>value-flags</var> and <var>the-value</var> have the
same meanings as in a <code>value-history-begin</code> annotation.
<p>When printing an array, <span class="sc">gdb</span> annotates it as follows:
<pre class="smallexample"> ^Z^Zarray-section-begin <var>array-index</var> <var>value-flags</var>
</pre>
<p class="noindent">where <var>array-index</var> is the index of the first element being
annotated and <var>value-flags</var> has the same meaning as in a
<code>value-history-begin</code> annotation. This is followed by any number
of elements, where is element can be either a single element:
<p><a name="index-elt-17"></a>
<pre class="smallexample"> &lsquo;<samp><span class="samp">,</span></samp>&rsquo; <var>whitespace</var> ; <span class="roman">omitted for the first element</span>
<var>the-value</var>
^Z^Zelt
</pre>
<p>or a repeated element
<p><a name="index-elt_002drep-18"></a><a name="index-elt_002drep_002dend-19"></a>
<pre class="smallexample"> &lsquo;<samp><span class="samp">,</span></samp>&rsquo; <var>whitespace</var> ; <span class="roman">omitted for the first element</span>
<var>the-value</var>
^Z^Zelt-rep <var>number-of-repetitions</var>
<var>repetition-string</var>
^Z^Zelt-rep-end
</pre>
<p>In both cases, <var>the-value</var> is the output for the value of the
element and <var>whitespace</var> can contain spaces, tabs, and newlines. In
the repeated case, <var>number-of-repetitions</var> is the number of
consecutive array elements which contain that value, and
<var>repetition-string</var> is a string which is designed to convey to the
user that repetition is being depicted.
<p><a name="index-array_002dsection_002dend-20"></a>Once all the array elements have been output, the array annotation is
ended with
<pre class="smallexample"> ^Z^Zarray-section-end
</pre>
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<body>
This file documents <span class="sc">gdb</span>'s obsolete annotations.
<p>Copyright &copy; 1994-2013 Free Software Foundation, Inc.
<p>Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3 or
any later version published by the Free Software Foundation; with no
Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
Texts. A copy of the license is included in the section entitled &ldquo;GNU
Free Documentation License&rdquo;.
<div class="node">
<p>
<a name="Top"></a>
Next:&nbsp;<a rel="next" accesskey="n" href="Annotations-Overview.html#Annotations-Overview">Annotations Overview</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="../index.html#dir">(dir)</a>
<hr>
</div>
<h2 class="unnumbered">GDB Annotations</h2>
<p>This document describes the obsolete level two annotation interface
implemented in older <span class="sc">gdb</span> versions.
<ul class="menu">
<li><a accesskey="1" href="Annotations-Overview.html#Annotations-Overview">Annotations Overview</a>: What annotations are; the general syntax.
<li><a accesskey="2" href="Limitations.html#Limitations">Limitations</a>: Limitations of the annotation interface.
<li><a accesskey="3" href="Migrating-to-GDB_002fMI.html#Migrating-to-GDB_002fMI">Migrating to GDB/MI</a>: Migrating to GDB/MI
<li><a accesskey="4" href="Server-Prefix.html#Server-Prefix">Server Prefix</a>: Issuing a command without affecting user state.
<li><a accesskey="5" href="Value-Annotations.html#Value-Annotations">Value Annotations</a>: Values are marked as such.
<li><a accesskey="6" href="Frame-Annotations.html#Frame-Annotations">Frame Annotations</a>: Stack frames are annotated.
<li><a accesskey="7" href="Displays.html#Displays">Displays</a>: <span class="sc">gdb</span> can be told to display something periodically.
<li><a accesskey="8" href="Prompting.html#Prompting">Prompting</a>: Annotations marking <span class="sc">gdb</span>'s need for input.
<li><a accesskey="9" href="Errors.html#Errors">Errors</a>: Annotations for error messages.
<li><a href="Breakpoint-Info.html#Breakpoint-Info">Breakpoint Info</a>: Information on breakpoints.
<li><a href="Invalidation.html#Invalidation">Invalidation</a>: Some annotations describe things now invalid.
<li><a href="Annotations-for-Running.html#Annotations-for-Running">Annotations for Running</a>
Whether the program is running, how it stopped, etc.
<li><a href="Source-Annotations.html#Source-Annotations">Source Annotations</a>: Annotations describing source code.
<li><a href="Multi_002dthreaded-Apps.html#Multi_002dthreaded-Apps">Multi-threaded Apps</a>: An annotation that reports multi-threadedness.
<li><a href="GNU-Free-Documentation-License.html#GNU-Free-Documentation-License">GNU Free Documentation License</a>
</ul>
<div class="contents">
<h2>Table of Contents</h2>
<ul>
<li><a name="toc_Top" href="index.html#Top">GDB Annotations</a>
<li><a name="toc_Annotations-Overview" href="Annotations-Overview.html#Annotations-Overview">1 What is an Annotation?</a>
<li><a name="toc_Limitations" href="Limitations.html#Limitations">2 Limitations of the Annotation Interface</a>
<ul>
<li><a href="Limitations.html#Limitations">2.1 Dependant on <span class="sc">cli</span> output</a>
<li><a href="Limitations.html#Limitations">2.2 Scalability</a>
<li><a href="Limitations.html#Limitations">2.3 Correctness</a>
<li><a href="Limitations.html#Limitations">2.4 Reliability</a>
<li><a href="Limitations.html#Limitations">2.5 Maintainability</a>
</li></ul>
<li><a name="toc_Migrating-to-GDB_002fMI" href="Migrating-to-GDB_002fMI.html#Migrating-to-GDB_002fMI">3 Migrating to <span class="sc">gdb/mi</span></a>
<li><a name="toc_Server-Prefix" href="Server-Prefix.html#Server-Prefix">4 The Server Prefix</a>
<li><a name="toc_Value-Annotations" href="Value-Annotations.html#Value-Annotations">5 Values</a>
<li><a name="toc_Frame-Annotations" href="Frame-Annotations.html#Frame-Annotations">6 Frames</a>
<li><a name="toc_Displays" href="Displays.html#Displays">7 Displays</a>
<li><a name="toc_Prompting" href="Prompting.html#Prompting">8 Annotation for <span class="sc">gdb</span> Input</a>
<li><a name="toc_Errors" href="Errors.html#Errors">9 Errors</a>
<li><a name="toc_Breakpoint-Info" href="Breakpoint-Info.html#Breakpoint-Info">10 Information on Breakpoints</a>
<li><a name="toc_Invalidation" href="Invalidation.html#Invalidation">11 Invalidation Notices</a>
<li><a name="toc_Annotations-for-Running" href="Annotations-for-Running.html#Annotations-for-Running">12 Running the Program</a>
<li><a name="toc_Source-Annotations" href="Source-Annotations.html#Source-Annotations">13 Displaying Source</a>
<li><a name="toc_Multi_002dthreaded-Apps" href="Multi_002dthreaded-Apps.html#Multi_002dthreaded-Apps">14 Multi-threaded Applications</a>
<li><a name="toc_GNU-Free-Documentation-License" href="GNU-Free-Documentation-License.html#GNU-Free-Documentation-License">Appendix A GNU Free Documentation License</a>
</li></ul>
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<a name="AArch64-Directives"></a>
Next:&nbsp;<a rel="next" accesskey="n" href="AArch64-Opcodes.html#AArch64-Opcodes">AArch64 Opcodes</a>,
Previous:&nbsp;<a rel="previous" accesskey="p" href="AArch64-Floating-Point.html#AArch64-Floating-Point">AArch64 Floating Point</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="AArch64_002dDependent.html#AArch64_002dDependent">AArch64-Dependent</a>
<hr>
</div>
<h4 class="subsection">9.1.4 AArch64 Machine Directives</h4>
<p><a name="index-machine-directives_002c-AArch64-536"></a><a name="index-AArch64-machine-directives-537"></a>
<dl>
<!-- AAAAAAAAAAAAAAAAAAAAAAAAA -->
<!-- BBBBBBBBBBBBBBBBBBBBBBBBBB -->
<p><a name="index-g_t_0040code_007b_002ebss_007d-directive_002c-AArch64-538"></a><dt><code>.bss</code><dd>This directive switches to the <code>.bss</code> section.
<!-- CCCCCCCCCCCCCCCCCCCCCCCCCC -->
<!-- DDDDDDDDDDDDDDDDDDDDDDDDDD -->
<!-- EEEEEEEEEEEEEEEEEEEEEEEEEE -->
<!-- FFFFFFFFFFFFFFFFFFFFFFFFFF -->
<!-- GGGGGGGGGGGGGGGGGGGGGGGGGG -->
<!-- HHHHHHHHHHHHHHHHHHHHHHHHHH -->
<!-- IIIIIIIIIIIIIIIIIIIIIIIIII -->
<!-- JJJJJJJJJJJJJJJJJJJJJJJJJJ -->
<!-- KKKKKKKKKKKKKKKKKKKKKKKKKK -->
<!-- LLLLLLLLLLLLLLLLLLLLLLLLLL -->
<p><a name="index-g_t_0040code_007b_002eltorg_007d-directive_002c-AArch64-539"></a><br><dt><code>.ltorg</code><dd>This directive causes the current contents of the literal pool to be
dumped into the current section (which is assumed to be the .text
section) at the current location (aligned to a word boundary).
<code>GAS</code> maintains a separate literal pool for each section and each
sub-section. The <code>.ltorg</code> directive will only affect the literal
pool of the current section and sub-section. At the end of assembly
all remaining, un-empty literal pools will automatically be dumped.
<p>Note - older versions of <code>GAS</code> would dump the current literal
pool any time a section change occurred. This is no longer done, since
it prevents accurate control of the placement of literal pools.
<!-- MMMMMMMMMMMMMMMMMMMMMMMMMM -->
<!-- NNNNNNNNNNNNNNNNNNNNNNNNNN -->
<!-- OOOOOOOOOOOOOOOOOOOOOOOOOO -->
<!-- PPPPPPPPPPPPPPPPPPPPPPPPPP -->
<p><a name="index-g_t_0040code_007b_002epool_007d-directive_002c-AArch64-540"></a><br><dt><code>.pool</code><dd>This is a synonym for .ltorg.
<!-- QQQQQQQQQQQQQQQQQQQQQQQQQQ -->
<!-- RRRRRRRRRRRRRRRRRRRRRRRRRR -->
<p><a name="index-g_t_0040code_007b_002ereq_007d-directive_002c-AArch64-541"></a><br><dt><var>name</var><code> .req </code><var>register name</var><dd>This creates an alias for <var>register name</var> called <var>name</var>. For
example:
<pre class="smallexample"> foo .req w0
</pre>
<!-- SSSSSSSSSSSSSSSSSSSSSSSSSS -->
<!-- TTTTTTTTTTTTTTTTTTTTTTTTTT -->
<!-- UUUUUUUUUUUUUUUUUUUUUUUUUU -->
<p><a name="index-g_t_0040code_007b_002eunreq_007d-directive_002c-AArch64-542"></a><br><dt><code>.unreq </code><var>alias-name</var><dd>This undefines a register alias which was previously defined using the
<code>req</code> directive. For example:
<pre class="smallexample"> foo .req w0
.unreq foo
</pre>
<p>An error occurs if the name is undefined. Note - this pseudo op can
be used to delete builtin in register name aliases (eg 'w0'). This
should only be done if it is really necessary.
<!-- VVVVVVVVVVVVVVVVVVVVVVVVVV -->
<!-- WWWWWWWWWWWWWWWWWWWWWWWWWW -->
<!-- XXXXXXXXXXXXXXXXXXXXXXXXXX -->
<!-- YYYYYYYYYYYYYYYYYYYYYYYYYY -->
<!-- ZZZZZZZZZZZZZZZZZZZZZZZZZZ -->
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<hr>
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<h4 class="subsection">9.1.3 Floating Point</h4>
<p><a name="index-floating-point_002c-AArch64-_0028_0040sc_007bieee_007d_0029-534"></a><a name="index-AArch64-floating-point-_0028_0040sc_007bieee_007d_0029-535"></a>The AArch64 architecture uses <span class="sc">ieee</span> floating-point numbers.
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<hr>
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<h4 class="subsection">9.1.6 Mapping Symbols</h4>
<p>The AArch64 ELF specification requires that special symbols be inserted
into object files to mark certain features:
<a name="index-g_t_0040code_007b_0024x_007d-546"></a>
<dl><dt><code>$x</code><dd>At the start of a region of code containing AArch64 instructions.
<p><a name="index-g_t_0040code_007b_0024d_007d-547"></a><br><dt><code>$d</code><dd>At the start of a region of data.
</dl>
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<p>
<a name="AArch64-Opcodes"></a>
Next:&nbsp;<a rel="next" accesskey="n" href="AArch64-Mapping-Symbols.html#AArch64-Mapping-Symbols">AArch64 Mapping Symbols</a>,
Previous:&nbsp;<a rel="previous" accesskey="p" href="AArch64-Directives.html#AArch64-Directives">AArch64 Directives</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="AArch64_002dDependent.html#AArch64_002dDependent">AArch64-Dependent</a>
<hr>
</div>
<h4 class="subsection">9.1.5 Opcodes</h4>
<p><a name="index-AArch64-opcodes-543"></a><a name="index-opcodes-for-AArch64-544"></a><code>as</code> implements all the standard AArch64 opcodes. It also
implements several pseudo opcodes, including several synthetic load
instructions.
<a name="index-g_t_0040code_007bLDR-reg_002c_003d_003cexpr_003e_007d-pseudo-op_002c-AArch64-545"></a>
<dl><dt><code>LDR =</code><dd>
<pre class="smallexample"> ldr &lt;register&gt; , =&lt;expression&gt;
</pre>
<p>The constant expression will be placed into the nearest literal pool (if it not
already there) and a PC-relative LDR instruction will be generated.
</dl>
<p>For more information on the AArch64 instruction set and assembly language
notation, see &lsquo;<samp><span class="samp">ARMv8 Instruction Set Overview</span></samp>&rsquo; available at
<a href="http://infocenter.arm.com">http://infocenter.arm.com</a>.
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<hr>
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<h4 class="subsection">9.1.1 Options</h4>
<p><a name="index-AArch64-options-_0028none_0029-517"></a><a name="index-options-for-AArch64-_0028none_0029-518"></a>
<!-- man begin OPTIONS -->
<a name="index-g_t_0040code_007b_002dEB_007d-command-line-option_002c-AArch64-519"></a>
<dl><dt><code>-EB</code><dd>This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
<p><a name="index-g_t_0040code_007b_002dEL_007d-command-line-option_002c-AArch64-520"></a><br><dt><code>-EL</code><dd>This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor.
</dl>
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<a name="AArch64-Syntax"></a>
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Previous:&nbsp;<a rel="previous" accesskey="p" href="AArch64-Options.html#AArch64-Options">AArch64 Options</a>,
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<hr>
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<h4 class="subsection">9.1.2 Syntax</h4>
<ul class="menu">
<li><a accesskey="1" href="AArch64_002dChars.html#AArch64_002dChars">AArch64-Chars</a>: Special Characters
<li><a accesskey="2" href="AArch64_002dRegs.html#AArch64_002dRegs">AArch64-Regs</a>: Register Names
<li><a accesskey="3" href="AArch64_002dRelocations.html#AArch64_002dRelocations">AArch64-Relocations</a>: Relocations
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<hr>
</div>
<h5 class="subsubsection">9.1.2.1 Special Characters</h5>
<p><a name="index-line-comment-character_002c-AArch64-521"></a><a name="index-AArch64-line-comment-character-522"></a>The presence of a &lsquo;<samp><span class="samp">//</span></samp>&rsquo; on a line indicates the start of a comment
that extends to the end of the current line. If a &lsquo;<samp><span class="samp">#</span></samp>&rsquo; appears as
the first character of a line, the whole line is treated as a comment.
<p><a name="index-line-separator_002c-AArch64-523"></a><a name="index-statement-separator_002c-AArch64-524"></a><a name="index-AArch64-line-separator-525"></a>The &lsquo;<samp><span class="samp">;</span></samp>&rsquo; character can be used instead of a newline to separate
statements.
<p><a name="index-immediate-character_002c-AArch64-526"></a><a name="index-AArch64-immediate-character-527"></a>The &lsquo;<samp><span class="samp">#</span></samp>&rsquo; can be optionally used to indicate immediate operands.
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<a name="AArch64_002dDependent"></a>
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<hr>
</div>
<h3 class="section">9.1 AArch64 Dependent Features</h3>
<p><a name="index-AArch64-support-515"></a><a name="index-Thumb-support-516"></a>
<ul class="menu">
<li><a accesskey="1" href="AArch64-Options.html#AArch64-Options">AArch64 Options</a>: Options
<li><a accesskey="2" href="AArch64-Syntax.html#AArch64-Syntax">AArch64 Syntax</a>: Syntax
<li><a accesskey="3" href="AArch64-Floating-Point.html#AArch64-Floating-Point">AArch64 Floating Point</a>: Floating Point
<li><a accesskey="4" href="AArch64-Directives.html#AArch64-Directives">AArch64 Directives</a>: AArch64 Machine Directives
<li><a accesskey="5" href="AArch64-Opcodes.html#AArch64-Opcodes">AArch64 Opcodes</a>: Opcodes
<li><a accesskey="6" href="AArch64-Mapping-Symbols.html#AArch64-Mapping-Symbols">AArch64 Mapping Symbols</a>: Mapping Symbols
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<h5 class="subsubsection">9.1.2.2 Register Names</h5>
<p><a name="index-AArch64-register-names-528"></a><a name="index-register-names_002c-AArch64-529"></a>Please refer to the section &lsquo;<samp><span class="samp">4.4 Register Names</span></samp>&rsquo; of
&lsquo;<samp><span class="samp">ARMv8 Instruction Set Overview</span></samp>&rsquo;, which is available at
<a href="http://infocenter.arm.com">http://infocenter.arm.com</a>.
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<a name="AArch64_002dRelocations"></a>
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<hr>
</div>
<h5 class="subsubsection">9.1.2.3 Relocations</h5>
<p><a name="index-relocations_002c-AArch64-530"></a><a name="index-AArch64-relocations-531"></a><a name="index-MOVN_002c-MOVZ-and-MOVK-group-relocations_002c-AArch64-532"></a>Relocations for &lsquo;<samp><span class="samp">MOVZ</span></samp>&rsquo; and &lsquo;<samp><span class="samp">MOVK</span></samp>&rsquo; instructions can be generated
by prefixing the label with &lsquo;<samp><span class="samp">#:abs_g2:</span></samp>&rsquo; etc.
For example to load the 48-bit absolute address of <var>foo</var> into x0:
<pre class="smallexample"> movz x0, #:abs_g2:foo // bits 32-47, overflow check
movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
</pre>
<p><a name="index-ADRP_002c-ADD_002c-LDR_002fSTR-group-relocations_002c-AArch64-533"></a>Relocations for &lsquo;<samp><span class="samp">ADRP</span></samp>&rsquo;, and &lsquo;<samp><span class="samp">ADD</span></samp>&rsquo;, &lsquo;<samp><span class="samp">LDR</span></samp>&rsquo; or &lsquo;<samp><span class="samp">STR</span></samp>&rsquo;
instructions can be generated by prefixing the label with
&lsquo;<samp><span class="samp">#:pg_hi21:</span></samp>&rsquo; and &lsquo;<samp><span class="samp">#:lo12:</span></samp>&rsquo; respectively.
<p>For example to use 33-bit (+/-4GB) pc-relative addressing to
load the address of <var>foo</var> into x0:
<pre class="smallexample"> adrp x0, #:pg_hi21:foo
add x0, x0, #:lo12:foo
</pre>
<p>Or to load the value of <var>foo</var> into x0:
<pre class="smallexample"> adrp x0, #:pg_hi21:foo
ldr x0, [x0, #:lo12:foo]
</pre>
<p>Note that &lsquo;<samp><span class="samp">#:pg_hi21:</span></samp>&rsquo; is optional.
<pre class="smallexample"> adrp x0, foo
</pre>
<p>is equivalent to
<pre class="smallexample"> adrp x0, #:pg_hi21:foo
</pre>
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<h3 class="section">7.2 <code>.ABORT</code> (COFF)</h3>
<p><a name="index-g_t_0040code_007bABORT_007d-directive-274"></a>When producing COFF output, <samp><span class="command">as</span></samp> accepts this directive as a
synonym for &lsquo;<samp><span class="samp">.abort</span></samp>&rsquo;.
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<a name="ARC-Directives"></a>
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<h4 class="subsection">9.3.4 ARC Machine Directives</h4>
<p><a name="index-machine-directives_002c-ARC-595"></a><a name="index-ARC-machine-directives-596"></a>The ARC version of <code>as</code> supports the following additional
machine directives:
<a name="index-g_t_0040code_007b2byte_007d-directive_002c-ARC-597"></a>
<dl><dt><code>.2byte </code><var>expressions</var><dd>*TODO*
<p><a name="index-g_t_0040code_007b3byte_007d-directive_002c-ARC-598"></a><br><dt><code>.3byte </code><var>expressions</var><dd>*TODO*
<p><a name="index-g_t_0040code_007b4byte_007d-directive_002c-ARC-599"></a><br><dt><code>.4byte </code><var>expressions</var><dd>*TODO*
<p><a name="index-g_t_0040code_007bextAuxRegister_007d-directive_002c-ARC-600"></a><br><dt><code>.extAuxRegister </code><var>name</var><code>,</code><var>address</var><code>,</code><var>mode</var><dd>The ARCtangent A4 has extensible auxiliary register space. The
auxiliary registers can be defined in the assembler source code by
using this directive. The first parameter is the <var>name</var> of the
new auxiallry register. The second parameter is the <var>address</var> of
the register in the auxiliary register memory map for the variant of
the ARC. The third parameter specifies the <var>mode</var> in which the
register can be operated is and it can be one of:
<dl>
<dt><code>r (readonly)</code><br><dt><code>w (write only)</code><br><dt><code>r|w (read or write)</code><dd></dl>
<p>For example:
<pre class="smallexample"> .extAuxRegister mulhi,0x12,w
</pre>
<p>This specifies an extension auxiliary register called <em>mulhi</em>
which is at address 0x12 in the memory space and which is only
writable.
<p><a name="index-g_t_0040code_007bextCondCode_007d-directive_002c-ARC-601"></a><br><dt><code>.extCondCode </code><var>suffix</var><code>,</code><var>value</var><dd>The condition codes on the ARCtangent A4 are extensible and can be
specified by means of this assembler directive. They are specified
by the suffix and the value for the condition code. They can be used to
specify extra condition codes with any values. For example:
<pre class="smallexample"> .extCondCode is_busy,0x14
add.is_busy r1,r2,r3
bis_busy _main
</pre>
<p><a name="index-g_t_0040code_007bextCoreRegister_007d-directive_002c-ARC-602"></a><br><dt><code>.extCoreRegister </code><var>name</var><code>,</code><var>regnum</var><code>,</code><var>mode</var><code>,</code><var>shortcut</var><dd>Specifies an extension core register <var>name</var> for the application.
This allows a register <var>name</var> with a valid <var>regnum</var> between 0
and 60, with the following as valid values for <var>mode</var>
<dl>
<dt>&lsquo;<samp><em>r</em><span class="samp"> (readonly)</span></samp>&rsquo;<br><dt>&lsquo;<samp><em>w</em><span class="samp"> (write only)</span></samp>&rsquo;<br><dt>&lsquo;<samp><em>r|w</em><span class="samp"> (read or write)</span></samp>&rsquo;<dd></dl>
<p>The other parameter gives a description of the register having a
<var>shortcut</var> in the pipeline. The valid values are:
<dl>
<dt><code>can_shortcut</code><br><dt><code>cannot_shortcut</code><dd></dl>
<p>For example:
<pre class="smallexample"> .extCoreRegister mlo,57,r,can_shortcut
</pre>
<p>This defines an extension core register mlo with the value 57 which
can shortcut the pipeline.
<p><a name="index-g_t_0040code_007bextInstruction_007d-directive_002c-ARC-603"></a><br><dt><code>.extInstruction </code><var>name</var><code>,</code><var>opcode</var><code>,</code><var>subopcode</var><code>,</code><var>suffixclass</var><code>,</code><var>syntaxclass</var><dd>The ARCtangent A4 allows the user to specify extension instructions.
The extension instructions are not macros. The assembler creates
encodings for use of these instructions according to the specification
by the user. The parameters are:
<dl>
<dt>&bull;<var>name</var><dd>Name of the extension instruction
<br><dt>&bull;<var>opcode</var><dd>Opcode to be used. (Bits 27:31 in the encoding). Valid values
0x10-0x1f or 0x03
<br><dt>&bull;<var>subopcode</var><dd>Subopcode to be used. Valid values are from 0x09-0x3f. However the
correct value also depends on <var>syntaxclass</var>
<br><dt>&bull;<var>suffixclass</var><dd>Determines the kinds of suffixes to be allowed. Valid values are
<code>SUFFIX_NONE</code>, <code>SUFFIX_COND</code>,
<code>SUFFIX_FLAG</code> which indicates the absence or presence of
conditional suffixes and flag setting by the extension instruction.
It is also possible to specify that an instruction sets the flags and
is conditional by using <code>SUFFIX_CODE</code> | <code>SUFFIX_FLAG</code>.
<br><dt>&bull;<var>syntaxclass</var><dd>Determines the syntax class for the instruction. It can have the
following values:
<dl>
<dt><code>SYNTAX_2OP:</code><dd>2 Operand Instruction
<br><dt><code>SYNTAX_3OP:</code><dd>3 Operand Instruction
</dl>
<p>In addition there could be modifiers for the syntax class as described
below:
<ul>
Syntax Class Modifiers are:
<li><code>OP1_MUST_BE_IMM</code>:
Modifies syntax class SYNTAX_3OP, specifying that the first operand
of a three-operand instruction must be an immediate (i.e., the result
is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with
SYNTAX_3OP as given in the example below. This could usually be used
to set the flags using specific instructions and not retain results.
<li><code>OP1_IMM_IMPLIED</code>:
Modifies syntax class SYNTAX_20P, it specifies that there is an
implied immediate destination operand which does not appear in the
syntax. For example, if the source code contains an instruction like:
<pre class="smallexample"> inst r1,r2
</pre>
<p>it really means that the first argument is an implied immediate (that
is, the result is discarded). This is the same as though the source
code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it
with SYNTAX_20P.
</ul>
</dl>
<p>For example, defining 64-bit multiplier with immediate operands:
<pre class="smallexample"> .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
SYNTAX_3OP|OP1_MUST_BE_IMM
</pre>
<p>The above specifies an extension instruction called mp64 which has 3 operands,
sets the flags, can be used with a condition code, for which the
first operand is an immediate. (Equivalent to discarding the result
of the operation).
<pre class="smallexample"> .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
</pre>
<p>This describes a 2 operand instruction with an implicit first
immediate operand. The result of this operation would be discarded.
<p><a name="index-g_t_0040code_007bhalf_007d-directive_002c-ARC-604"></a><br><dt><code>.half </code><var>expressions</var><dd>*TODO*
<p><a name="index-g_t_0040code_007blong_007d-directive_002c-ARC-605"></a><br><dt><code>.long </code><var>expressions</var><dd>*TODO*
<p><a name="index-g_t_0040code_007boption_007d-directive_002c-ARC-606"></a><br><dt><code>.option </code><var>arc|arc5|arc6|arc7|arc8</var><dd>The <code>.option</code> directive must be followed by the desired core
version. Again <code>arc</code> is an alias for
<code>arc6</code>.
<p>Note: the <code>.option</code> directive overrides the command line option
<code>-marc</code>; a warning is emitted when the version is not consistent
between the two - even for the implicit default core version
(arc6).
<p><a name="index-g_t_0040code_007bshort_007d-directive_002c-ARC-607"></a><br><dt><code>.short </code><var>expressions</var><dd>*TODO*
<p><a name="index-g_t_0040code_007bword_007d-directive_002c-ARC-608"></a><br><dt><code>.word </code><var>expressions</var><dd>*TODO*
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<h4 class="subsection">9.3.3 Floating Point</h4>
<p><a name="index-floating-point_002c-ARC-_0028_0040sc_007bieee_007d_0029-593"></a><a name="index-ARC-floating-point-_0028_0040sc_007bieee_007d_0029-594"></a>The ARC core does not currently have hardware floating point
support. Software floating point support is provided by <code>GCC</code>
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<h4 class="subsection">9.3.5 Opcodes</h4>
<p><a name="index-ARC-opcodes-609"></a><a name="index-opcodes-for-ARC-610"></a>
For information on the ARC instruction set, see <cite>ARC Programmers
Reference Manual</cite>, ARC International (www.arc.com)
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<h4 class="subsection">9.3.1 Options</h4>
<p><a name="index-ARC-options-_0028none_0029-577"></a><a name="index-options-for-ARC-_0028none_0029-578"></a>
<a name="index-g_t_0040code_007b_002dmarc_005b5_007c6_007c7_007c8_005d_007d-command-line-option_002c-ARC-579"></a>
<dl><dt><code>-marc[5|6|7|8]</code><dd>This option selects the core processor variant. Using
<code>-marc</code> is the same as <code>-marc6</code>, which
is also the default.
<a name="index-g_t_0040code_007barc5_007d-arc5_002c-ARC-580"></a>
<dl><dt><code>arc5</code><dd>Base instruction set.
<p><a name="index-g_t_0040code_007barc6_007d-arc6_002c-ARC-581"></a><br><dt><code>arc6</code><dd>Jump-and-link (jl) instruction. No requirement of an instruction between
setting flags and conditional jump. For example:
<pre class="smallexample"> mov.f r0,r1
beq foo
</pre>
<p><a name="index-g_t_0040code_007barc7_007d-arc7_002c-ARC-582"></a><br><dt><code>arc7</code><dd>Break (brk) and sleep (sleep) instructions.
<p><a name="index-g_t_0040code_007barc8_007d-arc8_002c-ARC-583"></a><br><dt><code>arc8</code><dd>Software interrupt (swi) instruction.
</dl>
<p>Note: the <code>.option</code> directive can to be used to select a core
variant from within assembly code.
<p><a name="index-g_t_0040code_007b_002dEB_007d-command-line-option_002c-ARC-584"></a><br><dt><code>-EB</code><dd>This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
<p><a name="index-g_t_0040code_007b_002dEL_007d-command-line-option_002c-ARC-585"></a><br><dt><code>-EL</code><dd>This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor - this is the
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<h4 class="subsection">9.3.2 Syntax</h4>
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<h5 class="subsubsection">9.3.2.1 Special Characters</h5>
<p><a name="index-line-comment-character_002c-ARC-586"></a><a name="index-ARC-line-comment-character-587"></a>The presence of a &lsquo;<samp><span class="samp">#</span></samp>&rsquo; on a line indicates the start of a comment
that extends to the end of the current line. Note that if a line
starts with a &lsquo;<samp><span class="samp">#</span></samp>&rsquo; character then it can also be a logical line
number directive (see <a href="Comments.html#Comments">Comments</a>) or a preprocessor
control command (see <a href="Preprocessing.html#Preprocessing">Preprocessing</a>).
<p><a name="index-line-separator_002c-ARC-588"></a><a name="index-statement-separator_002c-ARC-589"></a><a name="index-ARC-line-separator-590"></a>The ARC assembler does not support a line separator character.
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<h3 class="section">9.3 ARC Dependent Features</h3>
<p><a name="index-ARC-support-576"></a>
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<h5 class="subsubsection">9.3.2.2 Register Names</h5>
<p><a name="index-ARC-register-names-591"></a><a name="index-register-names_002c-ARC-592"></a>*TODO*
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<h4 class="subsection">9.4.4 ARM Machine Directives</h4>
<p><a name="index-machine-directives_002c-ARM-651"></a><a name="index-ARM-machine-directives-652"></a>
<dl>
<!-- AAAAAAAAAAAAAAAAAAAAAAAAA -->
<p><a name="index-g_t_0040code_007b_002e2byte_007d-directive_002c-ARM-653"></a><a name="index-g_t_0040code_007b_002e4byte_007d-directive_002c-ARM-654"></a><a name="index-g_t_0040code_007b_002e8byte_007d-directive_002c-ARM-655"></a><dt><code>.2byte </code><var>expression</var><code> [, </code><var>expression</var><code>]*</code><dt><code>.4byte </code><var>expression</var><code> [, </code><var>expression</var><code>]*</code><dt><code>.8byte </code><var>expression</var><code> [, </code><var>expression</var><code>]*</code><dd>These directives write 2, 4 or 8 byte values to the output section.
<p><a name="index-g_t_0040code_007b_002ealign_007d-directive_002c-ARM-656"></a><br><dt><code>.align </code><var>expression</var><code> [, </code><var>expression</var><code>]</code><dd>This is the generic <var>.align</var> directive. For the ARM however if the
first argument is zero (ie no alignment is needed) the assembler will
behave as if the argument had been 2 (ie pad to the next four byte
boundary). This is for compatibility with ARM's own assembler.
<p><a name="index-g_t_0040code_007b_002earch_007d-directive_002c-ARM-657"></a><br><dt><code>.arch </code><var>name</var><dd>Select the target architecture. Valid values for <var>name</var> are the same as
for the <samp><span class="option">-march</span></samp> commandline option.
<p>Specifying <code>.arch</code> clears any previously selected architecture
extensions.
<p><a name="index-g_t_0040code_007b_002earch_005fextension_007d-directive_002c-ARM-658"></a><br><dt><code>.arch_extension </code><var>name</var><dd>Add or remove an architecture extension to the target architecture. Valid
values for <var>name</var> are the same as those accepted as architectural
extensions by the <samp><span class="option">-mcpu</span></samp> commandline option.
<p><code>.arch_extension</code> may be used multiple times to add or remove extensions
incrementally to the architecture being compiled for.
<p><a name="index-g_t_0040code_007b_002earm_007d-directive_002c-ARM-659"></a><br><dt><code>.arm</code><dd>This performs the same action as <var>.code 32</var>.
<p><a name="arm_005fpad"></a><a name="index-g_t_0040code_007b_002epad_007d-directive_002c-ARM-660"></a><br><dt><code>.pad #</code><var>count</var><dd>Generate unwinder annotations for a stack adjustment of <var>count</var> bytes.
A positive value indicates the function prologue allocated stack space by
decrementing the stack pointer.
<!-- BBBBBBBBBBBBBBBBBBBBBBBBBB -->
<p><a name="index-g_t_0040code_007b_002ebss_007d-directive_002c-ARM-661"></a><br><dt><code>.bss</code><dd>This directive switches to the <code>.bss</code> section.
<!-- CCCCCCCCCCCCCCCCCCCCCCCCCC -->
<p><a name="index-g_t_0040code_007b_002ecantunwind_007d-directive_002c-ARM-662"></a><br><dt><code>.cantunwind</code><dd>Prevents unwinding through the current function. No personality routine
or exception table data is required or permitted.
<p><a name="index-g_t_0040code_007b_002ecode_007d-directive_002c-ARM-663"></a><br><dt><code>.code [16|32]</code><dd>This directive selects the instruction set being generated. The value 16
selects Thumb, with the value 32 selecting ARM.
<p><a name="index-g_t_0040code_007b_002ecpu_007d-directive_002c-ARM-664"></a><br><dt><code>.cpu </code><var>name</var><dd>Select the target processor. Valid values for <var>name</var> are the same as
for the <samp><span class="option">-mcpu</span></samp> commandline option.
<p>Specifying <code>.cpu</code> clears any previously selected architecture
extensions.
<!-- DDDDDDDDDDDDDDDDDDDDDDDDDD -->
<p><a name="index-g_t_0040code_007b_002edn_007d-and-_0040code_007b_002eqn_007d-directives_002c-ARM-665"></a><br><dt><var>name</var><code> .dn </code><var>register name</var><code> [</code><var>.type</var><code>] [[</code><var>index</var><code>]]</code><dt><var>name</var><code> .qn </code><var>register name</var><code> [</code><var>.type</var><code>] [[</code><var>index</var><code>]]</code><dd>
The <code>dn</code> and <code>qn</code> directives are used to create typed
and/or indexed register aliases for use in Advanced SIMD Extension
(Neon) instructions. The former should be used to create aliases
of double-precision registers, and the latter to create aliases of
quad-precision registers.
<p>If these directives are used to create typed aliases, those aliases can
be used in Neon instructions instead of writing types after the mnemonic
or after each operand. For example:
<pre class="smallexample"> x .dn d2.f32
y .dn d3.f32
z .dn d4.f32[1]
vmul x,y,z
</pre>
<p>This is equivalent to writing the following:
<pre class="smallexample"> vmul.f32 d2,d3,d4[1]
</pre>
<p>Aliases created using <code>dn</code> or <code>qn</code> can be destroyed using
<code>unreq</code>.
<!-- EEEEEEEEEEEEEEEEEEEEEEEEEE -->
<p><a name="index-g_t_0040code_007b_002eeabi_005fattribute_007d-directive_002c-ARM-666"></a><br><dt><code>.eabi_attribute </code><var>tag</var><code>, </code><var>value</var><dd>Set the EABI object attribute <var>tag</var> to <var>value</var>.
<p>The <var>tag</var> is either an attribute number, or one of the following:
<code>Tag_CPU_raw_name</code>, <code>Tag_CPU_name</code>, <code>Tag_CPU_arch</code>,
<code>Tag_CPU_arch_profile</code>, <code>Tag_ARM_ISA_use</code>,
<code>Tag_THUMB_ISA_use</code>, <code>Tag_FP_arch</code>, <code>Tag_WMMX_arch</code>,
<code>Tag_Advanced_SIMD_arch</code>, <code>Tag_PCS_config</code>,
<code>Tag_ABI_PCS_R9_use</code>, <code>Tag_ABI_PCS_RW_data</code>,
<code>Tag_ABI_PCS_RO_data</code>, <code>Tag_ABI_PCS_GOT_use</code>,
<code>Tag_ABI_PCS_wchar_t</code>, <code>Tag_ABI_FP_rounding</code>,
<code>Tag_ABI_FP_denormal</code>, <code>Tag_ABI_FP_exceptions</code>,
<code>Tag_ABI_FP_user_exceptions</code>, <code>Tag_ABI_FP_number_model</code>,
<code>Tag_ABI_align_needed</code>, <code>Tag_ABI_align_preserved</code>,
<code>Tag_ABI_enum_size</code>, <code>Tag_ABI_HardFP_use</code>,
<code>Tag_ABI_VFP_args</code>, <code>Tag_ABI_WMMX_args</code>,
<code>Tag_ABI_optimization_goals</code>, <code>Tag_ABI_FP_optimization_goals</code>,
<code>Tag_compatibility</code>, <code>Tag_CPU_unaligned_access</code>,
<code>Tag_FP_HP_extension</code>, <code>Tag_ABI_FP_16bit_format</code>,
<code>Tag_MPextension_use</code>, <code>Tag_DIV_use</code>,
<code>Tag_nodefaults</code>, <code>Tag_also_compatible_with</code>,
<code>Tag_conformance</code>, <code>Tag_T2EE_use</code>,
<code>Tag_Virtualization_use</code>
<p>The <var>value</var> is either a <code>number</code>, <code>"string"</code>, or
<code>number, "string"</code> depending on the tag.
<p>Note - the following legacy values are also accepted by <var>tag</var>:
<code>Tag_VFP_arch</code>, <code>Tag_ABI_align8_needed</code>,
<code>Tag_ABI_align8_preserved</code>, <code>Tag_VFP_HP_extension</code>,
<p><a name="index-g_t_0040code_007b_002eeven_007d-directive_002c-ARM-667"></a><br><dt><code>.even</code><dd>This directive aligns to an even-numbered address.
<p><a name="index-g_t_0040code_007b_002eextend_007d-directive_002c-ARM-668"></a><a name="index-g_t_0040code_007b_002eldouble_007d-directive_002c-ARM-669"></a><br><dt><code>.extend </code><var>expression</var><code> [, </code><var>expression</var><code>]*</code><dt><code>.ldouble </code><var>expression</var><code> [, </code><var>expression</var><code>]*</code><dd>These directives write 12byte long double floating-point values to the
output section. These are not compatible with current ARM processors
or ABIs.
<!-- FFFFFFFFFFFFFFFFFFFFFFFFFF -->
<p><a name="arm_005ffnend"></a><a name="index-g_t_0040code_007b_002efnend_007d-directive_002c-ARM-670"></a><br><dt><code>.fnend</code><dd>Marks the end of a function with an unwind table entry. The unwind index
table entry is created when this directive is processed.
<p>If no personality routine has been specified then standard personality
routine 0 or 1 will be used, depending on the number of unwind opcodes
required.
<p><a name="arm_005ffnstart"></a><a name="index-g_t_0040code_007b_002efnstart_007d-directive_002c-ARM-671"></a><br><dt><code>.fnstart</code><dd>Marks the start of a function with an unwind table entry.
<p><a name="index-g_t_0040code_007b_002eforce_005fthumb_007d-directive_002c-ARM-672"></a><br><dt><code>.force_thumb</code><dd>This directive forces the selection of Thumb instructions, even if the
target processor does not support those instructions
<p><a name="index-g_t_0040code_007b_002efpu_007d-directive_002c-ARM-673"></a><br><dt><code>.fpu </code><var>name</var><dd>Select the floating-point unit to assemble for. Valid values for <var>name</var>
are the same as for the <samp><span class="option">-mfpu</span></samp> commandline option.
<!-- GGGGGGGGGGGGGGGGGGGGGGGGGG -->
<!-- HHHHHHHHHHHHHHHHHHHHHHHHHH -->
<p><a name="index-g_t_0040code_007b_002ehandlerdata_007d-directive_002c-ARM-674"></a><br><dt><code>.handlerdata</code><dd>Marks the end of the current function, and the start of the exception table
entry for that function. Anything between this directive and the
<code>.fnend</code> directive will be added to the exception table entry.
<p>Must be preceded by a <code>.personality</code> or <code>.personalityindex</code>
directive.
<!-- IIIIIIIIIIIIIIIIIIIIIIIIII -->
<p><a name="index-g_t_0040code_007b_002einst_007d-directive_002c-ARM-675"></a><br><dt><code>.inst </code><var>opcode</var><code> [ , ... ]</code><dt><code>.inst.n </code><var>opcode</var><code> [ , ... ]</code><dt><code>.inst.w </code><var>opcode</var><code> [ , ... ]</code><dd>Generates the instruction corresponding to the numerical value <var>opcode</var>.
<code>.inst.n</code> and <code>.inst.w</code> allow the Thumb instruction size to be
specified explicitly, overriding the normal encoding rules.
<!-- JJJJJJJJJJJJJJJJJJJJJJJJJJ -->
<!-- KKKKKKKKKKKKKKKKKKKKKKKKKK -->
<!-- LLLLLLLLLLLLLLLLLLLLLLLLLL -->
<br><dt><code>.ldouble </code><var>expression</var><code> [, </code><var>expression</var><code>]*</code><dd>See <code>.extend</code>.
<p><a name="index-g_t_0040code_007b_002eltorg_007d-directive_002c-ARM-676"></a><br><dt><code>.ltorg</code><dd>This directive causes the current contents of the literal pool to be
dumped into the current section (which is assumed to be the .text
section) at the current location (aligned to a word boundary).
<code>GAS</code> maintains a separate literal pool for each section and each
sub-section. The <code>.ltorg</code> directive will only affect the literal
pool of the current section and sub-section. At the end of assembly
all remaining, un-empty literal pools will automatically be dumped.
<p>Note - older versions of <code>GAS</code> would dump the current literal
pool any time a section change occurred. This is no longer done, since
it prevents accurate control of the placement of literal pools.
<!-- MMMMMMMMMMMMMMMMMMMMMMMMMM -->
<p><a name="index-g_t_0040code_007b_002emovsp_007d-directive_002c-ARM-677"></a><br><dt><code>.movsp </code><var>reg</var><code> [, #</code><var>offset</var><code>]</code><dd>Tell the unwinder that <var>reg</var> contains an offset from the current
stack pointer. If <var>offset</var> is not specified then it is assumed to be
zero.
<!-- NNNNNNNNNNNNNNNNNNNNNNNNNN -->
<!-- OOOOOOOOOOOOOOOOOOOOOOOOOO -->
<p><a name="index-g_t_0040code_007b_002eobject_005farch_007d-directive_002c-ARM-678"></a><br><dt><code>.object_arch </code><var>name</var><dd>Override the architecture recorded in the EABI object attribute section.
Valid values for <var>name</var> are the same as for the <code>.arch</code> directive.
Typically this is useful when code uses runtime detection of CPU features.
<!-- PPPPPPPPPPPPPPPPPPPPPPPPPP -->
<p><a name="index-g_t_0040code_007b_002epacked_007d-directive_002c-ARM-679"></a><br><dt><code>.packed </code><var>expression</var><code> [, </code><var>expression</var><code>]*</code><dd>This directive writes 12-byte packed floating-point values to the
output section. These are not compatible with current ARM processors
or ABIs.
<p><a name="index-g_t_0040code_007b_002epad_007d-directive_002c-ARM-680"></a><br><dt><code>.pad #</code><var>count</var><dd>Generate unwinder annotations for a stack adjustment of <var>count</var> bytes.
A positive value indicates the function prologue allocated stack space by
decrementing the stack pointer.
<p><a name="index-g_t_0040code_007b_002epersonality_007d-directive_002c-ARM-681"></a><br><dt><code>.personality </code><var>name</var><dd>Sets the personality routine for the current function to <var>name</var>.
<p><a name="index-g_t_0040code_007b_002epersonalityindex_007d-directive_002c-ARM-682"></a><br><dt><code>.personalityindex </code><var>index</var><dd>Sets the personality routine for the current function to the EABI standard
routine number <var>index</var>
<p><a name="index-g_t_0040code_007b_002epool_007d-directive_002c-ARM-683"></a><br><dt><code>.pool</code><dd>This is a synonym for .ltorg.
<!-- QQQQQQQQQQQQQQQQQQQQQQQQQQ -->
<!-- RRRRRRRRRRRRRRRRRRRRRRRRRR -->
<p><a name="index-g_t_0040code_007b_002ereq_007d-directive_002c-ARM-684"></a><br><dt><var>name</var><code> .req </code><var>register name</var><dd>This creates an alias for <var>register name</var> called <var>name</var>. For
example:
<pre class="smallexample"> foo .req r0
</pre>
<!-- SSSSSSSSSSSSSSSSSSSSSSSSSS -->
<p><a name="arm_005fsave"></a><a name="index-g_t_0040code_007b_002esave_007d-directive_002c-ARM-685"></a><br><dt><code>.save </code><var>reglist</var><dd>Generate unwinder annotations to restore the registers in <var>reglist</var>.
The format of <var>reglist</var> is the same as the corresponding store-multiple
instruction.
<pre class="smallexample"> <br><em>core registers</em><br>
.save {r4, r5, r6, lr}
stmfd sp!, {r4, r5, r6, lr}
<br><em>FPA registers</em><br>
.save f4, 2
sfmfd f4, 2, [sp]!
<br><em>VFP registers</em><br>
.save {d8, d9, d10}
fstmdx sp!, {d8, d9, d10}
<br><em>iWMMXt registers</em><br>
.save {wr10, wr11}
wstrd wr11, [sp, #-8]!
wstrd wr10, [sp, #-8]!
or
.save wr11
wstrd wr11, [sp, #-8]!
.save wr10
wstrd wr10, [sp, #-8]!
</pre>
<p><a name="arm_005fsetfp"></a><a name="index-g_t_0040code_007b_002esetfp_007d-directive_002c-ARM-686"></a><br><dt><code>.setfp </code><var>fpreg</var><code>, </code><var>spreg</var><code> [, #</code><var>offset</var><code>]</code><dd>Make all unwinder annotations relative to a frame pointer. Without this
the unwinder will use offsets from the stack pointer.
<p>The syntax of this directive is the same as the <code>add</code> or <code>mov</code>
instruction used to set the frame pointer. <var>spreg</var> must be either
<code>sp</code> or mentioned in a previous <code>.movsp</code> directive.
<pre class="smallexample"> .movsp ip
mov ip, sp
...
.setfp fp, ip, #4
add fp, ip, #4
</pre>
<p><a name="index-g_t_0040code_007b_002esecrel32_007d-directive_002c-ARM-687"></a><br><dt><code>.secrel32 </code><var>expression</var><code> [, </code><var>expression</var><code>]*</code><dd>This directive emits relocations that evaluate to the section-relative
offset of each expression's symbol. This directive is only supported
for PE targets.
<p><a name="index-g_t_0040code_007b_002esyntax_007d-directive_002c-ARM-688"></a><br><dt><code>.syntax [unified | divided]</code><dd>This directive sets the Instruction Set Syntax as described in the
<a href="ARM_002dInstruction_002dSet.html#ARM_002dInstruction_002dSet">ARM-Instruction-Set</a> section.
<!-- TTTTTTTTTTTTTTTTTTTTTTTTTT -->
<p><a name="index-g_t_0040code_007b_002ethumb_007d-directive_002c-ARM-689"></a><br><dt><code>.thumb</code><dd>This performs the same action as <var>.code 16</var>.
<p><a name="index-g_t_0040code_007b_002ethumb_005ffunc_007d-directive_002c-ARM-690"></a><br><dt><code>.thumb_func</code><dd>This directive specifies that the following symbol is the name of a
Thumb encoded function. This information is necessary in order to allow
the assembler and linker to generate correct code for interworking
between Arm and Thumb instructions and should be used even if
interworking is not going to be performed. The presence of this
directive also implies <code>.thumb</code>
<p>This directive is not neccessary when generating EABI objects. On these
targets the encoding is implicit when generating Thumb code.
<p><a name="index-g_t_0040code_007b_002ethumb_005fset_007d-directive_002c-ARM-691"></a><br><dt><code>.thumb_set</code><dd>This performs the equivalent of a <code>.set</code> directive in that it
creates a symbol which is an alias for another symbol (possibly not yet
defined). This directive also has the added property in that it marks
the aliased symbol as being a thumb function entry point, in the same
way that the <code>.thumb_func</code> directive does.
<p><a name="index-g_t_0040code_007b_002etlsdescseq_007d-directive_002c-ARM-692"></a><br><dt><code>.tlsdescseq </code><var>tls-variable</var><dd>This directive is used to annotate parts of an inlined TLS descriptor
trampoline. Normally the trampoline is provided by the linker, and
this directive is not needed.
<!-- UUUUUUUUUUUUUUUUUUUUUUUUUU -->
<p><a name="index-g_t_0040code_007b_002eunreq_007d-directive_002c-ARM-693"></a><br><dt><code>.unreq </code><var>alias-name</var><dd>This undefines a register alias which was previously defined using the
<code>req</code>, <code>dn</code> or <code>qn</code> directives. For example:
<pre class="smallexample"> foo .req r0
.unreq foo
</pre>
<p>An error occurs if the name is undefined. Note - this pseudo op can
be used to delete builtin in register name aliases (eg 'r0'). This
should only be done if it is really necessary.
<p><a name="index-g_t_0040code_007b_002eunwind_005fraw_007d-directive_002c-ARM-694"></a><br><dt><code>.unwind_raw </code><var>offset</var><code>, </code><var>byte1</var><code>, ...</code><dd>Insert one of more arbitary unwind opcode bytes, which are known to adjust
the stack pointer by <var>offset</var> bytes.
<p>For example <code>.unwind_raw 4, 0xb1, 0x01</code> is equivalent to
<code>.save {r0}</code>
<!-- VVVVVVVVVVVVVVVVVVVVVVVVVV -->
<p><a name="index-g_t_0040code_007b_002evsave_007d-directive_002c-ARM-695"></a><br><dt><code>.vsave </code><var>vfp-reglist</var><dd>Generate unwinder annotations to restore the VFP registers in <var>vfp-reglist</var>
using FLDMD. Also works for VFPv3 registers
that are to be restored using VLDM.
The format of <var>vfp-reglist</var> is the same as the corresponding store-multiple
instruction.
<pre class="smallexample"> <br><em>VFP registers</em><br>
.vsave {d8, d9, d10}
fstmdd sp!, {d8, d9, d10}
<br><em>VFPv3 registers</em><br>
.vsave {d15, d16, d17}
vstm sp!, {d15, d16, d17}
</pre>
<p>Since FLDMX and FSTMX are now deprecated, this directive should be
used in favour of <code>.save</code> for saving VFP registers for ARMv6 and above.
<!-- WWWWWWWWWWWWWWWWWWWWWWWWWW -->
<!-- XXXXXXXXXXXXXXXXXXXXXXXXXX -->
<!-- YYYYYYYYYYYYYYYYYYYYYYYYYY -->
<!-- ZZZZZZZZZZZZZZZZZZZZZZZZZZ -->
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<h4 class="subsection">9.4.3 Floating Point</h4>
<p><a name="index-floating-point_002c-ARM-_0028_0040sc_007bieee_007d_0029-646"></a><a name="index-ARM-floating-point-_0028_0040sc_007bieee_007d_0029-647"></a>The ARM family uses <span class="sc">ieee</span> floating-point numbers.
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Previous:&nbsp;<a rel="previous" accesskey="p" href="ARM-Opcodes.html#ARM-Opcodes">ARM Opcodes</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="ARM_002dDependent.html#ARM_002dDependent">ARM-Dependent</a>
<hr>
</div>
<h4 class="subsection">9.4.6 Mapping Symbols</h4>
<p>The ARM ELF specification requires that special symbols be inserted
into object files to mark certain features:
<a name="index-g_t_0040code_007b_0024a_007d-702"></a>
<dl><dt><code>$a</code><dd>At the start of a region of code containing ARM instructions.
<p><a name="index-g_t_0040code_007b_0024t_007d-703"></a><br><dt><code>$t</code><dd>At the start of a region of code containing THUMB instructions.
<p><a name="index-g_t_0040code_007b_0024d_007d-704"></a><br><dt><code>$d</code><dd>At the start of a region of data.
</dl>
<p>The assembler will automatically insert these symbols for you - there
is no need to code them yourself. Support for tagging symbols ($b,
$f, $p and $m) which is also mentioned in the current ARM ELF
specification is not implemented. This is because they have been
dropped from the new EABI and so tools cannot rely upon their
presence.
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Previous:&nbsp;<a rel="previous" accesskey="p" href="ARM-Directives.html#ARM-Directives">ARM Directives</a>,
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<hr>
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<h4 class="subsection">9.4.5 Opcodes</h4>
<p><a name="index-ARM-opcodes-696"></a><a name="index-opcodes-for-ARM-697"></a><code>as</code> implements all the standard ARM opcodes. It also
implements several pseudo opcodes, including several synthetic load
instructions.
<a name="index-g_t_0040code_007bNOP_007d-pseudo-op_002c-ARM-698"></a>
<dl><dt><code>NOP</code><dd>
<pre class="smallexample"> nop
</pre>
<p>This pseudo op will always evaluate to a legal ARM instruction that does
nothing. Currently it will evaluate to MOV r0, r0.
<p><a name="index-g_t_0040code_007bLDR-reg_002c_003d_003clabel_003e_007d-pseudo-op_002c-ARM-699"></a><br><dt><code>LDR</code><dd>
<pre class="smallexample"> ldr &lt;register&gt; , = &lt;expression&gt;
</pre>
<p>If expression evaluates to a numeric constant then a MOV or MVN
instruction will be used in place of the LDR instruction, if the
constant can be generated by either of these instructions. Otherwise
the constant will be placed into the nearest literal pool (if it not
already there) and a PC relative LDR instruction will be generated.
<p><a name="index-g_t_0040code_007bADR-reg_002c_003clabel_003e_007d-pseudo-op_002c-ARM-700"></a><br><dt><code>ADR</code><dd>
<pre class="smallexample"> adr &lt;register&gt; &lt;label&gt;
</pre>
<p>This instruction will load the address of <var>label</var> into the indicated
register. The instruction will evaluate to a PC relative ADD or SUB
instruction depending upon where the label is located. If the label is
out of range, or if it is not defined in the same file (and section) as
the ADR instruction, then an error will be generated. This instruction
will not make use of the literal pool.
<p><a name="index-g_t_0040code_007bADRL-reg_002c_003clabel_003e_007d-pseudo-op_002c-ARM-701"></a><br><dt><code>ADRL</code><dd>
<pre class="smallexample"> adrl &lt;register&gt; &lt;label&gt;
</pre>
<p>This instruction will load the address of <var>label</var> into the indicated
register. The instruction will evaluate to one or two PC relative ADD
or SUB instructions depending upon where the label is located. If a
second instruction is not needed a NOP instruction will be generated in
its place, so that this instruction is always 8 bytes long.
<p>If the label is out of range, or if it is not defined in the same file
(and section) as the ADRL instruction, then an error will be generated.
This instruction will not make use of the literal pool.
</dl>
<p>For information on the ARM or Thumb instruction sets, see <cite>ARM
Software Development Toolkit Reference Manual</cite>, Advanced RISC Machines
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<h4 class="subsection">9.4.1 Options</h4>
<p><a name="index-ARM-options-_0028none_0029-613"></a><a name="index-options-for-ARM-_0028none_0029-614"></a>
<a name="index-g_t_0040code_007b_002dmcpu_003d_007d-command-line-option_002c-ARM-615"></a>
<dl><dt><code>-mcpu=</code><var>processor</var><code>[+</code><var>extension</var><code>...]</code><dd>This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
recognized:
<code>arm1</code>,
<code>arm2</code>,
<code>arm250</code>,
<code>arm3</code>,
<code>arm6</code>,
<code>arm60</code>,
<code>arm600</code>,
<code>arm610</code>,
<code>arm620</code>,
<code>arm7</code>,
<code>arm7m</code>,
<code>arm7d</code>,
<code>arm7dm</code>,
<code>arm7di</code>,
<code>arm7dmi</code>,
<code>arm70</code>,
<code>arm700</code>,
<code>arm700i</code>,
<code>arm710</code>,
<code>arm710t</code>,
<code>arm720</code>,
<code>arm720t</code>,
<code>arm740t</code>,
<code>arm710c</code>,
<code>arm7100</code>,
<code>arm7500</code>,
<code>arm7500fe</code>,
<code>arm7t</code>,
<code>arm7tdmi</code>,
<code>arm7tdmi-s</code>,
<code>arm8</code>,
<code>arm810</code>,
<code>strongarm</code>,
<code>strongarm1</code>,
<code>strongarm110</code>,
<code>strongarm1100</code>,
<code>strongarm1110</code>,
<code>arm9</code>,
<code>arm920</code>,
<code>arm920t</code>,
<code>arm922t</code>,
<code>arm940t</code>,
<code>arm9tdmi</code>,
<code>fa526</code> (Faraday FA526 processor),
<code>fa626</code> (Faraday FA626 processor),
<code>arm9e</code>,
<code>arm926e</code>,
<code>arm926ej-s</code>,
<code>arm946e-r0</code>,
<code>arm946e</code>,
<code>arm946e-s</code>,
<code>arm966e-r0</code>,
<code>arm966e</code>,
<code>arm966e-s</code>,
<code>arm968e-s</code>,
<code>arm10t</code>,
<code>arm10tdmi</code>,
<code>arm10e</code>,
<code>arm1020</code>,
<code>arm1020t</code>,
<code>arm1020e</code>,
<code>arm1022e</code>,
<code>arm1026ej-s</code>,
<code>fa606te</code> (Faraday FA606TE processor),
<code>fa616te</code> (Faraday FA616TE processor),
<code>fa626te</code> (Faraday FA626TE processor),
<code>fmp626</code> (Faraday FMP626 processor),
<code>fa726te</code> (Faraday FA726TE processor),
<code>arm1136j-s</code>,
<code>arm1136jf-s</code>,
<code>arm1156t2-s</code>,
<code>arm1156t2f-s</code>,
<code>arm1176jz-s</code>,
<code>arm1176jzf-s</code>,
<code>mpcore</code>,
<code>mpcorenovfp</code>,
<code>cortex-a5</code>,
<code>cortex-a7</code>,
<code>cortex-a8</code>,
<code>cortex-a9</code>,
<code>cortex-a15</code>,
<code>cortex-r4</code>,
<code>cortex-r4f</code>,
<code>cortex-r5</code>,
<code>cortex-r7</code>,
<code>cortex-m4</code>,
<code>cortex-m3</code>,
<code>cortex-m1</code>,
<code>cortex-m0</code>,
<code>cortex-m0plus</code>,
<code>ep9312</code> (ARM920 with Cirrus Maverick coprocessor),
<code>i80200</code> (Intel XScale processor)
<code>iwmmxt</code> (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
and
<code>xscale</code>.
The special name <code>all</code> may be used to allow the
assembler to accept instructions valid for any ARM processor.
<p>In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics that extend the processor using the
co-processor instruction space. For example, <code>-mcpu=arm920+maverick</code>
is equivalent to specifying <code>-mcpu=ep9312</code>.
<p>Multiple extensions may be specified, separated by a <code>+</code>. The
extensions should be specified in ascending alphabetical order.
<p>Some extensions may be restricted to particular architectures; this is
documented in the list of extensions below.
<p>Extension mnemonics may also be removed from those the assembler accepts.
This is done be prepending <code>no</code> to the option that adds the extension.
Extensions that are removed should be listed after all extensions which have
been added, again in ascending alphabetical order. For example,
<code>-mcpu=ep9312+nomaverick</code> is equivalent to specifying <code>-mcpu=arm920</code>.
<p>The following extensions are currently supported:
<code>crypto</code> (Cryptography Extensions for v8-A architecture, implies <code>fp+simd</code>),
<code>fp</code> (Floating Point Extensions for v8-A architecture),
<code>idiv</code> (Integer Divide Extensions for v7-A and v7-R architectures),
<code>iwmmxt</code>,
<code>iwmmxt2</code>,
<code>maverick</code>,
<code>mp</code> (Multiprocessing Extensions for v7-A and v7-R architectures),
<code>os</code> (Operating System for v6M architecture),
<code>sec</code> (Security Extensions for v6K and v7-A architectures),
<code>simd</code> (Advanced SIMD Extensions for v8-A architecture, implies <code>fp</code>),
<code>virt</code> (Virtualization Extensions for v7-A architecture, implies
<code>idiv</code>),
and
<code>xscale</code>.
<p><a name="index-g_t_0040code_007b_002dmarch_003d_007d-command-line-option_002c-ARM-616"></a><br><dt><code>-march=</code><var>architecture</var><code>[+</code><var>extension</var><code>...]</code><dd>This option specifies the target architecture. The assembler will issue
an error message if an attempt is made to assemble an instruction which
will not execute on the target architecture. The following architecture
names are recognized:
<code>armv1</code>,
<code>armv2</code>,
<code>armv2a</code>,
<code>armv2s</code>,
<code>armv3</code>,
<code>armv3m</code>,
<code>armv4</code>,
<code>armv4xm</code>,
<code>armv4t</code>,
<code>armv4txm</code>,
<code>armv5</code>,
<code>armv5t</code>,
<code>armv5txm</code>,
<code>armv5te</code>,
<code>armv5texp</code>,
<code>armv6</code>,
<code>armv6j</code>,
<code>armv6k</code>,
<code>armv6z</code>,
<code>armv6zk</code>,
<code>armv6-m</code>,
<code>armv6s-m</code>,
<code>armv7</code>,
<code>armv7-a</code>,
<code>armv7-r</code>,
<code>armv7-m</code>,
<code>armv7e-m</code>,
<code>armv8-a</code>,
<code>iwmmxt</code>
and
<code>xscale</code>.
If both <code>-mcpu</code> and
<code>-march</code> are specified, the assembler will use
the setting for <code>-mcpu</code>.
<p>The architecture option can be extended with the same instruction set
extension options as the <code>-mcpu</code> option.
<p><a name="index-g_t_0040code_007b_002dmfpu_003d_007d-command-line-option_002c-ARM-617"></a><br><dt><code>-mfpu=</code><var>floating-point-format</var><dd>
This option specifies the floating point format to assemble for. The
assembler will issue an error message if an attempt is made to assemble
an instruction which will not execute on the target floating point unit.
The following format options are recognized:
<code>softfpa</code>,
<code>fpe</code>,
<code>fpe2</code>,
<code>fpe3</code>,
<code>fpa</code>,
<code>fpa10</code>,
<code>fpa11</code>,
<code>arm7500fe</code>,
<code>softvfp</code>,
<code>softvfp+vfp</code>,
<code>vfp</code>,
<code>vfp10</code>,
<code>vfp10-r0</code>,
<code>vfp9</code>,
<code>vfpxd</code>,
<code>vfpv2</code>,
<code>vfpv3</code>,
<code>vfpv3-fp16</code>,
<code>vfpv3-d16</code>,
<code>vfpv3-d16-fp16</code>,
<code>vfpv3xd</code>,
<code>vfpv3xd-d16</code>,
<code>vfpv4</code>,
<code>vfpv4-d16</code>,
<code>fpv4-sp-d16</code>,
<code>fp-armv8</code>,
<code>arm1020t</code>,
<code>arm1020e</code>,
<code>arm1136jf-s</code>,
<code>maverick</code>,
<code>neon</code>,
<code>neon-vfpv4</code>,
<code>neon-fp-armv8</code>,
and
<code>crypto-neon-fp-armv8</code>.
<p>In addition to determining which instructions are assembled, this option
also affects the way in which the <code>.double</code> assembler directive behaves
when assembling little-endian code.
<p>The default is dependent on the processor selected. For Architecture 5 or
later, the default is to assembler for VFP instructions; for earlier
architectures the default is to assemble for FPA instructions.
<p><a name="index-g_t_0040code_007b_002dmthumb_007d-command-line-option_002c-ARM-618"></a><br><dt><code>-mthumb</code><dd>This option specifies that the assembler should start assembling Thumb
instructions; that is, it should behave as though the file starts with a
<code>.code 16</code> directive.
<p><a name="index-g_t_0040code_007b_002dmthumb_002dinterwork_007d-command-line-option_002c-ARM-619"></a><br><dt><code>-mthumb-interwork</code><dd>This option specifies that the output generated by the assembler should
be marked as supporting interworking.
<p><a name="index-g_t_0040code_007b_002dmimplicit_002dit_007d-command-line-option_002c-ARM-620"></a><br><dt><code>-mimplicit-it=never</code><dt><code>-mimplicit-it=always</code><dt><code>-mimplicit-it=arm</code><dt><code>-mimplicit-it=thumb</code><dd>The <code>-mimplicit-it</code> option controls the behavior of the assembler when
conditional instructions are not enclosed in IT blocks.
There are four possible behaviors.
If <code>never</code> is specified, such constructs cause a warning in ARM
code and an error in Thumb-2 code.
If <code>always</code> is specified, such constructs are accepted in both
ARM and Thumb-2 code, where the IT instruction is added implicitly.
If <code>arm</code> is specified, such constructs are accepted in ARM code
and cause an error in Thumb-2 code.
If <code>thumb</code> is specified, such constructs cause a warning in ARM
code and are accepted in Thumb-2 code. If you omit this option, the
behavior is equivalent to <code>-mimplicit-it=arm</code>.
<p><a name="index-g_t_0040code_007b_002dmapcs_002d26_007d-command-line-option_002c-ARM-621"></a><a name="index-g_t_0040code_007b_002dmapcs_002d32_007d-command-line-option_002c-ARM-622"></a><br><dt><code>-mapcs-26</code><dt><code>-mapcs-32</code><dd>These options specify that the output generated by the assembler should
be marked as supporting the indicated version of the Arm Procedure.
Calling Standard.
<p><a name="index-g_t_0040code_007b_002dmatpcs_007d-command-line-option_002c-ARM-623"></a><br><dt><code>-matpcs</code><dd>This option specifies that the output generated by the assembler should
be marked as supporting the Arm/Thumb Procedure Calling Standard. If
enabled this option will cause the assembler to create an empty
debugging section in the object file called .arm.atpcs. Debuggers can
use this to determine the ABI being used by.
<p><a name="index-g_t_0040code_007b_002dmapcs_002dfloat_007d-command-line-option_002c-ARM-624"></a><br><dt><code>-mapcs-float</code><dd>This indicates the floating point variant of the APCS should be
used. In this variant floating point arguments are passed in FP
registers rather than integer registers.
<p><a name="index-g_t_0040code_007b_002dmapcs_002dreentrant_007d-command-line-option_002c-ARM-625"></a><br><dt><code>-mapcs-reentrant</code><dd>This indicates that the reentrant variant of the APCS should be used.
This variant supports position independent code.
<p><a name="index-g_t_0040code_007b_002dmfloat_002dabi_003d_007d-command-line-option_002c-ARM-626"></a><br><dt><code>-mfloat-abi=</code><var>abi</var><dd>This option specifies that the output generated by the assembler should be
marked as using specified floating point ABI.
The following values are recognized:
<code>soft</code>,
<code>softfp</code>
and
<code>hard</code>.
<p><a name="index-g_t_0040code_007b_002deabi_003d_007d-command-line-option_002c-ARM-627"></a><br><dt><code>-meabi=</code><var>ver</var><dd>This option specifies which EABI version the produced object files should
conform to.
The following values are recognized:
<code>gnu</code>,
<code>4</code>
and
<code>5</code>.
<p><a name="index-g_t_0040code_007b_002dEB_007d-command-line-option_002c-ARM-628"></a><br><dt><code>-EB</code><dd>This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
<p><a name="index-g_t_0040code_007b_002dEL_007d-command-line-option_002c-ARM-629"></a><br><dt><code>-EL</code><dd>This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor.
<p><a name="index-g_t_0040code_007b_002dk_007d-command-line-option_002c-ARM-630"></a><a name="index-PIC-code-generation-for-ARM-631"></a><br><dt><code>-k</code><dd>This option specifies that the output of the assembler should be marked
as position-independent code (PIC).
<p><a name="index-g_t_0040code_007b_002d_002dfix_002dv4bx_007d-command-line-option_002c-ARM-632"></a><br><dt><code>--fix-v4bx</code><dd>Allow <code>BX</code> instructions in ARMv4 code. This is intended for use with
the linker option of the same name.
<p><a name="index-g_t_0040code_007b_002dmwarn_002ddeprecated_007d-command-line-option_002c-ARM-633"></a><br><dt><code>-mwarn-deprecated</code><dt><code>-mno-warn-deprecated</code><dd>Enable or disable warnings about using deprecated options or
features. The default is to warn.
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<h4 class="subsection">9.4.2 Syntax</h4>
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<li><a accesskey="1" href="ARM_002dInstruction_002dSet.html#ARM_002dInstruction_002dSet">ARM-Instruction-Set</a>: Instruction Set
<li><a accesskey="2" href="ARM_002dChars.html#ARM_002dChars">ARM-Chars</a>: Special Characters
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<h4 class="subsection">9.4.7 Unwinding</h4>
<p>The ABI for the ARM Architecture specifies a standard format for
exception unwind information. This information is used when an
exception is thrown to determine where control should be transferred.
In particular, the unwind information is used to determine which
function called the function that threw the exception, and which
function called that one, and so forth. This information is also used
to restore the values of callee-saved registers in the function
catching the exception.
<p>If you are writing functions in assembly code, and those functions
call other functions that throw exceptions, you must use assembly
pseudo ops to ensure that appropriate exception unwind information is
generated. Otherwise, if one of the functions called by your assembly
code throws an exception, the run-time library will be unable to
unwind the stack through your assembly code and your program will not
behave correctly.
<p>To illustrate the use of these pseudo ops, we will examine the code
that G++ generates for the following C++ input:
<pre class="verbatim">
void callee (int *);
int
caller ()
{
int i;
callee (&amp;i);
return i;
}
</pre>
<p>This example does not show how to throw or catch an exception from
assembly code. That is a much more complex operation and should
always be done in a high-level language, such as C++, that directly
supports exceptions.
<p>The code generated by one particular version of G++ when compiling the
example above is:
<pre class="verbatim">
_Z6callerv:
.fnstart
.LFB2:
@ Function supports interworking.
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 1, uses_anonymous_args = 0
stmfd sp!, {fp, lr}
.save {fp, lr}
.LCFI0:
.setfp fp, sp, #4
add fp, sp, #4
.LCFI1:
.pad #8
sub sp, sp, #8
.LCFI2:
sub r3, fp, #8
mov r0, r3
bl _Z6calleePi
ldr r3, [fp, #-8]
mov r0, r3
sub sp, fp, #4
ldmfd sp!, {fp, lr}
bx lr
.LFE2:
.fnend
</pre>
<p>Of course, the sequence of instructions varies based on the options
you pass to GCC and on the version of GCC in use. The exact
instructions are not important since we are focusing on the pseudo ops
that are used to generate unwind information.
<p>An important assumption made by the unwinder is that the stack frame
does not change during the body of the function. In particular, since
we assume that the assembly code does not itself throw an exception,
the only point where an exception can be thrown is from a call, such
as the <code>bl</code> instruction above. At each call site, the same saved
registers (including <code>lr</code>, which indicates the return address)
must be located in the same locations relative to the frame pointer.
<p>The <code>.fnstart</code> (see <a href="arm_005ffnstart.html#arm_005ffnstart">.fnstart pseudo op</a>) pseudo
op appears immediately before the first instruction of the function
while the <code>.fnend</code> (see <a href="arm_005ffnend.html#arm_005ffnend">.fnend pseudo op</a>) pseudo
op appears immediately after the last instruction of the function.
These pseudo ops specify the range of the function.
<p>Only the order of the other pseudos ops (e.g., <code>.setfp</code> or
<code>.pad</code>) matters; their exact locations are irrelevant. In the
example above, the compiler emits the pseudo ops with particular
instructions. That makes it easier to understand the code, but it is
not required for correctness. It would work just as well to emit all
of the pseudo ops other than <code>.fnend</code> in the same order, but
immediately after <code>.fnstart</code>.
<p>The <code>.save</code> (see <a href="arm_005fsave.html#arm_005fsave">.save pseudo op</a>) pseudo op
indicates registers that have been saved to the stack so that they can
be restored before the function returns. The argument to the
<code>.save</code> pseudo op is a list of registers to save. If a register
is &ldquo;callee-saved&rdquo; (as specified by the ABI) and is modified by the
function you are writing, then your code must save the value before it
is modified and restore the original value before the function
returns. If an exception is thrown, the run-time library restores the
values of these registers from their locations on the stack before
returning control to the exception handler. (Of course, if an
exception is not thrown, the function that contains the <code>.save</code>
pseudo op restores these registers in the function epilogue, as is
done with the <code>ldmfd</code> instruction above.)
<p>You do not have to save callee-saved registers at the very beginning
of the function and you do not need to use the <code>.save</code> pseudo op
immediately following the point at which the registers are saved.
However, if you modify a callee-saved register, you must save it on
the stack before modifying it and before calling any functions which
might throw an exception. And, you must use the <code>.save</code> pseudo
op to indicate that you have done so.
<p>The <code>.pad</code> (see <a href="arm_005fpad.html#arm_005fpad">.pad</a>) pseudo op indicates a
modification of the stack pointer that does not save any registers.
The argument is the number of bytes (in decimal) that are subtracted
from the stack pointer. (On ARM CPUs, the stack grows downwards, so
subtracting from the stack pointer increases the size of the stack.)
<p>The <code>.setfp</code> (see <a href="arm_005fsetfp.html#arm_005fsetfp">.setfp pseudo op</a>) pseudo op
indicates the register that contains the frame pointer. The first
argument is the register that is set, which is typically <code>fp</code>.
The second argument indicates the register from which the frame
pointer takes its value. The third argument, if present, is the value
(in decimal) added to the register specified by the second argument to
compute the value of the frame pointer. You should not modify the
frame pointer in the body of the function.
<p>If you do not use a frame pointer, then you should not use the
<code>.setfp</code> pseudo op. If you do not use a frame pointer, then you
should avoid modifying the stack pointer outside of the function
prologue. Otherwise, the run-time library will be unable to find
saved registers when it is unwinding the stack.
<p>The pseudo ops described above are sufficient for writing assembly
code that calls functions which may throw exceptions. If you need to
know more about the object-file format used to represent unwind
information, you may consult the <cite>Exception Handling ABI for the
ARM Architecture</cite> available from <a href="http://infocenter.arm.com">http://infocenter.arm.com</a>.
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<h5 class="subsubsection">9.4.2.2 Special Characters</h5>
<p><a name="index-line-comment-character_002c-ARM-634"></a><a name="index-ARM-line-comment-character-635"></a>The presence of a &lsquo;<samp><span class="samp">@</span></samp>&rsquo; anywhere on a line indicates the start of
a comment that extends to the end of that line.
<p>If a &lsquo;<samp><span class="samp">#</span></samp>&rsquo; appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (see <a href="Comments.html#Comments">Comments</a>) or a preprocessor
control command (see <a href="Preprocessing.html#Preprocessing">Preprocessing</a>).
<p><a name="index-line-separator_002c-ARM-636"></a><a name="index-statement-separator_002c-ARM-637"></a><a name="index-ARM-line-separator-638"></a>The &lsquo;<samp><span class="samp">;</span></samp>&rsquo; character can be used instead of a newline to separate
statements.
<p><a name="index-immediate-character_002c-ARM-639"></a><a name="index-ARM-immediate-character-640"></a>Either &lsquo;<samp><span class="samp">#</span></samp>&rsquo; or &lsquo;<samp><span class="samp">$</span></samp>&rsquo; can be used to indicate immediate operands.
<p><a name="index-identifiers_002c-ARM-641"></a><a name="index-ARM-identifiers-642"></a>*TODO* Explain about /data modifier on symbols.
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<h3 class="section">9.4 ARM Dependent Features</h3>
<p><a name="index-ARM-support-611"></a><a name="index-Thumb-support-612"></a>
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<h5 class="subsubsection">9.4.2.1 Instruction Set Syntax</h5>
<p>Two slightly different syntaxes are support for ARM and THUMB
instructions. The default, <code>divided</code>, uses the old style where
ARM and THUMB instructions had their own, separate syntaxes. The new,
<code>unified</code> syntax, which can be selected via the <code>.syntax</code>
directive, and has the following main features:
<dl>
<dt>&bull;<dd>Immediate operands do not require a <code>#</code> prefix.
<br><dt>&bull;<dd>The <code>IT</code> instruction may appear, and if it does it is validated
against subsequent conditional affixes. In ARM mode it does not
generate machine code, in THUMB mode it does.
<br><dt>&bull;<dd>For ARM instructions the conditional affixes always appear at the end
of the instruction. For THUMB instructions conditional affixes can be
used, but only inside the scope of an <code>IT</code> instruction.
<br><dt>&bull;<dd>All of the instructions new to the V6T2 architecture (and later) are
available. (Only a few such instructions can be written in the
<code>divided</code> syntax).
<br><dt>&bull;<dd>The <code>.N</code> and <code>.W</code> suffixes are recognized and honored.
<br><dt>&bull;<dd>All instructions set the flags if and only if they have an <code>s</code>
affix.
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<a name="ARM_002dNeon_002dAlignment"></a>
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Up:&nbsp;<a rel="up" accesskey="u" href="ARM-Syntax.html#ARM-Syntax">ARM Syntax</a>
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<h5 class="subsubsection">9.4.2.4 NEON Alignment Specifiers</h5>
<p><a name="index-alignment-for-NEON-instructions-645"></a>Some NEON load/store instructions allow an optional address
alignment qualifier.
The ARM documentation specifies that this is indicated by
&lsquo;<samp><span class="samp">@ </span><var>align</var></samp>&rsquo;. However GAS already interprets
the &lsquo;<samp><span class="samp">@</span></samp>&rsquo; character as a "line comment" start,
so &lsquo;<samp><span class="samp">: </span><var>align</var></samp>&rsquo; is used instead. For example:
<pre class="smallexample"> vld1.8 {q0}, [r0, :128]
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<h5 class="subsubsection">9.4.2.3 Register Names</h5>
<p><a name="index-ARM-register-names-643"></a><a name="index-register-names_002c-ARM-644"></a>*TODO* Explain about ARM register naming, and the predefined names.
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<a name="ARM_002dRelocations"></a>
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Previous:&nbsp;<a rel="previous" accesskey="p" href="ARM_002dRegs.html#ARM_002dRegs">ARM-Regs</a>,
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<h5 class="subsubsection">9.4.3.1 ARM relocation generation</h5>
<p><a name="index-data-relocations_002c-ARM-648"></a><a name="index-ARM-data-relocations-649"></a>Specific data relocations can be generated by putting the relocation name
in parentheses after the symbol name. For example:
<pre class="smallexample"> .word foo(TARGET1)
</pre>
<p>This will generate an &lsquo;<samp><span class="samp">R_ARM_TARGET1</span></samp>&rsquo; relocation against the symbol
<var>foo</var>.
The following relocations are supported:
<code>GOT</code>,
<code>GOTOFF</code>,
<code>TARGET1</code>,
<code>TARGET2</code>,
<code>SBREL</code>,
<code>TLSGD</code>,
<code>TLSLDM</code>,
<code>TLSLDO</code>,
<code>TLSDESC</code>,
<code>TLSCALL</code>,
<code>GOTTPOFF</code>,
<code>GOT_PREL</code>
and
<code>TPOFF</code>.
<p>For compatibility with older toolchains the assembler also accepts
<code>(PLT)</code> after branch targets. On legacy targets this will
generate the deprecated &lsquo;<samp><span class="samp">R_ARM_PLT32</span></samp>&rsquo; relocation. On EABI
targets it will encode either the &lsquo;<samp><span class="samp">R_ARM_CALL</span></samp>&rsquo; or
&lsquo;<samp><span class="samp">R_ARM_JUMP24</span></samp>&rsquo; relocation, as appropriate.
<p><a name="index-MOVW-and-MOVT-relocations_002c-ARM-650"></a>Relocations for &lsquo;<samp><span class="samp">MOVW</span></samp>&rsquo; and &lsquo;<samp><span class="samp">MOVT</span></samp>&rsquo; instructions can be generated
by prefixing the value with &lsquo;<samp><span class="samp">#:lower16:</span></samp>&rsquo; and &lsquo;<samp><span class="samp">#:upper16</span></samp>&rsquo;
respectively. For example to load the 32-bit address of foo into r0:
<pre class="smallexample"> MOVW r0, #:lower16:foo
MOVT r0, #:upper16:foo
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<a name="AVR-Opcodes"></a>
Previous:&nbsp;<a rel="previous" accesskey="p" href="AVR-Syntax.html#AVR-Syntax">AVR Syntax</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="AVR_002dDependent.html#AVR_002dDependent">AVR-Dependent</a>
<hr>
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<h4 class="subsection">9.5.3 Opcodes</h4>
<p><a name="index-AVR-opcode-summary-722"></a><a name="index-opcode-summary_002c-AVR-723"></a><a name="index-mnemonics_002c-AVR-724"></a><a name="index-instruction-summary_002c-AVR-725"></a>For detailed information on the AVR machine instruction set, see
<a href="www.atmel.com/products/AVR">www.atmel.com/products/AVR</a>.
<p><code>as</code> implements all the standard AVR opcodes.
The following table summarizes the AVR opcodes, and their arguments.
<pre class="smallexample"> <i>Legend:</i>
r <span class="roman">any register</span>
d <span class="roman">`ldi' register (r16-r31)</span>
v <span class="roman">`movw' even register (r0, r2, ..., r28, r30)</span>
a <span class="roman">`fmul' register (r16-r23)</span>
w <span class="roman">`adiw' register (r24,r26,r28,r30)</span>
e <span class="roman">pointer registers (X,Y,Z)</span>
b <span class="roman">base pointer register and displacement ([YZ]+disp)</span>
z <span class="roman">Z pointer register (for [e]lpm Rd,Z[+])</span>
M <span class="roman">immediate value from 0 to 255</span>
n <span class="roman">immediate value from 0 to 255 ( n = ~M ). Relocation impossible</span>
s <span class="roman">immediate value from 0 to 7</span>
P <span class="roman">Port address value from 0 to 63. (in, out)</span>
p <span class="roman">Port address value from 0 to 31. (cbi, sbi, sbic, sbis)</span>
K <span class="roman">immediate value from 0 to 63 (used in `adiw', `sbiw')</span>
i <span class="roman">immediate value</span>
l <span class="roman">signed pc relative offset from -64 to 63</span>
L <span class="roman">signed pc relative offset from -2048 to 2047</span>
h <span class="roman">absolute code address (call, jmp)</span>
S <span class="roman">immediate value from 0 to 7 (S = s &lt;&lt; 4)</span>
? <span class="roman">use this opcode entry if no parameters, else use next opcode entry</span>
1001010010001000 clc
1001010011011000 clh
1001010011111000 cli
1001010010101000 cln
1001010011001000 cls
1001010011101000 clt
1001010010111000 clv
1001010010011000 clz
1001010000001000 sec
1001010001011000 seh
1001010001111000 sei
1001010000101000 sen
1001010001001000 ses
1001010001101000 set
1001010000111000 sev
1001010000011000 sez
100101001SSS1000 bclr S
100101000SSS1000 bset S
1001010100001001 icall
1001010000001001 ijmp
1001010111001000 lpm ?
1001000ddddd010+ lpm r,z
1001010111011000 elpm ?
1001000ddddd011+ elpm r,z
0000000000000000 nop
1001010100001000 ret
1001010100011000 reti
1001010110001000 sleep
1001010110011000 break
1001010110101000 wdr
1001010111101000 spm
000111rdddddrrrr adc r,r
000011rdddddrrrr add r,r
001000rdddddrrrr and r,r
000101rdddddrrrr cp r,r
000001rdddddrrrr cpc r,r
000100rdddddrrrr cpse r,r
001001rdddddrrrr eor r,r
001011rdddddrrrr mov r,r
100111rdddddrrrr mul r,r
001010rdddddrrrr or r,r
000010rdddddrrrr sbc r,r
000110rdddddrrrr sub r,r
001001rdddddrrrr clr r
000011rdddddrrrr lsl r
000111rdddddrrrr rol r
001000rdddddrrrr tst r
0111KKKKddddKKKK andi d,M
0111KKKKddddKKKK cbr d,n
1110KKKKddddKKKK ldi d,M
11101111dddd1111 ser d
0110KKKKddddKKKK ori d,M
0110KKKKddddKKKK sbr d,M
0011KKKKddddKKKK cpi d,M
0100KKKKddddKKKK sbci d,M
0101KKKKddddKKKK subi d,M
1111110rrrrr0sss sbrc r,s
1111111rrrrr0sss sbrs r,s
1111100ddddd0sss bld r,s
1111101ddddd0sss bst r,s
10110PPdddddPPPP in r,P
10111PPrrrrrPPPP out P,r
10010110KKddKKKK adiw w,K
10010111KKddKKKK sbiw w,K
10011000pppppsss cbi p,s
10011010pppppsss sbi p,s
10011001pppppsss sbic p,s
10011011pppppsss sbis p,s
111101lllllll000 brcc l
111100lllllll000 brcs l
111100lllllll001 breq l
111101lllllll100 brge l
111101lllllll101 brhc l
111100lllllll101 brhs l
111101lllllll111 brid l
111100lllllll111 brie l
111100lllllll000 brlo l
111100lllllll100 brlt l
111100lllllll010 brmi l
111101lllllll001 brne l
111101lllllll010 brpl l
111101lllllll000 brsh l
111101lllllll110 brtc l
111100lllllll110 brts l
111101lllllll011 brvc l
111100lllllll011 brvs l
111101lllllllsss brbc s,l
111100lllllllsss brbs s,l
1101LLLLLLLLLLLL rcall L
1100LLLLLLLLLLLL rjmp L
1001010hhhhh111h call h
1001010hhhhh110h jmp h
1001010rrrrr0101 asr r
1001010rrrrr0000 com r
1001010rrrrr1010 dec r
1001010rrrrr0011 inc r
1001010rrrrr0110 lsr r
1001010rrrrr0001 neg r
1001000rrrrr1111 pop r
1001001rrrrr1111 push r
1001010rrrrr0111 ror r
1001010rrrrr0010 swap r
00000001ddddrrrr movw v,v
00000010ddddrrrr muls d,d
000000110ddd0rrr mulsu a,a
000000110ddd1rrr fmul a,a
000000111ddd0rrr fmuls a,a
000000111ddd1rrr fmulsu a,a
1001001ddddd0000 sts i,r
1001000ddddd0000 lds r,i
10o0oo0dddddbooo ldd r,b
100!000dddddee-+ ld r,e
10o0oo1rrrrrbooo std b,r
100!001rrrrree-+ st e,r
1001010100011001 eicall
1001010000011001 eijmp
</pre>
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<h4 class="subsection">9.5.1 Options</h4>
<p><a name="index-AVR-options-_0028none_0029-706"></a><a name="index-options-for-AVR-_0028none_0029-707"></a>
<a name="index-g_t_0040code_007b_002dmmcu_003d_007d-command-line-option_002c-AVR-708"></a>
<dl><dt><code>-mmcu=</code><var>mcu</var><dd>Specify ATMEL AVR instruction set or MCU type.
<p>Instruction set avr1 is for the minimal AVR core, not supported by the C
compiler, only for assembler programs (MCU types: at90s1200,
attiny11, attiny12, attiny15, attiny28).
<p>Instruction set avr2 (default) is for the classic AVR core with up to
8K program memory space (MCU types: at90s2313, at90s2323, at90s2333, at90s2343,
attiny22, attiny26, at90s4414, at90s4433, at90s4434, at90s8515, at90c8534,
at90s8535).
<p>Instruction set avr25 is for the classic AVR core with up to 8K program memory
space plus the MOVW instruction (MCU types: attiny13, attiny13a, attiny2313,
attiny2313a, attiny24, attiny24a, attiny4313, attiny44, attiny44a, attiny84,
attiny84a, attiny25, attiny45, attiny85, attiny261, attiny261a, attiny461,
attiny461a, attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88,
at86rf401, ata6289).
<p>Instruction set avr3 is for the classic AVR core with up to 128K program
memory space (MCU types: at43usb355, at76c711).
<p>Instruction set avr31 is for the classic AVR core with exactly 128K program
memory space (MCU types: atmega103, at43usb320).
<p>Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP
instructions (MCU types: attiny167, at90usb82, at90usb162, atmega8u2,
atmega16u2, atmega32u2).
<p>Instruction set avr4 is for the enhanced AVR core with up to 8K program
memory space (MCU types: atmega48, atmega48a, atmega48p, atmega8, atmega88,
atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1,
at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81).
<p>Instruction set avr5 is for the enhanced AVR core with up to 128K program
memory space (MCU types: atmega16, atmega16a, atmega161, atmega162, atmega163,
atmega164a, atmega164p, atmega165, atmega165a, atmega165p, atmega168,
atmega168a, atmega168p, atmega169, atmega169a, atmega169p, atmega169pa,
atmega32, atmega323, atmega324a, atmega324p, atmega325, atmega325a, atmega325p,
atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328,
atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, atmega3290,
atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega640,
atmega644, atmega644a, atmega644p, atmega644pa, atmega645, atmega645a,
atmega645p, atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a,
atmega649p, atmega6490, atmega6490a, atmega6490p, atmega16hva, atmega16hva2,
atmega16hvb, atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve,
at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316, atmega32c1,
atmega64c1, atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4,
atmega32u6, at90usb646, at90usb647, at94k, at90scr100).
<p>Instruction set avr51 is for the enhanced AVR core with exactly 128K program
memory space (MCU types: atmega128, atmega1280, atmega1281, atmega1284p,
atmega128rfa1, at90can128, at90usb1286, at90usb1287, m3000).
<p>Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types:
atmega2560, atmega2561).
<p>Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K program
memory space and less than 64K data space (MCU types: atxmega16a4, atxmega16d4,
atxmega16x1, atxmega32a4, atxmega32d4, atxmega32x1).
<p>Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K program
memory space and greater than 64K data space (MCU types: none).
<p>Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program
memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64d3).
<p>Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program
memory space and greater than 64K data space (MCU types: atxmega64a1,
atxmega64a1u).
<p>Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K program
memory space and less than 64K data space (MCU types: atxmega128a3,
atxmega128d3, atxmega192a3, atxmega128b1, atxmega192d3, atxmega256a3,
atxmega256a3b, atxmega256a3bu, atxmega192d3).
<p>Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K program
memory space and greater than 64K data space (MCU types: atxmega128a1,
atxmega128a1u).
<p><a name="index-g_t_0040code_007b_002dmall_002dopcodes_007d-command-line-option_002c-AVR-709"></a><br><dt><code>-mall-opcodes</code><dd>Accept all AVR opcodes, even if not supported by <code>-mmcu</code>.
<p><a name="index-g_t_0040code_007b_002dmno_002dskip_002dbug_007d-command-line-option_002c-AVR-710"></a><br><dt><code>-mno-skip-bug</code><dd>This option disable warnings for skipping two-word instructions.
<p><a name="index-g_t_0040code_007b_002dmno_002dwrap_007d-command-line-option_002c-AVR-711"></a><br><dt><code>-mno-wrap</code><dd>This option reject <code>rjmp/rcall</code> instructions with 8K wrap-around.
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<h4 class="subsection">9.5.2 Syntax</h4>
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<li><a accesskey="2" href="AVR_002dRegs.html#AVR_002dRegs">AVR-Regs</a>: Register Names
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<h5 class="subsubsection">9.5.2.1 Special Characters</h5>
<p><a name="index-line-comment-character_002c-AVR-712"></a><a name="index-AVR-line-comment-character-713"></a>
The presence of a &lsquo;<samp><span class="samp">;</span></samp>&rsquo; anywhere on a line indicates the start of a
comment that extends to the end of that line.
<p>If a &lsquo;<samp><span class="samp">#</span></samp>&rsquo; appears as the first character of a line, the whole line
is treated as a comment, but in this case the line can also be a
logical line number directive (see <a href="Comments.html#Comments">Comments</a>) or a preprocessor
control command (see <a href="Preprocessing.html#Preprocessing">Preprocessing</a>).
<p><a name="index-line-separator_002c-AVR-714"></a><a name="index-statement-separator_002c-AVR-715"></a><a name="index-AVR-line-separator-716"></a>
The &lsquo;<samp><span class="samp">$</span></samp>&rsquo; character can be used instead of a newline to separate
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<h3 class="section">9.5 AVR Dependent Features</h3>
<p><a name="index-AVR-support-705"></a>
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<h5 class="subsubsection">9.5.2.3 Relocatable Expression Modifiers</h5>
<p><a name="index-AVR-modifiers-719"></a><a name="index-syntax_002c-AVR-720"></a>
The assembler supports several modifiers when using relocatable addresses
in AVR instruction operands. The general syntax is the following:
<pre class="smallexample"> modifier(relocatable-expression)
</pre>
<a name="index-symbol-modifiers-721"></a>
<dl>
<dt><code>lo8</code><dd>
This modifier allows you to use bits 0 through 7 of
an address expression as 8 bit relocatable expression.
<br><dt><code>hi8</code><dd>
This modifier allows you to use bits 7 through 15 of an address expression
as 8 bit relocatable expression. This is useful with, for example, the
AVR &lsquo;<samp><span class="samp">ldi</span></samp>&rsquo; instruction and &lsquo;<samp><span class="samp">lo8</span></samp>&rsquo; modifier.
<p>For example
<pre class="smallexample"> ldi r26, lo8(sym+10)
ldi r27, hi8(sym+10)
</pre>
<br><dt><code>hh8</code><dd>
This modifier allows you to use bits 16 through 23 of
an address expression as 8 bit relocatable expression.
Also, can be useful for loading 32 bit constants.
<br><dt><code>hlo8</code><dd>
Synonym of &lsquo;<samp><span class="samp">hh8</span></samp>&rsquo;.
<br><dt><code>hhi8</code><dd>
This modifier allows you to use bits 24 through 31 of
an expression as 8 bit expression. This is useful with, for example, the
AVR &lsquo;<samp><span class="samp">ldi</span></samp>&rsquo; instruction and &lsquo;<samp><span class="samp">lo8</span></samp>&rsquo;, &lsquo;<samp><span class="samp">hi8</span></samp>&rsquo;, &lsquo;<samp><span class="samp">hlo8</span></samp>&rsquo;,
&lsquo;<samp><span class="samp">hhi8</span></samp>&rsquo;, modifier.
<p>For example
<pre class="smallexample"> ldi r26, lo8(285774925)
ldi r27, hi8(285774925)
ldi r28, hlo8(285774925)
ldi r29, hhi8(285774925)
; r29,r28,r27,r26 = 285774925
</pre>
<br><dt><code>pm_lo8</code><dd>
This modifier allows you to use bits 0 through 7 of
an address expression as 8 bit relocatable expression.
This modifier useful for addressing data or code from
Flash/Program memory. The using of &lsquo;<samp><span class="samp">pm_lo8</span></samp>&rsquo; similar
to &lsquo;<samp><span class="samp">lo8</span></samp>&rsquo;.
<br><dt><code>pm_hi8</code><dd>
This modifier allows you to use bits 8 through 15 of
an address expression as 8 bit relocatable expression.
This modifier useful for addressing data or code from
Flash/Program memory.
<br><dt><code>pm_hh8</code><dd>
This modifier allows you to use bits 15 through 23 of
an address expression as 8 bit relocatable expression.
This modifier useful for addressing data or code from
Flash/Program memory.
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<h5 class="subsubsection">9.5.2.2 Register Names</h5>
<p><a name="index-AVR-register-names-717"></a><a name="index-register-names_002c-AVR-718"></a>
The AVR has 32 x 8-bit general purpose working registers &lsquo;<samp><span class="samp">r0</span></samp>&rsquo;,
&lsquo;<samp><span class="samp">r1</span></samp>&rsquo;, ... &lsquo;<samp><span class="samp">r31</span></samp>&rsquo;.
Six of the 32 registers can be used as three 16-bit indirect address
register pointers for Data Space addressing. One of the these address
pointers can also be used as an address pointer for look up tables in
Flash program memory. These added function registers are the 16-bit
&lsquo;<samp><span class="samp">X</span></samp>&rsquo;, &lsquo;<samp><span class="samp">Y</span></samp>&rsquo; and &lsquo;<samp><span class="samp">Z</span></samp>&rsquo; - registers.
<pre class="smallexample"> X = <span class="roman">r26:r27</span>
Y = <span class="roman">r28:r29</span>
Z = <span class="roman">r30:r31</span>
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<h3 class="section">7.1 <code>.abort</code></h3>
<p><a name="index-g_t_0040code_007babort_007d-directive-272"></a><a name="index-stopping-the-assembly-273"></a>This directive stops the assembly immediately. It is for
compatibility with other assemblers. The original idea was that the
assembly language source would be piped into the assembler. If the sender
of the source quit, it could use this directive tells <samp><span class="command">as</span></samp> to
quit also. One day <code>.abort</code> will not be supported.
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<a name="Absolute-Literals-Directive"></a>
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<h5 class="subsubsection">9.50.5.7 absolute-literals</h5>
<p><a name="index-g_t_0040code_007babsolute_002dliterals_007d-directive-2329"></a><a name="index-g_t_0040code_007bno_002dabsolute_002dliterals_007d-directive-2330"></a>
The <code>absolute-literals</code> and <code>no-absolute-literals</code>
directives control the absolute vs. PC-relative mode for <code>L32R</code>
instructions. These are relevant only for Xtensa configurations that
include the absolute addressing option for <code>L32R</code> instructions.
<pre class="smallexample"> .begin [no-]absolute-literals
.end [no-]absolute-literals
</pre>
<p>These directives do not change the <code>L32R</code> mode&mdash;they only cause
the assembler to emit the appropriate kind of relocation for <code>L32R</code>
instructions and to place the literal values in the appropriate section.
To change the <code>L32R</code> mode, the program must write the
<code>LITBASE</code> special register. It is the programmer's responsibility
to keep track of the mode and indicate to the assembler which mode is
used in each region of code.
<p>If the Xtensa configuration includes the absolute <code>L32R</code> addressing
option, the default is to assume absolute <code>L32R</code> addressing unless
the &lsquo;<samp><span class="samp">--no-absolute-literals</span></samp>&rsquo; command-line option is specified.
Otherwise, the default is to assume PC-relative <code>L32R</code> addressing.
The <code>absolute-literals</code> directive can then be used to override
the default determined by the command-line options.
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Previous:&nbsp;<a rel="previous" accesskey="p" href="Reporting-Bugs.html#Reporting-Bugs">Reporting Bugs</a>,
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<h2 class="chapter">11 Acknowledgements</h2>
<p>If you have contributed to GAS and your name isn't listed here,
it is not meant as a slight. We just don't know about it. Send mail to the
maintainer, and we'll correct the situation. Currently
<!-- (January 1994), -->
the maintainer is Ken Raeburn (email address <code>raeburn@cygnus.com</code>).
<p>Dean Elsner wrote the original <span class="sc">gnu</span> assembler for the VAX.<a rel="footnote" href="#fn-1" name="fnd-1"><sup>1</sup></a>
<p>Jay Fenlason maintained GAS for a while, adding support for GDB-specific debug
information and the 68k series machines, most of the preprocessing pass, and
extensive changes in <samp><span class="file">messages.c</span></samp>, <samp><span class="file">input-file.c</span></samp>, <samp><span class="file">write.c</span></samp>.
<p>K. Richard Pixley maintained GAS for a while, adding various enhancements and
many bug fixes, including merging support for several processors, breaking GAS
up to handle multiple object file format back ends (including heavy rewrite,
testing, an integration of the coff and b.out back ends), adding configuration
including heavy testing and verification of cross assemblers and file splits
and renaming, converted GAS to strictly ANSI C including full prototypes, added
support for m680[34]0 and cpu32, did considerable work on i960 including a COFF
port (including considerable amounts of reverse engineering), a SPARC opcode
file rewrite, DECstation, rs6000, and hp300hpux host ports, updated &ldquo;know&rdquo;
assertions and made them work, much other reorganization, cleanup, and lint.
<p>Ken Raeburn wrote the high-level BFD interface code to replace most of the code
in format-specific I/O modules.
<p>The original VMS support was contributed by David L. Kashtan. Eric Youngdale
has done much work with it since.
<p>The Intel 80386 machine description was written by Eliot Dresselhaus.
<p>Minh Tran-Le at IntelliCorp contributed some AIX 386 support.
<p>The Motorola 88k machine description was contributed by Devon Bowen of Buffalo
University and Torbjorn Granlund of the Swedish Institute of Computer Science.
<p>Keith Knowles at the Open Software Foundation wrote the original MIPS back end
(<samp><span class="file">tc-mips.c</span></samp>, <samp><span class="file">tc-mips.h</span></samp>), and contributed Rose format support
(which hasn't been merged in yet). Ralph Campbell worked with the MIPS code to
support a.out format.
<p>Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k,
tc-h8300), and IEEE 695 object file format (obj-ieee), was written by
Steve Chamberlain of Cygnus Support. Steve also modified the COFF back end to
use BFD for some low-level operations, for use with the H8/300 and AMD 29k
targets.
<p>John Gilmore built the AMD 29000 support, added <code>.include</code> support, and
simplified the configuration of which versions accept which directives. He
updated the 68k machine description so that Motorola's opcodes always produced
fixed-size instructions (e.g., <code>jsr</code>), while synthetic instructions
remained shrinkable (<code>jbsr</code>). John fixed many bugs, including true tested
cross-compilation support, and one bug in relaxation that took a week and
required the proverbial one-bit fix.
<p>Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax for the
68k, completed support for some COFF targets (68k, i386 SVR3, and SCO Unix),
added support for MIPS ECOFF and ELF targets, wrote the initial RS/6000 and
PowerPC assembler, and made a few other minor patches.
<p>Steve Chamberlain made GAS able to generate listings.
<p>Hewlett-Packard contributed support for the HP9000/300.
<p>Jeff Law wrote GAS and BFD support for the native HPPA object format (SOM)
along with a fairly extensive HPPA testsuite (for both SOM and ELF object
formats). This work was supported by both the Center for Software Science at
the University of Utah and Cygnus Support.
<p>Support for ELF format files has been worked on by Mark Eichin of Cygnus
Support (original, incomplete implementation for SPARC), Pete Hoogenboom and
Jeff Law at the University of Utah (HPPA mainly), Michael Meissner of the Open
Software Foundation (i386 mainly), and Ken Raeburn of Cygnus Support (sparc,
and some initial 64-bit support).
<p>Linas Vepstas added GAS support for the ESA/390 &ldquo;IBM 370&rdquo; architecture.
<p>Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote GAS and BFD
support for openVMS/Alpha.
<p>Timothy Wall, Michael Hayes, and Greg Smart contributed to the various tic*
flavors.
<p>David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from Tensilica,
Inc. added support for Xtensa processors.
<p>Several engineers at Cygnus Support have also provided many small bug fixes and
configuration enhancements.
<p>Jon Beniston added support for the Lattice Mico32 architecture.
<p>Many others have contributed large or small bugfixes and enhancements. If
you have contributed significant work and are not mentioned on this list, and
want to be, let us know. Some of the history has been lost; we are not
intentionally leaving anyone out.
<div class="footnote">
<hr>
<h4>Footnotes</h4><p class="footnote"><small>[<a name="fn-1" href="#fnd-1">1</a>]</small> Any
more details?</p>
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<h3 class="section">7.3 <code>.align </code><var>abs-expr</var><code>, </code><var>abs-expr</var><code>, </code><var>abs-expr</var></h3>
<p><a name="index-padding-the-location-counter-275"></a><a name="index-g_t_0040code_007balign_007d-directive-276"></a>Pad the location counter (in the current subsection) to a particular storage
boundary. The first expression (which must be absolute) is the alignment
required, as described below.
<p>The second expression (also absolute) gives the fill value to be stored in the
padding bytes. It (and the comma) may be omitted. If it is omitted, the
padding bytes are normally zero. However, on some systems, if the section is
marked as containing code and the fill value is omitted, the space is filled
with no-op instructions.
<p>The third expression is also absolute, and is also optional. If it is present,
it is the maximum number of bytes that should be skipped by this alignment
directive. If doing the alignment would require skipping more bytes than the
specified maximum, then the alignment is not done at all. You can omit the
fill value (the second argument) entirely by simply using two commas after the
required alignment; this can be useful if you want the alignment to be filled
with no-op instructions when appropriate.
<p>The way the required alignment is specified varies from system to system.
For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32,
s390, sparc, tic4x, tic80 and xtensa, the first expression is the
alignment request in bytes. For example &lsquo;<samp><span class="samp">.align 8</span></samp>&rsquo; advances
the location counter until it is a multiple of 8. If the location counter
is already a multiple of 8, no change is needed. For the tic54x, the
first expression is the alignment request in words.
<p>For other systems, including ppc, i386 using a.out format, arm and
strongarm, it is the
number of low-order zero bits the location counter must have after
advancement. For example &lsquo;<samp><span class="samp">.align 3</span></samp>&rsquo; advances the location
counter until it a multiple of 8. If the location counter is already a
multiple of 8, no change is needed.
<p>This inconsistency is due to the different behaviors of the various
native assemblers for these systems which GAS must emulate.
GAS also provides <code>.balign</code> and <code>.p2align</code> directives,
described later, which have a consistent behavior across all
architectures (but are specific to GAS).
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<h4 class="subsection">9.2.5 Alpha Assembler Directives</h4>
<p><samp><span class="command">as</span></samp> for the Alpha supports many additional directives for
compatibility with the native assembler. This section describes them only
briefly.
<p><a name="index-Alpha_002donly-directives-575"></a>These are the additional directives in <code>as</code> for the Alpha:
<dl>
<dt><code>.arch </code><var>cpu</var><dd>Specifies the target processor. This is equivalent to the
<samp><span class="option">-m</span><var>cpu</var></samp> command-line option. See <a href="Alpha-Options.html#Alpha-Options">Options</a>,
for a list of values for <var>cpu</var>.
<br><dt><code>.ent </code><var>function</var><code>[, </code><var>n</var><code>]</code><dd>Mark the beginning of <var>function</var>. An optional number may follow for
compatibility with the OSF/1 assembler, but is ignored. When generating
<code>.mdebug</code> information, this will create a procedure descriptor for
the function. In ELF, it will mark the symbol as a function a-la the
generic <code>.type</code> directive.
<br><dt><code>.end </code><var>function</var><dd>Mark the end of <var>function</var>. In ELF, it will set the size of the symbol
a-la the generic <code>.size</code> directive.
<br><dt><code>.mask </code><var>mask</var><code>, </code><var>offset</var><dd>Indicate which of the integer registers are saved in the current
function's stack frame. <var>mask</var> is interpreted a bit mask in which
bit <var>n</var> set indicates that register <var>n</var> is saved. The registers
are saved in a block located <var>offset</var> bytes from the <dfn>canonical
frame address</dfn> (CFA) which is the value of the stack pointer on entry to
the function. The registers are saved sequentially, except that the
return address register (normally <code>$26</code>) is saved first.
<p>This and the other directives that describe the stack frame are
currently only used when generating <code>.mdebug</code> information. They
may in the future be used to generate DWARF2 <code>.debug_frame</code> unwind
information for hand written assembly.
<br><dt><code>.fmask </code><var>mask</var><code>, </code><var>offset</var><dd>Indicate which of the floating-point registers are saved in the current
stack frame. The <var>mask</var> and <var>offset</var> parameters are interpreted
as with <code>.mask</code>.
<br><dt><code>.frame </code><var>framereg</var><code>, </code><var>frameoffset</var><code>, </code><var>retreg</var><code>[, </code><var>argoffset</var><code>]</code><dd>Describes the shape of the stack frame. The frame pointer in use is
<var>framereg</var>; normally this is either <code>$fp</code> or <code>$sp</code>. The
frame pointer is <var>frameoffset</var> bytes below the CFA. The return
address is initially located in <var>retreg</var> until it is saved as
indicated in <code>.mask</code>. For compatibility with OSF/1 an optional
<var>argoffset</var> parameter is accepted and ignored. It is believed to
indicate the offset from the CFA to the saved argument registers.
<br><dt><code>.prologue </code><var>n</var><dd>Indicate that the stack frame is set up and all registers have been
spilled. The argument <var>n</var> indicates whether and how the function
uses the incoming <dfn>procedure vector</dfn> (the address of the called
function) in <code>$27</code>. 0 indicates that <code>$27</code> is not used; 1
indicates that the first two instructions of the function use <code>$27</code>
to perform a load of the GP register; 2 indicates that <code>$27</code> is
used in some non-standard way and so the linker cannot elide the load of
the procedure vector during relaxation.
<br><dt><code>.usepv </code><var>function</var><code>, </code><var>which</var><dd>Used to indicate the use of the <code>$27</code> register, similar to
<code>.prologue</code>, but without the other semantics of needing to
be inside an open <code>.ent</code>/<code>.end</code> block.
<p>The <var>which</var> argument should be either <code>no</code>, indicating that
<code>$27</code> is not used, or <code>std</code>, indicating that the first two
instructions of the function perform a GP load.
<p>One might use this directive instead of <code>.prologue</code> if you are
also using dwarf2 CFI directives.
<br><dt><code>.gprel32 </code><var>expression</var><dd>Computes the difference between the address in <var>expression</var> and the
GP for the current object file, and stores it in 4 bytes. In addition
to being smaller than a full 8 byte address, this also does not require
a dynamic relocation when used in a shared library.
<br><dt><code>.t_floating </code><var>expression</var><dd>Stores <var>expression</var> as an <span class="sc">ieee</span> double precision value.
<br><dt><code>.s_floating </code><var>expression</var><dd>Stores <var>expression</var> as an <span class="sc">ieee</span> single precision value.
<br><dt><code>.f_floating </code><var>expression</var><dd>Stores <var>expression</var> as a VAX F format value.
<br><dt><code>.g_floating </code><var>expression</var><dd>Stores <var>expression</var> as a VAX G format value.
<br><dt><code>.d_floating </code><var>expression</var><dd>Stores <var>expression</var> as a VAX D format value.
<br><dt><code>.set </code><var>feature</var><dd>Enables or disables various assembler features. Using the positive
name of the feature enables while using &lsquo;<samp><span class="samp">no</span><var>feature</var></samp>&rsquo; disables.
<dl>
<dt><code>at</code><dd>Indicates that macro expansions may clobber the <dfn>assembler
temporary</dfn> (<code>$at</code> or <code>$28</code>) register. Some macros may not be
expanded without this and will generate an error message if <code>noat</code>
is in effect. When <code>at</code> is in effect, a warning will be generated
if <code>$at</code> is used by the programmer.
<br><dt><code>macro</code><dd>Enables the expansion of macro instructions. Note that variants of real
instructions, such as <code>br label</code> vs <code>br $31,label</code> are
considered alternate forms and not macros.
<br><dt><code>move</code><dt><code>reorder</code><dt><code>volatile</code><dd>These control whether and how the assembler may re-order instructions.
Accepted for compatibility with the OSF/1 assembler, but <samp><span class="command">as</span></samp>
does not do instruction scheduling, so these features are ignored.
</dl>
</dl>
<p>The following directives are recognized for compatibility with the OSF/1
assembler but are ignored.
<pre class="example"> .proc .aproc
.reguse .livereg
.option .aent
.ugen .eflag
.alias .noalias
</pre>
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<h4 class="subsection">9.2.4 Floating Point</h4>
<p><a name="index-floating-point_002c-Alpha-_0028_0040sc_007bieee_007d_0029-573"></a><a name="index-Alpha-floating-point-_0028_0040sc_007bieee_007d_0029-574"></a>The Alpha family uses both <span class="sc">ieee</span> and VAX floating-point numbers.
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<h4 class="subsection">9.2.1 Notes</h4>
<p><a name="index-Alpha-notes-549"></a><a name="index-notes-for-Alpha-550"></a>
The documentation here is primarily for the ELF object format.
<code>as</code> also supports the ECOFF and EVAX formats, but
features specific to these formats are not yet documented.
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<h4 class="subsection">9.2.6 Opcodes</h4>
<p>For detailed information on the Alpha machine instruction set, see the
<!-- Attempt to work around a very overfull hbox. -->
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<h4 class="subsection">9.2.2 Options</h4>
<p><a name="index-Alpha-options-551"></a><a name="index-options-for-Alpha-552"></a>
<!-- man begin OPTIONS -->
<a name="index-g_t_0040code_007b_002dm_0040var_007bcpu_007d_007d-command-line-option_002c-Alpha-553"></a>
<dl><dt><code>-m</code><var>cpu</var><dd>This option specifies the target processor. If an attempt is made to
assemble an instruction which will not execute on the target processor,
the assembler may either expand the instruction as a macro or issue an
error message. This option is equivalent to the <code>.arch</code> directive.
<p>The following processor names are recognized:
<code>21064</code>,
<code>21064a</code>,
<code>21066</code>,
<code>21068</code>,
<code>21164</code>,
<code>21164a</code>,
<code>21164pc</code>,
<code>21264</code>,
<code>21264a</code>,
<code>21264b</code>,
<code>ev4</code>,
<code>ev5</code>,
<code>lca45</code>,
<code>ev5</code>,
<code>ev56</code>,
<code>pca56</code>,
<code>ev6</code>,
<code>ev67</code>,
<code>ev68</code>.
The special name <code>all</code> may be used to allow the assembler to accept
instructions valid for any Alpha processor.
<p>In order to support existing practice in OSF/1 with respect to <code>.arch</code>,
and existing practice within <samp><span class="command">MILO</span></samp> (the Linux ARC bootloader), the
numbered processor names (e.g. 21064) enable the processor-specific PALcode
instructions, while the &ldquo;electro-vlasic&rdquo; names (e.g. <code>ev4</code>) do not.
<p><a name="index-g_t_0040code_007b_002dmdebug_007d-command-line-option_002c-Alpha-554"></a><a name="index-g_t_0040code_007b_002dno_002dmdebug_007d-command-line-option_002c-Alpha-555"></a><br><dt><code>-mdebug</code><dt><code>-no-mdebug</code><dd>Enables or disables the generation of <code>.mdebug</code> encapsulation for
stabs directives and procedure descriptors. The default is to automatically
enable <code>.mdebug</code> when the first stabs directive is seen.
<p><a name="index-g_t_0040code_007b_002drelax_007d-command-line-option_002c-Alpha-556"></a><br><dt><code>-relax</code><dd>This option forces all relocations to be put into the object file, instead
of saving space and resolving some relocations at assembly time. Note that
this option does not propagate all symbol arithmetic into the object file,
because not all symbol arithmetic can be represented. However, the option
can still be useful in specific applications.
<p><a name="index-g_t_0040code_007b_002dreplace_007d-command-line-option_002c-Alpha-557"></a><a name="index-g_t_0040code_007b_002dnoreplace_007d-command-line-option_002c-Alpha-558"></a><br><dt><code>-replace</code><dt><code>-noreplace</code><dd>Enables or disables the optimization of procedure calls, both at assemblage
and at link time. These options are only available for VMS targets and
<code>-replace</code> is the default. See section 1.4.1 of the OpenVMS Linker
Utility Manual.
<p><a name="index-g_t_0040code_007b_002dg_007d-command-line-option_002c-Alpha-559"></a><br><dt><code>-g</code><dd>This option is used when the compiler generates debug information. When
<samp><span class="command">gcc</span></samp> is using <samp><span class="command">mips-tfile</span></samp> to generate debug
information for ECOFF, local labels must be passed through to the object
file. Otherwise this option has no effect.
<p><a name="index-g_t_0040code_007b_002dG_007d-command-line-option_002c-Alpha-560"></a><br><dt><code>-G</code><var>size</var><dd>A local common symbol larger than <var>size</var> is placed in <code>.bss</code>,
while smaller symbols are placed in <code>.sbss</code>.
<p><a name="index-g_t_0040code_007b_002dF_007d-command-line-option_002c-Alpha-561"></a><a name="index-g_t_0040code_007b_002d32addr_007d-command-line-option_002c-Alpha-562"></a><br><dt><code>-F</code><dt><code>-32addr</code><dd>These options are ignored for backward compatibility.
</dl>
<!-- man end -->
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<h4 class="subsection">9.2.3 Syntax</h4>
<p>The assembler syntax closely follow the Alpha Reference Manual;
assembler directives and general syntax closely follow the OSF/1 and
OpenVMS syntax, with a few differences for ELF.
<ul class="menu">
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<h5 class="subsubsection">9.2.3.1 Special Characters</h5>
<p><a name="index-line-comment-character_002c-Alpha-564"></a><a name="index-Alpha-line-comment-character-565"></a>&lsquo;<samp><span class="samp">#</span></samp>&rsquo; is the line comment character. Note that if &lsquo;<samp><span class="samp">#</span></samp>&rsquo; is the
first character on a line then it can also be a logical line number
directive (see <a href="Comments.html#Comments">Comments</a>) or a preprocessor control
command (see <a href="Preprocessing.html#Preprocessing">Preprocessing</a>).
<p><a name="index-line-separator_002c-Alpha-566"></a><a name="index-statement-separator_002c-Alpha-567"></a><a name="index-Alpha-line-separator-568"></a>&lsquo;<samp><span class="samp">;</span></samp>&rsquo; can be used instead of a newline to separate statements.
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<h3 class="section">9.2 Alpha Dependent Features</h3>
<p><a name="index-Alpha-support-548"></a>
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<h5 class="subsubsection">9.2.3.2 Register Names</h5>
<p><a name="index-Alpha-registers-569"></a><a name="index-register-names_002c-Alpha-570"></a>
The 32 integer registers are referred to as &lsquo;<samp><span class="samp">$</span><var>n</var></samp>&rsquo; or
&lsquo;<samp><span class="samp">$r</span><var>n</var></samp>&rsquo;. In addition, registers 15, 28, 29, and 30 may
be referred to by the symbols &lsquo;<samp><span class="samp">$fp</span></samp>&rsquo;, &lsquo;<samp><span class="samp">$at</span></samp>&rsquo;, &lsquo;<samp><span class="samp">$gp</span></samp>&rsquo;,
and &lsquo;<samp><span class="samp">$sp</span></samp>&rsquo; respectively.
<p>The 32 floating-point registers are referred to as &lsquo;<samp><span class="samp">$f</span><var>n</var></samp>&rsquo;.
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<h5 class="subsubsection">9.2.3.3 Relocations</h5>
<p><a name="index-Alpha-relocations-571"></a><a name="index-relocations_002c-Alpha-572"></a>
Some of these relocations are available for ECOFF, but mostly
only for ELF. They are modeled after the relocation format
introduced in Digital Unix 4.0, but there are additions.
<p>The format is &lsquo;<samp><span class="samp">!</span><var>tag</var></samp>&rsquo; or &lsquo;<samp><span class="samp">!</span><var>tag</var><span class="samp">!</span><var>number</var></samp>&rsquo;
where <var>tag</var> is the name of the relocation. In some cases
<var>number</var> is used to relate specific instructions.
<p>The relocation is placed at the end of the instruction like so:
<pre class="example"> ldah $0,a($29) !gprelhigh
lda $0,a($0) !gprellow
ldq $1,b($29) !literal!100
ldl $2,0($1) !lituse_base!100
</pre>
<dl>
<dt><code>!literal</code><dt><code>!literal!</code><var>N</var><dd>Used with an <code>ldq</code> instruction to load the address of a symbol
from the GOT.
<p>A sequence number <var>N</var> is optional, and if present is used to pair
<code>lituse</code> relocations with this <code>literal</code> relocation. The
<code>lituse</code> relocations are used by the linker to optimize the code
based on the final location of the symbol.
<p>Note that these optimizations are dependent on the data flow of the
program. Therefore, if <em>any</em> <code>lituse</code> is paired with a
<code>literal</code> relocation, then <em>all</em> uses of the register set by
the <code>literal</code> instruction must also be marked with <code>lituse</code>
relocations. This is because the original <code>literal</code> instruction
may be deleted or transformed into another instruction.
<p>Also note that there may be a one-to-many relationship between
<code>literal</code> and <code>lituse</code>, but not a many-to-one. That is, if
there are two code paths that load up the same address and feed the
value to a single use, then the use may not use a <code>lituse</code>
relocation.
<br><dt><code>!lituse_base!</code><var>N</var><dd>Used with any memory format instruction (e.g. <code>ldl</code>) to indicate
that the literal is used for an address load. The offset field of the
instruction must be zero. During relaxation, the code may be altered
to use a gp-relative load.
<br><dt><code>!lituse_jsr!</code><var>N</var><dd>Used with a register branch format instruction (e.g. <code>jsr</code>) to
indicate that the literal is used for a call. During relaxation, the
code may be altered to use a direct branch (e.g. <code>bsr</code>).
<br><dt><code>!lituse_jsrdirect!</code><var>N</var><dd>Similar to <code>lituse_jsr</code>, but also that this call cannot be vectored
through a PLT entry. This is useful for functions with special calling
conventions which do not allow the normal call-clobbered registers to be
clobbered.
<br><dt><code>!lituse_bytoff!</code><var>N</var><dd>Used with a byte mask instruction (e.g. <code>extbl</code>) to indicate
that only the low 3 bits of the address are relevant. During relaxation,
the code may be altered to use an immediate instead of a register shift.
<br><dt><code>!lituse_addr!</code><var>N</var><dd>Used with any other instruction to indicate that the original address
is in fact used, and the original <code>ldq</code> instruction may not be
altered or deleted. This is useful in conjunction with <code>lituse_jsr</code>
to test whether a weak symbol is defined.
<pre class="example"> ldq $27,foo($29) !literal!1
beq $27,is_undef !lituse_addr!1
jsr $26,($27),foo !lituse_jsr!1
</pre>
<br><dt><code>!lituse_tlsgd!</code><var>N</var><dd>Used with a register branch format instruction to indicate that the
literal is the call to <code>__tls_get_addr</code> used to compute the
address of the thread-local storage variable whose descriptor was
loaded with <code>!tlsgd!</code><var>N</var>.
<br><dt><code>!lituse_tlsldm!</code><var>N</var><dd>Used with a register branch format instruction to indicate that the
literal is the call to <code>__tls_get_addr</code> used to compute the
address of the base of the thread-local storage block for the current
module. The descriptor for the module must have been loaded with
<code>!tlsldm!</code><var>N</var>.
<br><dt><code>!gpdisp!</code><var>N</var><dd>Used with <code>ldah</code> and <code>lda</code> to load the GP from the current
address, a-la the <code>ldgp</code> macro. The source register for the
<code>ldah</code> instruction must contain the address of the <code>ldah</code>
instruction. There must be exactly one <code>lda</code> instruction paired
with the <code>ldah</code> instruction, though it may appear anywhere in
the instruction stream. The immediate operands must be zero.
<pre class="example"> bsr $26,foo
ldah $29,0($26) !gpdisp!1
lda $29,0($29) !gpdisp!1
</pre>
<br><dt><code>!gprelhigh</code><dd>Used with an <code>ldah</code> instruction to add the high 16 bits of a
32-bit displacement from the GP.
<br><dt><code>!gprellow</code><dd>Used with any memory format instruction to add the low 16 bits of a
32-bit displacement from the GP.
<br><dt><code>!gprel</code><dd>Used with any memory format instruction to add a 16-bit displacement
from the GP.
<br><dt><code>!samegp</code><dd>Used with any branch format instruction to skip the GP load at the
target address. The referenced symbol must have the same GP as the
source object file, and it must be declared to either not use <code>$27</code>
or perform a standard GP load in the first two instructions via the
<code>.prologue</code> directive.
<br><dt><code>!tlsgd</code><dt><code>!tlsgd!</code><var>N</var><dd>Used with an <code>lda</code> instruction to load the address of a TLS
descriptor for a symbol in the GOT.
<p>The sequence number <var>N</var> is optional, and if present it used to
pair the descriptor load with both the <code>literal</code> loading the
address of the <code>__tls_get_addr</code> function and the <code>lituse_tlsgd</code>
marking the call to that function.
<p>For proper relaxation, both the <code>tlsgd</code>, <code>literal</code> and
<code>lituse</code> relocations must be in the same extended basic block.
That is, the relocation with the lowest address must be executed
first at runtime.
<br><dt><code>!tlsldm</code><dt><code>!tlsldm!</code><var>N</var><dd>Used with an <code>lda</code> instruction to load the address of a TLS
descriptor for the current module in the GOT.
<p>Similar in other respects to <code>tlsgd</code>.
<br><dt><code>!gotdtprel</code><dd>Used with an <code>ldq</code> instruction to load the offset of the TLS
symbol within its module's thread-local storage block. Also known
as the dynamic thread pointer offset or dtp-relative offset.
<br><dt><code>!dtprelhi</code><dt><code>!dtprello</code><dt><code>!dtprel</code><dd>Like <code>gprel</code> relocations except they compute dtp-relative offsets.
<br><dt><code>!gottprel</code><dd>Used with an <code>ldq</code> instruction to load the offset of the TLS
symbol from the thread pointer. Also known as the tp-relative offset.
<br><dt><code>!tprelhi</code><dt><code>!tprello</code><dt><code>!tprel</code><dd>Like <code>gprel</code> relocations except they compute tp-relative offsets.
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<h3 class="section">7.4 <code>.altmacro</code></h3>
<p>Enable alternate macro mode, enabling:
<dl>
<dt><code>LOCAL </code><var>name</var><code> [ , ... ]</code><a name="index-LOCAL-_0040var_007bname_007d-_005b-_002c-_0040dots_007b_007d-_005d-277"></a><dd>One additional directive, <code>LOCAL</code>, is available. It is used to
generate a string replacement for each of the <var>name</var> arguments, and
replace any instances of <var>name</var> in each macro expansion. The
replacement string is unique in the assembly, and different for each
separate macro expansion. <code>LOCAL</code> allows you to write macros that
define symbols, without fear of conflict between separate macro expansions.
<br><dt><code>String delimiters</code><a name="index-String-delimiters-278"></a><dd>You can write strings delimited in these other ways besides
<code>"</code><var>string</var><code>"</code>:
<dl>
<dt><code>'</code><var>string</var><code>'</code><dd>You can delimit strings with single-quote characters.
<br><dt><code>&lt;</code><var>string</var><code>&gt;</code><dd>You can delimit strings with matching angle brackets.
</dl>
<br><dt><code>single-character string escape</code><a name="index-single_002dcharacter-string-escape-279"></a><dd>To include any single character literally in a string (even if the
character would otherwise have some special meaning), you can prefix the
character with &lsquo;<samp><span class="samp">!</span></samp>&rsquo; (an exclamation mark). For example, you can
write &lsquo;<samp><span class="samp">&lt;4.3 !&gt; 5.4!!&gt;</span></samp>&rsquo; to get the literal text &lsquo;<samp><span class="samp">4.3 &gt; 5.4!</span></samp>&rsquo;.
<br><dt><code>Expression results as strings</code><a name="index-Expression-results-as-strings-280"></a><dd>You can write &lsquo;<samp><span class="samp">%</span><var>expr</var></samp>&rsquo; to evaluate the expression <var>expr</var>
and use the result as a string.
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<h4 class="subsection">6.2.1 Arguments</h4>
<p><a name="index-expression-arguments-248"></a><a name="index-arguments-in-expressions-249"></a><a name="index-operands-in-expressions-250"></a><a name="index-arithmetic-operands-251"></a><dfn>Arguments</dfn> are symbols, numbers or subexpressions. In other
contexts arguments are sometimes called &ldquo;arithmetic operands&rdquo;. In
this manual, to avoid confusing them with the &ldquo;instruction operands&rdquo; of
the machine language, we use the term &ldquo;argument&rdquo; to refer to parts of
expressions only, reserving the word &ldquo;operand&rdquo; to refer only to machine
instruction operands.
<p>Symbols are evaluated to yield {<var>section</var> <var>NNN</var>} where
<var>section</var> is one of text, data, bss, absolute,
or undefined. <var>NNN</var> is a signed, 2's complement 32 bit
integer.
<p>Numbers are usually integers.
<p>A number can be a flonum or bignum. In this case, you are warned
that only the low order 32 bits are used, and <samp><span class="command">as</span></samp> pretends
these 32 bits are an integer. You may write integer-manipulating
instructions that act on exotic constants, compatible with other
assemblers.
<p><a name="index-subexpressions-252"></a>Subexpressions are a left parenthesis &lsquo;<samp><span class="samp">(</span></samp>&rsquo; followed by an integer
expression, followed by a right parenthesis &lsquo;<samp><span class="samp">)</span></samp>&rsquo;; or a prefix
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<h3 class="section">4.3 Assembler Internal Sections</h3>
<p><a name="index-internal-assembler-sections-200"></a><a name="index-sections-in-messages_002c-internal-201"></a>These sections are meant only for the internal use of <samp><span class="command">as</span></samp>. They
have no meaning at run-time. You do not really need to know about these
sections for most purposes; but they can be mentioned in <samp><span class="command">as</span></samp>
warning messages, so it might be helpful to have an idea of their
meanings to <samp><span class="command">as</span></samp>. These sections are used to permit the
value of every expression in your assembly language program to be a
section-relative address.
<a name="index-assembler-internal-logic-error-202"></a>
<dl><dt><b>ASSEMBLER-INTERNAL-LOGIC-ERROR!</b><dd>An internal assembler logic error has been found. This means there is a
bug in the assembler.
<p><a name="index-expr-_0028internal-section_0029-203"></a><br><dt><b>expr section</b><dd>The assembler stores complex expression internally as combinations of
symbols. When it needs to represent an expression as a symbol, it puts
it in the expr section.
<!-- FIXME item debug -->
<!-- FIXME item transfer[t] vector preload -->
<!-- FIXME item transfer[t] vector postload -->
<!-- FIXME item register -->
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<h3 class="section">7.5 <code>.ascii "</code><var>string</var><code>"</code><small class="dots">...</small></h3>
<p><a name="index-g_t_0040code_007bascii_007d-directive-281"></a><a name="index-string-literals-282"></a><code>.ascii</code> expects zero or more string literals (see <a href="Strings.html#Strings">Strings</a>)
separated by commas. It assembles each string (with no automatic
trailing zero byte) into consecutive addresses.
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<h3 class="section">7.6 <code>.asciz "</code><var>string</var><code>"</code><small class="dots">...</small></h3>
<p><a name="index-g_t_0040code_007basciz_007d-directive-283"></a><a name="index-zero_002dterminated-strings-284"></a><a name="index-null_002dterminated-strings-285"></a><code>.asciz</code> is just like <code>.ascii</code>, but each string is followed by
a zero byte. The &ldquo;z&rdquo; in &lsquo;<samp><span class="samp">.asciz</span></samp>&rsquo; stands for &ldquo;zero&rdquo;.
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<h3 class="section">7.7 <code>.balign[wl] </code><var>abs-expr</var><code>, </code><var>abs-expr</var><code>, </code><var>abs-expr</var></h3>
<p><a name="index-padding-the-location-counter-given-number-of-bytes-286"></a><a name="index-g_t_0040code_007bbalign_007d-directive-287"></a>Pad the location counter (in the current subsection) to a particular
storage boundary. The first expression (which must be absolute) is the
alignment request in bytes. For example &lsquo;<samp><span class="samp">.balign 8</span></samp>&rsquo; advances
the location counter until it is a multiple of 8. If the location counter
is already a multiple of 8, no change is needed.
<p>The second expression (also absolute) gives the fill value to be stored in the
padding bytes. It (and the comma) may be omitted. If it is omitted, the
padding bytes are normally zero. However, on some systems, if the section is
marked as containing code and the fill value is omitted, the space is filled
with no-op instructions.
<p>The third expression is also absolute, and is also optional. If it is present,
it is the maximum number of bytes that should be skipped by this alignment
directive. If doing the alignment would require skipping more bytes than the
specified maximum, then the alignment is not done at all. You can omit the
fill value (the second argument) entirely by simply using two commas after the
required alignment; this can be useful if you want the alignment to be filled
with no-op instructions when appropriate.
<p><a name="index-g_t_0040code_007bbalignw_007d-directive-288"></a><a name="index-g_t_0040code_007bbalignl_007d-directive-289"></a>The <code>.balignw</code> and <code>.balignl</code> directives are variants of the
<code>.balign</code> directive. The <code>.balignw</code> directive treats the fill
pattern as a two byte word value. The <code>.balignl</code> directives treats the
fill pattern as a four byte longword value. For example, <code>.balignw
4,0x368d</code> will align to a multiple of 4. If it skips two bytes, they will be
filled in with the value 0x368d (the exact placement of the bytes depends upon
the endianness of the processor). If it skips 1 or 3 bytes, the fill value is
undefined.
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<h5 class="subsubsection">3.6.2.2 Bignums</h5>
<p><a name="index-bignums-179"></a><a name="index-constants_002c-bignum-180"></a>A <dfn>bignum</dfn> has the same syntax and semantics as an integer
except that the number (or its negative) takes more than 32 bits to
represent in binary. The distinction is made because in some places
integers are permitted while bignums are not.
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<hr>
</div>
<h4 class="subsection">9.6.3 Directives</h4>
<p><a name="index-Blackfin-directives-735"></a><a name="index-directives_002c-Blackfin-736"></a>
The following directives are provided for compatibility with the VDSP assembler.
<dl>
<dt><code>.byte2</code><dd>Initializes a two byte data object.
<p>This maps to the <code>.short</code> directive.
<br><dt><code>.byte4</code><dd>Initializes a four byte data object.
<p>This maps to the <code>.int</code> directive.
<br><dt><code>.db</code><dd>Initializes a single byte data object.
<p>This directive is a synonym for <code>.byte</code>.
<br><dt><code>.dw</code><dd>Initializes a two byte data object.
<p>This directive is a synonym for <code>.byte2</code>.
<br><dt><code>.dd</code><dd>Initializes a four byte data object.
<p>This directive is a synonym for <code>.byte4</code>.
<br><dt><code>.var</code><dd>Define and initialize a 32 bit data object.
</dl>
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<h4 class="subsection">9.6.1 Options</h4>
<p><a name="index-Blackfin-options-_0028none_0029-727"></a><a name="index-options-for-Blackfin-_0028none_0029-728"></a>
<!-- man begin OPTIONS -->
<a name="index-g_t_0040code_007b_002dmcpu_003d_007d-command-line-option_002c-Blackfin-729"></a>
<dl><dt><code>-mcpu=</code><var>processor</var><span class="roman">[</span><code>-</code><var>sirevision</var><span class="roman">]</span><dd>This option specifies the target processor. The optional <var>sirevision</var>
is not used in assembler. It's here such that GCC can easily pass down its
<code>-mcpu=</code> option. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
recognized:
<code>bf504</code>,
<code>bf506</code>,
<code>bf512</code>,
<code>bf514</code>,
<code>bf516</code>,
<code>bf518</code>,
<code>bf522</code>,
<code>bf523</code>,
<code>bf524</code>,
<code>bf525</code>,
<code>bf526</code>,
<code>bf527</code>,
<code>bf531</code>,
<code>bf532</code>,
<code>bf533</code>,
<code>bf534</code>,
<code>bf535</code> (not implemented yet),
<code>bf536</code>,
<code>bf537</code>,
<code>bf538</code>,
<code>bf539</code>,
<code>bf542</code>,
<code>bf542m</code>,
<code>bf544</code>,
<code>bf544m</code>,
<code>bf547</code>,
<code>bf547m</code>,
<code>bf548</code>,
<code>bf548m</code>,
<code>bf549</code>,
<code>bf549m</code>,
<code>bf561</code>,
and
<code>bf592</code>.
<p><a name="index-g_t_0040code_007b_002dmfdpic_007d-command-line-option_002c-Blackfin-730"></a><br><dt><code>-mfdpic</code><dd>Assemble for the FDPIC ABI.
<p><a name="index-g_t_0040code_007b_002dmno_002dfdpic_007d-command-line-option_002c-Blackfin-731"></a><a name="index-g_t_0040code_007b_002dmnopic_007d-command-line-option_002c-Blackfin-732"></a><br><dt><code>-mno-fdpic</code><dt><code>-mnopic</code><dd>Disable -mfdpic.
</dl>
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<h4 class="subsection">9.6.2 Syntax</h4>
<p><a name="index-Blackfin-syntax-733"></a><a name="index-syntax_002c-Blackfin-734"></a>
<dl>
<dt><code>Special Characters</code><dd>Assembler input is free format and may appear anywhere on the line.
One instruction may extend across multiple lines or more than one
instruction may appear on the same line. White space (space, tab,
comments or newline) may appear anywhere between tokens. A token must
not have embedded spaces. Tokens include numbers, register names,
keywords, user identifiers, and also some multicharacter special
symbols like "+=", "/*" or "||".
<p>Comments are introduced by the &lsquo;<samp><span class="samp">#</span></samp>&rsquo; character and extend to the
end of the current line. If the &lsquo;<samp><span class="samp">#</span></samp>&rsquo; appears as the first
character of a line, the whole line is treated as a comment, but in
this case the line can also be a logical line number directive
(see <a href="Comments.html#Comments">Comments</a>) or a preprocessor control command
(see <a href="Preprocessing.html#Preprocessing">Preprocessing</a>).
<br><dt><code>Instruction Delimiting</code><dd>A semicolon must terminate every instruction. Sometimes a complete
instruction will consist of more than one operation. There are two
cases where this occurs. The first is when two general operations
are combined. Normally a comma separates the different parts, as in
<pre class="smallexample"> a0= r3.h * r2.l, a1 = r3.l * r2.h ;
</pre>
<p>The second case occurs when a general instruction is combined with one
or two memory references for joint issue. The latter portions are
set off by a "||" token.
<pre class="smallexample"> a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
</pre>
<p>Multiple instructions can occur on the same line. Each must be
terminated by a semicolon character.
<br><dt><code>Register Names</code><dd>
The assembler treats register names and instruction keywords in a case
insensitive manner. User identifiers are case sensitive. Thus, R3.l,
R3.L, r3.l and r3.L are all equivalent input to the assembler.
<p>Register names are reserved and may not be used as program identifiers.
<p>Some operations (such as "Move Register") require a register pair.
Register pairs are always data registers and are denoted using a colon,
eg., R3:2. The larger number must be written firsts. Note that the
hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
<p>Some instructions (such as &ndash;SP (Push Multiple)) require a group of
adjacent registers. Adjacent registers are denoted in the syntax by
the range enclosed in parentheses and separated by a colon, eg., (R7:3).
Again, the larger number appears first.
<p>Portions of a particular register may be individually specified. This
is written with a dot (".") following the register name and then a
letter denoting the desired portion. For 32-bit registers, ".H"
denotes the most significant ("High") portion. ".L" denotes the
least-significant portion. The subdivisions of the 40-bit registers
are described later.
<br><dt><code>Accumulators</code><dd>The set of 40-bit registers A1 and A0 that normally contain data that
is being manipulated. Each accumulator can be accessed in four ways.
<dl>
<dt><code>one 40-bit register</code><dd>The register will be referred to as A1 or A0.
<br><dt><code>one 32-bit register</code><dd>The registers are designated as A1.W or A0.W.
<br><dt><code>two 16-bit registers</code><dd>The registers are designated as A1.H, A1.L, A0.H or A0.L.
<br><dt><code>one 8-bit register</code><dd>The registers are designated as A1.X or A0.X for the bits that
extend beyond bit 31.
</dl>
<br><dt><code>Data Registers</code><dd>The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
normally contain data for manipulation. These are abbreviated as
D-register or Dreg. Data registers can be accessed as 32-bit registers
or as two independent 16-bit registers. The least significant 16 bits
of each register is called the "low" half and is designated with ".L"
following the register name. The most significant 16 bits are called
the "high" half and is designated with ".H" following the name.
<pre class="smallexample"> R7.L, r2.h, r4.L, R0.H
</pre>
<br><dt><code>Pointer Registers</code><dd>The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that
normally contain byte addresses of data structures. These are
abbreviated as P-register or Preg.
<pre class="smallexample"> p2, p5, fp, sp
</pre>
<br><dt><code>Stack Pointer SP</code><dd>The stack pointer contains the 32-bit address of the last occupied
byte location in the stack. The stack grows by decrementing the
stack pointer.
<br><dt><code>Frame Pointer FP</code><dd>The frame pointer contains the 32-bit address of the previous frame
pointer in the stack. It is located at the top of a frame.
<br><dt><code>Loop Top</code><dd>LT0 and LT1. These registers contain the 32-bit address of the top of
a zero overhead loop.
<br><dt><code>Loop Count</code><dd>LC0 and LC1. These registers contain the 32-bit counter of the zero
overhead loop executions.
<br><dt><code>Loop Bottom</code><dd>LB0 and LB1. These registers contain the 32-bit address of the bottom
of a zero overhead loop.
<br><dt><code>Index Registers</code><dd>The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
addresses of data structures. Abbreviated I-register or Ireg.
<br><dt><code>Modify Registers</code><dd>The set of 32-bit registers (M0, M1, M2, M3) that normally contain
offset values that are added and subtracted to one of the index
registers. Abbreviated as Mreg.
<br><dt><code>Length Registers</code><dd>The set of 32-bit registers (L0, L1, L2, L3) that normally contain the
length in bytes of the circular buffer. Abbreviated as Lreg. Clear
the Lreg to disable circular addressing for the corresponding Ireg.
<br><dt><code>Base Registers</code><dd>The set of 32-bit registers (B0, B1, B2, B3) that normally contain the
base address in bytes of the circular buffer. Abbreviated as Breg.
<br><dt><code>Floating Point</code><dd>The Blackfin family has no hardware floating point but the .float
directive generates ieee floating point numbers for use with software
floating point libraries.
<br><dt><code>Blackfin Opcodes</code><dd>For detailed information on the Blackfin machine instruction set, see
the Blackfin(r) Processor Instruction Set Reference.
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<h3 class="section">9.6 Blackfin Dependent Features</h3>
<p><a name="index-Blackfin-support-726"></a>
<ul class="menu">
<li><a accesskey="1" href="Blackfin-Options.html#Blackfin-Options">Blackfin Options</a>: Blackfin Options
<li><a accesskey="2" href="Blackfin-Syntax.html#Blackfin-Syntax">Blackfin Syntax</a>: Blackfin Syntax
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<h3 class="section">10.1 Have You Found a Bug?</h3>
<p><a name="index-bug-criteria-2333"></a>
If you are not sure whether you have found a bug, here are some guidelines:
<a name="index-fatal-signal-2334"></a>
<a name="index-assembler-crash-2335"></a>
<a name="index-crash-of-assembler-2336"></a>
<ul><li>If the assembler gets a fatal signal, for any input whatever, that is a
<samp><span class="command">as</span></samp> bug. Reliable assemblers never crash.
<p><a name="index-error-on-valid-input-2337"></a><li>If <samp><span class="command">as</span></samp> produces an error message for valid input, that is a bug.
<p><a name="index-invalid-input-2338"></a><li>If <samp><span class="command">as</span></samp> does not produce an error message for invalid input, that
is a bug. However, you should note that your idea of &ldquo;invalid input&rdquo; might
be our idea of &ldquo;an extension&rdquo; or &ldquo;support for traditional practice&rdquo;.
<li>If you are an experienced user of assemblers, your suggestions for improvement
of <samp><span class="command">as</span></samp> are welcome in any case.
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<h3 class="section">10.2 How to Report Bugs</h3>
<p><a name="index-bug-reports-2339"></a><a name="index-assembler-bugs_002c-reporting-2340"></a>
A number of companies and individuals offer support for <span class="sc">gnu</span> products. If
you obtained <samp><span class="command">as</span></samp> from a support organization, we recommend you
contact that organization first.
<p>You can find contact information for many support companies and
individuals in the file <samp><span class="file">etc/SERVICE</span></samp> in the <span class="sc">gnu</span> Emacs
distribution.
<p>In any event, we also recommend that you send bug reports for <samp><span class="command">as</span></samp>
to <a href="http://www.sourceware.org/bugzilla/">http://www.sourceware.org/bugzilla/</a>.
<p>The fundamental principle of reporting bugs usefully is this:
<strong>report all the facts</strong>. If you are not sure whether to state a
fact or leave it out, state it!
<p>Often people omit facts because they think they know what causes the problem
and assume that some details do not matter. Thus, you might assume that the
name of a symbol you use in an example does not matter. Well, probably it does
not, but one cannot be sure. Perhaps the bug is a stray memory reference which
happens to fetch from the location where that name is stored in memory;
perhaps, if the name were different, the contents of that location would fool
the assembler into doing the right thing despite the bug. Play it safe and
give a specific, complete example. That is the easiest thing for you to do,
and the most helpful.
<p>Keep in mind that the purpose of a bug report is to enable us to fix the bug if
it is new to us. Therefore, always write your bug reports on the assumption
that the bug has not been reported previously.
<p>Sometimes people give a few sketchy facts and ask, &ldquo;Does this ring a
bell?&rdquo; This cannot help us fix a bug, so it is basically useless. We
respond by asking for enough details to enable us to investigate.
You might as well expedite matters by sending them to begin with.
<p>To enable us to fix the bug, you should include all these things:
<ul>
<li>The version of <samp><span class="command">as</span></samp>. <samp><span class="command">as</span></samp> announces it if you start
it with the &lsquo;<samp><span class="samp">--version</span></samp>&rsquo; argument.
<p>Without this, we will not know whether there is any point in looking for
the bug in the current version of <samp><span class="command">as</span></samp>.
<li>Any patches you may have applied to the <samp><span class="command">as</span></samp> source.
<li>The type of machine you are using, and the operating system name and
version number.
<li>What compiler (and its version) was used to compile <samp><span class="command">as</span></samp>&mdash;e.g.
&ldquo;<code>gcc-2.7</code>&rdquo;.
<li>The command arguments you gave the assembler to assemble your example and
observe the bug. To guarantee you will not omit something important, list them
all. A copy of the Makefile (or the output from make) is sufficient.
<p>If we were to try to guess the arguments, we would probably guess wrong
and then we might not encounter the bug.
<li>A complete input file that will reproduce the bug. If the bug is observed when
the assembler is invoked via a compiler, send the assembler source, not the
high level language source. Most compilers will produce the assembler source
when run with the &lsquo;<samp><span class="samp">-S</span></samp>&rsquo; option. If you are using <code>gcc</code>, use
the options &lsquo;<samp><span class="samp">-v --save-temps</span></samp>&rsquo;; this will save the assembler source in a
file with an extension of <samp><span class="file">.s</span></samp>, and also show you exactly how
<samp><span class="command">as</span></samp> is being run.
<li>A description of what behavior you observe that you believe is
incorrect. For example, &ldquo;It gets a fatal signal.&rdquo;
<p>Of course, if the bug is that <samp><span class="command">as</span></samp> gets a fatal signal, then we
will certainly notice it. But if the bug is incorrect output, we might not
notice unless it is glaringly wrong. You might as well not give us a chance to
make a mistake.
<p>Even if the problem you experience is a fatal signal, you should still say so
explicitly. Suppose something strange is going on, such as, your copy of
<samp><span class="command">as</span></samp> is out of sync, or you have encountered a bug in the C
library on your system. (This has happened!) Your copy might crash and ours
would not. If you told us to expect a crash, then when ours fails to crash, we
would know that the bug was not happening for us. If you had not told us to
expect a crash, then we would not be able to draw any conclusion from our
observations.
<li>If you wish to suggest changes to the <samp><span class="command">as</span></samp> source, send us context
diffs, as generated by <code>diff</code> with the &lsquo;<samp><span class="samp">-u</span></samp>&rsquo;, &lsquo;<samp><span class="samp">-c</span></samp>&rsquo;, or &lsquo;<samp><span class="samp">-p</span></samp>&rsquo;
option. Always send diffs from the old file to the new file. If you even
discuss something in the <samp><span class="command">as</span></samp> source, refer to it by context, not
by line number.
<p>The line numbers in our development sources will not match those in your
sources. Your line numbers would convey no useful information to us.
</ul>
<p>Here are some things that are not necessary:
<ul>
<li>A description of the envelope of the bug.
<p>Often people who encounter a bug spend a lot of time investigating
which changes to the input file will make the bug go away and which
changes will not affect it.
<p>This is often time consuming and not very useful, because the way we
will find the bug is by running a single example under the debugger
with breakpoints, not by pure deduction from a series of examples.
We recommend that you save your time for something else.
<p>Of course, if you can find a simpler example to report <em>instead</em>
of the original one, that is a convenience for us. Errors in the
output will be easier to spot, running under the debugger will take
less time, and so on.
<p>However, simplification is not vital; if you do not want to do this,
report the bug anyway and send us the entire test case you used.
<li>A patch for the bug.
<p>A patch for the bug does help us if it is a good one. But do not omit
the necessary information, such as the test case, on the assumption that
a patch is all we need. We might see problems with your patch and decide
to fix the problem another way, or we might not understand it at all.
<p>Sometimes with a program as complicated as <samp><span class="command">as</span></samp> it is very hard to
construct an example that will make the program follow a certain path through
the code. If you do not send us the example, we will not be able to construct
one, so we will not be able to verify that the bug is fixed.
<p>And if we cannot understand what bug you are trying to fix, or why your
patch should be an improvement, we will not install it. A test case will
help us to understand.
<li>A guess about what the bug is or what it depends on.
<p>Such guesses are usually wrong. Even we cannot guess right about such
things without first using the debugger to find the facts.
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<h3 class="section">7.8 <code>.bundle_align_mode </code><var>abs-expr</var></h3>
<p><a name="index-g_t_0040code_007bbundle_005falign_005fmode_007d-directive-290"></a><a name="index-bundle-291"></a><a name="index-instruction-bundle-292"></a><a name="index-aligned-instruction-bundle-293"></a><code>.bundle_align_mode</code> enables or disables <dfn>aligned instruction
bundle</dfn> mode. In this mode, sequences of adjacent instructions are grouped
into fixed-sized <dfn>bundles</dfn>. If the argument is zero, this mode is
disabled (which is the default state). If the argument it not zero, it
gives the size of an instruction bundle as a power of two (as for the
<code>.p2align</code> directive, see <a href="P2align.html#P2align">P2align</a>).
<p>For some targets, it's an ABI requirement that no instruction may span a
certain aligned boundary. A <dfn>bundle</dfn> is simply a sequence of
instructions that starts on an aligned boundary. For example, if
<var>abs-expr</var> is <code>5</code> then the bundle size is 32, so each aligned
chunk of 32 bytes is a bundle. When aligned instruction bundle mode is in
effect, no single instruction may span a boundary between bundles. If an
instruction would start too close to the end of a bundle for the length of
that particular instruction to fit within the bundle, then the space at the
end of that bundle is filled with no-op instructions so the instruction
starts in the next bundle. As a corollary, it's an error if any single
instruction's encoding is longer than the bundle size.
<h3 class="section">7.9 <code>.bundle_lock</code> and <code>.bundle_unlock</code></h3>
<p><a name="index-g_t_0040code_007bbundle_005flock_007d-directive-294"></a><a name="index-g_t_0040code_007bbundle_005funlock_007d-directive-295"></a>The <code>.bundle_lock</code> and directive <code>.bundle_unlock</code> directives
allow explicit control over instruction bundle padding. These directives
are only valid when <code>.bundle_align_mode</code> has been used to enable
aligned instruction bundle mode. It's an error if they appear when
<code>.bundle_align_mode</code> has not been used at all, or when the last
directive was <code>.bundle_align_mode&nbsp;0</code><!-- /@w -->.
<p><a name="index-bundle_002dlocked-296"></a>For some targets, it's an ABI requirement that certain instructions may
appear only as part of specified permissible sequences of multiple
instructions, all within the same bundle. A pair of <code>.bundle_lock</code>
and <code>.bundle_unlock</code> directives define a <dfn>bundle-locked</dfn>
instruction sequence. For purposes of aligned instruction bundle mode, a
sequence starting with <code>.bundle_lock</code> and ending with
<code>.bundle_unlock</code> is treated as a single instruction. That is, the
entire sequence must fit into a single bundle and may not span a bundle
boundary. If necessary, no-op instructions will be inserted before the
first instruction of the sequence so that the whole sequence starts on an
aligned bundle boundary. It's an error if the sequence is longer than the
bundle size.
<p>For convenience when using <code>.bundle_lock</code> and <code>.bundle_unlock</code>
inside assembler macros (see <a href="Macro.html#Macro">Macro</a>), bundle-locked sequences may be
nested. That is, a second <code>.bundle_lock</code> directive before the next
<code>.bundle_unlock</code> directive has no effect except that it must be
matched by another closing <code>.bundle_unlock</code> so that there is the
same number of <code>.bundle_lock</code> and <code>.bundle_unlock</code> directives.
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<h3 class="section">7.10 <code>.byte </code><var>expressions</var></h3>
<p><a name="index-g_t_0040code_007bbyte_007d-directive-297"></a><a name="index-integers_002c-one-byte-298"></a><code>.byte</code> expects zero or more expressions, separated by commas.
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<h3 class="section">7.11 <code>.cfi_sections </code><var>section_list</var></h3>
<p><a name="index-g_t_0040code_007bcfi_005fsections_007d-directive-299"></a><code>.cfi_sections</code> may be used to specify whether CFI directives
should emit <code>.eh_frame</code> section and/or <code>.debug_frame</code> section.
If <var>section_list</var> is <code>.eh_frame</code>, <code>.eh_frame</code> is emitted,
if <var>section_list</var> is <code>.debug_frame</code>, <code>.debug_frame</code> is emitted.
To emit both use <code>.eh_frame, .debug_frame</code>. The default if this
directive is not used is <code>.cfi_sections .eh_frame</code>.
<h3 class="section">7.12 <code>.cfi_startproc [simple]</code></h3>
<p><a name="index-g_t_0040code_007bcfi_005fstartproc_007d-directive-300"></a><code>.cfi_startproc</code> is used at the beginning of each function that
should have an entry in <code>.eh_frame</code>. It initializes some internal
data structures. Don't forget to close the function by
<code>.cfi_endproc</code>.
<p>Unless <code>.cfi_startproc</code> is used along with parameter <code>simple</code>
it also emits some architecture dependent initial CFI instructions.
<h3 class="section">7.13 <code>.cfi_endproc</code></h3>
<p><a name="index-g_t_0040code_007bcfi_005fendproc_007d-directive-301"></a><code>.cfi_endproc</code> is used at the end of a function where it closes its
unwind entry previously opened by
<code>.cfi_startproc</code>, and emits it to <code>.eh_frame</code>.
<h3 class="section">7.14 <code>.cfi_personality </code><var>encoding</var><code> [, </code><var>exp</var><code>]</code></h3>
<p><code>.cfi_personality</code> defines personality routine and its encoding.
<var>encoding</var> must be a constant determining how the personality
should be encoded. If it is 255 (<code>DW_EH_PE_omit</code>), second
argument is not present, otherwise second argument should be
a constant or a symbol name. When using indirect encodings,
the symbol provided should be the location where personality
can be loaded from, not the personality routine itself.
The default after <code>.cfi_startproc</code> is <code>.cfi_personality 0xff</code>,
no personality routine.
<h3 class="section">7.15 <code>.cfi_lsda </code><var>encoding</var><code> [, </code><var>exp</var><code>]</code></h3>
<p><code>.cfi_lsda</code> defines LSDA and its encoding.
<var>encoding</var> must be a constant determining how the LSDA
should be encoded. If it is 255 (<code>DW_EH_PE_omit</code>), second
argument is not present, otherwise second argument should be a constant
or a symbol name. The default after <code>.cfi_startproc</code> is <code>.cfi_lsda 0xff</code>,
no LSDA.
<h3 class="section">7.16 <code>.cfi_def_cfa </code><var>register</var><code>, </code><var>offset</var></h3>
<p><code>.cfi_def_cfa</code> defines a rule for computing CFA as: <i>take
address from </i><var>register</var><i> and add </i><var>offset</var><i> to it</i>.
<h3 class="section">7.17 <code>.cfi_def_cfa_register </code><var>register</var></h3>
<p><code>.cfi_def_cfa_register</code> modifies a rule for computing CFA. From
now on <var>register</var> will be used instead of the old one. Offset
remains the same.
<h3 class="section">7.18 <code>.cfi_def_cfa_offset </code><var>offset</var></h3>
<p><code>.cfi_def_cfa_offset</code> modifies a rule for computing CFA. Register
remains the same, but <var>offset</var> is new. Note that it is the
absolute offset that will be added to a defined register to compute
CFA address.
<h3 class="section">7.19 <code>.cfi_adjust_cfa_offset </code><var>offset</var></h3>
<p>Same as <code>.cfi_def_cfa_offset</code> but <var>offset</var> is a relative
value that is added/substracted from the previous offset.
<h3 class="section">7.20 <code>.cfi_offset </code><var>register</var><code>, </code><var>offset</var></h3>
<p>Previous value of <var>register</var> is saved at offset <var>offset</var> from
CFA.
<h3 class="section">7.21 <code>.cfi_rel_offset </code><var>register</var><code>, </code><var>offset</var></h3>
<p>Previous value of <var>register</var> is saved at offset <var>offset</var> from
the current CFA register. This is transformed to <code>.cfi_offset</code>
using the known displacement of the CFA register from the CFA.
This is often easier to use, because the number will match the
code it's annotating.
<h3 class="section">7.22 <code>.cfi_register </code><var>register1</var><code>, </code><var>register2</var></h3>
<p>Previous value of <var>register1</var> is saved in register <var>register2</var>.
<h3 class="section">7.23 <code>.cfi_restore </code><var>register</var></h3>
<p><code>.cfi_restore</code> says that the rule for <var>register</var> is now the
same as it was at the beginning of the function, after all initial
instruction added by <code>.cfi_startproc</code> were executed.
<h3 class="section">7.24 <code>.cfi_undefined </code><var>register</var></h3>
<p>From now on the previous value of <var>register</var> can't be restored anymore.
<h3 class="section">7.25 <code>.cfi_same_value </code><var>register</var></h3>
<p>Current value of <var>register</var> is the same like in the previous frame,
i.e. no restoration needed.
<h3 class="section">7.26 <code>.cfi_remember_state</code>,</h3>
<p>First save all current rules for all registers by <code>.cfi_remember_state</code>,
then totally screw them up by subsequent <code>.cfi_*</code> directives and when
everything is hopelessly bad, use <code>.cfi_restore_state</code> to restore
the previous saved state.
<h3 class="section">7.27 <code>.cfi_return_column </code><var>register</var></h3>
<p>Change return column <var>register</var>, i.e. the return address is either
directly in <var>register</var> or can be accessed by rules for <var>register</var>.
<h3 class="section">7.28 <code>.cfi_signal_frame</code></h3>
<p>Mark current function as signal trampoline.
<h3 class="section">7.29 <code>.cfi_window_save</code></h3>
<p>SPARC register window has been saved.
<h3 class="section">7.30 <code>.cfi_escape</code> <var>expression</var>[, <small class="dots">...</small>]</h3>
<p>Allows the user to add arbitrary bytes to the unwind info. One
might use this to add OS-specific CFI opcodes, or generic CFI
opcodes that GAS does not yet support.
<h3 class="section">7.31 <code>.cfi_val_encoded_addr </code><var>register</var><code>, </code><var>encoding</var><code>, </code><var>label</var></h3>
<p>The current value of <var>register</var> is <var>label</var>. The value of <var>label</var>
will be encoded in the output file according to <var>encoding</var>; see the
description of <code>.cfi_personality</code> for details on this encoding.
<p>The usefulness of equating a register to a fixed label is probably
limited to the return address register. Here, it can be useful to
mark a code segment that has only one return address which is reached
by a direct branch and no copy of the return address exists in memory
or another register.
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<h4 class="subsection">5.5.4 Symbol Attributes for COFF</h4>
<p><a name="index-COFF-symbol-attributes-235"></a><a name="index-symbol-attributes_002c-COFF-236"></a>
The COFF format supports a multitude of auxiliary symbol attributes;
like the primary symbol attributes, they are set between <code>.def</code> and
<code>.endef</code> directives.
<h5 class="subsubsection">5.5.4.1 Primary Attributes</h5>
<p><a name="index-primary-attributes_002c-COFF-symbols-237"></a>The symbol name is set with <code>.def</code>; the value and type,
respectively, with <code>.val</code> and <code>.type</code>.
<h5 class="subsubsection">5.5.4.2 Auxiliary Attributes</h5>
<p><a name="index-auxiliary-attributes_002c-COFF-symbols-238"></a>The <samp><span class="command">as</span></samp> directives <code>.dim</code>, <code>.line</code>, <code>.scl</code>,
<code>.size</code>, <code>.tag</code>, and <code>.weak</code> can generate auxiliary symbol
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<h4 class="subsection">9.7.1 CR16 Operand Qualifiers</h4>
<p><a name="index-CR16-Operand-Qualifiers-738"></a>
The National Semiconductor CR16 target of <code>as</code> has a few machine dependent operand qualifiers.
<p>Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The <code>@</code> is required. CR16 architecture uses one of the following expression qualifiers:
<dl>
<dt><code>s</code><dd>- <code>Specifies expression operand type as small</code>
<br><dt><code>m</code><dd>- <code>Specifies expression operand type as medium</code>
<br><dt><code>l</code><dd>- <code>Specifies expression operand type as large</code>
<br><dt><code>c</code><dd>- <code>Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.</code>
<br><dt><code>got/GOT</code><dd>- <code>Specifies the CR16 Assembler generates a relocation entry for the operand, offset from Global Offset Table. The linker uses this relocation entry to update the operand address at link time</code>
<br><dt><code>cgot/cGOT</code><dd>- <code>Specifies the CompactRISC Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.</code>
</dl>
<p>CR16 target operand qualifiers and its size (in bits):
<dl>
<dt>&lsquo;<samp><span class="samp">Immediate Operand</span></samp>&rsquo;<dd>- s &mdash;&ndash; 4 bits
<br><dt>&lsquo;<samp></samp>&rsquo;<dd>- m &mdash;&ndash; 16 bits, for movb and movw instructions.
<br><dt>&lsquo;<samp></samp>&rsquo;<dd>- m &mdash;&ndash; 20 bits, movd instructions.
<br><dt>&lsquo;<samp></samp>&rsquo;<dd>- l &mdash;&ndash; 32 bits
<br><dt>&lsquo;<samp><span class="samp">Absolute Operand</span></samp>&rsquo;<dd>- s &mdash;&ndash; Illegal specifier for this operand.
<br><dt>&lsquo;<samp></samp>&rsquo;<dd>- m &mdash;&ndash; 20 bits, movd instructions.
<br><dt>&lsquo;<samp><span class="samp">Displacement Operand</span></samp>&rsquo;<dd>- s &mdash;&ndash; 8 bits
<br><dt>&lsquo;<samp></samp>&rsquo;<dd>- m &mdash;&ndash; 16 bits
<br><dt>&lsquo;<samp></samp>&rsquo;<dd>- l &mdash;&ndash; 24 bits
</dl>
<p>For example:
<pre class="example"> 1 <code>movw $_myfun@c,r1</code>
This loads the address of _myfun, shifted right by 1, into r1.
2 <code>movd $_myfun@c,(r2,r1)</code>
This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
3 <code>_myfun_ptr:</code>
<code>.long _myfun@c</code>
<code>loadd _myfun_ptr, (r1,r0)</code>
<code>jal (r1,r0)</code>
This .long directive, the address of _myfunc, shifted right by 1 at link time.
4 <code>loadd _data1@GOT(r12), (r1,r0)</code>
This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1.
5 <code>loadd _myfunc@cGOT(r12), (r1,r0)</code>
This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.
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<h4 class="subsection">9.7.2 CR16 Syntax</h4>
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<h5 class="subsubsection">9.7.2.1 Special Characters</h5>
<p><a name="index-line-comment-character_002c-CR16-739"></a><a name="index-CR16-line-comment-character-740"></a>The presence of a &lsquo;<samp><span class="samp">#</span></samp>&rsquo; on a line indicates the start of a comment
that extends to the end of the current line. If the &lsquo;<samp><span class="samp">#</span></samp>&rsquo; appears
as the first character of a line, the whole line is treated as a
comment, but in this case the line can also be a logical line number
directive (see <a href="Comments.html#Comments">Comments</a>) or a preprocessor control command
(see <a href="Preprocessing.html#Preprocessing">Preprocessing</a>).
<p><a name="index-line-separator_002c-CR16-741"></a><a name="index-statement-separator_002c-CR16-742"></a><a name="index-CR16-line-separator-743"></a>The &lsquo;<samp><span class="samp">;</span></samp>&rsquo; character can be used to separate statements on the same
line.
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<h3 class="section">9.7 CR16 Dependent Features</h3>
<p><a name="index-CR16-support-737"></a>
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<h5 class="subsubsection">9.8.4.1 Special Characters</h5>
<p><a name="index-line-comment-characters_002c-CRIS-775"></a><a name="index-CRIS-line-comment-characters-776"></a>
The character &lsquo;<samp><span class="samp">#</span></samp>&rsquo; is a line comment character. It starts a
comment if and only if it is placed at the beginning of a line.
<p>A &lsquo;<samp><span class="samp">;</span></samp>&rsquo; character starts a comment anywhere on the line,
causing all characters up to the end of the line to be ignored.
<p>A &lsquo;<samp><span class="samp">@</span></samp>&rsquo; character is handled as a line separator equivalent
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<h3 class="section">9.8 CRIS Dependent Features</h3>
<p><a name="index-CRIS-support-744"></a>
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<li><a accesskey="1" href="CRIS_002dOpts.html#CRIS_002dOpts">CRIS-Opts</a>: Command-line Options
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<h4 class="subsection">9.8.2 Instruction expansion</h4>
<p><a name="index-instruction-expansion_002c-CRIS-769"></a><a name="index-CRIS-instruction-expansion-770"></a><code>as</code> will silently choose an instruction that fits
the operand size for &lsquo;<samp><span class="samp">[register+constant]</span></samp>&rsquo; operands. For
example, the offset <code>127</code> in <code>move.d [r3+127],r4</code> fits
in an instruction using a signed-byte offset. Similarly,
<code>move.d [r2+32767],r1</code> will generate an instruction using a
16-bit offset. For symbolic expressions and constants that do
not fit in 16 bits including the sign bit, a 32-bit offset is
generated.
<p>For branches, <code>as</code> will expand from a 16-bit branch
instruction into a sequence of instructions that can reach a
full 32-bit address. Since this does not correspond to a single
instruction, such expansions can optionally be warned about.
See <a href="CRIS_002dOpts.html#CRIS_002dOpts">CRIS-Opts</a>.
<p>If the operand is found to fit the range, a <code>lapc</code> mnemonic
will translate to a <code>lapcq</code> instruction. Use <code>lapc.d</code>
to force the 32-bit <code>lapc</code> instruction.
<p>Similarly, the <code>addo</code> mnemonic will translate to the
shortest fitting instruction of <code>addoq</code>, <code>addo.w</code> and
<code>addo.d</code>, when used with a operand that is a constant known
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<h4 class="subsection">9.8.1 Command-line Options</h4>
<p><a name="index-options_002c-CRIS-745"></a><a name="index-CRIS-options-746"></a>The CRIS version of <code>as</code> has these
machine-dependent command-line options.
<p><a name="index-g_t_0040option_007b_002d_002demulation_003dcriself_007d-command-line-option_002c-CRIS-747"></a><a name="index-g_t_0040option_007b_002d_002demulation_003dcrisaout_007d-command-line-option_002c-CRIS-748"></a><a name="index-CRIS-_0040option_007b_002d_002demulation_003dcriself_007d-command-line-option-749"></a><a name="index-CRIS-_0040option_007b_002d_002demulation_003dcrisaout_007d-command-line-option-750"></a>
The format of the generated object files can be either ELF or
a.out, specified by the command-line options
<samp><span class="option">--emulation=crisaout</span></samp> and <samp><span class="option">--emulation=criself</span></samp>.
The default is ELF (criself), unless <code>as</code> has been
configured specifically for a.out by using the configuration
name <code>cris-axis-aout</code>.
<p><a name="index-g_t_0040option_007b_002d_002dunderscore_007d-command-line-option_002c-CRIS-751"></a><a name="index-g_t_0040option_007b_002d_002dno_002dunderscore_007d-command-line-option_002c-CRIS-752"></a><a name="index-CRIS-_0040option_007b_002d_002dunderscore_007d-command-line-option-753"></a><a name="index-CRIS-_0040option_007b_002d_002dno_002dunderscore_007d-command-line-option-754"></a>There are two different link-incompatible ELF object file
variants for CRIS, for use in environments where symbols are
expected to be prefixed by a leading &lsquo;<samp><span class="samp">_</span></samp>&rsquo; character and for
environments without such a symbol prefix. The variant used for
GNU/Linux port has no symbol prefix. Which variant to produce
is specified by either of the options <samp><span class="option">--underscore</span></samp> and
<samp><span class="option">--no-underscore</span></samp>. The default is <samp><span class="option">--underscore</span></samp>.
Since symbols in CRIS a.out objects are expected to have a
&lsquo;<samp><span class="samp">_</span></samp>&rsquo; prefix, specifying <samp><span class="option">--no-underscore</span></samp> when
generating a.out objects is an error. Besides the object format
difference, the effect of this option is to parse register names
differently (see <a href="crisnous.html#crisnous">crisnous</a>). The <samp><span class="option">--no-underscore</span></samp>
option makes a &lsquo;<samp><span class="samp">$</span></samp>&rsquo; register prefix mandatory.
<p><a name="index-g_t_0040option_007b_002d_002dpic_007d-command-line-option_002c-CRIS-755"></a><a name="index-CRIS-_0040option_007b_002d_002dpic_007d-command-line-option-756"></a><a name="index-Position_002dindependent-code_002c-CRIS-757"></a><a name="index-CRIS-position_002dindependent-code-758"></a>The option <samp><span class="option">--pic</span></samp> must be passed to <code>as</code> in
order to recognize the symbol syntax used for ELF (SVR4 PIC)
position-independent-code (see <a href="crispic.html#crispic">crispic</a>). This will also
affect expansion of instructions. The expansion with
<samp><span class="option">--pic</span></samp> will use PC-relative rather than (slightly
faster) absolute addresses in those expansions. This option is only
valid when generating ELF format object files.
<p><a name="index-g_t_0040option_007b_002d_002dmarch_003d_0040var_007barchitecture_007d_007d-command-line-option_002c-CRIS-759"></a><a name="index-CRIS-_0040option_007b_002d_002dmarch_003d_0040var_007barchitecture_007d_007d-command-line-option-760"></a><a name="index-Architecture-variant-option_002c-CRIS-761"></a><a name="index-CRIS-architecture-variant-option-762"></a>The option <samp><span class="option">--march=</span><var>architecture</var></samp>
<a name="march_002doption"></a>specifies the recognized instruction set
and recognized register names. It also controls the
architecture type of the object file. Valid values for
<var>architecture</var> are:
<dl>
<dt><code>v0_v10</code><dd>All instructions and register names for any architecture variant
in the set v0<small class="dots">...</small>v10 are recognized. This is the
default if the target is configured as cris-*.
<br><dt><code>v10</code><dd>Only instructions and register names for CRIS v10 (as found in
ETRAX 100 LX) are recognized. This is the default if the target
is configured as crisv10-*.
<br><dt><code>v32</code><dd>Only instructions and register names for CRIS v32 (code name
Guinness) are recognized. This is the default if the target is
configured as crisv32-*. This value implies
<samp><span class="option">--no-mul-bug-abort</span></samp>. (A subsequent
<samp><span class="option">--mul-bug-abort</span></samp> will turn it back on.)
<br><dt><code>common_v10_v32</code><dd>Only instructions with register names and addressing modes with
opcodes common to the v10 and v32 are recognized.
</dl>
<p><a name="index-g_t_0040option_007b_002dN_007d-command-line-option_002c-CRIS-763"></a><a name="index-CRIS-_0040option_007b_002dN_007d-command-line-option-764"></a>When <samp><span class="option">-N</span></samp> is specified, <code>as</code> will emit a
warning when a 16-bit branch instruction is expanded into a
32-bit multiple-instruction construct (see <a href="CRIS_002dExpand.html#CRIS_002dExpand">CRIS-Expand</a>).
<p><a name="index-g_t_0040option_007b_002d_002dno_002dmul_002dbug_002dabort_007d-command-line-option_002c-CRIS-765"></a><a name="index-g_t_0040option_007b_002d_002dmul_002dbug_002dabort_007d-command-line-option_002c-CRIS-766"></a><a name="index-CRIS-_0040option_007b_002d_002dno_002dmul_002dbug_002dabort_007d-command-line-option-767"></a><a name="index-CRIS-_0040option_007b_002d_002dmul_002dbug_002dabort_007d-command-line-option-768"></a>
Some versions of the CRIS v10, for example in the Etrax 100 LX,
contain a bug that causes destabilizing memory accesses when a
multiply instruction is executed with certain values in the
first operand just before a cache-miss. When the
<samp><span class="option">--mul-bug-abort</span></samp> command line option is active (the
default value), <code>as</code> will refuse to assemble a file
containing a multiply instruction at a dangerous offset, one
that could be the last on a cache-line, or is in a section with
insufficient alignment. This placement checking does not catch
any case where the multiply instruction is dangerously placed
because it is located in a delay-slot. The
<samp><span class="option">--mul-bug-abort</span></samp> command line option turns off the
checking.
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<h5 class="subsubsection">9.8.4.2 Symbols in position-independent code</h5>
<p><a name="index-Symbols-in-position_002dindependent-code_002c-CRIS-777"></a><a name="index-CRIS-symbols-in-position_002dindependent-code-778"></a><a name="index-Position_002dindependent-code_002c-symbols-in_002c-CRIS-779"></a>
When generating <a name="crispic"></a>position-independent code (SVR4
PIC) for use in cris-axis-linux-gnu or crisv32-axis-linux-gnu
shared libraries, symbol
suffixes are used to specify what kind of run-time symbol lookup
will be used, expressed in the object as different
<em>relocation types</em>. Usually, all absolute symbol values
must be located in a table, the <em>global offset table</em>,
leaving the code position-independent; independent of values of
global symbols and independent of the address of the code. The
suffix modifies the value of the symbol, into for example an
index into the global offset table where the real symbol value
is entered, or a PC-relative value, or a value relative to the
start of the global offset table. All symbol suffixes start
with the character &lsquo;<samp><span class="samp">:</span></samp>&rsquo; (omitted in the list below). Every
symbol use in code or a read-only section must therefore have a
PIC suffix to enable a useful shared library to be created.
Usually, these constructs must not be used with an additive
constant offset as is usually allowed, i.e. no 4 as in
<code>symbol + 4</code> is allowed. This restriction is checked at
link-time, not at assembly-time.
<dl>
<dt><code>GOT</code><dd>
Attaching this suffix to a symbol in an instruction causes the
symbol to be entered into the global offset table. The value is
a 32-bit index for that symbol into the global offset table.
The name of the corresponding relocation is
&lsquo;<samp><span class="samp">R_CRIS_32_GOT</span></samp>&rsquo;. Example: <code>move.d
[$r0+extsym:GOT],$r9</code>
<br><dt><code>GOT16</code><dd>
Same as for &lsquo;<samp><span class="samp">GOT</span></samp>&rsquo;, but the value is a 16-bit index into the
global offset table. The corresponding relocation is
&lsquo;<samp><span class="samp">R_CRIS_16_GOT</span></samp>&rsquo;. Example: <code>move.d
[$r0+asymbol:GOT16],$r10</code>
<br><dt><code>PLT</code><dd>
This suffix is used for function symbols. It causes a
<em>procedure linkage table</em>, an array of code stubs, to be
created at the time the shared object is created or linked
against, together with a global offset table entry. The value
is a pc-relative offset to the corresponding stub code in the
procedure linkage table. This arrangement causes the run-time
symbol resolver to be called to look up and set the value of the
symbol the first time the function is called (at latest;
depending environment variables). It is only safe to leave the
symbol unresolved this way if all references are function calls.
The name of the relocation is &lsquo;<samp><span class="samp">R_CRIS_32_PLT_PCREL</span></samp>&rsquo;.
Example: <code>add.d fnname:PLT,$pc</code>
<br><dt><code>PLTG</code><dd>
Like PLT, but the value is relative to the beginning of the
global offset table. The relocation is
&lsquo;<samp><span class="samp">R_CRIS_32_PLT_GOTREL</span></samp>&rsquo;. Example: <code>move.d
fnname:PLTG,$r3</code>
<br><dt><code>GOTPLT</code><dd>
Similar to &lsquo;<samp><span class="samp">PLT</span></samp>&rsquo;, but the value of the symbol is a 32-bit
index into the global offset table. This is somewhat of a mix
between the effect of the &lsquo;<samp><span class="samp">GOT</span></samp>&rsquo; and the &lsquo;<samp><span class="samp">PLT</span></samp>&rsquo; suffix;
the difference to &lsquo;<samp><span class="samp">GOT</span></samp>&rsquo; is that there will be a procedure
linkage table entry created, and that the symbol is assumed to
be a function entry and will be resolved by the run-time
resolver as with &lsquo;<samp><span class="samp">PLT</span></samp>&rsquo;. The relocation is
&lsquo;<samp><span class="samp">R_CRIS_32_GOTPLT</span></samp>&rsquo;. Example: <code>jsr
[$r0+fnname:GOTPLT]</code>
<br><dt><code>GOTPLT16</code><dd>
A variant of &lsquo;<samp><span class="samp">GOTPLT</span></samp>&rsquo; giving a 16-bit value. Its
relocation name is &lsquo;<samp><span class="samp">R_CRIS_16_GOTPLT</span></samp>&rsquo;. Example: <code>jsr
[$r0+fnname:GOTPLT16]</code>
<br><dt><code>GOTOFF</code><dd>
This suffix must only be attached to a local symbol, but may be
used in an expression adding an offset. The value is the
address of the symbol relative to the start of the global offset
table. The relocation name is &lsquo;<samp><span class="samp">R_CRIS_32_GOTREL</span></samp>&rsquo;.
Example: <code>move.d [$r0+localsym:GOTOFF],r3</code>
</dl>
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Previous:&nbsp;<a rel="previous" accesskey="p" href="CRIS_002dRegs.html#CRIS_002dRegs">CRIS-Regs</a>,
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<h5 class="subsubsection">9.8.4.4 Assembler Directives</h5>
<p><a name="index-assembler-directives_002c-CRIS-782"></a><a name="index-pseudo_002dops_002c-CRIS-783"></a><a name="index-CRIS-assembler-directives-784"></a><a name="index-CRIS-pseudo_002dops-785"></a>
There are a few CRIS-specific pseudo-directives in addition to
the generic ones. See <a href="Pseudo-Ops.html#Pseudo-Ops">Pseudo Ops</a>. Constants emitted by
pseudo-directives are in little-endian order for CRIS. There is
no support for floating-point-specific directives for CRIS.
<dl>
<dt><code>.dword EXPRESSIONS</code><dd><a name="index-assembler-directive-_002edword_002c-CRIS-786"></a><a name="index-pseudo_002dop-_002edword_002c-CRIS-787"></a><a name="index-CRIS-assembler-directive-_002edword-788"></a><a name="index-CRIS-pseudo_002dop-_002edword-789"></a>
The <code>.dword</code> directive is a synonym for <code>.int</code>,
expecting zero or more EXPRESSIONS, separated by commas. For
each expression, a 32-bit little-endian constant is emitted.
<br><dt><code>.syntax ARGUMENT</code><dd><a name="index-assembler-directive-_002esyntax_002c-CRIS-790"></a><a name="index-pseudo_002dop-_002esyntax_002c-CRIS-791"></a><a name="index-CRIS-assembler-directive-_002esyntax-792"></a><a name="index-CRIS-pseudo_002dop-_002esyntax-793"></a>The <code>.syntax</code> directive takes as <var>ARGUMENT</var> one of the
following case-sensitive choices.
<dl>
<dt><code>no_register_prefix</code><dd>
The <code>.syntax no_register_prefix</code> <a name="crisnous"></a>directive
makes a &lsquo;<samp><span class="samp">$</span></samp>&rsquo; character prefix on all registers optional. It
overrides a previous setting, including the corresponding effect
of the option <samp><span class="option">--no-underscore</span></samp>. If this directive is
used when ordinary symbols do not have a &lsquo;<samp><span class="samp">_</span></samp>&rsquo; character
prefix, care must be taken to avoid ambiguities whether an
operand is a register or a symbol; using symbols with names the
same as general or special registers then invoke undefined
behavior.
<br><dt><code>register_prefix</code><dd>
This directive makes a &lsquo;<samp><span class="samp">$</span></samp>&rsquo; character prefix on all
registers mandatory. It overrides a previous setting, including
the corresponding effect of the option <samp><span class="option">--underscore</span></samp>.
<br><dt><code>leading_underscore</code><dd>
This is an assertion directive, emitting an error if the
<samp><span class="option">--no-underscore</span></samp> option is in effect.
<br><dt><code>no_leading_underscore</code><dd>
This is the opposite of the <code>.syntax leading_underscore</code>
directive and emits an error if the option <samp><span class="option">--underscore</span></samp>
is in effect.
</dl>
<br><dt><code>.arch ARGUMENT</code><dd><a name="index-assembler-directive-_002earch_002c-CRIS-794"></a><a name="index-pseudo_002dop-_002earch_002c-CRIS-795"></a><a name="index-CRIS-assembler-directive-_002earch-796"></a><a name="index-CRIS-pseudo_002dop-_002earch-797"></a>This is an assertion directive, giving an error if the specified
<var>ARGUMENT</var> is not the same as the specified or default value
for the <samp><span class="option">--march=</span><var>architecture</var></samp> option
(see <a href="march_002doption.html#march_002doption">march-option</a>).
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</dl>
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<h5 class="subsubsection">9.8.4.3 Register names</h5>
<p><a name="index-register-names_002c-CRIS-780"></a><a name="index-CRIS-register-names-781"></a>
A &lsquo;<samp><span class="samp">$</span></samp>&rsquo; character may always prefix a general or special
register name in an instruction operand but is mandatory when
the option <samp><span class="option">--no-underscore</span></samp> is specified or when the
<code>.syntax register_prefix</code> directive is in effect
(see <a href="crisnous.html#crisnous">crisnous</a>). Register names are case-insensitive.
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<a name="CRIS_002dSymbols"></a>
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Previous:&nbsp;<a rel="previous" accesskey="p" href="CRIS_002dExpand.html#CRIS_002dExpand">CRIS-Expand</a>,
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<h4 class="subsection">9.8.3 Symbols</h4>
<p><a name="index-Symbols_002c-built_002din_002c-CRIS-771"></a><a name="index-Symbols_002c-CRIS_002c-built_002din-772"></a><a name="index-CRIS-built_002din-symbols-773"></a><a name="index-Built_002din-symbols_002c-CRIS-774"></a>
Some symbols are defined by the assembler. They're intended to
be used in conditional assembly, for example:
<pre class="smallexample"> .if ..asm.arch.cris.v32
<var>code for CRIS v32</var>
.elseif ..asm.arch.cris.common_v10_v32
<var>code common to CRIS v32 and CRIS v10</var>
.elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
<var>code for v10</var>
.else
.error "Code needs to be added here."
.endif
</pre>
<p>These symbols are defined in the assembler, reflecting
command-line options, either when specified or the default.
They are always defined, to 0 or 1.
<dl>
<dt><code>..asm.arch.cris.any_v0_v10</code><dd>This symbol is non-zero when <samp><span class="option">--march=v0_v10</span></samp> is specified
or the default.
<br><dt><code>..asm.arch.cris.common_v10_v32</code><dd>Set according to the option <samp><span class="option">--march=common_v10_v32</span></samp>.
<br><dt><code>..asm.arch.cris.v10</code><dd>Reflects the option <samp><span class="option">--march=v10</span></samp>.
<br><dt><code>..asm.arch.cris.v32</code><dd>Corresponds to <samp><span class="option">--march=v10</span></samp>.
</dl>
<p>Speaking of symbols, when a symbol is used in code, it can have
a suffix modifying its value for use in position-independent
code. See <a href="CRIS_002dPic.html#CRIS_002dPic">CRIS-Pic</a>.
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<h4 class="subsection">9.8.4 Syntax</h4>
<p>There are different aspects of the CRIS assembly syntax.
<ul class="menu">
<li><a accesskey="1" href="CRIS_002dChars.html#CRIS_002dChars">CRIS-Chars</a>: Special Characters
<li><a accesskey="2" href="CRIS_002dPic.html#CRIS_002dPic">CRIS-Pic</a>: Position-Independent Code Symbols
<li><a accesskey="3" href="CRIS_002dRegs.html#CRIS_002dRegs">CRIS-Regs</a>: Register Names
<li><a accesskey="4" href="CRIS_002dPseudos.html#CRIS_002dPseudos">CRIS-Pseudos</a>: Assembler Directives
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