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motify compile link error

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motify compile link error
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ant 2016-09-18 09:03:25 +08:00
parent 923914edae
commit 03e74a8e50
5418 changed files with 1367914 additions and 206149 deletions
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582
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c
View file

@ -1,291 +1,291 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_gdma.h"
#include "hal_gdma.h"
#ifndef CONFIG_CHIP_E_CUT
BOOL
HalGdmaChBlockSetingRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pGdmaChLli;
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 ChEn = pHalGdmaAdapter->ChEn;
u8 GdmaChIsrBitmap = (ChEn & 0xFF);
u8 PendingIsrIndex;
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
//4 1) Check chanel is avaliable
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
//4 Disable Channel
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
HalGdmaChDisRtl8195a(Data);
}
//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
u32 PendRaw, PendStstus;
PendRaw = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
PendStstus = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
//4 Clear Pending Isr
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
(PendStstus & (GdmaChIsrBitmap))
);
}
}
//4 Fill in SARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChSar)
);
//4 Fill in DARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChDar)
);
//4 3) Process CTLx
CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
//4 Clear Config low register bits
CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
BIT_INVC_CTLX_LO_DST_TR_WIDTH &
BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
BIT_INVC_CTLX_LO_DINC &
BIT_INVC_CTLX_LO_SINC &
BIT_INVC_CTLX_LO_DEST_MSIZE &
BIT_INVC_CTLX_LO_SRC_MSIZE &
BIT_INVC_CTLX_LO_TT_FC &
BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
//4 Clear Config upper register bits
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
BIT_INVC_CTLX_UP_DONE);
CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
CtlxLow;
CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
CtlxUp;
//4 Fill in CTLx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
CtlxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
CtlxUp
);
//4 4) Program CFGx
CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
BIT_INVC_CFGX_LO_CH_SUSP &
BIT_INVC_CFGX_LO_HS_SEL_DST &
BIT_INVC_CFGX_LO_HS_SEL_SRC &
BIT_INVC_CFGX_LO_LOCK_CH_L &
BIT_INVC_CFGX_LO_LOCK_B_L &
BIT_INVC_CFGX_LO_LOCK_CH &
BIT_INVC_CFGX_LO_LOCK_B &
BIT_INVC_CFGX_LO_RELOAD_SRC &
BIT_INVC_CFGX_LO_RELOAD_DST);
CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
BIT_INVC_CFGX_UP_DS_UPD_EN &
BIT_INVC_CFGX_UP_SS_UPD_EN &
BIT_INVC_CFGX_UP_SRC_PER &
BIT_INVC_CFGX_UP_DEST_PER);
CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
CfgxLow;
CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
CfgxUp;
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
CfgxUp
);
//4 Check 4 Bytes Alignment
if ((u32)(pLliEle) & 0x3) {
DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n",
pHalGdmaAdapter->pLli);
return _FALSE;
}
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
pLliEle
);
//4 Update the first llp0
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
while (MultiBlockCount > 1) {
MultiBlockCount--;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pLliEle = pGdmaChLli->pLliEle;
if (NULL == pLliEle) {
DBG_GDMA_ERR("pLliEle Null Point!!!!!\n");
return _FALSE;
}
//4 Clear the last element llp enable bit
if (1 == MultiBlockCount) {
if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 1){
CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
}
}
//4 Update block size for transfer
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
//4 Update tje Lli and Block size list point to next llp
pGdmaChLli = pGdmaChLli->pNextLli;
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
//4 Updatethe Llpx context
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
}
return _TRUE;
}
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
if (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN) & (pHalGdmaAdapter->ChEn)) {
return 1;
} else {
return 0;
}
}
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_gdma.h"
#include "hal_gdma.h"
#ifndef CONFIG_CHIP_E_CUT
BOOL
HalGdmaChBlockSetingRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pGdmaChLli;
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 ChEn = pHalGdmaAdapter->ChEn;
u8 GdmaChIsrBitmap = (ChEn & 0xFF);
u8 PendingIsrIndex;
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
//4 1) Check chanel is avaliable
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
//4 Disable Channel
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
HalGdmaChDisRtl8195a(Data);
}
//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
u32 PendRaw, PendStstus;
PendRaw = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
PendStstus = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
//4 Clear Pending Isr
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
(PendStstus & (GdmaChIsrBitmap))
);
}
}
//4 Fill in SARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChSar)
);
//4 Fill in DARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChDar)
);
//4 3) Process CTLx
CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
//4 Clear Config low register bits
CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
BIT_INVC_CTLX_LO_DST_TR_WIDTH &
BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
BIT_INVC_CTLX_LO_DINC &
BIT_INVC_CTLX_LO_SINC &
BIT_INVC_CTLX_LO_DEST_MSIZE &
BIT_INVC_CTLX_LO_SRC_MSIZE &
BIT_INVC_CTLX_LO_TT_FC &
BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
//4 Clear Config upper register bits
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
BIT_INVC_CTLX_UP_DONE);
CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
CtlxLow;
CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
CtlxUp;
//4 Fill in CTLx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
CtlxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
CtlxUp
);
//4 4) Program CFGx
CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
BIT_INVC_CFGX_LO_CH_SUSP &
BIT_INVC_CFGX_LO_HS_SEL_DST &
BIT_INVC_CFGX_LO_HS_SEL_SRC &
BIT_INVC_CFGX_LO_LOCK_CH_L &
BIT_INVC_CFGX_LO_LOCK_B_L &
BIT_INVC_CFGX_LO_LOCK_CH &
BIT_INVC_CFGX_LO_LOCK_B &
BIT_INVC_CFGX_LO_RELOAD_SRC &
BIT_INVC_CFGX_LO_RELOAD_DST);
CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
BIT_INVC_CFGX_UP_DS_UPD_EN &
BIT_INVC_CFGX_UP_SS_UPD_EN &
BIT_INVC_CFGX_UP_SRC_PER &
BIT_INVC_CFGX_UP_DEST_PER);
CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
CfgxLow;
CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
CfgxUp;
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
CfgxUp
);
//4 Check 4 Bytes Alignment
if ((u32)(pLliEle) & 0x3) {
DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n",
pHalGdmaAdapter->pLli);
return _FALSE;
}
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
pLliEle
);
//4 Update the first llp0
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
while (MultiBlockCount > 1) {
MultiBlockCount--;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pLliEle = pGdmaChLli->pLliEle;
if (NULL == pLliEle) {
DBG_GDMA_ERR("pLliEle Null Point!!!!!\n");
return _FALSE;
}
//4 Clear the last element llp enable bit
if (1 == MultiBlockCount) {
if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 1){
CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
}
}
//4 Update block size for transfer
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
//4 Update tje Lli and Block size list point to next llp
pGdmaChLli = pGdmaChLli->pNextLli;
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
//4 Updatethe Llpx context
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
}
return _TRUE;
}
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
if (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN) & (pHalGdmaAdapter->ChEn)) {
return 1;
} else {
return 0;
}
}
#endif

718
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c
View file

@ -1,359 +1,359 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_pcm.h"
#include "hal_pcm.h"
extern void *
_memset( void *s, int c, SIZE_T n );
VOID
HalPcmOnOffRtl8195a (
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
//todo on off pcm
}
//default sampling rate 8khz, linear, 10ms frame size, time slot 0 , tx+rx
// master mode, enable endian swap
// Question: need local tx/rx page?
BOOL
HalPcmInitRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
_memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER));
//4 1) Initial PcmChCNR03 Register
pHalPcmAdapter->PcmChCNR03.CH0MuA = 0;
pHalPcmAdapter->PcmChCNR03.CH0Band = 0;
//4 1) Initial PcmTSR03 Register
pHalPcmAdapter->PcmTSR03.CH0TSA = 0;
//4 1) Initial PcmBSize03 Register
pHalPcmAdapter->PcmBSize03.CH0BSize = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte
//4 2) Initial Ctl Register
pHalPcmAdapter->PcmCtl.Pcm_En = 1;
pHalPcmAdapter->PcmCtl.SlaveMode = 0;
pHalPcmAdapter->PcmCtl.FsInv = 0;
pHalPcmAdapter->PcmCtl.LinearMode = 0;
pHalPcmAdapter->PcmCtl.LoopBack = 0;
pHalPcmAdapter->PcmCtl.EndianSwap = 1;
return _TRUE;
}
BOOL
HalPcmSettingRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03;
u32 Isr03;
PcmCh=0;
//4 1) Check Pcm index is avaliable
if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
//4 2) Check if there are the pending isr
Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03);
Isr03 &= 0xff000000;
//4 Clear Pending Isr
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03);
//}
//4 3) Process RegCtl
RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL);
//4 Clear Ctl register bits
RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL &
BIT_INV_CTLX_FSINV &
BIT_INV_CTLX_PCM_EN &
BIT_INV_CTLX_LINEARMODE &
BIT_INV_CTLX_LOOP_BACK &
BIT_INV_CTLX_ENDIAN_SWAP);
RegCtl = BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) |
BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) |
BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) |
BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) |
BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) |
BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) |
RegCtl;
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl);
//4 4) Program ChCNR03 Register
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE &
BIT_INV_CHCNR03_CH0TE &
BIT_INV_CHCNR03_CH0MUA &
BIT_INV_CHCNR03_CH0BAND);
RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) |
BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) |
BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) |
BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) |
RegChCNR03;
DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03);
// time slot
RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03);
RegTSR03 &= (BIT_INV_TSR03_CH0TSA);
RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) |
RegTSR03;
DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03);
// buffer size
RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03);
RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE);
RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) |
RegBSize03;
DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03);
return _TRUE;
}
BOOL
HalPcmEnRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 1;
//4 1) Check Pcm index is avaliable
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
if (RegChCNR03 & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25);
pHalPcmAdapter->PcmChCNR03.CH0RE = 1;
pHalPcmAdapter->PcmChCNR03.CH0TE = 1;
return _TRUE;
}
BOOL
HalPcmDisRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 0;
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25)));
pHalPcmAdapter->PcmChCNR03.CH0RE = 0;
pHalPcmAdapter->PcmChCNR03.CH0TE = 0;
return _TRUE;
}
BOOL
HalPcmIsrEnAndDisRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrMask, Addr, IsrCtrl;
u8 IsrTypeIndex = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
Addr = (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8);
IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr);
IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask):
((~pHalGdmaAdapter->ChEn) & IsrMask));
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
Addr,
IsrCtrl
);
}
}
*/
return _TRUE;
}
BOOL
HalPcmDumpRegRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
BOOL
HalPcmRtl8195a (
IN VOID *Data
)
{
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
~(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
/*
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrStatus;
u8 IsrTypeIndex = 0, IsrActBitMap = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8));
// DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus);
IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF));
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)),
(IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF))
);
IsrActBitMap |= BIT_(IsrTypeIndex);
}
}
return IsrActBitMap;
}
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
*/
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_pcm.h"
#include "hal_pcm.h"
extern void *
_memset( void *s, int c, SIZE_T n );
VOID
HalPcmOnOffRtl8195a (
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
//todo on off pcm
}
//default sampling rate 8khz, linear, 10ms frame size, time slot 0 , tx+rx
// master mode, enable endian swap
// Question: need local tx/rx page?
BOOL
HalPcmInitRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
_memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER));
//4 1) Initial PcmChCNR03 Register
pHalPcmAdapter->PcmChCNR03.CH0MuA = 0;
pHalPcmAdapter->PcmChCNR03.CH0Band = 0;
//4 1) Initial PcmTSR03 Register
pHalPcmAdapter->PcmTSR03.CH0TSA = 0;
//4 1) Initial PcmBSize03 Register
pHalPcmAdapter->PcmBSize03.CH0BSize = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte
//4 2) Initial Ctl Register
pHalPcmAdapter->PcmCtl.Pcm_En = 1;
pHalPcmAdapter->PcmCtl.SlaveMode = 0;
pHalPcmAdapter->PcmCtl.FsInv = 0;
pHalPcmAdapter->PcmCtl.LinearMode = 0;
pHalPcmAdapter->PcmCtl.LoopBack = 0;
pHalPcmAdapter->PcmCtl.EndianSwap = 1;
return _TRUE;
}
BOOL
HalPcmSettingRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03;
u32 Isr03;
PcmCh=0;
//4 1) Check Pcm index is avaliable
if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
//4 2) Check if there are the pending isr
Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03);
Isr03 &= 0xff000000;
//4 Clear Pending Isr
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03);
//}
//4 3) Process RegCtl
RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL);
//4 Clear Ctl register bits
RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL &
BIT_INV_CTLX_FSINV &
BIT_INV_CTLX_PCM_EN &
BIT_INV_CTLX_LINEARMODE &
BIT_INV_CTLX_LOOP_BACK &
BIT_INV_CTLX_ENDIAN_SWAP);
RegCtl = BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) |
BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) |
BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) |
BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) |
BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) |
BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) |
RegCtl;
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl);
//4 4) Program ChCNR03 Register
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE &
BIT_INV_CHCNR03_CH0TE &
BIT_INV_CHCNR03_CH0MUA &
BIT_INV_CHCNR03_CH0BAND);
RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) |
BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) |
BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) |
BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) |
RegChCNR03;
DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03);
// time slot
RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03);
RegTSR03 &= (BIT_INV_TSR03_CH0TSA);
RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) |
RegTSR03;
DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03);
// buffer size
RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03);
RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE);
RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) |
RegBSize03;
DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03);
return _TRUE;
}
BOOL
HalPcmEnRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 1;
//4 1) Check Pcm index is avaliable
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
if (RegChCNR03 & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25);
pHalPcmAdapter->PcmChCNR03.CH0RE = 1;
pHalPcmAdapter->PcmChCNR03.CH0TE = 1;
return _TRUE;
}
BOOL
HalPcmDisRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 0;
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25)));
pHalPcmAdapter->PcmChCNR03.CH0RE = 0;
pHalPcmAdapter->PcmChCNR03.CH0TE = 0;
return _TRUE;
}
BOOL
HalPcmIsrEnAndDisRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrMask, Addr, IsrCtrl;
u8 IsrTypeIndex = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
Addr = (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8);
IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr);
IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask):
((~pHalGdmaAdapter->ChEn) & IsrMask));
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
Addr,
IsrCtrl
);
}
}
*/
return _TRUE;
}
BOOL
HalPcmDumpRegRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
BOOL
HalPcmRtl8195a (
IN VOID *Data
)
{
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
~(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
/*
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrStatus;
u8 IsrTypeIndex = 0, IsrActBitMap = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8));
// DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus);
IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF));
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)),
(IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF))
);
IsrActBitMap |= BIT_(IsrTypeIndex);
}
}
return IsrActBitMap;
}
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
*/

3204
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
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File diff suppressed because it is too large Load diff

680
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_timer.c
View file

@ -1,340 +1,340 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_timer.h"
extern u32 gTimerRecord;
extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM];
#ifdef CONFIG_CHIP_A_CUT
HAL_RAM_BSS_SECTION u32 gTimerRecord;
#endif
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#else
u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#endif
VOID
HalTimerIrq2To7Handle_Patch(
IN VOID *Data
)
{
u32 TimerIrqStatus = 0, CheckIndex;
IRQ_FUN pHandler;
TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF);
DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus);
for (CheckIndex = 2; CheckIndex<8; CheckIndex++) {
//3 Check IRQ status bit and Timer X IRQ enable bit
if ((TimerIrqStatus & BIT_(CheckIndex)) &&
(HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) {
//3 Execute Timer callback function
pHandler = Timer2To7VectorTable[CheckIndex-2];
if (pHandler != NULL) {
pHandler((void*)Timer2To7HandlerData[CheckIndex-2]);
}
//3 Clear Timer ISR
HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF);
}
}
}
HAL_Status
HalTimerIrqRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
IRQ_HANDLE TimerIrqHandle;
//IRQ_FUN BackUpIrqFun = NULL;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
TimerIrqHandle.IrqNum = TIMER2_7_IRQ;
TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] =
(IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
Timer2To7HandlerData[pHalTimerAdap->TimerId-2] =
(uint32_t) pHalTimerAdap->IrqHandle.Data;
}
else {
TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
}
TimerIrqHandle.Data = (u32)pHalTimerAdap;
InterruptRegister(&TimerIrqHandle);
}
return HAL_OK;
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
// Patch for A/B Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
u32 ControlReg;
if ((gTimerRecord & (1<<pHalTimerAdap->TimerId)) != 0) {
DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_BUSY;
}
//4 1) Config Timer Setting
ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2);
/*
set TimerControlReg
0: Timer enable (0,disable; 1,enable)
1: Timer Mode (0, free-running mode; 1, user-defined count mode)
2: Timer Interrupt Mask (0, not masked; 1,masked)
*/
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
ControlReg);
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
else {
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF),
0xFFFFFFFF);
}
//4 2) Setting Timer IRQ
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
//4 2.1) Initial TimerIRQHandle
ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap);
if (HAL_OK != ret) {
DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return ret;
}
//4 2.2) Enable TimerIRQ for Platform
InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
}
else {
DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
}
//4 4) Enable Timer
// HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
// (ControlReg|0x1));
gTimerRecord |= (1<<pHalTimerAdap->TimerId);
return ret;
}
#elif defined(CONFIG_CHIP_C_CUT)
// Patch for C Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
ret = HalTimerInitRtl8195aV02(Data);
// Patch the Rom code to load the correct count value
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
return ret;
}
#endif
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
HAL_Status
HalTimerIrqUnRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
PIRQ_HANDLE pTimerIrqHandle;
u32 i;
pTimerIrqHandle = &pHalTimerAdap->IrqHandle;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
pTimerIrqHandle->IrqNum = TIMER2_7_IRQ;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL;
for (i=0;i<MAX_TIMER_VECTOR_TABLE_NUM;i++) {
if (Timer2To7VectorTable[i] != NULL) {
break;
}
}
if (i == MAX_TIMER_VECTOR_TABLE_NUM) {
// All timer UnRegister Interrupt
InterruptDis((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
InterruptUnRegister(pTimerIrqHandle);
}
}
else {
pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
InterruptUnRegister(pTimerIrqHandle);
}
}
return HAL_OK;
}
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
u32 timer_id;
timer_id = pHalTimerAdap->TimerId;
HalTimerDisRtl8195a (timer_id);
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap);
}
}
gTimerRecord &= ~(1<<pHalTimerAdap->TimerId);
}
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
)
{
u32 TimerCountOld;
u32 TimerCountNew;
u32 TimerRDCnt;
TimerRDCnt = 0;
TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
while(1) {
TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
if (TimerCountOld == TimerCountNew) {
return (u32)TimerCountOld;
}
else {
TimerRDCnt++;
TimerCountOld = TimerCountNew;
if (TimerRDCnt >= 2){
return (u32)TimerCountOld;
}
}
}
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
)
{
u32 LoadCount = 0;
u32 ms125; // how many 125ms
u32 remain_us;
ms125 = LoadUs/125000;
remain_us = LoadUs - (ms125*125000);
LoadCount = ms125 * (GTIMER_CLK_HZ/8);
LoadCount += (remain_us*GTIMER_CLK_HZ)/1000000;
if (LoadCount == 0) {
LoadCount = 1;
}
// DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount);
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF),
LoadCount);
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~(BIT2)));
}
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT2));
}
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_EOI_OFF);
}
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT0));
}
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
)
{
// Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~BIT0));
}
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_timer.h"
extern u32 gTimerRecord;
extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM];
#ifdef CONFIG_CHIP_A_CUT
HAL_RAM_BSS_SECTION u32 gTimerRecord;
#endif
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#else
u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#endif
VOID
HalTimerIrq2To7Handle_Patch(
IN VOID *Data
)
{
u32 TimerIrqStatus = 0, CheckIndex;
IRQ_FUN pHandler;
TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF);
DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus);
for (CheckIndex = 2; CheckIndex<8; CheckIndex++) {
//3 Check IRQ status bit and Timer X IRQ enable bit
if ((TimerIrqStatus & BIT_(CheckIndex)) &&
(HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) {
//3 Execute Timer callback function
pHandler = Timer2To7VectorTable[CheckIndex-2];
if (pHandler != NULL) {
pHandler((void*)Timer2To7HandlerData[CheckIndex-2]);
}
//3 Clear Timer ISR
HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF);
}
}
}
HAL_Status
HalTimerIrqRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
IRQ_HANDLE TimerIrqHandle;
//IRQ_FUN BackUpIrqFun = NULL;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
TimerIrqHandle.IrqNum = TIMER2_7_IRQ;
TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] =
(IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
Timer2To7HandlerData[pHalTimerAdap->TimerId-2] =
(uint32_t) pHalTimerAdap->IrqHandle.Data;
}
else {
TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
}
TimerIrqHandle.Data = (u32)pHalTimerAdap;
InterruptRegister(&TimerIrqHandle);
}
return HAL_OK;
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
// Patch for A/B Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
u32 ControlReg;
if ((gTimerRecord & (1<<pHalTimerAdap->TimerId)) != 0) {
DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_BUSY;
}
//4 1) Config Timer Setting
ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2);
/*
set TimerControlReg
0: Timer enable (0,disable; 1,enable)
1: Timer Mode (0, free-running mode; 1, user-defined count mode)
2: Timer Interrupt Mask (0, not masked; 1,masked)
*/
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
ControlReg);
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
else {
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF),
0xFFFFFFFF);
}
//4 2) Setting Timer IRQ
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
//4 2.1) Initial TimerIRQHandle
ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap);
if (HAL_OK != ret) {
DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return ret;
}
//4 2.2) Enable TimerIRQ for Platform
InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
}
else {
DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
}
//4 4) Enable Timer
// HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
// (ControlReg|0x1));
gTimerRecord |= (1<<pHalTimerAdap->TimerId);
return ret;
}
#elif defined(CONFIG_CHIP_C_CUT)
// Patch for C Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
ret = HalTimerInitRtl8195aV02(Data);
// Patch the Rom code to load the correct count value
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
return ret;
}
#endif
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
HAL_Status
HalTimerIrqUnRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
PIRQ_HANDLE pTimerIrqHandle;
u32 i;
pTimerIrqHandle = &pHalTimerAdap->IrqHandle;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
pTimerIrqHandle->IrqNum = TIMER2_7_IRQ;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL;
for (i=0;i<MAX_TIMER_VECTOR_TABLE_NUM;i++) {
if (Timer2To7VectorTable[i] != NULL) {
break;
}
}
if (i == MAX_TIMER_VECTOR_TABLE_NUM) {
// All timer UnRegister Interrupt
InterruptDis((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
InterruptUnRegister(pTimerIrqHandle);
}
}
else {
pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
InterruptUnRegister(pTimerIrqHandle);
}
}
return HAL_OK;
}
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
u32 timer_id;
timer_id = pHalTimerAdap->TimerId;
HalTimerDisRtl8195a (timer_id);
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap);
}
}
gTimerRecord &= ~(1<<pHalTimerAdap->TimerId);
}
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
)
{
u32 TimerCountOld;
u32 TimerCountNew;
u32 TimerRDCnt;
TimerRDCnt = 0;
TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
while(1) {
TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
if (TimerCountOld == TimerCountNew) {
return (u32)TimerCountOld;
}
else {
TimerRDCnt++;
TimerCountOld = TimerCountNew;
if (TimerRDCnt >= 2){
return (u32)TimerCountOld;
}
}
}
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
)
{
u32 LoadCount = 0;
u32 ms125; // how many 125ms
u32 remain_us;
ms125 = LoadUs/125000;
remain_us = LoadUs - (ms125*125000);
LoadCount = ms125 * (GTIMER_CLK_HZ/8);
LoadCount += (remain_us*GTIMER_CLK_HZ)/1000000;
if (LoadCount == 0) {
LoadCount = 1;
}
// DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount);
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF),
LoadCount);
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~(BIT2)));
}
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT2));
}
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_EOI_OFF);
}
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT0));
}
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
)
{
// Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~BIT0));
}