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motify compile link error

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motify compile link error
This commit is contained in:
ant 2016-09-18 09:03:25 +08:00
parent 923914edae
commit 03e74a8e50
5418 changed files with 1367914 additions and 206149 deletions
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1056
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gdma.h
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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h
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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h
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122
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h
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@ -1,61 +1,61 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_PWM_H_
#define _RTL8195A_PWM_H_
extern void
HAL_Pwm_SetDuty_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern HAL_Status
HAL_Pwm_Init_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Enable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Disable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
#ifdef CONFIG_CHIP_E_CUT
extern _LONG_CALL_ void
HAL_Pwm_SetDuty_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern _LONG_CALL_ HAL_Status
HAL_Pwm_Init_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern _LONG_CALL_ void
HAL_Pwm_Enable_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern _LONG_CALL_ void
HAL_Pwm_Disable_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
#endif
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_PWM_H_
#define _RTL8195A_PWM_H_
extern void
HAL_Pwm_SetDuty_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern HAL_Status
HAL_Pwm_Init_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Enable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Disable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
#ifdef CONFIG_CHIP_E_CUT
extern _LONG_CALL_ void
HAL_Pwm_SetDuty_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern _LONG_CALL_ HAL_Status
HAL_Pwm_Init_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern _LONG_CALL_ void
HAL_Pwm_Enable_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern _LONG_CALL_ void
HAL_Pwm_Disable_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
#endif
#endif

758
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdr.h
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@ -1,379 +1,379 @@
#ifndef _RTL8195A_SDR_H
#define _RTL8195A_SDR_H
#define MS_0_CTRL_BASE BSP_MS_I_DRAMC_0_BASE
#define MS_0_CTRL_PHY_BASE (BSP_MS_I_DRAMC_0_BASE)
#define MS_0_WRAP_BASE (MS_0_CTRL_BASE + 0x200)
#define MS_1_CTRL_BASE BSP_MS_I_DRAMC_1_BASE
#define MS_1_CTRL_PHY_BASE (BSP_MS_I_DRAMC_1_BASE)
#define MS_1_WRAP_BASE (MS_1_CTRL_BASE + 0x200)
#define MS_PCTL_CCR_OFFSET 0x000
#define MS_PCTL_DCR_OFFSET 0x004
#define MS_PCTL_IOCR_OFFSET 0x008
#define MS_PCTL_CSR_OFFSET 0x00c
#define MS_PCTL_DRR_OFFSET 0x010
#define MS_PCTL_TPR0_OFFSET 0x014
#define MS_PCTL_TPR1_OFFSET 0x018
#define MS_PCTL_TPR2_OFFSET 0x01c
#define MS_PCTL_MR_OFFSET 0x020
#define MS_PCTL_EMR1_OFFSET 0x024
#define MS_PCTL_EMR2_OFFSET 0x028
#define MS_PCTL_EMR3_OFFSET 0x02c
#define MS_PCTL_CSR2_OFFSET 0x030
#define MS_PCTL_SRST_OFFSET 0x034
#define MS_PCTL_DTR2_OFFSET 0x038
#define MS_PCTL_DTR3_OFFSET 0x03c
#define MS_PCTL_GDLLCR_OFFSET 0x040
#define MS_PCTL_DLLCR0_OFFSET 0x044
#define MS_PCTL_DLLCR1_OFFSET 0x048
#define MS_PCTL_DLLCR2_OFFSET 0x04c
#define MS_PCTL_DLLCR3_OFFSET 0x050
#define MS_PCTL_DLLCR4_OFFSET 0x054
#define MS_PCTL_DLLCR5_OFFSET 0x058
#define MS_PCTL_DLLCR6_OFFSET 0x05c
#define MS_PCTL_DLLCR7_OFFSET 0x060
#define MS_PCTL_DLLCR8_OFFSET 0x064
#define MS_PCTL_DQTR0_OFFSET 0x068
#define MS_PCTL_DQTR1_OFFSET 0x06c
#define MS_PCTL_DQTR2_OFFSET 0x070
#define MS_PCTL_DQTR3_OFFSET 0x074
#define MS_PCTL_DQTR4_OFFSET 0x078
#define MS_PCTL_DQTR5_OFFSET 0x07c
#define MS_PCTL_DQTR6_OFFSET 0x080
#define MS_PCTL_DQTR7_OFFSET 0x084
#define MS_PCTL_DQSTR_OFFSET 0x088
#define MS_PCTL_DQSBTR_OFFSET 0x08c
#define MS_PCTL_ODTCR_OFFSET 0x090
#define MS_PCTL_DTR0_OFFSET 0x094
#define MS_PCTL_DTR1_OFFSET 0x098
#define MS_PCTL_DTAR_OFFSET 0x09c
#define MS_PCTL_ZQCR0_OFFSET 0x0a0
#define MS_PCTL_ZQCR1_OFFSET 0x0a4
#define MS_PCTL_ZQSR_OFFSET 0x0a8
#define MS_PCTL_RSLR0_OFFSET 0x0ac
#define MS_PCTL_RSLR1_OFFSET 0x0b0
#define MS_PCTL_RSLR2_OFFSET 0x0b4
#define MS_PCTL_RSLR3_OFFSET 0x0b8
#define MS_PCTL_RDGR0_OFFSET 0x0bc
#define MS_PCTL_RDGR1_OFFSET 0x0c0
#define MS_PCTL_RDGR2_OFFSET 0x0c4
#define MS_PCTL_RDGR3_OFFSET 0x0c8
#define MS_PCTL_MXSL_OFFSET 0x0cc
#define MS_PCTL_BCR_OFFSET 0x0d0
#define MS_PCTL_BALR0_OFFSET 0x0d4
#define MS_PCTL_BALR1_OFFSET 0x0d8
#define MS_PCTL_BDR0_OFFSET 0x0dc
#define MS_PCTL_BDR1_OFFSET 0x0e0
#define MS_PCTL_BBR_OFFSET 0x0e4
#define MS_PCTL_BSR_OFFSET 0x0e8
#define MS_PCTL_BYR_OFFSET 0x0ec
#define MS_PCTL_BFA_OFFSET 0x0f0
#define MS_PCTL_IDR_OFFSET 0x0f8
#define MS_PCTL_ERR_OFFSET 0x0fc
#define MS_WRAP_SCR_OFFSET 0x224
#define MS_WRAP_QCR_OFFSET 0x230
#define MS_WRAP_PCR_OFFSET 0x234
#define MS_WRAP_QTR0_OFFSET 0x240
#define MS_WRAP_QTR1_OFFSET 0x244
#define MS_WRAP_QTR2_OFFSET 0x248
#define MS_WRAP_QTR3_OFFSET 0x24c
#define MS_WRAP_QTR4_OFFSET 0x250
#define MS_WRAP_QTR5_OFFSET 0x254
#define MS_WRAP_QTR6_OFFSET 0x258
#define MS_WRAP_QTR7_OFFSET 0x25c
#define MS_WRAP_QTR8_OFFSET 0x260
#define MS_WRAP_QTR9_OFFSET 0x264
#define MS_WRAP_QTR10_OFFSET 0x268
#define MS_WRAP_QTR11_OFFSET 0x26c
#define MS_WRAP_QTR12_OFFSET 0x270
#define MS_WRAP_QTR13_OFFSET 0x274
#define MS_WRAP_QTR14_OFFSET 0x278
#define MS_WRAP_QTR15_OFFSET 0x27c
#define MS_PHY_DLY0 0x100
#define MS_PHY_DLY1_RST 0x104
#define MS_PHY_DLY_CLK 0x108
#define MS_PHY_DLY_ST 0x10c
#define MS_PHY_DLY_NUM 0x100
#define PCTL_CCR_INIT_BFO 0
#define PCTL_CCR_INIT_BFW 1
#define PCTL_CCR_DTT_BFO 1
#define PCTL_CCR_DTT_BFW 1
#define PCTL_CCR_BTT_BFO 2
#define PCTL_CCR_BTT_BFW 1
#define PCTL_CCR_DPIT_BFO 3
#define PCTL_CCR_DPIT_BFW 1
#define PCTL_CCR_FLUSH_FIFO_BFO 8
#define PCTL_CCR_FLUSH_FIFO_BFW 1
#define PCTL_DCR_DDR3_BFO 0
#define PCTL_DCR_DDR3_BFW 1
#define PCTL_DCR_SDR_BFO 1
#define PCTL_DCR_SDR_BFW 1
#define PCTL_DCR_DQ32_BFO 4
#define PCTL_DCR_DQ32_BFW 1
#define PCTL_DCR_DFI_RATE_BFO 8
#define PCTL_DCR_DFI_RATE_BFW 3
#define PCTL_IOCR_RD_PIPE_BFO 8
#define PCTL_IOCR_RD_PIPE_BFW 4
#define PCTL_IOCR_TPHY_WD_BFO 12
#define PCTL_IOCR_TPHY_WD_BFW 5
#define PCTL_IOCR_TPHY_WL_BFO 17
#define PCTL_IOCR_TPHY_WL_BFW 3
#define PCTL_IOCR_TPHY_RD_EN_BFO 20
#define PCTL_IOCR_TPHY_RD_EN_BFW 5
#define PCTL_CSR_MEM_IDLE_BFO 8
#define PCTL_CSR_MEM_IDLE_BFW 1
#define PCTL_CSR_DT_IDLE_BFO 9
#define PCTL_CSR_DT_IDLE_BFW 1
#define PCTL_CSR_BIST_IDLE_BFO 10
#define PCTL_CSR_BIST_IDLE_BFW 1
#define PCTL_CSR_DT_FAIL_BFO 11
#define PCTL_CSR_DT_FAIL_BFW 1
#define PCTL_CSR_BT_FAIL_BFO 12
#define PCTL_CSR_BT_FAIL_BFW 1
#define PCTL_DRR_TRFC_BFO 0
#define PCTL_DRR_TRFC_BFW 7
#define PCTL_DRR_TREF_BFO 8
#define PCTL_DRR_TREF_BFW 24
#define PCTL_DRR_REF_NUM_BFO 24
#define PCTL_DRR_REF_NUM_BFW 4
#define PCTL_DRR_REF_DIS_BFO 28
#define PCTL_DRR_REF_DIS_BFW 1
#define PCTL_TPR0_TRP_BFO 0
#define PCTL_TPR0_TRP_BFW 4
#define PCTL_TPR0_TRAS_BFO 4
#define PCTL_TPR0_TRAS_BFW 5
#define PCTL_TPR0_TWR_BFO 9
#define PCTL_TPR0_TWR_BFW 4
#define PCTL_TPR0_TRTP_BFO 13
#define PCTL_TPR0_TRTP_BFW 3
#define PCTL_TPR1_TRRD_BFO 0
#define PCTL_TPR1_TRRD_BFW 4
#define PCTL_TPR1_TRC_BFO 4
#define PCTL_TPR1_TRC_BFW 6
#define PCTL_TPR1_TRCD_BFO 10
#define PCTL_TPR1_TRCD_BFW 4
#define PCTL_TPR1_TCCD_BFO 14
#define PCTL_TPR1_TCCD_BFW 3
#define PCTL_TPR1_TWTR_BFO 17
#define PCTL_TPR1_TWTR_BFW 3
#define PCTL_TPR1_TRTW_BFO 20
#define PCTL_TPR1_TRTW_BFW 4
#define PCTL_TPR2_INIT_REF_NUM_BFO 0
#define PCTL_TPR2_INIT_REF_NUM_BFW 4
#define PCTL_TPR2_INIT_NS_EN_BFO 4
#define PCTL_TPR2_INIT_NS_EN_BFW 1
#define PCTL_TPR2_TMRD_BFO 5
#define PCTL_TPR2_TMRD_BFW 2
#define PCTL_MR_BL_BFO 0
#define PCTL_MR_BL_BFW 3
#define PCTL_MR_BT_BFO 3
#define PCTL_MR_BT_BFW 1
#define PCTL_MR_CAS_BFO 4
#define PCTL_MR_CAS_BFW 3
#define PCTL_MR_OP_BFO 8
#define PCTL_MR_OP_BFW 12
#define PCTL_EMR1_ADDLAT_BFO 3
#define PCTL_EMR1_ADDLAT_BFW 3
#define PCTL_CMD_DPIN_RSTN_BFO 0
#define PCTL_CMD_DPIN_RSTN_BFW 1
#define PCTL_CMD_DPIN_CKE_BFO 1
#define PCTL_CMD_DPIN_CKE_BFW 1
#define PCTL_CMD_DPIN_ODT_BFO 2
#define PCTL_CMD_DPIN_ODT_BFW 1
#define PCTL_BCR_STOP_BFO 0
#define PCTL_BCR_STOP_BFW 1
#define PCTL_BCR_CMP_BFO 1
#define PCTL_BCR_CMP_BFW 1
#define PCTL_BCR_LOOP_BFO 2
#define PCTL_BCR_LOOP_BFW 1
#define PCTL_BCR_DIS_MASK_BFO 3
#define PCTL_BCR_DIS_MASK_BFW 1
#define PCTL_BCR_AT_STOP_BFO 4
#define PCTL_BCR_AT_STOP_BFW 1
#define PCTL_BCR_FLUSH_CMD_BFO 8
#define PCTL_BCR_FLUSH_CMD_BFW 1
#define PCTL_BCR_FLUSH_WD_BFO 9
#define PCTL_BCR_FLUSH_WD_BFW 1
#define PCTL_BCR_FLUSH_RGD_BFO 10
#define PCTL_BCR_FLUSH_RGD_BFW 1
#define PCTL_BCR_FLUSH_RD_BFO 11
#define PCTL_BCR_FLUSH_RD_BFW 1
#define PCTL_BCR_FLUSH_RD_EXPC_BFO 16
#define PCTL_BCR_FLUSH_RD_EXPC_BFW 14
#define PCTL_BST_ERR_FST_TH_BFO 0
#define PCTL_BST_ERR_FST_TH_BFW 12
#define PCTL_BST_ERR_CNT_BFO 16
#define PCTL_BST_ERR_CNT_BFW 14
#define PCTL_BSRAM0_CMD_LEVEL_BFO 0
#define PCTL_BSRAM0_CMD_LEVEL_BFW 12
#define PCTL_BSRAM0_WD_LEVEL_BFO 16
#define PCTL_BSRAM0_WD_LEVEL_BFW 14
#define PCTL_BSRAM1_RG_LEVEL_BFO 0
#define PCTL_BSRAM1_RG_LEVEL_BFW 14
#define PCTL_BSRAM1_RD_LEVEL_BFO 16
#define PCTL_BSRAM1_RD_LEVEL_BFW 14
#define WRAP_MISC_PAGE_SIZE_BFO 0
#define WRAP_MISC_PAGE_SIZE_BFW 4
#define WRAP_MISC_BANK_SIZE_BFO 4
#define WRAP_MISC_BANK_SIZE_BFW 2
#define WRAP_MISC_BST_SIZE_BFO 6
#define WRAP_MISC_BST_SIZE_BFW 2
#define WRAP_MISC_DDR_PARAL_BFO 8
#define WRAP_MISC_DDR_PARAL_BFW 1
struct ms_rxi310_portmap {
volatile unsigned int ccr; /* 0x000 */
volatile unsigned int dcr; /* 0x004 */
volatile unsigned int iocr; /* 0x008 */
volatile unsigned int csr; /* 0x00c */
volatile unsigned int drr; /* 0x010 */
volatile unsigned int tpr0; /* 0x014 */
volatile unsigned int tpr1; /* 0x018 */
volatile unsigned int tpr2; /* 0x01c */
volatile unsigned int mr; /* 0x020 */
volatile unsigned int emr1; /* 0x024 */
volatile unsigned int emr2; /* 0x028 */
volatile unsigned int emr3; /* 0x02c */
volatile unsigned int cdpin; /* 0x030 */
volatile unsigned int tdpin; /* 0x034 */
volatile unsigned int dtr2; /* 0x038 */
volatile unsigned int dtr3; /* 0x03c */
volatile unsigned int gdllcr; /* 0x040 */
volatile unsigned int dllcr0; /* 0x044 */
volatile unsigned int dllcr1; /* 0x048 */
volatile unsigned int dllcr2; /* 0x04c */
volatile unsigned int dllcr3; /* 0x050 */
volatile unsigned int dllcr4; /* 0x054 */
volatile unsigned int dllcr5; /* 0x058 */
volatile unsigned int dllcr6; /* 0x05c */
volatile unsigned int dllcr7; /* 0x060 */
volatile unsigned int dllcr8; /* 0x064 */
volatile unsigned int dqtr0; /* 0x068 */
volatile unsigned int dqtr1; /* 0x06c */
volatile unsigned int dqtr2; /* 0x070 */
volatile unsigned int dqtr3; /* 0x074 */
volatile unsigned int dqtr4; /* 0x078 */
volatile unsigned int dqtr5; /* 0x07c */
volatile unsigned int dqtr6; /* 0x080 */
volatile unsigned int dqtr7; /* 0x084 */
volatile unsigned int dqstr; /* 0x088 */
volatile unsigned int dqsbtr; /* 0x08c */
volatile unsigned int odtcr; /* 0x090 */
volatile unsigned int dtr0; /* 0x094 */
volatile unsigned int dtr1; /* 0x098 */
volatile unsigned int dtar; /* 0x09c */
volatile unsigned int zqcr0; /* 0x0a0 */
volatile unsigned int zqcr1; /* 0x0a4 */
volatile unsigned int zqsr; /* 0x0a8 */
volatile unsigned int rslr0; /* 0x0ac */
volatile unsigned int rslr1; /* 0x0b0 */
volatile unsigned int rslr2; /* 0x0b4 */
volatile unsigned int rslr3; /* 0x0b8 */
volatile unsigned int rdgr0; /* 0x0bc */
volatile unsigned int rdgr1; /* 0x0c0 */
volatile unsigned int rdgr2; /* 0x0c4 */
volatile unsigned int rdgr3; /* 0x0c8 */
volatile unsigned int mxsl; /* 0x0cc */
volatile unsigned int bcr; /* 0x0d0 */
volatile unsigned int bst; /* 0x0d4 */
volatile unsigned int bsram0; /* 0x0d8 */
volatile unsigned int bsram1; /* 0x0dc */
volatile unsigned int bdr1; /* 0x0e0 */
volatile unsigned int bbr; /* 0x0e4 */
volatile unsigned int bsr; /* 0x0e8 */
volatile unsigned int byr; /* 0x0ec */
volatile unsigned int bfa; /* 0x0f0 */
volatile unsigned int pctl_svn; /* 0x0f4 */
volatile unsigned int pctl_idr; /* 0x0f8 */
volatile unsigned int err; /* 0x0fc */
// SDR_PHY CONTROL REGISTER
volatile unsigned int phy_dly0; /* 0x100 */
volatile unsigned int phy_dly1_rst; /* 0x104 */
volatile unsigned int phy_dly_clk; /* 0x108 */
volatile unsigned int phy_dly_st; /* 0x10c */
volatile unsigned int phy_dly_num; /* 0x110 */
volatile unsigned int reserved0[68];
// WRAP CONTROL REGISTER
volatile unsigned int misc; /* 0x224 */
volatile unsigned int cq_ver; /* 0x228 */
volatile unsigned int cq_mon; /* 0x22c */
volatile unsigned int wq_ver; /* 0x230 */
volatile unsigned int wq_mon; /* 0x234 */
volatile unsigned int rq_ver; /* 0x240 */
volatile unsigned int rq_mon; /* 0x244 */
volatile unsigned int reserved1[22];
volatile unsigned int wwrap_idr; /* 0x2a0 */
volatile unsigned int wrap_svn; /* 0x2a4 */
}; //ms_rxi310_portmap
#define QFIFO_CMD_BANK_BFO (35 - QFIFO_CMD_WRRD_BFO) // [38:35]
#define QFIFO_CMD_BANK_BFW 4
#define QFIFO_CMD_PAGE_BFO (20 - QFIFO_CMD_WRRD_BFO) // [34:20]
#define QFIFO_CMD_PAGE_BFW 15
#define QFIFO_CMD_COLU_BFO (7 - QFIFO_CMD_WRRD_BFO) // [19: 7]
#define QFIFO_CMD_COLU_BFW 13 // [19: 7]
#define QFIFO_BST_LEN_BFO (3 - QFIFO_CMD_WRRD_BFO) // [6:3]
#define QFIFO_BST_LEN_BFW 4 // [6:3]
#define QFIFO_CMD_WRRD_BFO 2 // [2], remove bit[1:0]
#define QFIFO_CMD_WRRD_BFW 1 // [2], remove bit[1:0]
//====================================================//
#define REG_SDR_CCR 0x00
#define REG_SDR_DCR 0x04
#define REG_SDR_IOCR 0x08
#define REG_SDR_CSR 0x0C
#define REG_SDR_DRR 0x10
#define REG_SDR_TPR0 0x14
#define REG_SDR_TPR1 0x18
#define REG_SDR_TPR2 0x1C
#define REG_SDR_MR 0x20
#define REG_SDR_EMR1 0x24
#define REG_SDR_EMR2 0x28
#define REG_SDR_EMR3 0x2C
#define REG_SDR_CMD_DPIN 0x30
#define REG_SDR_TIE_DPIN 0x34
#define REG_SDR_BCR 0xD0
#define REG_SDR_BST 0xD4
#define REG_SDR_BSRAM0 0xD8
#define REG_SDR_BSRAM1 0xDC
#define REG_SDR_PCTL_SVN_ID 0xF4
#define REG_SDR_PCTL_IDR 0xF8
#define REG_SDR_DLY0 0x100
#define REG_SDR_DLY1 0x104
#define REG_SDR_DCM_RST 0x104
#define REG_SDR_DLY_CLK_PHA 0x108
#define REG_SDR_DLY_ST 0x10C
#define REG_SDR_MISC 0x224
#define REG_SDR_OCP_WRAP_IDR 0x2A0
#define REG_SDR_OCP_WRAP_VERSION 0x2A4
#endif // end of "#ifndef _RTL8195A_SDR_H"
#ifndef _RTL8195A_SDR_H
#define _RTL8195A_SDR_H
#define MS_0_CTRL_BASE BSP_MS_I_DRAMC_0_BASE
#define MS_0_CTRL_PHY_BASE (BSP_MS_I_DRAMC_0_BASE)
#define MS_0_WRAP_BASE (MS_0_CTRL_BASE + 0x200)
#define MS_1_CTRL_BASE BSP_MS_I_DRAMC_1_BASE
#define MS_1_CTRL_PHY_BASE (BSP_MS_I_DRAMC_1_BASE)
#define MS_1_WRAP_BASE (MS_1_CTRL_BASE + 0x200)
#define MS_PCTL_CCR_OFFSET 0x000
#define MS_PCTL_DCR_OFFSET 0x004
#define MS_PCTL_IOCR_OFFSET 0x008
#define MS_PCTL_CSR_OFFSET 0x00c
#define MS_PCTL_DRR_OFFSET 0x010
#define MS_PCTL_TPR0_OFFSET 0x014
#define MS_PCTL_TPR1_OFFSET 0x018
#define MS_PCTL_TPR2_OFFSET 0x01c
#define MS_PCTL_MR_OFFSET 0x020
#define MS_PCTL_EMR1_OFFSET 0x024
#define MS_PCTL_EMR2_OFFSET 0x028
#define MS_PCTL_EMR3_OFFSET 0x02c
#define MS_PCTL_CSR2_OFFSET 0x030
#define MS_PCTL_SRST_OFFSET 0x034
#define MS_PCTL_DTR2_OFFSET 0x038
#define MS_PCTL_DTR3_OFFSET 0x03c
#define MS_PCTL_GDLLCR_OFFSET 0x040
#define MS_PCTL_DLLCR0_OFFSET 0x044
#define MS_PCTL_DLLCR1_OFFSET 0x048
#define MS_PCTL_DLLCR2_OFFSET 0x04c
#define MS_PCTL_DLLCR3_OFFSET 0x050
#define MS_PCTL_DLLCR4_OFFSET 0x054
#define MS_PCTL_DLLCR5_OFFSET 0x058
#define MS_PCTL_DLLCR6_OFFSET 0x05c
#define MS_PCTL_DLLCR7_OFFSET 0x060
#define MS_PCTL_DLLCR8_OFFSET 0x064
#define MS_PCTL_DQTR0_OFFSET 0x068
#define MS_PCTL_DQTR1_OFFSET 0x06c
#define MS_PCTL_DQTR2_OFFSET 0x070
#define MS_PCTL_DQTR3_OFFSET 0x074
#define MS_PCTL_DQTR4_OFFSET 0x078
#define MS_PCTL_DQTR5_OFFSET 0x07c
#define MS_PCTL_DQTR6_OFFSET 0x080
#define MS_PCTL_DQTR7_OFFSET 0x084
#define MS_PCTL_DQSTR_OFFSET 0x088
#define MS_PCTL_DQSBTR_OFFSET 0x08c
#define MS_PCTL_ODTCR_OFFSET 0x090
#define MS_PCTL_DTR0_OFFSET 0x094
#define MS_PCTL_DTR1_OFFSET 0x098
#define MS_PCTL_DTAR_OFFSET 0x09c
#define MS_PCTL_ZQCR0_OFFSET 0x0a0
#define MS_PCTL_ZQCR1_OFFSET 0x0a4
#define MS_PCTL_ZQSR_OFFSET 0x0a8
#define MS_PCTL_RSLR0_OFFSET 0x0ac
#define MS_PCTL_RSLR1_OFFSET 0x0b0
#define MS_PCTL_RSLR2_OFFSET 0x0b4
#define MS_PCTL_RSLR3_OFFSET 0x0b8
#define MS_PCTL_RDGR0_OFFSET 0x0bc
#define MS_PCTL_RDGR1_OFFSET 0x0c0
#define MS_PCTL_RDGR2_OFFSET 0x0c4
#define MS_PCTL_RDGR3_OFFSET 0x0c8
#define MS_PCTL_MXSL_OFFSET 0x0cc
#define MS_PCTL_BCR_OFFSET 0x0d0
#define MS_PCTL_BALR0_OFFSET 0x0d4
#define MS_PCTL_BALR1_OFFSET 0x0d8
#define MS_PCTL_BDR0_OFFSET 0x0dc
#define MS_PCTL_BDR1_OFFSET 0x0e0
#define MS_PCTL_BBR_OFFSET 0x0e4
#define MS_PCTL_BSR_OFFSET 0x0e8
#define MS_PCTL_BYR_OFFSET 0x0ec
#define MS_PCTL_BFA_OFFSET 0x0f0
#define MS_PCTL_IDR_OFFSET 0x0f8
#define MS_PCTL_ERR_OFFSET 0x0fc
#define MS_WRAP_SCR_OFFSET 0x224
#define MS_WRAP_QCR_OFFSET 0x230
#define MS_WRAP_PCR_OFFSET 0x234
#define MS_WRAP_QTR0_OFFSET 0x240
#define MS_WRAP_QTR1_OFFSET 0x244
#define MS_WRAP_QTR2_OFFSET 0x248
#define MS_WRAP_QTR3_OFFSET 0x24c
#define MS_WRAP_QTR4_OFFSET 0x250
#define MS_WRAP_QTR5_OFFSET 0x254
#define MS_WRAP_QTR6_OFFSET 0x258
#define MS_WRAP_QTR7_OFFSET 0x25c
#define MS_WRAP_QTR8_OFFSET 0x260
#define MS_WRAP_QTR9_OFFSET 0x264
#define MS_WRAP_QTR10_OFFSET 0x268
#define MS_WRAP_QTR11_OFFSET 0x26c
#define MS_WRAP_QTR12_OFFSET 0x270
#define MS_WRAP_QTR13_OFFSET 0x274
#define MS_WRAP_QTR14_OFFSET 0x278
#define MS_WRAP_QTR15_OFFSET 0x27c
#define MS_PHY_DLY0 0x100
#define MS_PHY_DLY1_RST 0x104
#define MS_PHY_DLY_CLK 0x108
#define MS_PHY_DLY_ST 0x10c
#define MS_PHY_DLY_NUM 0x100
#define PCTL_CCR_INIT_BFO 0
#define PCTL_CCR_INIT_BFW 1
#define PCTL_CCR_DTT_BFO 1
#define PCTL_CCR_DTT_BFW 1
#define PCTL_CCR_BTT_BFO 2
#define PCTL_CCR_BTT_BFW 1
#define PCTL_CCR_DPIT_BFO 3
#define PCTL_CCR_DPIT_BFW 1
#define PCTL_CCR_FLUSH_FIFO_BFO 8
#define PCTL_CCR_FLUSH_FIFO_BFW 1
#define PCTL_DCR_DDR3_BFO 0
#define PCTL_DCR_DDR3_BFW 1
#define PCTL_DCR_SDR_BFO 1
#define PCTL_DCR_SDR_BFW 1
#define PCTL_DCR_DQ32_BFO 4
#define PCTL_DCR_DQ32_BFW 1
#define PCTL_DCR_DFI_RATE_BFO 8
#define PCTL_DCR_DFI_RATE_BFW 3
#define PCTL_IOCR_RD_PIPE_BFO 8
#define PCTL_IOCR_RD_PIPE_BFW 4
#define PCTL_IOCR_TPHY_WD_BFO 12
#define PCTL_IOCR_TPHY_WD_BFW 5
#define PCTL_IOCR_TPHY_WL_BFO 17
#define PCTL_IOCR_TPHY_WL_BFW 3
#define PCTL_IOCR_TPHY_RD_EN_BFO 20
#define PCTL_IOCR_TPHY_RD_EN_BFW 5
#define PCTL_CSR_MEM_IDLE_BFO 8
#define PCTL_CSR_MEM_IDLE_BFW 1
#define PCTL_CSR_DT_IDLE_BFO 9
#define PCTL_CSR_DT_IDLE_BFW 1
#define PCTL_CSR_BIST_IDLE_BFO 10
#define PCTL_CSR_BIST_IDLE_BFW 1
#define PCTL_CSR_DT_FAIL_BFO 11
#define PCTL_CSR_DT_FAIL_BFW 1
#define PCTL_CSR_BT_FAIL_BFO 12
#define PCTL_CSR_BT_FAIL_BFW 1
#define PCTL_DRR_TRFC_BFO 0
#define PCTL_DRR_TRFC_BFW 7
#define PCTL_DRR_TREF_BFO 8
#define PCTL_DRR_TREF_BFW 24
#define PCTL_DRR_REF_NUM_BFO 24
#define PCTL_DRR_REF_NUM_BFW 4
#define PCTL_DRR_REF_DIS_BFO 28
#define PCTL_DRR_REF_DIS_BFW 1
#define PCTL_TPR0_TRP_BFO 0
#define PCTL_TPR0_TRP_BFW 4
#define PCTL_TPR0_TRAS_BFO 4
#define PCTL_TPR0_TRAS_BFW 5
#define PCTL_TPR0_TWR_BFO 9
#define PCTL_TPR0_TWR_BFW 4
#define PCTL_TPR0_TRTP_BFO 13
#define PCTL_TPR0_TRTP_BFW 3
#define PCTL_TPR1_TRRD_BFO 0
#define PCTL_TPR1_TRRD_BFW 4
#define PCTL_TPR1_TRC_BFO 4
#define PCTL_TPR1_TRC_BFW 6
#define PCTL_TPR1_TRCD_BFO 10
#define PCTL_TPR1_TRCD_BFW 4
#define PCTL_TPR1_TCCD_BFO 14
#define PCTL_TPR1_TCCD_BFW 3
#define PCTL_TPR1_TWTR_BFO 17
#define PCTL_TPR1_TWTR_BFW 3
#define PCTL_TPR1_TRTW_BFO 20
#define PCTL_TPR1_TRTW_BFW 4
#define PCTL_TPR2_INIT_REF_NUM_BFO 0
#define PCTL_TPR2_INIT_REF_NUM_BFW 4
#define PCTL_TPR2_INIT_NS_EN_BFO 4
#define PCTL_TPR2_INIT_NS_EN_BFW 1
#define PCTL_TPR2_TMRD_BFO 5
#define PCTL_TPR2_TMRD_BFW 2
#define PCTL_MR_BL_BFO 0
#define PCTL_MR_BL_BFW 3
#define PCTL_MR_BT_BFO 3
#define PCTL_MR_BT_BFW 1
#define PCTL_MR_CAS_BFO 4
#define PCTL_MR_CAS_BFW 3
#define PCTL_MR_OP_BFO 8
#define PCTL_MR_OP_BFW 12
#define PCTL_EMR1_ADDLAT_BFO 3
#define PCTL_EMR1_ADDLAT_BFW 3
#define PCTL_CMD_DPIN_RSTN_BFO 0
#define PCTL_CMD_DPIN_RSTN_BFW 1
#define PCTL_CMD_DPIN_CKE_BFO 1
#define PCTL_CMD_DPIN_CKE_BFW 1
#define PCTL_CMD_DPIN_ODT_BFO 2
#define PCTL_CMD_DPIN_ODT_BFW 1
#define PCTL_BCR_STOP_BFO 0
#define PCTL_BCR_STOP_BFW 1
#define PCTL_BCR_CMP_BFO 1
#define PCTL_BCR_CMP_BFW 1
#define PCTL_BCR_LOOP_BFO 2
#define PCTL_BCR_LOOP_BFW 1
#define PCTL_BCR_DIS_MASK_BFO 3
#define PCTL_BCR_DIS_MASK_BFW 1
#define PCTL_BCR_AT_STOP_BFO 4
#define PCTL_BCR_AT_STOP_BFW 1
#define PCTL_BCR_FLUSH_CMD_BFO 8
#define PCTL_BCR_FLUSH_CMD_BFW 1
#define PCTL_BCR_FLUSH_WD_BFO 9
#define PCTL_BCR_FLUSH_WD_BFW 1
#define PCTL_BCR_FLUSH_RGD_BFO 10
#define PCTL_BCR_FLUSH_RGD_BFW 1
#define PCTL_BCR_FLUSH_RD_BFO 11
#define PCTL_BCR_FLUSH_RD_BFW 1
#define PCTL_BCR_FLUSH_RD_EXPC_BFO 16
#define PCTL_BCR_FLUSH_RD_EXPC_BFW 14
#define PCTL_BST_ERR_FST_TH_BFO 0
#define PCTL_BST_ERR_FST_TH_BFW 12
#define PCTL_BST_ERR_CNT_BFO 16
#define PCTL_BST_ERR_CNT_BFW 14
#define PCTL_BSRAM0_CMD_LEVEL_BFO 0
#define PCTL_BSRAM0_CMD_LEVEL_BFW 12
#define PCTL_BSRAM0_WD_LEVEL_BFO 16
#define PCTL_BSRAM0_WD_LEVEL_BFW 14
#define PCTL_BSRAM1_RG_LEVEL_BFO 0
#define PCTL_BSRAM1_RG_LEVEL_BFW 14
#define PCTL_BSRAM1_RD_LEVEL_BFO 16
#define PCTL_BSRAM1_RD_LEVEL_BFW 14
#define WRAP_MISC_PAGE_SIZE_BFO 0
#define WRAP_MISC_PAGE_SIZE_BFW 4
#define WRAP_MISC_BANK_SIZE_BFO 4
#define WRAP_MISC_BANK_SIZE_BFW 2
#define WRAP_MISC_BST_SIZE_BFO 6
#define WRAP_MISC_BST_SIZE_BFW 2
#define WRAP_MISC_DDR_PARAL_BFO 8
#define WRAP_MISC_DDR_PARAL_BFW 1
struct ms_rxi310_portmap {
volatile unsigned int ccr; /* 0x000 */
volatile unsigned int dcr; /* 0x004 */
volatile unsigned int iocr; /* 0x008 */
volatile unsigned int csr; /* 0x00c */
volatile unsigned int drr; /* 0x010 */
volatile unsigned int tpr0; /* 0x014 */
volatile unsigned int tpr1; /* 0x018 */
volatile unsigned int tpr2; /* 0x01c */
volatile unsigned int mr; /* 0x020 */
volatile unsigned int emr1; /* 0x024 */
volatile unsigned int emr2; /* 0x028 */
volatile unsigned int emr3; /* 0x02c */
volatile unsigned int cdpin; /* 0x030 */
volatile unsigned int tdpin; /* 0x034 */
volatile unsigned int dtr2; /* 0x038 */
volatile unsigned int dtr3; /* 0x03c */
volatile unsigned int gdllcr; /* 0x040 */
volatile unsigned int dllcr0; /* 0x044 */
volatile unsigned int dllcr1; /* 0x048 */
volatile unsigned int dllcr2; /* 0x04c */
volatile unsigned int dllcr3; /* 0x050 */
volatile unsigned int dllcr4; /* 0x054 */
volatile unsigned int dllcr5; /* 0x058 */
volatile unsigned int dllcr6; /* 0x05c */
volatile unsigned int dllcr7; /* 0x060 */
volatile unsigned int dllcr8; /* 0x064 */
volatile unsigned int dqtr0; /* 0x068 */
volatile unsigned int dqtr1; /* 0x06c */
volatile unsigned int dqtr2; /* 0x070 */
volatile unsigned int dqtr3; /* 0x074 */
volatile unsigned int dqtr4; /* 0x078 */
volatile unsigned int dqtr5; /* 0x07c */
volatile unsigned int dqtr6; /* 0x080 */
volatile unsigned int dqtr7; /* 0x084 */
volatile unsigned int dqstr; /* 0x088 */
volatile unsigned int dqsbtr; /* 0x08c */
volatile unsigned int odtcr; /* 0x090 */
volatile unsigned int dtr0; /* 0x094 */
volatile unsigned int dtr1; /* 0x098 */
volatile unsigned int dtar; /* 0x09c */
volatile unsigned int zqcr0; /* 0x0a0 */
volatile unsigned int zqcr1; /* 0x0a4 */
volatile unsigned int zqsr; /* 0x0a8 */
volatile unsigned int rslr0; /* 0x0ac */
volatile unsigned int rslr1; /* 0x0b0 */
volatile unsigned int rslr2; /* 0x0b4 */
volatile unsigned int rslr3; /* 0x0b8 */
volatile unsigned int rdgr0; /* 0x0bc */
volatile unsigned int rdgr1; /* 0x0c0 */
volatile unsigned int rdgr2; /* 0x0c4 */
volatile unsigned int rdgr3; /* 0x0c8 */
volatile unsigned int mxsl; /* 0x0cc */
volatile unsigned int bcr; /* 0x0d0 */
volatile unsigned int bst; /* 0x0d4 */
volatile unsigned int bsram0; /* 0x0d8 */
volatile unsigned int bsram1; /* 0x0dc */
volatile unsigned int bdr1; /* 0x0e0 */
volatile unsigned int bbr; /* 0x0e4 */
volatile unsigned int bsr; /* 0x0e8 */
volatile unsigned int byr; /* 0x0ec */
volatile unsigned int bfa; /* 0x0f0 */
volatile unsigned int pctl_svn; /* 0x0f4 */
volatile unsigned int pctl_idr; /* 0x0f8 */
volatile unsigned int err; /* 0x0fc */
// SDR_PHY CONTROL REGISTER
volatile unsigned int phy_dly0; /* 0x100 */
volatile unsigned int phy_dly1_rst; /* 0x104 */
volatile unsigned int phy_dly_clk; /* 0x108 */
volatile unsigned int phy_dly_st; /* 0x10c */
volatile unsigned int phy_dly_num; /* 0x110 */
volatile unsigned int reserved0[68];
// WRAP CONTROL REGISTER
volatile unsigned int misc; /* 0x224 */
volatile unsigned int cq_ver; /* 0x228 */
volatile unsigned int cq_mon; /* 0x22c */
volatile unsigned int wq_ver; /* 0x230 */
volatile unsigned int wq_mon; /* 0x234 */
volatile unsigned int rq_ver; /* 0x240 */
volatile unsigned int rq_mon; /* 0x244 */
volatile unsigned int reserved1[22];
volatile unsigned int wwrap_idr; /* 0x2a0 */
volatile unsigned int wrap_svn; /* 0x2a4 */
}; //ms_rxi310_portmap
#define QFIFO_CMD_BANK_BFO (35 - QFIFO_CMD_WRRD_BFO) // [38:35]
#define QFIFO_CMD_BANK_BFW 4
#define QFIFO_CMD_PAGE_BFO (20 - QFIFO_CMD_WRRD_BFO) // [34:20]
#define QFIFO_CMD_PAGE_BFW 15
#define QFIFO_CMD_COLU_BFO (7 - QFIFO_CMD_WRRD_BFO) // [19: 7]
#define QFIFO_CMD_COLU_BFW 13 // [19: 7]
#define QFIFO_BST_LEN_BFO (3 - QFIFO_CMD_WRRD_BFO) // [6:3]
#define QFIFO_BST_LEN_BFW 4 // [6:3]
#define QFIFO_CMD_WRRD_BFO 2 // [2], remove bit[1:0]
#define QFIFO_CMD_WRRD_BFW 1 // [2], remove bit[1:0]
//====================================================//
#define REG_SDR_CCR 0x00
#define REG_SDR_DCR 0x04
#define REG_SDR_IOCR 0x08
#define REG_SDR_CSR 0x0C
#define REG_SDR_DRR 0x10
#define REG_SDR_TPR0 0x14
#define REG_SDR_TPR1 0x18
#define REG_SDR_TPR2 0x1C
#define REG_SDR_MR 0x20
#define REG_SDR_EMR1 0x24
#define REG_SDR_EMR2 0x28
#define REG_SDR_EMR3 0x2C
#define REG_SDR_CMD_DPIN 0x30
#define REG_SDR_TIE_DPIN 0x34
#define REG_SDR_BCR 0xD0
#define REG_SDR_BST 0xD4
#define REG_SDR_BSRAM0 0xD8
#define REG_SDR_BSRAM1 0xDC
#define REG_SDR_PCTL_SVN_ID 0xF4
#define REG_SDR_PCTL_IDR 0xF8
#define REG_SDR_DLY0 0x100
#define REG_SDR_DLY1 0x104
#define REG_SDR_DCM_RST 0x104
#define REG_SDR_DLY_CLK_PHA 0x108
#define REG_SDR_DLY_ST 0x10C
#define REG_SDR_MISC 0x224
#define REG_SDR_OCP_WRAP_IDR 0x2A0
#define REG_SDR_OCP_WRAP_VERSION 0x2A4
#endif // end of "#ifndef _RTL8195A_SDR_H"

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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h
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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_ssi.h
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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h
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component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h
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@ -1,257 +1,257 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_TIMER_H_
#define _RTL8195A_TIMER_H_
#define TIMER_TICK_US 31
#define TIMER_LOAD_COUNT_OFF 0x00
#define TIMER_CURRENT_VAL_OFF 0x04
#define TIMER_CTL_REG_OFF 0x08
#define TIMER_EOI_OFF 0x0c
#define TIMER_INT_STATUS_OFF 0x10
#define TIMER_INTERVAL 0x14
#define TIMERS_INT_STATUS_OFF 0xa0
#define TIMERS_EOI_OFF 0xa4
#define TIMERS_RAW_INT_STATUS_OFF 0xa8
#define TIMERS_COMP_VER_OFF 0xac
#define MAX_TIMER_VECTOR_TABLE_NUM 6
#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value)
_LONG_CALL_ u32
HalGetTimerIdRtl8195a(
IN u32 *TimerID
);
_LONG_CALL_ BOOL
HalTimerInitRtl8195a(
IN VOID *Data
);
_LONG_CALL_ u32
HalTimerReadCountRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerIrqClearRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDisRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerEnRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDumpRegRtl8195a(
IN u32 TimerId
);
// ROM Code patch
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
);
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
);
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
);
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
);
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
__weak _LONG_CALL_
VOID
HalTimerIrq2To7HandleV02(
IN VOID *Data
);
__weak _LONG_CALL_ROM_
HAL_Status
HalTimerIrqRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
HAL_Status
HalTimerInitRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
u32
HalTimerReadCountRtl8195aV02(
IN u32 TimerId
);
__weak _LONG_CALL_
VOID
HalTimerReLoadRtl8195aV02(
IN u32 TimerId,
IN u32 LoadUs
);
__weak _LONG_CALL_ROM_
HAL_Status
HalTimerIrqUnRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
VOID
HalTimerDeInitRtl8195aV02(
IN VOID *Data
);
#endif // end of "#ifdef CONFIG_CHIP_C_CUT"
#ifdef CONFIG_CHIP_E_CUT
_LONG_CALL_ VOID
HalTimerReLoadRtl8195a_V04(
IN u32 TimerId,
IN u32 LoadUs
);
_LONG_CALL_ HAL_Status
HalTimerInitRtl8195a_V04(
IN VOID *Data
);
#endif // #ifdef CONFIG_CHIP_E_CUT
// HAL functions wrapper
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
static __inline HAL_Status
HalTimerInit(
IN VOID *Data
)
{
#ifdef CONFIG_CHIP_E_CUT
return (HalTimerInitRtl8195a_V04(Data));
#else
return (HalTimerInitRtl8195a_Patch(Data));
#endif
}
static __inline VOID
HalTimerEnable(
IN u32 TimerId
)
{
HalTimerIrqEnRtl8195a(TimerId);
HalTimerEnRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerDisable(
IN u32 TimerId
)
{
HalTimerDisRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerClearIsr(
IN u32 TimerId
)
{
HalTimerClearIsrRtl8195a(TimerId);
}
static __inline VOID
HalTimerReLoad(
IN u32 TimerId,
IN u32 LoadUs
)
{
#ifdef CONFIG_CHIP_E_CUT
HalTimerReLoadRtl8195a_V04(TimerId, LoadUs);
#else
HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs);
#endif
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195a_Patch(Data);
}
#else
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195aV02(Data);
}
#endif // end of "#ifndef CONFIG_CHIP_C_CUT"
#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#endif //_RTL8195A_TIMER_H_
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_TIMER_H_
#define _RTL8195A_TIMER_H_
#define TIMER_TICK_US 31
#define TIMER_LOAD_COUNT_OFF 0x00
#define TIMER_CURRENT_VAL_OFF 0x04
#define TIMER_CTL_REG_OFF 0x08
#define TIMER_EOI_OFF 0x0c
#define TIMER_INT_STATUS_OFF 0x10
#define TIMER_INTERVAL 0x14
#define TIMERS_INT_STATUS_OFF 0xa0
#define TIMERS_EOI_OFF 0xa4
#define TIMERS_RAW_INT_STATUS_OFF 0xa8
#define TIMERS_COMP_VER_OFF 0xac
#define MAX_TIMER_VECTOR_TABLE_NUM 6
#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value)
_LONG_CALL_ u32
HalGetTimerIdRtl8195a(
IN u32 *TimerID
);
_LONG_CALL_ BOOL
HalTimerInitRtl8195a(
IN VOID *Data
);
_LONG_CALL_ u32
HalTimerReadCountRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerIrqClearRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDisRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerEnRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDumpRegRtl8195a(
IN u32 TimerId
);
// ROM Code patch
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
);
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
);
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
);
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
);
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
__weak _LONG_CALL_
VOID
HalTimerIrq2To7HandleV02(
IN VOID *Data
);
__weak _LONG_CALL_ROM_
HAL_Status
HalTimerIrqRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
HAL_Status
HalTimerInitRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
u32
HalTimerReadCountRtl8195aV02(
IN u32 TimerId
);
__weak _LONG_CALL_
VOID
HalTimerReLoadRtl8195aV02(
IN u32 TimerId,
IN u32 LoadUs
);
__weak _LONG_CALL_ROM_
HAL_Status
HalTimerIrqUnRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
VOID
HalTimerDeInitRtl8195aV02(
IN VOID *Data
);
#endif // end of "#ifdef CONFIG_CHIP_C_CUT"
#ifdef CONFIG_CHIP_E_CUT
_LONG_CALL_ VOID
HalTimerReLoadRtl8195a_V04(
IN u32 TimerId,
IN u32 LoadUs
);
_LONG_CALL_ HAL_Status
HalTimerInitRtl8195a_V04(
IN VOID *Data
);
#endif // #ifdef CONFIG_CHIP_E_CUT
// HAL functions wrapper
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
static __inline HAL_Status
HalTimerInit(
IN VOID *Data
)
{
#ifdef CONFIG_CHIP_E_CUT
return (HalTimerInitRtl8195a_V04(Data));
#else
return (HalTimerInitRtl8195a_Patch(Data));
#endif
}
static __inline VOID
HalTimerEnable(
IN u32 TimerId
)
{
HalTimerIrqEnRtl8195a(TimerId);
HalTimerEnRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerDisable(
IN u32 TimerId
)
{
HalTimerDisRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerClearIsr(
IN u32 TimerId
)
{
HalTimerClearIsrRtl8195a(TimerId);
}
static __inline VOID
HalTimerReLoad(
IN u32 TimerId,
IN u32 LoadUs
)
{
#ifdef CONFIG_CHIP_E_CUT
HalTimerReLoadRtl8195a_V04(TimerId, LoadUs);
#else
HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs);
#endif
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195a_Patch(Data);
}
#else
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195aV02(Data);
}
#endif // end of "#ifndef CONFIG_CHIP_C_CUT"
#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#endif //_RTL8195A_TIMER_H_

172
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_wdt.h
View file

@ -1,86 +1,86 @@
/*
* Routines to access hardware
*
* Copyright (c) 2014 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_WDT_H_
#define _RTL8195A_WDT_H_
#define WDGTIMERELY (10*1024) //us
typedef struct _WDG_REG_ {
u16 WdgScalar;
u8 WdgEnByte;
u8 WdgClear:1;
u8 WdgCunLimit:4;
u8 Rsvd:1;
u8 WdgMode:1;
u8 WdgToISR:1;
}WDG_REG, *PWDG_REG;
typedef struct _WDG_ADAPTER_ {
WDG_REG Ctrl;
IRQ_HANDLE IrqHandle;
TIMER_ADAPTER WdgGTimer;
VOID (*UserCallback)(u32 callback_id); // User callback function
u32 callback_id;
}WDG_ADAPTER, *PWDG_ADAPTER;
typedef enum _WDG_CNTLMT_ {
CNT1H = 0,
CNT3H = 1,
CNT7H = 2,
CNTFH = 3,
CNT1FH = 4,
CNT3FH = 5,
CNT7FH = 6,
CNTFFH = 7,
CNT1FFH = 8,
CNT3FFH = 9,
CNT7FFH = 10,
CNTFFFH = 11
}WDG_CNTLMT, *PWDG_CNTLMT;
typedef enum _WDG_MODE_ {
INT_MODE = 0,
RESET_MODE = 1
}WDG_MODE, *PWDG_MODE;
extern VOID
WDGInitial(
IN u32 Period
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGStop(
VOID
);
extern VOID
WDGRefresh(
VOID
);
extern VOID
WDGIrqCallBackReg(
IN VOID *CallBack,
IN u32 Id
);
#endif //_RTL8195A_WDT_H_
/*
* Routines to access hardware
*
* Copyright (c) 2014 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_WDT_H_
#define _RTL8195A_WDT_H_
#define WDGTIMERELY (10*1024) //us
typedef struct _WDG_REG_ {
u16 WdgScalar;
u8 WdgEnByte;
u8 WdgClear:1;
u8 WdgCunLimit:4;
u8 Rsvd:1;
u8 WdgMode:1;
u8 WdgToISR:1;
}WDG_REG, *PWDG_REG;
typedef struct _WDG_ADAPTER_ {
WDG_REG Ctrl;
IRQ_HANDLE IrqHandle;
TIMER_ADAPTER WdgGTimer;
VOID (*UserCallback)(u32 callback_id); // User callback function
u32 callback_id;
}WDG_ADAPTER, *PWDG_ADAPTER;
typedef enum _WDG_CNTLMT_ {
CNT1H = 0,
CNT3H = 1,
CNT7H = 2,
CNTFH = 3,
CNT1FH = 4,
CNT3FH = 5,
CNT7FH = 6,
CNTFFH = 7,
CNT1FFH = 8,
CNT3FFH = 9,
CNT7FFH = 10,
CNTFFFH = 11
}WDG_CNTLMT, *PWDG_CNTLMT;
typedef enum _WDG_MODE_ {
INT_MODE = 0,
RESET_MODE = 1
}WDG_MODE, *PWDG_MODE;
extern VOID
WDGInitial(
IN u32 Period
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGStop(
VOID
);
extern VOID
WDGRefresh(
VOID
);
extern VOID
WDGIrqCallBackReg(
IN VOID *CallBack,
IN u32 Id
);
#endif //_RTL8195A_WDT_H_

582
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c
View file

@ -1,291 +1,291 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_gdma.h"
#include "hal_gdma.h"
#ifndef CONFIG_CHIP_E_CUT
BOOL
HalGdmaChBlockSetingRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pGdmaChLli;
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 ChEn = pHalGdmaAdapter->ChEn;
u8 GdmaChIsrBitmap = (ChEn & 0xFF);
u8 PendingIsrIndex;
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
//4 1) Check chanel is avaliable
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
//4 Disable Channel
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
HalGdmaChDisRtl8195a(Data);
}
//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
u32 PendRaw, PendStstus;
PendRaw = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
PendStstus = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
//4 Clear Pending Isr
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
(PendStstus & (GdmaChIsrBitmap))
);
}
}
//4 Fill in SARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChSar)
);
//4 Fill in DARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChDar)
);
//4 3) Process CTLx
CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
//4 Clear Config low register bits
CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
BIT_INVC_CTLX_LO_DST_TR_WIDTH &
BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
BIT_INVC_CTLX_LO_DINC &
BIT_INVC_CTLX_LO_SINC &
BIT_INVC_CTLX_LO_DEST_MSIZE &
BIT_INVC_CTLX_LO_SRC_MSIZE &
BIT_INVC_CTLX_LO_TT_FC &
BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
//4 Clear Config upper register bits
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
BIT_INVC_CTLX_UP_DONE);
CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
CtlxLow;
CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
CtlxUp;
//4 Fill in CTLx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
CtlxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
CtlxUp
);
//4 4) Program CFGx
CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
BIT_INVC_CFGX_LO_CH_SUSP &
BIT_INVC_CFGX_LO_HS_SEL_DST &
BIT_INVC_CFGX_LO_HS_SEL_SRC &
BIT_INVC_CFGX_LO_LOCK_CH_L &
BIT_INVC_CFGX_LO_LOCK_B_L &
BIT_INVC_CFGX_LO_LOCK_CH &
BIT_INVC_CFGX_LO_LOCK_B &
BIT_INVC_CFGX_LO_RELOAD_SRC &
BIT_INVC_CFGX_LO_RELOAD_DST);
CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
BIT_INVC_CFGX_UP_DS_UPD_EN &
BIT_INVC_CFGX_UP_SS_UPD_EN &
BIT_INVC_CFGX_UP_SRC_PER &
BIT_INVC_CFGX_UP_DEST_PER);
CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
CfgxLow;
CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
CfgxUp;
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
CfgxUp
);
//4 Check 4 Bytes Alignment
if ((u32)(pLliEle) & 0x3) {
DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n",
pHalGdmaAdapter->pLli);
return _FALSE;
}
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
pLliEle
);
//4 Update the first llp0
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
while (MultiBlockCount > 1) {
MultiBlockCount--;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pLliEle = pGdmaChLli->pLliEle;
if (NULL == pLliEle) {
DBG_GDMA_ERR("pLliEle Null Point!!!!!\n");
return _FALSE;
}
//4 Clear the last element llp enable bit
if (1 == MultiBlockCount) {
if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 1){
CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
}
}
//4 Update block size for transfer
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
//4 Update tje Lli and Block size list point to next llp
pGdmaChLli = pGdmaChLli->pNextLli;
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
//4 Updatethe Llpx context
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
}
return _TRUE;
}
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
if (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN) & (pHalGdmaAdapter->ChEn)) {
return 1;
} else {
return 0;
}
}
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_gdma.h"
#include "hal_gdma.h"
#ifndef CONFIG_CHIP_E_CUT
BOOL
HalGdmaChBlockSetingRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pGdmaChLli;
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 ChEn = pHalGdmaAdapter->ChEn;
u8 GdmaChIsrBitmap = (ChEn & 0xFF);
u8 PendingIsrIndex;
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
//4 1) Check chanel is avaliable
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
//4 Disable Channel
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
HalGdmaChDisRtl8195a(Data);
}
//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
u32 PendRaw, PendStstus;
PendRaw = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
PendStstus = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
//4 Clear Pending Isr
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
(PendStstus & (GdmaChIsrBitmap))
);
}
}
//4 Fill in SARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChSar)
);
//4 Fill in DARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChDar)
);
//4 3) Process CTLx
CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
//4 Clear Config low register bits
CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
BIT_INVC_CTLX_LO_DST_TR_WIDTH &
BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
BIT_INVC_CTLX_LO_DINC &
BIT_INVC_CTLX_LO_SINC &
BIT_INVC_CTLX_LO_DEST_MSIZE &
BIT_INVC_CTLX_LO_SRC_MSIZE &
BIT_INVC_CTLX_LO_TT_FC &
BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
//4 Clear Config upper register bits
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
BIT_INVC_CTLX_UP_DONE);
CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
CtlxLow;
CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
CtlxUp;
//4 Fill in CTLx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
CtlxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
CtlxUp
);
//4 4) Program CFGx
CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
BIT_INVC_CFGX_LO_CH_SUSP &
BIT_INVC_CFGX_LO_HS_SEL_DST &
BIT_INVC_CFGX_LO_HS_SEL_SRC &
BIT_INVC_CFGX_LO_LOCK_CH_L &
BIT_INVC_CFGX_LO_LOCK_B_L &
BIT_INVC_CFGX_LO_LOCK_CH &
BIT_INVC_CFGX_LO_LOCK_B &
BIT_INVC_CFGX_LO_RELOAD_SRC &
BIT_INVC_CFGX_LO_RELOAD_DST);
CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
BIT_INVC_CFGX_UP_DS_UPD_EN &
BIT_INVC_CFGX_UP_SS_UPD_EN &
BIT_INVC_CFGX_UP_SRC_PER &
BIT_INVC_CFGX_UP_DEST_PER);
CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
CfgxLow;
CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
CfgxUp;
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
CfgxUp
);
//4 Check 4 Bytes Alignment
if ((u32)(pLliEle) & 0x3) {
DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n",
pHalGdmaAdapter->pLli);
return _FALSE;
}
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
pLliEle
);
//4 Update the first llp0
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
while (MultiBlockCount > 1) {
MultiBlockCount--;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pLliEle = pGdmaChLli->pLliEle;
if (NULL == pLliEle) {
DBG_GDMA_ERR("pLliEle Null Point!!!!!\n");
return _FALSE;
}
//4 Clear the last element llp enable bit
if (1 == MultiBlockCount) {
if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 1){
CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
}
}
//4 Update block size for transfer
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
//4 Update tje Lli and Block size list point to next llp
pGdmaChLli = pGdmaChLli->pNextLli;
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
//4 Updatethe Llpx context
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
}
return _TRUE;
}
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
if (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN) & (pHalGdmaAdapter->ChEn)) {
return 1;
} else {
return 0;
}
}
#endif

718
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c
View file

@ -1,359 +1,359 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_pcm.h"
#include "hal_pcm.h"
extern void *
_memset( void *s, int c, SIZE_T n );
VOID
HalPcmOnOffRtl8195a (
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
//todo on off pcm
}
//default sampling rate 8khz, linear, 10ms frame size, time slot 0 , tx+rx
// master mode, enable endian swap
// Question: need local tx/rx page?
BOOL
HalPcmInitRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
_memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER));
//4 1) Initial PcmChCNR03 Register
pHalPcmAdapter->PcmChCNR03.CH0MuA = 0;
pHalPcmAdapter->PcmChCNR03.CH0Band = 0;
//4 1) Initial PcmTSR03 Register
pHalPcmAdapter->PcmTSR03.CH0TSA = 0;
//4 1) Initial PcmBSize03 Register
pHalPcmAdapter->PcmBSize03.CH0BSize = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte
//4 2) Initial Ctl Register
pHalPcmAdapter->PcmCtl.Pcm_En = 1;
pHalPcmAdapter->PcmCtl.SlaveMode = 0;
pHalPcmAdapter->PcmCtl.FsInv = 0;
pHalPcmAdapter->PcmCtl.LinearMode = 0;
pHalPcmAdapter->PcmCtl.LoopBack = 0;
pHalPcmAdapter->PcmCtl.EndianSwap = 1;
return _TRUE;
}
BOOL
HalPcmSettingRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03;
u32 Isr03;
PcmCh=0;
//4 1) Check Pcm index is avaliable
if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
//4 2) Check if there are the pending isr
Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03);
Isr03 &= 0xff000000;
//4 Clear Pending Isr
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03);
//}
//4 3) Process RegCtl
RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL);
//4 Clear Ctl register bits
RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL &
BIT_INV_CTLX_FSINV &
BIT_INV_CTLX_PCM_EN &
BIT_INV_CTLX_LINEARMODE &
BIT_INV_CTLX_LOOP_BACK &
BIT_INV_CTLX_ENDIAN_SWAP);
RegCtl = BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) |
BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) |
BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) |
BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) |
BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) |
BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) |
RegCtl;
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl);
//4 4) Program ChCNR03 Register
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE &
BIT_INV_CHCNR03_CH0TE &
BIT_INV_CHCNR03_CH0MUA &
BIT_INV_CHCNR03_CH0BAND);
RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) |
BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) |
BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) |
BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) |
RegChCNR03;
DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03);
// time slot
RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03);
RegTSR03 &= (BIT_INV_TSR03_CH0TSA);
RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) |
RegTSR03;
DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03);
// buffer size
RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03);
RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE);
RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) |
RegBSize03;
DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03);
return _TRUE;
}
BOOL
HalPcmEnRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 1;
//4 1) Check Pcm index is avaliable
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
if (RegChCNR03 & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25);
pHalPcmAdapter->PcmChCNR03.CH0RE = 1;
pHalPcmAdapter->PcmChCNR03.CH0TE = 1;
return _TRUE;
}
BOOL
HalPcmDisRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 0;
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25)));
pHalPcmAdapter->PcmChCNR03.CH0RE = 0;
pHalPcmAdapter->PcmChCNR03.CH0TE = 0;
return _TRUE;
}
BOOL
HalPcmIsrEnAndDisRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrMask, Addr, IsrCtrl;
u8 IsrTypeIndex = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
Addr = (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8);
IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr);
IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask):
((~pHalGdmaAdapter->ChEn) & IsrMask));
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
Addr,
IsrCtrl
);
}
}
*/
return _TRUE;
}
BOOL
HalPcmDumpRegRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
BOOL
HalPcmRtl8195a (
IN VOID *Data
)
{
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
~(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
/*
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrStatus;
u8 IsrTypeIndex = 0, IsrActBitMap = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8));
// DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus);
IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF));
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)),
(IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF))
);
IsrActBitMap |= BIT_(IsrTypeIndex);
}
}
return IsrActBitMap;
}
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
*/
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_pcm.h"
#include "hal_pcm.h"
extern void *
_memset( void *s, int c, SIZE_T n );
VOID
HalPcmOnOffRtl8195a (
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
//todo on off pcm
}
//default sampling rate 8khz, linear, 10ms frame size, time slot 0 , tx+rx
// master mode, enable endian swap
// Question: need local tx/rx page?
BOOL
HalPcmInitRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
_memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER));
//4 1) Initial PcmChCNR03 Register
pHalPcmAdapter->PcmChCNR03.CH0MuA = 0;
pHalPcmAdapter->PcmChCNR03.CH0Band = 0;
//4 1) Initial PcmTSR03 Register
pHalPcmAdapter->PcmTSR03.CH0TSA = 0;
//4 1) Initial PcmBSize03 Register
pHalPcmAdapter->PcmBSize03.CH0BSize = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte
//4 2) Initial Ctl Register
pHalPcmAdapter->PcmCtl.Pcm_En = 1;
pHalPcmAdapter->PcmCtl.SlaveMode = 0;
pHalPcmAdapter->PcmCtl.FsInv = 0;
pHalPcmAdapter->PcmCtl.LinearMode = 0;
pHalPcmAdapter->PcmCtl.LoopBack = 0;
pHalPcmAdapter->PcmCtl.EndianSwap = 1;
return _TRUE;
}
BOOL
HalPcmSettingRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03;
u32 Isr03;
PcmCh=0;
//4 1) Check Pcm index is avaliable
if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
//4 2) Check if there are the pending isr
Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03);
Isr03 &= 0xff000000;
//4 Clear Pending Isr
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03);
//}
//4 3) Process RegCtl
RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL);
//4 Clear Ctl register bits
RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL &
BIT_INV_CTLX_FSINV &
BIT_INV_CTLX_PCM_EN &
BIT_INV_CTLX_LINEARMODE &
BIT_INV_CTLX_LOOP_BACK &
BIT_INV_CTLX_ENDIAN_SWAP);
RegCtl = BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) |
BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) |
BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) |
BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) |
BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) |
BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) |
RegCtl;
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl);
//4 4) Program ChCNR03 Register
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE &
BIT_INV_CHCNR03_CH0TE &
BIT_INV_CHCNR03_CH0MUA &
BIT_INV_CHCNR03_CH0BAND);
RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) |
BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) |
BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) |
BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) |
RegChCNR03;
DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03);
// time slot
RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03);
RegTSR03 &= (BIT_INV_TSR03_CH0TSA);
RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) |
RegTSR03;
DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03);
// buffer size
RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03);
RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE);
RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) |
RegBSize03;
DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03);
return _TRUE;
}
BOOL
HalPcmEnRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 1;
//4 1) Check Pcm index is avaliable
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
if (RegChCNR03 & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25);
pHalPcmAdapter->PcmChCNR03.CH0RE = 1;
pHalPcmAdapter->PcmChCNR03.CH0TE = 1;
return _TRUE;
}
BOOL
HalPcmDisRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 0;
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25)));
pHalPcmAdapter->PcmChCNR03.CH0RE = 0;
pHalPcmAdapter->PcmChCNR03.CH0TE = 0;
return _TRUE;
}
BOOL
HalPcmIsrEnAndDisRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrMask, Addr, IsrCtrl;
u8 IsrTypeIndex = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
Addr = (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8);
IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr);
IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask):
((~pHalGdmaAdapter->ChEn) & IsrMask));
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
Addr,
IsrCtrl
);
}
}
*/
return _TRUE;
}
BOOL
HalPcmDumpRegRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
BOOL
HalPcmRtl8195a (
IN VOID *Data
)
{
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
~(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
/*
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrStatus;
u8 IsrTypeIndex = 0, IsrActBitMap = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8));
// DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus);
IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF));
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)),
(IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF))
);
IsrActBitMap |= BIT_(IsrTypeIndex);
}
}
return IsrActBitMap;
}
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
*/

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component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
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component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_timer.c
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@ -1,340 +1,340 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_timer.h"
extern u32 gTimerRecord;
extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM];
#ifdef CONFIG_CHIP_A_CUT
HAL_RAM_BSS_SECTION u32 gTimerRecord;
#endif
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#else
u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#endif
VOID
HalTimerIrq2To7Handle_Patch(
IN VOID *Data
)
{
u32 TimerIrqStatus = 0, CheckIndex;
IRQ_FUN pHandler;
TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF);
DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus);
for (CheckIndex = 2; CheckIndex<8; CheckIndex++) {
//3 Check IRQ status bit and Timer X IRQ enable bit
if ((TimerIrqStatus & BIT_(CheckIndex)) &&
(HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) {
//3 Execute Timer callback function
pHandler = Timer2To7VectorTable[CheckIndex-2];
if (pHandler != NULL) {
pHandler((void*)Timer2To7HandlerData[CheckIndex-2]);
}
//3 Clear Timer ISR
HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF);
}
}
}
HAL_Status
HalTimerIrqRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
IRQ_HANDLE TimerIrqHandle;
//IRQ_FUN BackUpIrqFun = NULL;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
TimerIrqHandle.IrqNum = TIMER2_7_IRQ;
TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] =
(IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
Timer2To7HandlerData[pHalTimerAdap->TimerId-2] =
(uint32_t) pHalTimerAdap->IrqHandle.Data;
}
else {
TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
}
TimerIrqHandle.Data = (u32)pHalTimerAdap;
InterruptRegister(&TimerIrqHandle);
}
return HAL_OK;
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
// Patch for A/B Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
u32 ControlReg;
if ((gTimerRecord & (1<<pHalTimerAdap->TimerId)) != 0) {
DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_BUSY;
}
//4 1) Config Timer Setting
ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2);
/*
set TimerControlReg
0: Timer enable (0,disable; 1,enable)
1: Timer Mode (0, free-running mode; 1, user-defined count mode)
2: Timer Interrupt Mask (0, not masked; 1,masked)
*/
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
ControlReg);
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
else {
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF),
0xFFFFFFFF);
}
//4 2) Setting Timer IRQ
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
//4 2.1) Initial TimerIRQHandle
ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap);
if (HAL_OK != ret) {
DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return ret;
}
//4 2.2) Enable TimerIRQ for Platform
InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
}
else {
DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
}
//4 4) Enable Timer
// HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
// (ControlReg|0x1));
gTimerRecord |= (1<<pHalTimerAdap->TimerId);
return ret;
}
#elif defined(CONFIG_CHIP_C_CUT)
// Patch for C Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
ret = HalTimerInitRtl8195aV02(Data);
// Patch the Rom code to load the correct count value
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
return ret;
}
#endif
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
HAL_Status
HalTimerIrqUnRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
PIRQ_HANDLE pTimerIrqHandle;
u32 i;
pTimerIrqHandle = &pHalTimerAdap->IrqHandle;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
pTimerIrqHandle->IrqNum = TIMER2_7_IRQ;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL;
for (i=0;i<MAX_TIMER_VECTOR_TABLE_NUM;i++) {
if (Timer2To7VectorTable[i] != NULL) {
break;
}
}
if (i == MAX_TIMER_VECTOR_TABLE_NUM) {
// All timer UnRegister Interrupt
InterruptDis((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
InterruptUnRegister(pTimerIrqHandle);
}
}
else {
pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
InterruptUnRegister(pTimerIrqHandle);
}
}
return HAL_OK;
}
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
u32 timer_id;
timer_id = pHalTimerAdap->TimerId;
HalTimerDisRtl8195a (timer_id);
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap);
}
}
gTimerRecord &= ~(1<<pHalTimerAdap->TimerId);
}
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
)
{
u32 TimerCountOld;
u32 TimerCountNew;
u32 TimerRDCnt;
TimerRDCnt = 0;
TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
while(1) {
TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
if (TimerCountOld == TimerCountNew) {
return (u32)TimerCountOld;
}
else {
TimerRDCnt++;
TimerCountOld = TimerCountNew;
if (TimerRDCnt >= 2){
return (u32)TimerCountOld;
}
}
}
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
)
{
u32 LoadCount = 0;
u32 ms125; // how many 125ms
u32 remain_us;
ms125 = LoadUs/125000;
remain_us = LoadUs - (ms125*125000);
LoadCount = ms125 * (GTIMER_CLK_HZ/8);
LoadCount += (remain_us*GTIMER_CLK_HZ)/1000000;
if (LoadCount == 0) {
LoadCount = 1;
}
// DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount);
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF),
LoadCount);
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~(BIT2)));
}
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT2));
}
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_EOI_OFF);
}
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT0));
}
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
)
{
// Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~BIT0));
}
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_timer.h"
extern u32 gTimerRecord;
extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM];
#ifdef CONFIG_CHIP_A_CUT
HAL_RAM_BSS_SECTION u32 gTimerRecord;
#endif
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#else
u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#endif
VOID
HalTimerIrq2To7Handle_Patch(
IN VOID *Data
)
{
u32 TimerIrqStatus = 0, CheckIndex;
IRQ_FUN pHandler;
TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF);
DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus);
for (CheckIndex = 2; CheckIndex<8; CheckIndex++) {
//3 Check IRQ status bit and Timer X IRQ enable bit
if ((TimerIrqStatus & BIT_(CheckIndex)) &&
(HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) {
//3 Execute Timer callback function
pHandler = Timer2To7VectorTable[CheckIndex-2];
if (pHandler != NULL) {
pHandler((void*)Timer2To7HandlerData[CheckIndex-2]);
}
//3 Clear Timer ISR
HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF);
}
}
}
HAL_Status
HalTimerIrqRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
IRQ_HANDLE TimerIrqHandle;
//IRQ_FUN BackUpIrqFun = NULL;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
TimerIrqHandle.IrqNum = TIMER2_7_IRQ;
TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] =
(IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
Timer2To7HandlerData[pHalTimerAdap->TimerId-2] =
(uint32_t) pHalTimerAdap->IrqHandle.Data;
}
else {
TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
}
TimerIrqHandle.Data = (u32)pHalTimerAdap;
InterruptRegister(&TimerIrqHandle);
}
return HAL_OK;
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
// Patch for A/B Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
u32 ControlReg;
if ((gTimerRecord & (1<<pHalTimerAdap->TimerId)) != 0) {
DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_BUSY;
}
//4 1) Config Timer Setting
ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2);
/*
set TimerControlReg
0: Timer enable (0,disable; 1,enable)
1: Timer Mode (0, free-running mode; 1, user-defined count mode)
2: Timer Interrupt Mask (0, not masked; 1,masked)
*/
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
ControlReg);
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
else {
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF),
0xFFFFFFFF);
}
//4 2) Setting Timer IRQ
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
//4 2.1) Initial TimerIRQHandle
ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap);
if (HAL_OK != ret) {
DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return ret;
}
//4 2.2) Enable TimerIRQ for Platform
InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
}
else {
DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
}
//4 4) Enable Timer
// HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
// (ControlReg|0x1));
gTimerRecord |= (1<<pHalTimerAdap->TimerId);
return ret;
}
#elif defined(CONFIG_CHIP_C_CUT)
// Patch for C Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
ret = HalTimerInitRtl8195aV02(Data);
// Patch the Rom code to load the correct count value
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
return ret;
}
#endif
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
HAL_Status
HalTimerIrqUnRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
PIRQ_HANDLE pTimerIrqHandle;
u32 i;
pTimerIrqHandle = &pHalTimerAdap->IrqHandle;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
pTimerIrqHandle->IrqNum = TIMER2_7_IRQ;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL;
for (i=0;i<MAX_TIMER_VECTOR_TABLE_NUM;i++) {
if (Timer2To7VectorTable[i] != NULL) {
break;
}
}
if (i == MAX_TIMER_VECTOR_TABLE_NUM) {
// All timer UnRegister Interrupt
InterruptDis((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
InterruptUnRegister(pTimerIrqHandle);
}
}
else {
pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
InterruptUnRegister(pTimerIrqHandle);
}
}
return HAL_OK;
}
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
u32 timer_id;
timer_id = pHalTimerAdap->TimerId;
HalTimerDisRtl8195a (timer_id);
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap);
}
}
gTimerRecord &= ~(1<<pHalTimerAdap->TimerId);
}
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
)
{
u32 TimerCountOld;
u32 TimerCountNew;
u32 TimerRDCnt;
TimerRDCnt = 0;
TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
while(1) {
TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
if (TimerCountOld == TimerCountNew) {
return (u32)TimerCountOld;
}
else {
TimerRDCnt++;
TimerCountOld = TimerCountNew;
if (TimerRDCnt >= 2){
return (u32)TimerCountOld;
}
}
}
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
)
{
u32 LoadCount = 0;
u32 ms125; // how many 125ms
u32 remain_us;
ms125 = LoadUs/125000;
remain_us = LoadUs - (ms125*125000);
LoadCount = ms125 * (GTIMER_CLK_HZ/8);
LoadCount += (remain_us*GTIMER_CLK_HZ)/1000000;
if (LoadCount == 0) {
LoadCount = 1;
}
// DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount);
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF),
LoadCount);
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~(BIT2)));
}
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT2));
}
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_EOI_OFF);
}
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT0));
}
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
)
{
// Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~BIT0));
}