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motify compile link error

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motify compile link error
This commit is contained in:
ant 2016-09-18 09:03:25 +08:00
parent 923914edae
commit 03e74a8e50
5418 changed files with 1367914 additions and 206149 deletions
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252
component/soc/realtek/8195a/fwlib/hal_api.h
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@ -1,126 +1,126 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_API_H_
#define _HAL_API_H_
#include "basic_types.h"
#include "hal_irqn.h"
#define HAL_READ32(base, addr) \
rtk_le32_to_cpu(*((volatile u32*)(base + addr)))
#define HAL_WRITE32(base, addr, value32) \
((*((volatile u32*)(base + addr))) = rtk_cpu_to_le32(value32))
#define HAL_READ16(base, addr) \
rtk_le16_to_cpu(*((volatile u16*)(base + addr)))
#define HAL_WRITE16(base, addr, value) \
((*((volatile u16*)(base + addr))) = rtk_cpu_to_le16(value))
#define HAL_READ8(base, addr) \
(*((volatile u8*)(base + addr)))
#define HAL_WRITE8(base, addr, value) \
((*((volatile u8*)(base + addr))) = value)
#if 0
// These "extern _LONG_CALL_" function declaration are for RAM code building only
// For ROM code building, thses code should be marked off
extern _LONG_CALL_ u8
HalPinCtrlRtl8195A(
IN u32 Function,
IN u32 PinLocation,
IN BOOL Operation
);
extern _LONG_CALL_ VOID
HalSerialPutcRtl8195a(
IN u8 c
);
extern _LONG_CALL_ u8
HalSerialGetcRtl8195a(
IN BOOL PullMode
);
extern _LONG_CALL_ u32
HalSerialGetIsrEnRegRtl8195a(VOID);
extern _LONG_CALL_ VOID
HalSerialSetIrqEnRegRtl8195a (
IN u32 SetValue
);
extern _LONG_CALL_ VOID
VectorTableInitForOSRtl8195A(
IN VOID *PortSVC,
IN VOID *PortPendSVH,
IN VOID *PortSysTick
);
extern _LONG_CALL_ BOOL
VectorIrqRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ BOOL
VectorIrqUnRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ VOID
VectorIrqEnRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ VOID
VectorIrqDisRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
#endif
extern BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
extern VOID InitWDGIRQ(VOID);
#define PinCtrl HalPinCtrlRtl8195A
#define DiagPutChar HalSerialPutcRtl8195a
#define DiagGetChar HalSerialGetcRtl8195a
#define DiagGetIsrEnReg HalSerialGetIsrEnRegRtl8195a
#define DiagSetIsrEnReg HalSerialSetIrqEnRegRtl8195a
#define InterruptForOSInit VectorTableInitForOSRtl8195A
#define InterruptRegister VectorIrqRegisterRtl8195A
#define InterruptUnRegister VectorIrqUnRegisterRtl8195A
#define InterruptEn VectorIrqEnRtl8195A
#define InterruptDis VectorIrqDisRtl8195A
#define SpicFlashInit SpicFlashInitRtl8195A
#define Calibration32k En32KCalibration
#define WDGInit InitWDGIRQ
typedef enum _HAL_Status
{
HAL_OK = 0x00,
HAL_BUSY = 0x01,
HAL_TIMEOUT = 0x02,
HAL_ERR_PARA = 0x03, // error with invaild parameters
HAL_ERR_MEM = 0x04, // error with memory allocation failed
HAL_ERR_HW = 0x05, // error with hardware error
HAL_ERR_UNKNOWN = 0xee // unknown error
} HAL_Status;
#endif //_HAL_API_H_
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_API_H_
#define _HAL_API_H_
#include "basic_types.h"
#include "hal_irqn.h"
#define HAL_READ32(base, addr) \
rtk_le32_to_cpu(*((volatile u32*)(base + addr)))
#define HAL_WRITE32(base, addr, value32) \
((*((volatile u32*)(base + addr))) = rtk_cpu_to_le32(value32))
#define HAL_READ16(base, addr) \
rtk_le16_to_cpu(*((volatile u16*)(base + addr)))
#define HAL_WRITE16(base, addr, value) \
((*((volatile u16*)(base + addr))) = rtk_cpu_to_le16(value))
#define HAL_READ8(base, addr) \
(*((volatile u8*)(base + addr)))
#define HAL_WRITE8(base, addr, value) \
((*((volatile u8*)(base + addr))) = value)
#if 0
// These "extern _LONG_CALL_" function declaration are for RAM code building only
// For ROM code building, thses code should be marked off
extern _LONG_CALL_ u8
HalPinCtrlRtl8195A(
IN u32 Function,
IN u32 PinLocation,
IN BOOL Operation
);
extern _LONG_CALL_ VOID
HalSerialPutcRtl8195a(
IN u8 c
);
extern _LONG_CALL_ u8
HalSerialGetcRtl8195a(
IN BOOL PullMode
);
extern _LONG_CALL_ u32
HalSerialGetIsrEnRegRtl8195a(VOID);
extern _LONG_CALL_ VOID
HalSerialSetIrqEnRegRtl8195a (
IN u32 SetValue
);
extern _LONG_CALL_ VOID
VectorTableInitForOSRtl8195A(
IN VOID *PortSVC,
IN VOID *PortPendSVH,
IN VOID *PortSysTick
);
extern _LONG_CALL_ BOOL
VectorIrqRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ BOOL
VectorIrqUnRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ VOID
VectorIrqEnRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ VOID
VectorIrqDisRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
#endif
extern BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
extern VOID InitWDGIRQ(VOID);
#define PinCtrl HalPinCtrlRtl8195A
#define DiagPutChar HalSerialPutcRtl8195a
#define DiagGetChar HalSerialGetcRtl8195a
#define DiagGetIsrEnReg HalSerialGetIsrEnRegRtl8195a
#define DiagSetIsrEnReg HalSerialSetIrqEnRegRtl8195a
#define InterruptForOSInit VectorTableInitForOSRtl8195A
#define InterruptRegister VectorIrqRegisterRtl8195A
#define InterruptUnRegister VectorIrqUnRegisterRtl8195A
#define InterruptEn VectorIrqEnRtl8195A
#define InterruptDis VectorIrqDisRtl8195A
#define SpicFlashInit SpicFlashInitRtl8195A
#define Calibration32k En32KCalibration
#define WDGInit InitWDGIRQ
typedef enum _HAL_Status
{
HAL_OK = 0x00,
HAL_BUSY = 0x01,
HAL_TIMEOUT = 0x02,
HAL_ERR_PARA = 0x03, // error with invaild parameters
HAL_ERR_MEM = 0x04, // error with memory allocation failed
HAL_ERR_HW = 0x05, // error with hardware error
HAL_ERR_UNKNOWN = 0xee // unknown error
} HAL_Status;
#endif //_HAL_API_H_

214
component/soc/realtek/8195a/fwlib/hal_diag.h
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@ -1,107 +1,107 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_DIAG_H_
#define _HAL_DIAG_H_
//Register offset
#define UART_REV_BUF_OFF 0x00
#define UART_TRAN_HOLD_OFF 0x00
#define UART_DLH_OFF 0x04
#define UART_DLL_OFF 0x00
#define UART_INTERRUPT_EN_REG_OFF 0x04
#define UART_INTERRUPT_IDEN_REG_OFF 0x08
#define UART_FIFO_CTL_REG_OFF 0x08
#define UART_LINE_CTL_REG_OFF 0x0c
#define UART_MODEM_CTL_REG_OFF 0x10
#define UART_LINE_STATUS_REG_OFF 0x14
#define UART_MODEM_STATUS_REG_OFF 0x18
#define UART_FIFO_ACCESS_REG_OFF 0x70
#define UART_STATUS_REG_OFF 0x7c
#define UART_TFL_OFF 0x80
#define UART_RFL_OFF 0x84
//Buad rate
#define UART_BAUD_RATE_2400 2400
#define UART_BAUD_RATE_4800 4800
#define UART_BAUD_RATE_9600 9600
#define UART_BAUD_RATE_19200 19200
#define UART_BAUD_RATE_38400 38400
#define UART_BAUD_RATE_57600 57600
#define UART_BAUD_RATE_115200 115200
#define UART_BAUD_RATE_921600 921600
#define UART_BAUD_RATE_1152000 1152000
#define UART_PARITY_ENABLE 0x08
#define UART_PARITY_DISABLE 0
#define UART_DATA_LEN_5BIT 0x0
#define UART_DATA_LEN_6BIT 0x1
#define UART_DATA_LEN_7BIT 0x2
#define UART_DATA_LEN_8BIT 0x3
#define UART_STOP_1BIT 0x0
#define UART_STOP_2BIT 0x4
#define HAL_UART_READ32(addr) HAL_READ32(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE32(addr, value) HAL_WRITE32(LOG_UART_REG_BASE, addr, value)
#define HAL_UART_READ16(addr) HAL_READ16(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE16(addr, value) HAL_WRITE16(LOG_UART_REG_BASE, addr, value)
#define HAL_UART_READ8(addr) HAL_READ8(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE8(addr, value) HAL_WRITE8(LOG_UART_REG_BASE, addr, value)
typedef struct _LOG_UART_ADAPTER_ {
u32 BaudRate;
u32 FIFOControl;
u32 IntEnReg;
u8 Parity;
u8 Stop;
u8 DataLength;
}LOG_UART_ADAPTER, *PLOG_UART_ADAPTER;
typedef struct _COMMAND_TABLE_ {
const u8* cmd;
u16 ArgvCnt;
u32 (*func)(u16 argc, u8* argv[]);
const u8* msg;
}COMMAND_TABLE, *PCOMMAND_TABLE;
//VOID
//HalLogUartHandle(void);
extern _LONG_CALL_ROM_ u32
HalLogUartInit(
IN LOG_UART_ADAPTER UartAdapter
);
extern _LONG_CALL_ROM_ VOID
HalSerialPutcRtl8195a(
IN u8 c
);
extern _LONG_CALL_ROM_ u8
HalSerialGetcRtl8195a(
IN BOOL PullMode
);
extern _LONG_CALL_ROM_ u32
HalSerialGetIsrEnRegRtl8195a(VOID);
extern _LONG_CALL_ROM_ VOID
HalSerialSetIrqEnRegRtl8195a (
IN u32 SetValue
);
#endif//_HAL_DIAG_H_
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_DIAG_H_
#define _HAL_DIAG_H_
//Register offset
#define UART_REV_BUF_OFF 0x00
#define UART_TRAN_HOLD_OFF 0x00
#define UART_DLH_OFF 0x04
#define UART_DLL_OFF 0x00
#define UART_INTERRUPT_EN_REG_OFF 0x04
#define UART_INTERRUPT_IDEN_REG_OFF 0x08
#define UART_FIFO_CTL_REG_OFF 0x08
#define UART_LINE_CTL_REG_OFF 0x0c
#define UART_MODEM_CTL_REG_OFF 0x10
#define UART_LINE_STATUS_REG_OFF 0x14
#define UART_MODEM_STATUS_REG_OFF 0x18
#define UART_FIFO_ACCESS_REG_OFF 0x70
#define UART_STATUS_REG_OFF 0x7c
#define UART_TFL_OFF 0x80
#define UART_RFL_OFF 0x84
//Buad rate
#define UART_BAUD_RATE_2400 2400
#define UART_BAUD_RATE_4800 4800
#define UART_BAUD_RATE_9600 9600
#define UART_BAUD_RATE_19200 19200
#define UART_BAUD_RATE_38400 38400
#define UART_BAUD_RATE_57600 57600
#define UART_BAUD_RATE_115200 115200
#define UART_BAUD_RATE_921600 921600
#define UART_BAUD_RATE_1152000 1152000
#define UART_PARITY_ENABLE 0x08
#define UART_PARITY_DISABLE 0
#define UART_DATA_LEN_5BIT 0x0
#define UART_DATA_LEN_6BIT 0x1
#define UART_DATA_LEN_7BIT 0x2
#define UART_DATA_LEN_8BIT 0x3
#define UART_STOP_1BIT 0x0
#define UART_STOP_2BIT 0x4
#define HAL_UART_READ32(addr) HAL_READ32(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE32(addr, value) HAL_WRITE32(LOG_UART_REG_BASE, addr, value)
#define HAL_UART_READ16(addr) HAL_READ16(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE16(addr, value) HAL_WRITE16(LOG_UART_REG_BASE, addr, value)
#define HAL_UART_READ8(addr) HAL_READ8(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE8(addr, value) HAL_WRITE8(LOG_UART_REG_BASE, addr, value)
typedef struct _LOG_UART_ADAPTER_ {
u32 BaudRate;
u32 FIFOControl;
u32 IntEnReg;
u8 Parity;
u8 Stop;
u8 DataLength;
}LOG_UART_ADAPTER, *PLOG_UART_ADAPTER;
typedef struct _COMMAND_TABLE_ {
const u8* cmd;
u16 ArgvCnt;
u32 (*func)(u16 argc, u8* argv[]);
const u8* msg;
}COMMAND_TABLE, *PCOMMAND_TABLE;
//VOID
//HalLogUartHandle(void);
extern _LONG_CALL_ROM_ u32
HalLogUartInit(
IN LOG_UART_ADAPTER UartAdapter
);
extern _LONG_CALL_ROM_ VOID
HalSerialPutcRtl8195a(
IN u8 c
);
extern _LONG_CALL_ROM_ u8
HalSerialGetcRtl8195a(
IN BOOL PullMode
);
extern _LONG_CALL_ROM_ u32
HalSerialGetIsrEnRegRtl8195a(VOID);
extern _LONG_CALL_ROM_ VOID
HalSerialSetIrqEnRegRtl8195a (
IN u32 SetValue
);
#endif//_HAL_DIAG_H_

44
component/soc/realtek/8195a/fwlib/hal_efuse.h
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@ -1,22 +1,22 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_EFUSE_H_
#define _HAL_EFUSE_H_
_LONG_CALL_ROM_ extern VOID HalEFUSEPowerSwitch8195AROM(IN u8 bWrite, IN u8 PwrState, IN u8 L25OutVoltage);
extern u32 HALEFUSEOneByteReadRAM(IN u32 CtrlSetting, IN u16 Addr, OUT u8 *Data, IN u8 L25OutVoltage);
extern u32 HALEFUSEOneByteWriteRAM(IN u32 CtrlSetting, IN u16 Addr, IN u8 Data, IN u8 L25OutVoltage);
#define EFUSERead8 HALEFUSEOneByteReadRAM
#define EFUSEWrite8 HALEFUSEOneByteWriteRAM
#define L25EOUTVOLTAGE 7
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_EFUSE_H_
#define _HAL_EFUSE_H_
_LONG_CALL_ROM_ extern VOID HalEFUSEPowerSwitch8195AROM(IN u8 bWrite, IN u8 PwrState, IN u8 L25OutVoltage);
extern u32 HALEFUSEOneByteReadRAM(IN u32 CtrlSetting, IN u16 Addr, OUT u8 *Data, IN u8 L25OutVoltage);
extern u32 HALEFUSEOneByteWriteRAM(IN u32 CtrlSetting, IN u16 Addr, IN u8 Data, IN u8 L25OutVoltage);
#define EFUSERead8 HALEFUSEOneByteReadRAM
#define EFUSEWrite8 HALEFUSEOneByteWriteRAM
#define L25EOUTVOLTAGE 7
#endif

282
component/soc/realtek/8195a/fwlib/hal_gdma.h
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@ -1,141 +1,141 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_GDMA_H_
#define _HAL_GDMA_H_
#include "rtl8195a_gdma.h"
typedef struct _GDMA_CH_LLI_ELE_ {
u32 Sarx;
u32 Darx;
u32 Llpx;
u32 CtlxLow;
u32 CtlxUp;
u32 Temp;
}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
#if 1
#if 0
typedef struct _GDMA_CH_LLI_ {
PGDMA_CH_LLI_ELE pLliEle;
PGDMA_CH_LLI pNextLli;
}GDMA_CH_LLI, *PGDMA_CH_LLI;
typedef struct _BLOCK_SIZE_LIST_ {
u32 BlockSize;
PBLOCK_SIZE_LIST pNextBlockSiz;
}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
#else
struct GDMA_CH_LLI {
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pNextLli;
};
struct BLOCK_SIZE_LIST {
u32 BlockSize;
struct BLOCK_SIZE_LIST *pNextBlockSiz;
};
#endif
#endif
typedef struct _HAL_GDMA_ADAPTER_ {
u32 ChSar;
u32 ChDar;
GDMA_CHANNEL_NUM ChEn;
GDMA_CTL_REG GdmaCtl;
GDMA_CFG_REG GdmaCfg;
u32 PacketLen;
u32 BlockLen;
u32 MuliBlockCunt;
u32 MaxMuliBlock;
struct GDMA_CH_LLI *pLlix;
struct BLOCK_SIZE_LIST *pBlockSizeList;
PGDMA_CH_LLI_ELE pLli;
u32 NextPlli;
u8 TestItem;
u8 ChNum;
u8 GdmaIndex;
u8 IsrCtrl:1;
u8 GdmaOnOff:1;
u8 Llpctrl:1;
u8 Lli0:1;
u8 Rsvd4to7:4;
u8 GdmaIsrType;
}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
typedef struct _HAL_GDMA_CHNL_ {
u8 GdmaIndx;
u8 GdmaChnl;
u8 IrqNum;
u8 Reserved;
}HAL_GDMA_CHNL, *PHAL_GDMA_CHNL;
typedef struct _HAL_GDMA_BLOCK_ {
u32 SrcAddr;
u32 DstAddr;
u32 BlockLength;
u32 SrcOffset;
u32 DstOffset;
}HAL_GDMA_BLOCK, *PHAL_GDMA_BLOCK;
typedef struct _HAL_GDMA_OP_ {
VOID (*HalGdmaOnOff)(VOID *Data);
BOOL (*HalGdamChInit)(VOID *Data);
BOOL (*HalGdmaChSeting)(VOID *Data);
BOOL (*HalGdmaChBlockSeting)(VOID *Data);
VOID (*HalGdmaChDis)(VOID *Data);
VOID (*HalGdmaChEn)(VOID *Data);
VOID (*HalGdmaChIsrEnAndDis) (VOID *Data);
u8 (*HalGdmaChIsrClean)(VOID *Data);
VOID (*HalGdmaChCleanAutoSrc)(VOID *Data);
VOID (*HalGdmaChCleanAutoDst)(VOID *Data);
}HAL_GDMA_OP, *PHAL_GDMA_OP;
typedef struct _HAL_GDMA_OBJ_ {
HAL_GDMA_ADAPTER HalGdmaAdapter;
IRQ_HANDLE GdmaIrqHandle;
volatile GDMA_CH_LLI_ELE GdmaChLli[16];
struct GDMA_CH_LLI Lli[16];
struct BLOCK_SIZE_LIST BlockSizeList[16];
u8 Busy; // is transfering
u8 BlockNum;
} HAL_GDMA_OBJ, *PHAL_GDMA_OBJ;
VOID HalGdmaOpInit(IN VOID *Data);
VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
extern HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum);
extern VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum);
extern PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption);
extern VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl);
extern BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len);
extern VOID HalGdmaMemAggr(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock);
extern BOOL HalGdmaMemCpyAggrInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern const HAL_GDMA_OP _HalGdmaOp;
extern const HAL_GDMA_CHNL GDMA_Chnl_Option[];
extern const HAL_GDMA_CHNL GDMA_Multi_Block_Chnl_Option[];
extern const u16 HalGdmaChnlEn[6];
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_GDMA_H_
#define _HAL_GDMA_H_
#include "rtl8195a_gdma.h"
typedef struct _GDMA_CH_LLI_ELE_ {
u32 Sarx;
u32 Darx;
u32 Llpx;
u32 CtlxLow;
u32 CtlxUp;
u32 Temp;
}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
#if 1
#if 0
typedef struct _GDMA_CH_LLI_ {
PGDMA_CH_LLI_ELE pLliEle;
PGDMA_CH_LLI pNextLli;
}GDMA_CH_LLI, *PGDMA_CH_LLI;
typedef struct _BLOCK_SIZE_LIST_ {
u32 BlockSize;
PBLOCK_SIZE_LIST pNextBlockSiz;
}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
#else
struct GDMA_CH_LLI {
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pNextLli;
};
struct BLOCK_SIZE_LIST {
u32 BlockSize;
struct BLOCK_SIZE_LIST *pNextBlockSiz;
};
#endif
#endif
typedef struct _HAL_GDMA_ADAPTER_ {
u32 ChSar;
u32 ChDar;
GDMA_CHANNEL_NUM ChEn;
GDMA_CTL_REG GdmaCtl;
GDMA_CFG_REG GdmaCfg;
u32 PacketLen;
u32 BlockLen;
u32 MuliBlockCunt;
u32 MaxMuliBlock;
struct GDMA_CH_LLI *pLlix;
struct BLOCK_SIZE_LIST *pBlockSizeList;
PGDMA_CH_LLI_ELE pLli;
u32 NextPlli;
u8 TestItem;
u8 ChNum;
u8 GdmaIndex;
u8 IsrCtrl:1;
u8 GdmaOnOff:1;
u8 Llpctrl:1;
u8 Lli0:1;
u8 Rsvd4to7:4;
u8 GdmaIsrType;
}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
typedef struct _HAL_GDMA_CHNL_ {
u8 GdmaIndx;
u8 GdmaChnl;
u8 IrqNum;
u8 Reserved;
}HAL_GDMA_CHNL, *PHAL_GDMA_CHNL;
typedef struct _HAL_GDMA_BLOCK_ {
u32 SrcAddr;
u32 DstAddr;
u32 BlockLength;
u32 SrcOffset;
u32 DstOffset;
}HAL_GDMA_BLOCK, *PHAL_GDMA_BLOCK;
typedef struct _HAL_GDMA_OP_ {
VOID (*HalGdmaOnOff)(VOID *Data);
BOOL (*HalGdamChInit)(VOID *Data);
BOOL (*HalGdmaChSeting)(VOID *Data);
BOOL (*HalGdmaChBlockSeting)(VOID *Data);
VOID (*HalGdmaChDis)(VOID *Data);
VOID (*HalGdmaChEn)(VOID *Data);
VOID (*HalGdmaChIsrEnAndDis) (VOID *Data);
u8 (*HalGdmaChIsrClean)(VOID *Data);
VOID (*HalGdmaChCleanAutoSrc)(VOID *Data);
VOID (*HalGdmaChCleanAutoDst)(VOID *Data);
}HAL_GDMA_OP, *PHAL_GDMA_OP;
typedef struct _HAL_GDMA_OBJ_ {
HAL_GDMA_ADAPTER HalGdmaAdapter;
IRQ_HANDLE GdmaIrqHandle;
volatile GDMA_CH_LLI_ELE GdmaChLli[16];
struct GDMA_CH_LLI Lli[16];
struct BLOCK_SIZE_LIST BlockSizeList[16];
u8 Busy; // is transfering
u8 BlockNum;
} HAL_GDMA_OBJ, *PHAL_GDMA_OBJ;
VOID HalGdmaOpInit(IN VOID *Data);
VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
extern HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum);
extern VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum);
extern PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption);
extern VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl);
extern BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len);
extern VOID HalGdmaMemAggr(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock);
extern BOOL HalGdmaMemCpyAggrInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern const HAL_GDMA_OP _HalGdmaOp;
extern const HAL_GDMA_CHNL GDMA_Chnl_Option[];
extern const HAL_GDMA_CHNL GDMA_Multi_Block_Chnl_Option[];
extern const u16 HalGdmaChnlEn[6];
#endif

484
component/soc/realtek/8195a/fwlib/hal_gpio.h
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@ -1,242 +1,242 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_GPIO_H_
#define _HAL_GPIO_H_
#define HAL_GPIO_PIN_INT_MODE 0x80
typedef enum {
_PORT_A = 0,
_PORT_B = 1,
_PORT_C = 2,
_PORT_D = 3,
_PORT_E = 4,
_PORT_F = 5,
_PORT_G = 6,
_PORT_H = 7,
_PORT_I = 8,
_PORT_J = 9,
_PORT_K = 10,
_PORT_MAX
} HAL_GPIO_PORT_NAME;
typedef enum {
_PA_0 = (_PORT_A<<4|0),
_PA_1 = (_PORT_A<<4|1),
_PA_2 = (_PORT_A<<4|2),
_PA_3 = (_PORT_A<<4|3),
_PA_4 = (_PORT_A<<4|4),
_PA_5 = (_PORT_A<<4|5),
_PA_6 = (_PORT_A<<4|6),
_PA_7 = (_PORT_A<<4|7),
_PB_0 = (_PORT_B<<4|0),
_PB_1 = (_PORT_B<<4|1),
_PB_2 = (_PORT_B<<4|2),
_PB_3 = (_PORT_B<<4|3),
_PB_4 = (_PORT_B<<4|4),
_PB_5 = (_PORT_B<<4|5),
_PB_6 = (_PORT_B<<4|6),
_PB_7 = (_PORT_B<<4|7),
_PC_0 = (_PORT_C<<4|0),
_PC_1 = (_PORT_C<<4|1),
_PC_2 = (_PORT_C<<4|2),
_PC_3 = (_PORT_C<<4|3),
_PC_4 = (_PORT_C<<4|4),
_PC_5 = (_PORT_C<<4|5),
_PC_6 = (_PORT_C<<4|6),
_PC_7 = (_PORT_C<<4|7),
_PC_8 = (_PORT_C<<4|8),
_PC_9 = (_PORT_C<<4|9),
_PD_0 = (_PORT_D<<4|0),
_PD_1 = (_PORT_D<<4|1),
_PD_2 = (_PORT_D<<4|2),
_PD_3 = (_PORT_D<<4|3),
_PD_4 = (_PORT_D<<4|4),
_PD_5 = (_PORT_D<<4|5),
_PD_6 = (_PORT_D<<4|6),
_PD_7 = (_PORT_D<<4|7),
_PD_8 = (_PORT_D<<4|8),
_PD_9 = (_PORT_D<<4|9),
_PE_0 = (_PORT_E<<4|0),
_PE_1 = (_PORT_E<<4|1),
_PE_2 = (_PORT_E<<4|2),
_PE_3 = (_PORT_E<<4|3),
_PE_4 = (_PORT_E<<4|4),
_PE_5 = (_PORT_E<<4|5),
_PE_6 = (_PORT_E<<4|6),
_PE_7 = (_PORT_E<<4|7),
_PE_8 = (_PORT_E<<4|8),
_PE_9 = (_PORT_E<<4|9),
_PE_A = (_PORT_E<<4|10),
_PF_0 = (_PORT_F<<4|0),
_PF_1 = (_PORT_F<<4|1),
_PF_2 = (_PORT_F<<4|2),
_PF_3 = (_PORT_F<<4|3),
_PF_4 = (_PORT_F<<4|4),
_PF_5 = (_PORT_F<<4|5),
// _PF_6 = (_PORT_F<<4|6),
// _PF_7 = (_PORT_F<<4|7),
_PG_0 = (_PORT_G<<4|0),
_PG_1 = (_PORT_G<<4|1),
_PG_2 = (_PORT_G<<4|2),
_PG_3 = (_PORT_G<<4|3),
_PG_4 = (_PORT_G<<4|4),
_PG_5 = (_PORT_G<<4|5),
_PG_6 = (_PORT_G<<4|6),
_PG_7 = (_PORT_G<<4|7),
_PH_0 = (_PORT_H<<4|0),
_PH_1 = (_PORT_H<<4|1),
_PH_2 = (_PORT_H<<4|2),
_PH_3 = (_PORT_H<<4|3),
_PH_4 = (_PORT_H<<4|4),
_PH_5 = (_PORT_H<<4|5),
_PH_6 = (_PORT_H<<4|6),
_PH_7 = (_PORT_H<<4|7),
_PI_0 = (_PORT_I<<4|0),
_PI_1 = (_PORT_I<<4|1),
_PI_2 = (_PORT_I<<4|2),
_PI_3 = (_PORT_I<<4|3),
_PI_4 = (_PORT_I<<4|4),
_PI_5 = (_PORT_I<<4|5),
_PI_6 = (_PORT_I<<4|6),
_PI_7 = (_PORT_I<<4|7),
_PJ_0 = (_PORT_J<<4|0),
_PJ_1 = (_PORT_J<<4|1),
_PJ_2 = (_PORT_J<<4|2),
_PJ_3 = (_PORT_J<<4|3),
_PJ_4 = (_PORT_J<<4|4),
_PJ_5 = (_PORT_J<<4|5),
_PJ_6 = (_PORT_J<<4|6),
// _PJ_7 = (_PORT_J<<4|7),
_PK_0 = (_PORT_K<<4|0),
_PK_1 = (_PORT_K<<4|1),
_PK_2 = (_PORT_K<<4|2),
_PK_3 = (_PORT_K<<4|3),
_PK_4 = (_PORT_K<<4|4),
_PK_5 = (_PORT_K<<4|5),
_PK_6 = (_PORT_K<<4|6),
// _PK_7 = (_PORT_K<<4|7),
// Not connected
_PIN_NC = (int)0xFFFFFFFF
} HAL_PIN_NAME;
typedef enum
{
GPIO_PIN_LOW = 0,
GPIO_PIN_HIGH = 1,
GPIO_PIN_ERR = 2 // read Pin error
} HAL_GPIO_PIN_STATE;
typedef enum {
DIN_PULL_NONE = 0, //floating or high impedance ?
DIN_PULL_LOW = 1,
DIN_PULL_HIGH = 2,
DOUT_PUSH_PULL = 3,
DOUT_OPEN_DRAIN = 4,
INT_LOW = (5|HAL_GPIO_PIN_INT_MODE), // Interrupt Low level trigger
INT_HIGH = (6|HAL_GPIO_PIN_INT_MODE), // Interrupt High level trigger
INT_FALLING = (7|HAL_GPIO_PIN_INT_MODE), // Interrupt Falling edge trigger
INT_RISING = (8|HAL_GPIO_PIN_INT_MODE) // Interrupt Rising edge trigger
} HAL_GPIO_PIN_MODE;
enum {
GPIO_PORT_A = 0,
GPIO_PORT_B = 1,
GPIO_PORT_C = 2,
GPIO_PORT_D = 3
};
typedef enum {
hal_PullNone = 0,
hal_PullUp = 1,
hal_PullDown = 2,
hal_OpenDrain = 3,
hal_PullDefault = hal_PullNone
} HAL_PinMode;
typedef struct _HAL_GPIO_PORT_ {
u32 out_data; // to write the GPIO port
u32 in_data; // to read the GPIO port
u32 dir; // config each pin direction
}HAL_GPIO_PORT, *PHAL_GPIO_PORT;
#define HAL_GPIO_PIN_NAME(port,pin) (((port)<<5)|(pin))
#define HAL_GPIO_GET_PORT_BY_NAME(x) ((x>>5) & 0x03)
#define HAL_GPIO_GET_PIN_BY_NAME(x) (x & 0x1f)
typedef struct _HAL_GPIO_PIN_ {
HAL_GPIO_PIN_MODE pin_mode;
u32 pin_name; // Pin: [7:5]: port number, [4:0]: pin number
}HAL_GPIO_PIN, *PHAL_GPIO_PIN;
typedef struct _HAL_GPIO_OP_ {
#if defined(__ICCARM__)
void* dummy;
#endif
}HAL_GPIO_OP, *PHAL_GPIO_OP;
typedef void (*GPIO_IRQ_FUN)(VOID *Data, u32 Id);
typedef void (*GPIO_USER_IRQ_FUN)(u32 Id);
typedef struct _HAL_GPIO_ADAPTER_ {
IRQ_HANDLE IrqHandle; // GPIO HAL IRQ Handle
GPIO_USER_IRQ_FUN UserIrqHandler; // GPIO IRQ Handler
GPIO_IRQ_FUN PortA_IrqHandler[32]; // The interrupt handler triggered by Port A[x]
VOID *PortA_IrqData[32];
VOID (*EnterCritical)(void);
VOID (*ExitCritical)(void);
u32 Local_Gpio_Dir[3]; // to record direction setting: 0- IN, 1- Out
u8 Gpio_Func_En; // Is GPIO HW function enabled ?
u8 Locked;
}HAL_GPIO_ADAPTER, *PHAL_GPIO_ADAPTER;
u32
HAL_GPIO_GetPinName(
u32 chip_pin
);
VOID
HAL_GPIO_PullCtrl(
u32 pin,
u32 mode
);
VOID
HAL_GPIO_Init(
HAL_GPIO_PIN *GPIO_Pin
);
VOID
HAL_GPIO_Irq_Init(
HAL_GPIO_PIN *GPIO_Pin
);
VOID
HAL_GPIO_IP_DeInit(
VOID
);
#endif // end of "#define _HAL_GPIO_H_"
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_GPIO_H_
#define _HAL_GPIO_H_
#define HAL_GPIO_PIN_INT_MODE 0x80
typedef enum {
_PORT_A = 0,
_PORT_B = 1,
_PORT_C = 2,
_PORT_D = 3,
_PORT_E = 4,
_PORT_F = 5,
_PORT_G = 6,
_PORT_H = 7,
_PORT_I = 8,
_PORT_J = 9,
_PORT_K = 10,
_PORT_MAX
} HAL_GPIO_PORT_NAME;
typedef enum {
_PA_0 = (_PORT_A<<4|0),
_PA_1 = (_PORT_A<<4|1),
_PA_2 = (_PORT_A<<4|2),
_PA_3 = (_PORT_A<<4|3),
_PA_4 = (_PORT_A<<4|4),
_PA_5 = (_PORT_A<<4|5),
_PA_6 = (_PORT_A<<4|6),
_PA_7 = (_PORT_A<<4|7),
_PB_0 = (_PORT_B<<4|0),
_PB_1 = (_PORT_B<<4|1),
_PB_2 = (_PORT_B<<4|2),
_PB_3 = (_PORT_B<<4|3),
_PB_4 = (_PORT_B<<4|4),
_PB_5 = (_PORT_B<<4|5),
_PB_6 = (_PORT_B<<4|6),
_PB_7 = (_PORT_B<<4|7),
_PC_0 = (_PORT_C<<4|0),
_PC_1 = (_PORT_C<<4|1),
_PC_2 = (_PORT_C<<4|2),
_PC_3 = (_PORT_C<<4|3),
_PC_4 = (_PORT_C<<4|4),
_PC_5 = (_PORT_C<<4|5),
_PC_6 = (_PORT_C<<4|6),
_PC_7 = (_PORT_C<<4|7),
_PC_8 = (_PORT_C<<4|8),
_PC_9 = (_PORT_C<<4|9),
_PD_0 = (_PORT_D<<4|0),
_PD_1 = (_PORT_D<<4|1),
_PD_2 = (_PORT_D<<4|2),
_PD_3 = (_PORT_D<<4|3),
_PD_4 = (_PORT_D<<4|4),
_PD_5 = (_PORT_D<<4|5),
_PD_6 = (_PORT_D<<4|6),
_PD_7 = (_PORT_D<<4|7),
_PD_8 = (_PORT_D<<4|8),
_PD_9 = (_PORT_D<<4|9),
_PE_0 = (_PORT_E<<4|0),
_PE_1 = (_PORT_E<<4|1),
_PE_2 = (_PORT_E<<4|2),
_PE_3 = (_PORT_E<<4|3),
_PE_4 = (_PORT_E<<4|4),
_PE_5 = (_PORT_E<<4|5),
_PE_6 = (_PORT_E<<4|6),
_PE_7 = (_PORT_E<<4|7),
_PE_8 = (_PORT_E<<4|8),
_PE_9 = (_PORT_E<<4|9),
_PE_A = (_PORT_E<<4|10),
_PF_0 = (_PORT_F<<4|0),
_PF_1 = (_PORT_F<<4|1),
_PF_2 = (_PORT_F<<4|2),
_PF_3 = (_PORT_F<<4|3),
_PF_4 = (_PORT_F<<4|4),
_PF_5 = (_PORT_F<<4|5),
// _PF_6 = (_PORT_F<<4|6),
// _PF_7 = (_PORT_F<<4|7),
_PG_0 = (_PORT_G<<4|0),
_PG_1 = (_PORT_G<<4|1),
_PG_2 = (_PORT_G<<4|2),
_PG_3 = (_PORT_G<<4|3),
_PG_4 = (_PORT_G<<4|4),
_PG_5 = (_PORT_G<<4|5),
_PG_6 = (_PORT_G<<4|6),
_PG_7 = (_PORT_G<<4|7),
_PH_0 = (_PORT_H<<4|0),
_PH_1 = (_PORT_H<<4|1),
_PH_2 = (_PORT_H<<4|2),
_PH_3 = (_PORT_H<<4|3),
_PH_4 = (_PORT_H<<4|4),
_PH_5 = (_PORT_H<<4|5),
_PH_6 = (_PORT_H<<4|6),
_PH_7 = (_PORT_H<<4|7),
_PI_0 = (_PORT_I<<4|0),
_PI_1 = (_PORT_I<<4|1),
_PI_2 = (_PORT_I<<4|2),
_PI_3 = (_PORT_I<<4|3),
_PI_4 = (_PORT_I<<4|4),
_PI_5 = (_PORT_I<<4|5),
_PI_6 = (_PORT_I<<4|6),
_PI_7 = (_PORT_I<<4|7),
_PJ_0 = (_PORT_J<<4|0),
_PJ_1 = (_PORT_J<<4|1),
_PJ_2 = (_PORT_J<<4|2),
_PJ_3 = (_PORT_J<<4|3),
_PJ_4 = (_PORT_J<<4|4),
_PJ_5 = (_PORT_J<<4|5),
_PJ_6 = (_PORT_J<<4|6),
// _PJ_7 = (_PORT_J<<4|7),
_PK_0 = (_PORT_K<<4|0),
_PK_1 = (_PORT_K<<4|1),
_PK_2 = (_PORT_K<<4|2),
_PK_3 = (_PORT_K<<4|3),
_PK_4 = (_PORT_K<<4|4),
_PK_5 = (_PORT_K<<4|5),
_PK_6 = (_PORT_K<<4|6),
// _PK_7 = (_PORT_K<<4|7),
// Not connected
_PIN_NC = (int)0xFFFFFFFF
} HAL_PIN_NAME;
typedef enum
{
GPIO_PIN_LOW = 0,
GPIO_PIN_HIGH = 1,
GPIO_PIN_ERR = 2 // read Pin error
} HAL_GPIO_PIN_STATE;
typedef enum {
DIN_PULL_NONE = 0, //floating or high impedance ?
DIN_PULL_LOW = 1,
DIN_PULL_HIGH = 2,
DOUT_PUSH_PULL = 3,
DOUT_OPEN_DRAIN = 4,
INT_LOW = (5|HAL_GPIO_PIN_INT_MODE), // Interrupt Low level trigger
INT_HIGH = (6|HAL_GPIO_PIN_INT_MODE), // Interrupt High level trigger
INT_FALLING = (7|HAL_GPIO_PIN_INT_MODE), // Interrupt Falling edge trigger
INT_RISING = (8|HAL_GPIO_PIN_INT_MODE) // Interrupt Rising edge trigger
} HAL_GPIO_PIN_MODE;
enum {
GPIO_PORT_A = 0,
GPIO_PORT_B = 1,
GPIO_PORT_C = 2,
GPIO_PORT_D = 3
};
typedef enum {
hal_PullNone = 0,
hal_PullUp = 1,
hal_PullDown = 2,
hal_OpenDrain = 3,
hal_PullDefault = hal_PullNone
} HAL_PinMode;
typedef struct _HAL_GPIO_PORT_ {
u32 out_data; // to write the GPIO port
u32 in_data; // to read the GPIO port
u32 dir; // config each pin direction
}HAL_GPIO_PORT, *PHAL_GPIO_PORT;
#define HAL_GPIO_PIN_NAME(port,pin) (((port)<<5)|(pin))
#define HAL_GPIO_GET_PORT_BY_NAME(x) ((x>>5) & 0x03)
#define HAL_GPIO_GET_PIN_BY_NAME(x) (x & 0x1f)
typedef struct _HAL_GPIO_PIN_ {
HAL_GPIO_PIN_MODE pin_mode;
u32 pin_name; // Pin: [7:5]: port number, [4:0]: pin number
}HAL_GPIO_PIN, *PHAL_GPIO_PIN;
typedef struct _HAL_GPIO_OP_ {
#if defined(__ICCARM__)
void* dummy;
#endif
}HAL_GPIO_OP, *PHAL_GPIO_OP;
typedef void (*GPIO_IRQ_FUN)(VOID *Data, u32 Id);
typedef void (*GPIO_USER_IRQ_FUN)(u32 Id);
typedef struct _HAL_GPIO_ADAPTER_ {
IRQ_HANDLE IrqHandle; // GPIO HAL IRQ Handle
GPIO_USER_IRQ_FUN UserIrqHandler; // GPIO IRQ Handler
GPIO_IRQ_FUN PortA_IrqHandler[32]; // The interrupt handler triggered by Port A[x]
VOID *PortA_IrqData[32];
VOID (*EnterCritical)(void);
VOID (*ExitCritical)(void);
u32 Local_Gpio_Dir[3]; // to record direction setting: 0- IN, 1- Out
u8 Gpio_Func_En; // Is GPIO HW function enabled ?
u8 Locked;
}HAL_GPIO_ADAPTER, *PHAL_GPIO_ADAPTER;
u32
HAL_GPIO_GetPinName(
u32 chip_pin
);
VOID
HAL_GPIO_PullCtrl(
u32 pin,
u32 mode
);
VOID
HAL_GPIO_Init(
HAL_GPIO_PIN *GPIO_Pin
);
VOID
HAL_GPIO_Irq_Init(
HAL_GPIO_PIN *GPIO_Pin
);
VOID
HAL_GPIO_IP_DeInit(
VOID
);
#endif // end of "#define _HAL_GPIO_H_"

1188
component/soc/realtek/8195a/fwlib/hal_i2c.h
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224
component/soc/realtek/8195a/fwlib/hal_irqn.h
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@ -1,112 +1,112 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_IRQN_H_
#define _HAL_IRQN_H_
#define PERIPHERAL_IRQ_BASE_NUM 64
typedef enum _IRQn_Type_ {
#if 0
/****** Cortex-M3 Processor Exceptions Numbers ********/
NON_MASKABLE_INT_IRQ = -14,
HARD_FAULT_IRQ = -13,
MEM_MANAGE_FAULT_IRQ = -12,
BUS_FAULT_IRQ = -11,
USAGE_FAULT_IRQ = -10,
SVCALL_IRQ = -5,
DEBUG_MONITOR_IRQ = -4,
PENDSVC_IRQ = -2,
SYSTICK_IRQ = -1,
#else
/****** Cortex-M3 Processor Exceptions Numbers ********/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
#endif
/****** RTL8195A Specific Interrupt Numbers ************/
SYSTEM_ON_IRQ = 0,
WDG_IRQ = 1,
TIMER0_IRQ = 2,
TIMER1_IRQ = 3,
I2C3_IRQ = 4,
TIMER2_7_IRQ = 5,
SPI0_IRQ = 6,
GPIO_IRQ = 7,
UART0_IRQ = 8,
SPI_FLASH_IRQ = 9,
USB_OTG_IRQ = 10,
SDIO_HOST_IRQ = 11,
SDIO_DEVICE_IRQ = 12,
I2S0_PCM0_IRQ = 13,
I2S1_PCM1_IRQ = 14,
WL_DMA_IRQ = 15,
WL_PROTOCOL_IRQ = 16,
CRYPTO_IRQ = 17,
GMAC_IRQ = 18,
PERIPHERAL_IRQ = 19,
GDMA0_CHANNEL0_IRQ = 20,
GDMA0_CHANNEL1_IRQ = 21,
GDMA0_CHANNEL2_IRQ = 22,
GDMA0_CHANNEL3_IRQ = 23,
GDMA0_CHANNEL4_IRQ = 24,
GDMA0_CHANNEL5_IRQ = 25,
GDMA1_CHANNEL0_IRQ = 26,
GDMA1_CHANNEL1_IRQ = 27,
GDMA1_CHANNEL2_IRQ = 28,
GDMA1_CHANNEL3_IRQ = 29,
GDMA1_CHANNEL4_IRQ = 30,
GDMA1_CHANNEL5_IRQ = 31,
/****** RTL8195A Peripheral Interrupt Numbers ************/
I2C0_IRQ = 64,// 0 + 64,
I2C1_IRQ = 65,// 1 + 64,
I2C2_IRQ = 66,// 2 + 64,
SPI1_IRQ = 72,// 8 + 64,
SPI2_IRQ = 73,// 9 + 64,
UART1_IRQ = 80,// 16 + 64,
UART2_IRQ = 81,// 17 + 64,
UART_LOG_IRQ = 88,// 24 + 64,
ADC_IRQ = 89,// 25 + 64,
DAC0_IRQ = 91,// 27 + 64,
DAC1_IRQ = 92,// 28 + 64,
//RXI300_IRQ = 93// 29 + 64
LP_EXTENSION_IRQ = 93,// 29+64
PTA_TRX_IRQ = 95,// 31+64
RXI300_IRQ = 96,// 0+32 + 64
NFC_IRQ = 97// 1+32+64
} IRQn_Type, *PIRQn_Type;
typedef VOID (*HAL_VECTOR_FUN) (VOID);
typedef enum _VECTOR_TABLE_TYPE_{
DEDECATED_VECTRO_TABLE,
PERIPHERAL_VECTOR_TABLE
}VECTOR_TABLE_TYPE, *PVECTOR_TABLE_TYPE;
typedef void (*IRQ_FUN)(VOID *Data);
typedef struct _IRQ_HANDLE_ {
IRQ_FUN IrqFun;
IRQn_Type IrqNum;
u32 Data;
u32 Priority;
}IRQ_HANDLE, *PIRQ_HANDLE;
#endif //_HAL_IRQN_H_
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_IRQN_H_
#define _HAL_IRQN_H_
#define PERIPHERAL_IRQ_BASE_NUM 64
typedef enum _IRQn_Type_ {
#if 0
/****** Cortex-M3 Processor Exceptions Numbers ********/
NON_MASKABLE_INT_IRQ = -14,
HARD_FAULT_IRQ = -13,
MEM_MANAGE_FAULT_IRQ = -12,
BUS_FAULT_IRQ = -11,
USAGE_FAULT_IRQ = -10,
SVCALL_IRQ = -5,
DEBUG_MONITOR_IRQ = -4,
PENDSVC_IRQ = -2,
SYSTICK_IRQ = -1,
#else
/****** Cortex-M3 Processor Exceptions Numbers ********/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
#endif
/****** RTL8195A Specific Interrupt Numbers ************/
SYSTEM_ON_IRQ = 0,
WDG_IRQ = 1,
TIMER0_IRQ = 2,
TIMER1_IRQ = 3,
I2C3_IRQ = 4,
TIMER2_7_IRQ = 5,
SPI0_IRQ = 6,
GPIO_IRQ = 7,
UART0_IRQ = 8,
SPI_FLASH_IRQ = 9,
USB_OTG_IRQ = 10,
SDIO_HOST_IRQ = 11,
SDIO_DEVICE_IRQ = 12,
I2S0_PCM0_IRQ = 13,
I2S1_PCM1_IRQ = 14,
WL_DMA_IRQ = 15,
WL_PROTOCOL_IRQ = 16,
CRYPTO_IRQ = 17,
GMAC_IRQ = 18,
PERIPHERAL_IRQ = 19,
GDMA0_CHANNEL0_IRQ = 20,
GDMA0_CHANNEL1_IRQ = 21,
GDMA0_CHANNEL2_IRQ = 22,
GDMA0_CHANNEL3_IRQ = 23,
GDMA0_CHANNEL4_IRQ = 24,
GDMA0_CHANNEL5_IRQ = 25,
GDMA1_CHANNEL0_IRQ = 26,
GDMA1_CHANNEL1_IRQ = 27,
GDMA1_CHANNEL2_IRQ = 28,
GDMA1_CHANNEL3_IRQ = 29,
GDMA1_CHANNEL4_IRQ = 30,
GDMA1_CHANNEL5_IRQ = 31,
/****** RTL8195A Peripheral Interrupt Numbers ************/
I2C0_IRQ = 64,// 0 + 64,
I2C1_IRQ = 65,// 1 + 64,
I2C2_IRQ = 66,// 2 + 64,
SPI1_IRQ = 72,// 8 + 64,
SPI2_IRQ = 73,// 9 + 64,
UART1_IRQ = 80,// 16 + 64,
UART2_IRQ = 81,// 17 + 64,
UART_LOG_IRQ = 88,// 24 + 64,
ADC_IRQ = 89,// 25 + 64,
DAC0_IRQ = 91,// 27 + 64,
DAC1_IRQ = 92,// 28 + 64,
//RXI300_IRQ = 93// 29 + 64
LP_EXTENSION_IRQ = 93,// 29+64
PTA_TRX_IRQ = 95,// 31+64
RXI300_IRQ = 96,// 0+32 + 64
NFC_IRQ = 97// 1+32+64
} IRQn_Type, *PIRQn_Type;
typedef VOID (*HAL_VECTOR_FUN) (VOID);
typedef enum _VECTOR_TABLE_TYPE_{
DEDECATED_VECTRO_TABLE,
PERIPHERAL_VECTOR_TABLE
}VECTOR_TABLE_TYPE, *PVECTOR_TABLE_TYPE;
typedef void (*IRQ_FUN)(VOID *Data);
typedef struct _IRQ_HANDLE_ {
IRQ_FUN IrqFun;
IRQn_Type IrqNum;
u32 Data;
u32 Priority;
}IRQ_HANDLE, *PIRQ_HANDLE;
#endif //_HAL_IRQN_H_

300
component/soc/realtek/8195a/fwlib/hal_log_uart.h
View file

@ -1,150 +1,150 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_LOG_UART_H_
#define _HAL_LOG_UART_H_
#include "hal_diag.h"
#define LOG_UART_WAIT_FOREVER 0xffffffff
// Define Line Control Register Bits
typedef enum {
LCR_DLS_5B = 0, // Data Length: 5 bits
LCR_DLS_6B = BIT(0), // Data Length: 6 bits
LCR_DLS_7B = BIT(1), // Data Length: 7 bits
LCR_DLS_8B = (BIT(1)|BIT(0)), // Data Length: 7 bits
LCR_STOP_1B = 0, // Number of stop bits: 1
LCR_STOP_2B = BIT(2), // Number of stop bits: 1.5(data len=5) or 2
LCR_PARITY_NONE = 0, // Parity Enable: 0
LCR_PARITY_ODD = BIT(3), // Parity Enable: 1, Even Parity: 0
LCR_PARITY_EVEN = (BIT(4)|BIT(3)), // Parity Enable: 1, Even Parity: 1
LCR_BC = BIT(6), // Break Control Bit
LCR_DLAB = BIT(7) // Divisor Latch Access Bit
} LOG_UART_LINE_CTRL;
// define Log UART Interrupt Indication ID
/*
IIR[3:0]:
0000 = modem status
0001 = no interrupt pending
0010 = THR empty
0100 = received data available
0110 = receiver line status
0111 = busy detect
1100 = character timeout
*/
typedef enum {
IIR_MODEM_STATUS = 0, //Clear to send or data set ready or ring indicator or data carrier detect.
IIR_NO_PENDING = 1,
IIR_THR_EMPTY = 2, // TX FIFO level lower than threshold or FIFO empty
IIR_RX_RDY = 4, // RX data ready
IIR_RX_LINE_STATUS = 6, // Overrun/parity/framing errors or break interrupt
IIR_BUSY = 7,
IIR_CHAR_TIMEOUT = 12 // timeout: Rx dara ready but no read
} LOG_UART_INT_ID;
// Define Interrupt Enable Bit
typedef enum {
IER_ERBFI = BIT(0), // Enable Received Data Available Interrupt
IER_ETBEI = BIT(1), // Enable Transmit Holding Register Empty Interrupt
IER_ELSI = BIT(2), // Enable Receiver Line Status Interrupt
IER_EDSSI = BIT(3), // Enable Modem Status Interrupt
IER_PTIME = BIT(7) // Programmable THRE Interrupt Mode Enable
} LOG_UART_INT_EN;
// Define Line Status Bit
typedef enum {
LSR_DR = BIT(0), // Data Ready bit
LSR_OE = BIT(1), // Overrun error bit
LSR_PE = BIT(2), // Parity Error bit
LSR_FE = BIT(3), // Framing Error bit
LSR_BI = BIT(4), // Break Interrupt bit
LSR_THRE = BIT(5), // Transmit Holding Register Empty bit(IER_PTIME=0)
LSR_FIFOF = BIT(5), // Transmit FIFO Full bit(IER_PTIME=1)
LSR_TEMT = BIT(6), // Transmitter Empty bit
LSR_RFE = BIT(7) // Receiver FIFO Error bit
} LOG_UART_LINE_STATUS;
enum {
LOG_UART_RST_TX_FIFO = 0x01,
LOG_UART_RST_RX_FIFO = 0x02
};
#define LOG_UART_TX_FIFO_DEPTH 16
#define LOG_UART_RX_FIFO_DEPTH 16
// Define FIFO Control Register Bits
typedef enum {
FCR_FIFO_EN = BIT(0), // FIFO Enable.
FCR_RST_RX = BIT(1), // RCVR FIFO Reset, self clear
FCR_RST_TX = BIT(2), // XMIT FIFO Reset, self clear
FCR_TX_TRIG_EMP = 0, // TX Empty Trigger: FIFO empty
FCR_TX_TRIG_2CH = BIT(4), // TX Empty Trigger: 2 characters in the FIFO
FCR_TX_TRIG_QF = BIT(5), // TX Empty Trigger: FIFO 1/4 full
FCR_TX_TRIG_HF = (BIT(5)|BIT(4)), // TX Empty Trigger: FIFO 1/2 full
FCR_TX_TRIG_MASK = (BIT(5)|BIT(4)), // TX Empty Trigger Bit Mask
FCR_RX_TRIG_1CH = 0, // RCVR Trigger: 1 character in the FIFO
FCR_RX_TRIG_QF = BIT(6), // RCVR Trigger: FIFO 1/4 full
FCR_RX_TRIG_HF = BIT(7), // RCVR Trigger: FIFO 1/2 full
FCR_RX_TRIG_AF = (BIT(7)|BIT(6)), // RCVR Trigger: FIFO 2 less than full
FCR_RX_TRIG_MASK = (BIT(7)|BIT(6)) // RCVR Trigger bits Mask
} LOG_UART_FIFO_CTRL;
typedef struct _HAL_LOG_UART_ADAPTER_ {
u32 BaudRate;
u32 FIFOControl;
u32 IntEnReg;
u8 Parity;
u8 Stop;
u8 DataLength;
u8 LineStatus;
volatile u32 TxCount; // how many byte to TX
volatile u32 RxCount; // how many bytes to RX
volatile u8 *pTxBuf;
volatile u8 *pRxBuf;
u8 *pTxStartAddr;
u8 *pRxStartAddr;
IRQ_HANDLE IrqHandle;
VOID (*LineStatusCallback)(VOID *para, u8 status); // User Line Status interrupt callback
VOID (*TxCompCallback)(VOID *para); // User Tx complete callback
VOID (*RxCompCallback)(VOID *para); // User Rx complete callback
VOID *LineStatusCbPara; // the argument for LineStatusCallback
VOID *TxCompCbPara; // the argument for TxCompCallback
VOID *RxCompCbPara; // the argument for RxCompCallback
void (*api_irq_handler)(u32 id, LOG_UART_INT_ID event);
u32 api_irq_id;
}HAL_LOG_UART_ADAPTER, *PHAL_LOG_UART_ADAPTER;
VOID HalLogUartIrqHandle(VOID * Data);
VOID HalLogUartSetBaudRate(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartSetLineCtrl(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartSetIntEn(HAL_LOG_UART_ADAPTER *pUartAdapter);
u32 HalLogUartInitSetting(HAL_LOG_UART_ADAPTER *pUartAdapter);
u32 HalLogUartRecv(HAL_LOG_UART_ADAPTER *pUartAdapter,
u8 *pRxData, u32 Length, u32 TimeoutMS);
u32 HalLogUartSend(HAL_LOG_UART_ADAPTER *pUartAdapter,
u8 *pTxData, u32 Length, u32 TimeoutMS);
HAL_Status HalLogUartIntSend(HAL_LOG_UART_ADAPTER *pUartAdapter,
u8 *pTxData, u32 Length);
HAL_Status HalLogUartIntRecv(HAL_LOG_UART_ADAPTER *pUartAdapter,
u8 *pRxData, u32 Length);
VOID HalLogUartAbortIntSend(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartAbortIntRecv(HAL_LOG_UART_ADAPTER *pUartAdapter);
HAL_Status HalLogUartRstFIFO(HAL_LOG_UART_ADAPTER *pUartAdapter, u8 RstCtrl);
VOID HalLogUartEnable(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartDisable(HAL_LOG_UART_ADAPTER *pUartAdapter);
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_LOG_UART_H_
#define _HAL_LOG_UART_H_
#include "hal_diag.h"
#define LOG_UART_WAIT_FOREVER 0xffffffff
// Define Line Control Register Bits
typedef enum {
LCR_DLS_5B = 0, // Data Length: 5 bits
LCR_DLS_6B = BIT(0), // Data Length: 6 bits
LCR_DLS_7B = BIT(1), // Data Length: 7 bits
LCR_DLS_8B = (BIT(1)|BIT(0)), // Data Length: 7 bits
LCR_STOP_1B = 0, // Number of stop bits: 1
LCR_STOP_2B = BIT(2), // Number of stop bits: 1.5(data len=5) or 2
LCR_PARITY_NONE = 0, // Parity Enable: 0
LCR_PARITY_ODD = BIT(3), // Parity Enable: 1, Even Parity: 0
LCR_PARITY_EVEN = (BIT(4)|BIT(3)), // Parity Enable: 1, Even Parity: 1
LCR_BC = BIT(6), // Break Control Bit
LCR_DLAB = BIT(7) // Divisor Latch Access Bit
} LOG_UART_LINE_CTRL;
// define Log UART Interrupt Indication ID
/*
IIR[3:0]:
0000 = modem status
0001 = no interrupt pending
0010 = THR empty
0100 = received data available
0110 = receiver line status
0111 = busy detect
1100 = character timeout
*/
typedef enum {
IIR_MODEM_STATUS = 0, //Clear to send or data set ready or ring indicator or data carrier detect.
IIR_NO_PENDING = 1,
IIR_THR_EMPTY = 2, // TX FIFO level lower than threshold or FIFO empty
IIR_RX_RDY = 4, // RX data ready
IIR_RX_LINE_STATUS = 6, // Overrun/parity/framing errors or break interrupt
IIR_BUSY = 7,
IIR_CHAR_TIMEOUT = 12 // timeout: Rx dara ready but no read
} LOG_UART_INT_ID;
// Define Interrupt Enable Bit
typedef enum {
IER_ERBFI = BIT(0), // Enable Received Data Available Interrupt
IER_ETBEI = BIT(1), // Enable Transmit Holding Register Empty Interrupt
IER_ELSI = BIT(2), // Enable Receiver Line Status Interrupt
IER_EDSSI = BIT(3), // Enable Modem Status Interrupt
IER_PTIME = BIT(7) // Programmable THRE Interrupt Mode Enable
} LOG_UART_INT_EN;
// Define Line Status Bit
typedef enum {
LSR_DR = BIT(0), // Data Ready bit
LSR_OE = BIT(1), // Overrun error bit
LSR_PE = BIT(2), // Parity Error bit
LSR_FE = BIT(3), // Framing Error bit
LSR_BI = BIT(4), // Break Interrupt bit
LSR_THRE = BIT(5), // Transmit Holding Register Empty bit(IER_PTIME=0)
LSR_FIFOF = BIT(5), // Transmit FIFO Full bit(IER_PTIME=1)
LSR_TEMT = BIT(6), // Transmitter Empty bit
LSR_RFE = BIT(7) // Receiver FIFO Error bit
} LOG_UART_LINE_STATUS;
enum {
LOG_UART_RST_TX_FIFO = 0x01,
LOG_UART_RST_RX_FIFO = 0x02
};
#define LOG_UART_TX_FIFO_DEPTH 16
#define LOG_UART_RX_FIFO_DEPTH 16
// Define FIFO Control Register Bits
typedef enum {
FCR_FIFO_EN = BIT(0), // FIFO Enable.
FCR_RST_RX = BIT(1), // RCVR FIFO Reset, self clear
FCR_RST_TX = BIT(2), // XMIT FIFO Reset, self clear
FCR_TX_TRIG_EMP = 0, // TX Empty Trigger: FIFO empty
FCR_TX_TRIG_2CH = BIT(4), // TX Empty Trigger: 2 characters in the FIFO
FCR_TX_TRIG_QF = BIT(5), // TX Empty Trigger: FIFO 1/4 full
FCR_TX_TRIG_HF = (BIT(5)|BIT(4)), // TX Empty Trigger: FIFO 1/2 full
FCR_TX_TRIG_MASK = (BIT(5)|BIT(4)), // TX Empty Trigger Bit Mask
FCR_RX_TRIG_1CH = 0, // RCVR Trigger: 1 character in the FIFO
FCR_RX_TRIG_QF = BIT(6), // RCVR Trigger: FIFO 1/4 full
FCR_RX_TRIG_HF = BIT(7), // RCVR Trigger: FIFO 1/2 full
FCR_RX_TRIG_AF = (BIT(7)|BIT(6)), // RCVR Trigger: FIFO 2 less than full
FCR_RX_TRIG_MASK = (BIT(7)|BIT(6)) // RCVR Trigger bits Mask
} LOG_UART_FIFO_CTRL;
typedef struct _HAL_LOG_UART_ADAPTER_ {
u32 BaudRate;
u32 FIFOControl;
u32 IntEnReg;
u8 Parity;
u8 Stop;
u8 DataLength;
u8 LineStatus;
volatile u32 TxCount; // how many byte to TX
volatile u32 RxCount; // how many bytes to RX
volatile u8 *pTxBuf;
volatile u8 *pRxBuf;
u8 *pTxStartAddr;
u8 *pRxStartAddr;
IRQ_HANDLE IrqHandle;
VOID (*LineStatusCallback)(VOID *para, u8 status); // User Line Status interrupt callback
VOID (*TxCompCallback)(VOID *para); // User Tx complete callback
VOID (*RxCompCallback)(VOID *para); // User Rx complete callback
VOID *LineStatusCbPara; // the argument for LineStatusCallback
VOID *TxCompCbPara; // the argument for TxCompCallback
VOID *RxCompCbPara; // the argument for RxCompCallback
void (*api_irq_handler)(u32 id, LOG_UART_INT_ID event);
u32 api_irq_id;
}HAL_LOG_UART_ADAPTER, *PHAL_LOG_UART_ADAPTER;
VOID HalLogUartIrqHandle(VOID * Data);
VOID HalLogUartSetBaudRate(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartSetLineCtrl(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartSetIntEn(HAL_LOG_UART_ADAPTER *pUartAdapter);
u32 HalLogUartInitSetting(HAL_LOG_UART_ADAPTER *pUartAdapter);
u32 HalLogUartRecv(HAL_LOG_UART_ADAPTER *pUartAdapter,
u8 *pRxData, u32 Length, u32 TimeoutMS);
u32 HalLogUartSend(HAL_LOG_UART_ADAPTER *pUartAdapter,
u8 *pTxData, u32 Length, u32 TimeoutMS);
HAL_Status HalLogUartIntSend(HAL_LOG_UART_ADAPTER *pUartAdapter,
u8 *pTxData, u32 Length);
HAL_Status HalLogUartIntRecv(HAL_LOG_UART_ADAPTER *pUartAdapter,
u8 *pRxData, u32 Length);
VOID HalLogUartAbortIntSend(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartAbortIntRecv(HAL_LOG_UART_ADAPTER *pUartAdapter);
HAL_Status HalLogUartRstFIFO(HAL_LOG_UART_ADAPTER *pUartAdapter, u8 RstCtrl);
VOID HalLogUartEnable(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartDisable(HAL_LOG_UART_ADAPTER *pUartAdapter);
#endif

44
component/soc/realtek/8195a/fwlib/hal_nfc.h
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@ -1,22 +1,22 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_NFC_H_
#define _HAL_NFC_H_
#include "rtl8195a_nfc.h"
VOID HalNFCOpInit(
IN VOID *Data
);
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_NFC_H_
#define _HAL_NFC_H_
#include "rtl8195a_nfc.h"
VOID HalNFCOpInit(
IN VOID *Data
);
#endif

208
component/soc/realtek/8195a/fwlib/hal_pcm.h
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@ -1,104 +1,104 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PCM_H_
#define _HAL_PCM_H_
#include "rtl8195a_pcm.h"
/*
typedef struct _GDMA_CH_LLI_ELE_ {
u32 Sarx;
u32 Darx;
u32 Llpx;
u32 CtlxLow;
u32 CtlxUp;
u32 Temp;
}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
#if 1
#if 0
typedef struct _GDMA_CH_LLI_ {
PGDMA_CH_LLI_ELE pLliEle;
PGDMA_CH_LLI pNextLli;
}GDMA_CH_LLI, *PGDMA_CH_LLI;
typedef struct _BLOCK_SIZE_LIST_ {
u32 BlockSize;
PBLOCK_SIZE_LIST pNextBlockSiz;
}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
#else
struct GDMA_CH_LLI {
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pNextLli;
};
struct BLOCK_SIZE_LIST {
u32 BlockSize;
struct BLOCK_SIZE_LIST *pNextBlockSiz;
};
#endif
#endif
typedef struct _HAL_GDMA_ADAPTER_ {
u32 ChSar;
u32 ChDar;
GDMA_CHANNEL_NUM ChEn;
GDMA_CTL_REG GdmaCtl;
GDMA_CFG_REG GdmaCfg;
u32 PacketLen;
u32 BlockLen;
u32 MuliBlockCunt;
u32 MaxMuliBlock;
struct GDMA_CH_LLI *pLlix;
struct BLOCK_SIZE_LIST *pBlockSizeList;
PGDMA_CH_LLI_ELE pLli;
u32 NextPlli;
u8 TestItem;
u8 ChNum;
u8 GdmaIndex;
u8 IsrCtrl:1;
u8 GdmaOnOff:1;
u8 Llpctrl:1;
u8 Lli0:1;
u8 Rsvd4to7:4;
u8 GdmaIsrType;
}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
*/
typedef struct _HAL_PCM_ADAPTER_ {
u32 Enable:1;
PCM_CTL_REG PcmCtl;
PCM_CHCNR03_REG PcmChCNR03;
PCM_TSR03_REG PcmTSR03;
PCM_BSIZE03_REG PcmBSize03;
u32 abc;
u8 PcmIndex;
u8 PcmCh;
}HAL_PCM_ADAPTER, *PHAL_PCM_ADAPTER;
typedef struct _HAL_PCM_OP_ {
VOID (*HalPcmOnOff)(VOID *Data);
BOOL (*HalPcmInit)(VOID *Data);
BOOL (*HalPcmSetting)(VOID *Data);
BOOL (*HalPcmEn)(VOID *Data);
BOOL (*HalPcmIsrEnAndDis) (VOID *Data);
BOOL (*HalPcmDumpReg)(VOID *Data);
BOOL (*HalPcm)(VOID *Data);
}HAL_PCM_OP, *PHAL_PCM_OP;
VOID HalPcmOpInit(
IN VOID *Data
);
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PCM_H_
#define _HAL_PCM_H_
#include "rtl8195a_pcm.h"
/*
typedef struct _GDMA_CH_LLI_ELE_ {
u32 Sarx;
u32 Darx;
u32 Llpx;
u32 CtlxLow;
u32 CtlxUp;
u32 Temp;
}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
#if 1
#if 0
typedef struct _GDMA_CH_LLI_ {
PGDMA_CH_LLI_ELE pLliEle;
PGDMA_CH_LLI pNextLli;
}GDMA_CH_LLI, *PGDMA_CH_LLI;
typedef struct _BLOCK_SIZE_LIST_ {
u32 BlockSize;
PBLOCK_SIZE_LIST pNextBlockSiz;
}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
#else
struct GDMA_CH_LLI {
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pNextLli;
};
struct BLOCK_SIZE_LIST {
u32 BlockSize;
struct BLOCK_SIZE_LIST *pNextBlockSiz;
};
#endif
#endif
typedef struct _HAL_GDMA_ADAPTER_ {
u32 ChSar;
u32 ChDar;
GDMA_CHANNEL_NUM ChEn;
GDMA_CTL_REG GdmaCtl;
GDMA_CFG_REG GdmaCfg;
u32 PacketLen;
u32 BlockLen;
u32 MuliBlockCunt;
u32 MaxMuliBlock;
struct GDMA_CH_LLI *pLlix;
struct BLOCK_SIZE_LIST *pBlockSizeList;
PGDMA_CH_LLI_ELE pLli;
u32 NextPlli;
u8 TestItem;
u8 ChNum;
u8 GdmaIndex;
u8 IsrCtrl:1;
u8 GdmaOnOff:1;
u8 Llpctrl:1;
u8 Lli0:1;
u8 Rsvd4to7:4;
u8 GdmaIsrType;
}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
*/
typedef struct _HAL_PCM_ADAPTER_ {
u32 Enable:1;
PCM_CTL_REG PcmCtl;
PCM_CHCNR03_REG PcmChCNR03;
PCM_TSR03_REG PcmTSR03;
PCM_BSIZE03_REG PcmBSize03;
u32 abc;
u8 PcmIndex;
u8 PcmCh;
}HAL_PCM_ADAPTER, *PHAL_PCM_ADAPTER;
typedef struct _HAL_PCM_OP_ {
VOID (*HalPcmOnOff)(VOID *Data);
BOOL (*HalPcmInit)(VOID *Data);
BOOL (*HalPcmSetting)(VOID *Data);
BOOL (*HalPcmEn)(VOID *Data);
BOOL (*HalPcmIsrEnAndDis) (VOID *Data);
BOOL (*HalPcmDumpReg)(VOID *Data);
BOOL (*HalPcm)(VOID *Data);
}HAL_PCM_OP, *PHAL_PCM_OP;
VOID HalPcmOpInit(
IN VOID *Data
);
#endif

902
component/soc/realtek/8195a/fwlib/hal_peri_on.h
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@ -1,451 +1,451 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PERI_ON_H_
#define _HAL_PERI_ON_H_
#define MASK_ALLON 0xFFFFFFFF
#define HAL_PERI_ON_READ32(addr) HAL_READ32(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE32(addr, value) HAL_WRITE32(PERI_ON_BASE, addr, value)
#define HAL_PERI_ON_READ16(addr) HAL_READ16(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE16(addr, value) HAL_WRITE16(PERI_ON_BASE, addr, value)
#define HAL_PERI_ON_READ8(addr) HAL_READ8(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE8(addr, value) HAL_WRITE8(PERI_ON_BASE, addr, value)
#define HAL_PERL_ON_FUNC_CTRL(addr,value,ctrl) \
HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~value))|((MASK_ALLON - ctrl + 1) & value)))
#define HAL_PERL_ON_PIN_SEL(addr,mask,value) \
HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~mask)) | value))
//40 REG_SYS_REGU_CTRL0
#define LDO25M_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_REGU_CTRL0, BIT_SYS_REGU_LDO25M_EN, ctrl)
//A0 SYS_DEBUG_CTRL
#define DEBUG_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_DEBUG_CTRL, BIT_SYS_DBG_PIN_EN, ctrl)
//A4 SYS_PINMUX_CTRL
#define SIC_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_SIC_PIN_EN, ctrl)
#define EEPROM_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_EEPROM_PIN_EN, ctrl)
//210 SOV_FUNC_EN
#define LXBUS_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LXBUS_EN, ctrl)
#define FLASH_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI_FLASH_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_FLASH_EN, ctrl);}
#define MEM_CTRL_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDR_SDRAM_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_MEM_CTRL_EN, ctrl);}
#define LOC_UART_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(LOG_UART_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LOG_UART_EN, ctrl);}
#define GDMA0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GDMA0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA0_EN, ctrl);}
#define GDMA1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GDMA1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA1_EN, ctrl);}
#define GTIMER_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(TIMER_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GTIMER_EN, ctrl);}
#define SECURITY_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(CRYPTO_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_SECURITY_ENGINE_EN, ctrl);}
//214 SOC_HCI_COM_FUNC_EN
#define SDIOD_ON_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN, ctrl);}
#define SDIOD_OFF_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN, ctrl);}
#define SDIOH_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_HOST_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN, ctrl);}
#define SDIO_ON_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_RST_MUX, ctrl)
#define OTG_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(USB_OTG_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_EN, ctrl);}
#define OTG_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_RST_MUX, ctrl)
#define MII_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(MII_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_MII_EN, ctrl);}
#define MII_MUX_SEL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SM_SEL, ctrl)
#define WL_MACON_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(WIFI_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_WL_MACON_EN, ctrl);}
//218 SOC_PERI_FUNC0_EN
#define UART0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART0_EN, ctrl);}
#define UART1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART1_EN, ctrl);}
#define UART2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART2_EN, ctrl);}
#define SPI0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI0_EN, ctrl);}
#define SPI1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI1_EN, ctrl);}
#define SPI2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI2_EN, ctrl);}
#define I2C0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C0_EN, ctrl);}
#define I2C1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C1_EN, ctrl);}
#define I2C2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C2_EN, ctrl);}
#define I2C3_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C3_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C3_EN, ctrl);}
#define I2S0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2S0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S0_EN, ctrl);}
#define I2S1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2S1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S1_EN, ctrl);}
#define PCM0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(PCM0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM0_EN, ctrl);}
#define PCM1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(PCM1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM1_EN, ctrl);}
//21C SOC_PERI_FUNC1_EN
#define ADC0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(ADC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_ADC0_EN, ctrl);}
#define DAC0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(DAC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC0_EN, ctrl);}
#define DAC1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(DAC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC1_EN, ctrl);}
#define GPIO_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GPIO_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_GPIO_EN, ctrl);}
//220 SOC_PERI_BD_FUNC0_EN
#define UART0_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART0_BD_EN, ctrl);}
#define UART1_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART1_BD_EN, ctrl);}
#define UART2_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART2_BD_EN, ctrl);}
//230 PESOC_CLK_CTRL
#define ACTCK_CPU_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_CKE_PLFM, ctrl)
#define ACTCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TRACE_EN, ctrl)
#define SLPCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TRACE_EN, ctrl)
#define ACTCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_VENDOR_REG_EN, ctrl)
#define SLPCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_VENDOR_REG_EN, ctrl)
#define ACTCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_FLASH_EN, ctrl)
#define SLPCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_FLASH_EN, ctrl)
#define ACTCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_SDR_EN, ctrl)
#define SLPCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_SDR_EN, ctrl)
#define ACTCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_LOG_UART_EN, ctrl)
#define SLPCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_LOG_UART_EN, ctrl)
#define ACTCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TIMER_EN, ctrl)
#define SLPCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TIMER_EN, ctrl)
#define ACTCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA0_EN, ctrl)
#define SLPCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA0_EN, ctrl)
#define ACTCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA1_EN, ctrl)
#define SLPCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA1_EN, ctrl)
#define ACTCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GPIO_EN, ctrl)
#define SLPCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GPIO_EN, ctrl)
#define ACTCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_BTCMD_EN, ctrl)
#define SLPCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_BTCMD_EN, ctrl)
//234 PESOC_PERI_CLK_CTRL0
#define ACTCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART0_EN, ctrl)
#define SLPCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART0_EN, ctrl)
#define ACTCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART1_EN, ctrl)
#define SLPCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART1_EN, ctrl)
#define ACTCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART2_EN, ctrl)
#define SLPCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART2_EN, ctrl)
#define ACTCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI0_EN, ctrl)
#define SLPCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI0_EN, ctrl)
#define ACTCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI1_EN, ctrl)
#define SLPCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI1_EN, ctrl)
#define ACTCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI2_EN, ctrl)
#define SLPCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI2_EN, ctrl)
//238 PESOC_PERI_CLK_CTRL1
#define ACTCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C0_EN, ctrl)
#define SLPCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C0_EN, ctrl)
#define ACTCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C1_EN, ctrl)
#define SLPCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C1_EN, ctrl)
#define ACTCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C2_EN, ctrl)
#define SLPCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C2_EN, ctrl)
#define ACTCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C3_EN, ctrl)
#define SLPCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C3_EN, ctrl)
#define ACTCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2S_EN, ctrl)
#define SLPCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2S_EN, ctrl)
#define ACTCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_PCM_EN, ctrl)
#define SLPCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_PCM_EN, ctrl)
#define ACTCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_ADC_EN, ctrl)
#define SLPCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_ADC_EN, ctrl)
#define ACTCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_DAC_EN, ctrl)
#define SLPCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_DAC_EN, ctrl)
//240 PESOC_HCI_CLK_CTRL0
#define ACTCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_DEV_EN, ctrl)
#define SLPCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_DEV_EN, ctrl)
#define ACTCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_HST_EN, ctrl)
#define SLPCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_HST_EN, ctrl)
#define ACTCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_OTG_EN, ctrl)
#define SLPCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_OTG_EN, ctrl)
#define ACTCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_MII_MPHY_EN, ctrl)
#define SLPCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_MII_MPHY_EN, ctrl)
//244 PESOC_COM_CLK_CTRL1
#define ACTCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_WL_EN, ctrl)
#define SLPCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_WL_EN, ctrl)
#define ACTCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_SECURITY_ENG_EN, ctrl)
#define SLPCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_SECURITY_ENG_EN, ctrl)
#define ACTCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_NFC_EN, ctrl)
#define SLPCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_NFC_EN, ctrl)
#define NFC_CAL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_NFC_CAL_EN, ctrl)
//250 REG_PERI_CLK_SEL
#define TRACE_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_TRACE_CK_SEL << BIT_SHIFT_PESOC_TRACE_CK_SEL), BIT_PESOC_TRACE_CK_SEL(num))
#define FLASH_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_FLASH_CK_SEL << BIT_SHIFT_PESOC_FLASH_CK_SEL), BIT_PESOC_FLASH_CK_SEL(num))
#define SDR_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_SDR_CK_SEL << BIT_SHIFT_PESOC_SDR_CK_SEL), BIT_PESOC_SDR_CK_SEL(num))
#define I2C_SCLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_PERI_SCLK_SEL << BIT_SHIFT_PESOC_PERI_SCLK_SEL), BIT_PESOC_PERI_SCLK_SEL(num))
//270 REG_OSC32K_CTRL
#define OSC32K_CKGEN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_OSC32K_CTRL, BIT_32K_POW_CKGEN_EN, ctrl)
//280 REG_UART_MUX_CTRL
#define UART0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART0_PIN_EN, ctrl)
#define UART0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART0_PIN_SEL << BIT_SHIFT_UART0_PIN_SEL), BIT_UART0_PIN_SEL(num))
#define UART1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART1_PIN_EN, ctrl)
#define UART1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART1_PIN_SEL << BIT_SHIFT_UART1_PIN_SEL), BIT_UART1_PIN_SEL(num))
#define UART2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART2_PIN_EN, ctrl)
#define UART2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART2_PIN_SEL << BIT_SHIFT_UART2_PIN_SEL), BIT_UART2_PIN_SEL(num))
//284 REG_SPI_MUX_CTRL
#define SPI0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_PIN_EN, ctrl)
#define SPI0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI0_PIN_SEL << BIT_SHIFT_SPI0_PIN_SEL), BIT_SPI0_PIN_SEL(num))
#define SPI1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI1_PIN_EN, ctrl)
#define SPI1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI1_PIN_SEL << BIT_SHIFT_SPI1_PIN_SEL), BIT_SPI1_PIN_SEL(num))
#define SPI2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI2_PIN_EN, ctrl)
#define SPI2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI2_PIN_SEL << BIT_SHIFT_SPI2_PIN_SEL), BIT_SPI2_PIN_SEL(num))
#define SPI0_MULTI_CS_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_MULTI_CS_EN, ctrl)
//288 REG_I2C_MUX_CTRL
#define I2C0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C0_PIN_EN, ctrl)
#define I2C0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C0_PIN_SEL << BIT_SHIFT_I2C0_PIN_SEL), BIT_I2C0_PIN_SEL(num))
#define I2C1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C1_PIN_EN, ctrl)
#define I2C1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C1_PIN_SEL << BIT_SHIFT_I2C1_PIN_SEL), BIT_I2C1_PIN_SEL(num))
#define I2C2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C2_PIN_EN, ctrl)
#define I2C2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C2_PIN_SEL << BIT_SHIFT_I2C2_PIN_SEL), BIT_I2C2_PIN_SEL(num))
#define I2C3_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C3_PIN_EN, ctrl)
#define I2C3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C3_PIN_SEL << BIT_SHIFT_I2C3_PIN_SEL), BIT_I2C3_PIN_SEL(num))
//28C REG_I2S_MUX_CTRL
#define I2S0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_PIN_EN, ctrl)
#define I2S0_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_MCK_EN, ctrl)
#define I2S0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S0_PIN_SEL << BIT_SHIFT_I2S0_PIN_SEL), BIT_I2S0_PIN_SEL(num))
#define I2S1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_PIN_EN, ctrl)
#define I2S1_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_MCK_EN, ctrl)
#define I2S1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S1_PIN_SEL << BIT_SHIFT_I2S1_PIN_SEL), BIT_I2S1_PIN_SEL(num))
#define PCM0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM0_PIN_EN, ctrl)
#define PCM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM0_PIN_SEL << BIT_SHIFT_PCM0_PIN_SEL), BIT_PCM0_PIN_SEL(num))
#define PCM1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM1_PIN_EN, ctrl)
#define PCM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM1_PIN_SEL << BIT_SHIFT_PCM1_PIN_SEL), BIT_PCM1_PIN_SEL(num))
//2A0 HCI_PINMUX_CTRL
#define SDIOD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN, ctrl)
#define SDIOH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN, ctrl)
#define MII_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN, ctrl)
//2A4 WL_PINMUX_CTRL
#define LED_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_LED_PIN_EN, ctrl)
#define LED_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_WL_PINMUX_CTRL, (BIT_MASK_WL_LED_PIN_SEL << BIT_SHIFT_WL_LED_PIN_SEL), BIT_WL_LED_PIN_SEL(num))
#define ANT0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT0_PIN_EN, ctrl)
#define ANT1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT1_PIN_EN, ctrl)
#define BTCOEX_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCOEX_PIN_EN, ctrl)
#define BTCMD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCMD_PIN_EN, ctrl)
#define NFC_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_NFC_PIN_EN, ctrl)
//2AC PWM_PINMUX_CTRL
#define PWM0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM0_PIN_EN, ctrl)
#define PWM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM0_PIN_SEL << BIT_SHIFT_PWM0_PIN_SEL), BIT_PWM0_PIN_SEL(num))
#define PWM1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM1_PIN_EN, ctrl)
#define PWM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM1_PIN_SEL << BIT_SHIFT_PWM1_PIN_SEL), BIT_PWM1_PIN_SEL(num))
#define PWM2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM2_PIN_EN, ctrl)
#define PWM2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM2_PIN_SEL << BIT_SHIFT_PWM2_PIN_SEL), BIT_PWM2_PIN_SEL(num))
#define PWM3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM3_PIN_EN, ctrl)
#define PWM3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM3_PIN_SEL << BIT_SHIFT_PWM3_PIN_SEL), BIT_PWM3_PIN_SEL(num))
#define ETE0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE0_PIN_EN, ctrl)
#define ETE0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE0_PIN_SEL << BIT_SHIFT_ETE0_PIN_SEL), BIT_ETE0_PIN_SEL(num))
#define ETE1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE1_PIN_EN, ctrl)
#define ETE1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE1_PIN_SEL << BIT_SHIFT_ETE1_PIN_SEL), BIT_ETE1_PIN_SEL(num))
#define ETE2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE2_PIN_EN, ctrl)
#define ETE2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE2_PIN_SEL << BIT_SHIFT_ETE2_PIN_SEL), BIT_ETE2_PIN_SEL(num))
#define ETE3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE3_PIN_EN, ctrl)
#define ETE3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE3_PIN_SEL << BIT_SHIFT_ETE3_PIN_SEL), BIT_ETE3_PIN_SEL(num))
//2C0 CPU_PERIPHERAL_CTRL
#define SPI_FLASH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SPI_FLSH_PIN_EN, ctrl)
#define SPI_FLASH_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_CPU_PERIPHERAL_CTRL, (BIT_MASK_SPI_FLSH_PIN_SEL << BIT_SHIFT_SPI_FLSH_PIN_SEL), BIT_SPI_FLSH_PIN_SEL(num))
#define SDR_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SDR_PIN_EN, ctrl)
#define TRACE_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_TRACE_PIN_EN, ctrl)
#define LOG_UART_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_PIN_EN, ctrl)
#define LOG_UART_IR_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_IR_EN, ctrl)
//300 REG_PESOC_MEM_CTRL
#define SDR_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_SDR_DDL_CTRL << BIT_SHIFT_PESOC_SDR_DDL_CTRL), BIT_PESOC_SDR_DDL_CTRL(ctrl))
#define FLASH_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_FLASH_DDL_CTRL << BIT_SHIFT_PESOC_FLASH_DDL_CTRL), BIT_PESOC_FLASH_DDL_CTRL(ctrl))
//304 REG_PESOC_SOC_CTRL
#define SRAM_MUX_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_SRAM_MUX_CFG << BIT_SHIFT_PESOC_SRAM_MUX_CFG), BIT_PESOC_SRAM_MUX_CFG(num))
#define LX_WL_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_WL_SWAP_SEL, ctrl)
#define LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_MST_SWAP_SEL, ctrl)
#define LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_SLV_SWAP_SEL, ctrl)
#define MII_LX_WRAPPER_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_WRAPPER_EN, ctrl)
#define MII_LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_MST_SWAP_SEL, ctrl)
#define MII_LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_SLV_SWAP_SEL, ctrl)
#define GDMA_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_GDMA_CFG << BIT_SHIFT_PESOC_GDMA_CFG), BIT_PESOC_GDMA_CFG(num))
//308 PESOC_PERI_CTRL
#define SPI_RN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CTRL, BIT_SOC_FUNC_SPI_RN, ctrl)
//320 GPIO_SHTDN_CTRL
#define GPIO_GPA_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPA_SHTDN_N, ctrl)
#define GPIO_GPB_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPB_SHTDN_N, ctrl)
#define GPIO_GPC_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPC_SHTDN_N, ctrl)
#define GPIO_GPD_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPD_SHTDN_N, ctrl)
#define GPIO_GPE_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPE_SHTDN_N, ctrl)
#define GPIO_GPF_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPF_SHTDN_N, ctrl)
#define GPIO_GPG_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPG_SHTDN_N, ctrl)
#define GPIO_GPH_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPH_SHTDN_N, ctrl)
#define GPIO_GPI_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPI_SHTDN_N, ctrl)
#define GPIO_GPJ_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPJ_SHTDN_N, ctrl)
#define GPIO_GPK_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPK_SHTDN_N, ctrl)
//374
#define EGTIM_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PERI_EGTIM_CTRL, BIT_PERI_EGTIM_EN, ctrl)
#define EGTIM_RSIG_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_REF_SIG_SEL << BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL), BIT_PERI_EGTIM_REF_SIG_SEL(num))
#define EGTIME_PIN_G0_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP0_OPT_SEL(num))
#define EGTIME_PIN_G1_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP1_OPT_SEL(num))
#define EGTIME_PIN_G2_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP2_OPT_SEL(num))
#endif //_HAL_PERI_ON_H_
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PERI_ON_H_
#define _HAL_PERI_ON_H_
#define MASK_ALLON 0xFFFFFFFF
#define HAL_PERI_ON_READ32(addr) HAL_READ32(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE32(addr, value) HAL_WRITE32(PERI_ON_BASE, addr, value)
#define HAL_PERI_ON_READ16(addr) HAL_READ16(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE16(addr, value) HAL_WRITE16(PERI_ON_BASE, addr, value)
#define HAL_PERI_ON_READ8(addr) HAL_READ8(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE8(addr, value) HAL_WRITE8(PERI_ON_BASE, addr, value)
#define HAL_PERL_ON_FUNC_CTRL(addr,value,ctrl) \
HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~value))|((MASK_ALLON - ctrl + 1) & value)))
#define HAL_PERL_ON_PIN_SEL(addr,mask,value) \
HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~mask)) | value))
//40 REG_SYS_REGU_CTRL0
#define LDO25M_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_REGU_CTRL0, BIT_SYS_REGU_LDO25M_EN, ctrl)
//A0 SYS_DEBUG_CTRL
#define DEBUG_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_DEBUG_CTRL, BIT_SYS_DBG_PIN_EN, ctrl)
//A4 SYS_PINMUX_CTRL
#define SIC_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_SIC_PIN_EN, ctrl)
#define EEPROM_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_EEPROM_PIN_EN, ctrl)
//210 SOV_FUNC_EN
#define LXBUS_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LXBUS_EN, ctrl)
#define FLASH_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI_FLASH_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_FLASH_EN, ctrl);}
#define MEM_CTRL_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDR_SDRAM_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_MEM_CTRL_EN, ctrl);}
#define LOC_UART_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(LOG_UART_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LOG_UART_EN, ctrl);}
#define GDMA0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GDMA0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA0_EN, ctrl);}
#define GDMA1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GDMA1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA1_EN, ctrl);}
#define GTIMER_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(TIMER_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GTIMER_EN, ctrl);}
#define SECURITY_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(CRYPTO_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_SECURITY_ENGINE_EN, ctrl);}
//214 SOC_HCI_COM_FUNC_EN
#define SDIOD_ON_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN, ctrl);}
#define SDIOD_OFF_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN, ctrl);}
#define SDIOH_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_HOST_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN, ctrl);}
#define SDIO_ON_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_RST_MUX, ctrl)
#define OTG_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(USB_OTG_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_EN, ctrl);}
#define OTG_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_RST_MUX, ctrl)
#define MII_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(MII_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_MII_EN, ctrl);}
#define MII_MUX_SEL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SM_SEL, ctrl)
#define WL_MACON_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(WIFI_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_WL_MACON_EN, ctrl);}
//218 SOC_PERI_FUNC0_EN
#define UART0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART0_EN, ctrl);}
#define UART1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART1_EN, ctrl);}
#define UART2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART2_EN, ctrl);}
#define SPI0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI0_EN, ctrl);}
#define SPI1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI1_EN, ctrl);}
#define SPI2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI2_EN, ctrl);}
#define I2C0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C0_EN, ctrl);}
#define I2C1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C1_EN, ctrl);}
#define I2C2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C2_EN, ctrl);}
#define I2C3_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C3_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C3_EN, ctrl);}
#define I2S0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2S0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S0_EN, ctrl);}
#define I2S1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2S1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S1_EN, ctrl);}
#define PCM0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(PCM0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM0_EN, ctrl);}
#define PCM1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(PCM1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM1_EN, ctrl);}
//21C SOC_PERI_FUNC1_EN
#define ADC0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(ADC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_ADC0_EN, ctrl);}
#define DAC0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(DAC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC0_EN, ctrl);}
#define DAC1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(DAC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC1_EN, ctrl);}
#define GPIO_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GPIO_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_GPIO_EN, ctrl);}
//220 SOC_PERI_BD_FUNC0_EN
#define UART0_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART0_BD_EN, ctrl);}
#define UART1_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART1_BD_EN, ctrl);}
#define UART2_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART2_BD_EN, ctrl);}
//230 PESOC_CLK_CTRL
#define ACTCK_CPU_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_CKE_PLFM, ctrl)
#define ACTCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TRACE_EN, ctrl)
#define SLPCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TRACE_EN, ctrl)
#define ACTCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_VENDOR_REG_EN, ctrl)
#define SLPCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_VENDOR_REG_EN, ctrl)
#define ACTCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_FLASH_EN, ctrl)
#define SLPCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_FLASH_EN, ctrl)
#define ACTCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_SDR_EN, ctrl)
#define SLPCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_SDR_EN, ctrl)
#define ACTCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_LOG_UART_EN, ctrl)
#define SLPCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_LOG_UART_EN, ctrl)
#define ACTCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TIMER_EN, ctrl)
#define SLPCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TIMER_EN, ctrl)
#define ACTCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA0_EN, ctrl)
#define SLPCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA0_EN, ctrl)
#define ACTCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA1_EN, ctrl)
#define SLPCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA1_EN, ctrl)
#define ACTCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GPIO_EN, ctrl)
#define SLPCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GPIO_EN, ctrl)
#define ACTCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_BTCMD_EN, ctrl)
#define SLPCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_BTCMD_EN, ctrl)
//234 PESOC_PERI_CLK_CTRL0
#define ACTCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART0_EN, ctrl)
#define SLPCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART0_EN, ctrl)
#define ACTCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART1_EN, ctrl)
#define SLPCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART1_EN, ctrl)
#define ACTCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART2_EN, ctrl)
#define SLPCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART2_EN, ctrl)
#define ACTCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI0_EN, ctrl)
#define SLPCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI0_EN, ctrl)
#define ACTCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI1_EN, ctrl)
#define SLPCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI1_EN, ctrl)
#define ACTCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI2_EN, ctrl)
#define SLPCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI2_EN, ctrl)
//238 PESOC_PERI_CLK_CTRL1
#define ACTCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C0_EN, ctrl)
#define SLPCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C0_EN, ctrl)
#define ACTCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C1_EN, ctrl)
#define SLPCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C1_EN, ctrl)
#define ACTCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C2_EN, ctrl)
#define SLPCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C2_EN, ctrl)
#define ACTCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C3_EN, ctrl)
#define SLPCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C3_EN, ctrl)
#define ACTCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2S_EN, ctrl)
#define SLPCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2S_EN, ctrl)
#define ACTCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_PCM_EN, ctrl)
#define SLPCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_PCM_EN, ctrl)
#define ACTCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_ADC_EN, ctrl)
#define SLPCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_ADC_EN, ctrl)
#define ACTCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_DAC_EN, ctrl)
#define SLPCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_DAC_EN, ctrl)
//240 PESOC_HCI_CLK_CTRL0
#define ACTCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_DEV_EN, ctrl)
#define SLPCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_DEV_EN, ctrl)
#define ACTCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_HST_EN, ctrl)
#define SLPCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_HST_EN, ctrl)
#define ACTCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_OTG_EN, ctrl)
#define SLPCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_OTG_EN, ctrl)
#define ACTCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_MII_MPHY_EN, ctrl)
#define SLPCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_MII_MPHY_EN, ctrl)
//244 PESOC_COM_CLK_CTRL1
#define ACTCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_WL_EN, ctrl)
#define SLPCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_WL_EN, ctrl)
#define ACTCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_SECURITY_ENG_EN, ctrl)
#define SLPCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_SECURITY_ENG_EN, ctrl)
#define ACTCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_NFC_EN, ctrl)
#define SLPCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_NFC_EN, ctrl)
#define NFC_CAL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_NFC_CAL_EN, ctrl)
//250 REG_PERI_CLK_SEL
#define TRACE_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_TRACE_CK_SEL << BIT_SHIFT_PESOC_TRACE_CK_SEL), BIT_PESOC_TRACE_CK_SEL(num))
#define FLASH_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_FLASH_CK_SEL << BIT_SHIFT_PESOC_FLASH_CK_SEL), BIT_PESOC_FLASH_CK_SEL(num))
#define SDR_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_SDR_CK_SEL << BIT_SHIFT_PESOC_SDR_CK_SEL), BIT_PESOC_SDR_CK_SEL(num))
#define I2C_SCLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_PERI_SCLK_SEL << BIT_SHIFT_PESOC_PERI_SCLK_SEL), BIT_PESOC_PERI_SCLK_SEL(num))
//270 REG_OSC32K_CTRL
#define OSC32K_CKGEN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_OSC32K_CTRL, BIT_32K_POW_CKGEN_EN, ctrl)
//280 REG_UART_MUX_CTRL
#define UART0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART0_PIN_EN, ctrl)
#define UART0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART0_PIN_SEL << BIT_SHIFT_UART0_PIN_SEL), BIT_UART0_PIN_SEL(num))
#define UART1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART1_PIN_EN, ctrl)
#define UART1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART1_PIN_SEL << BIT_SHIFT_UART1_PIN_SEL), BIT_UART1_PIN_SEL(num))
#define UART2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART2_PIN_EN, ctrl)
#define UART2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART2_PIN_SEL << BIT_SHIFT_UART2_PIN_SEL), BIT_UART2_PIN_SEL(num))
//284 REG_SPI_MUX_CTRL
#define SPI0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_PIN_EN, ctrl)
#define SPI0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI0_PIN_SEL << BIT_SHIFT_SPI0_PIN_SEL), BIT_SPI0_PIN_SEL(num))
#define SPI1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI1_PIN_EN, ctrl)
#define SPI1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI1_PIN_SEL << BIT_SHIFT_SPI1_PIN_SEL), BIT_SPI1_PIN_SEL(num))
#define SPI2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI2_PIN_EN, ctrl)
#define SPI2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI2_PIN_SEL << BIT_SHIFT_SPI2_PIN_SEL), BIT_SPI2_PIN_SEL(num))
#define SPI0_MULTI_CS_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_MULTI_CS_EN, ctrl)
//288 REG_I2C_MUX_CTRL
#define I2C0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C0_PIN_EN, ctrl)
#define I2C0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C0_PIN_SEL << BIT_SHIFT_I2C0_PIN_SEL), BIT_I2C0_PIN_SEL(num))
#define I2C1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C1_PIN_EN, ctrl)
#define I2C1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C1_PIN_SEL << BIT_SHIFT_I2C1_PIN_SEL), BIT_I2C1_PIN_SEL(num))
#define I2C2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C2_PIN_EN, ctrl)
#define I2C2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C2_PIN_SEL << BIT_SHIFT_I2C2_PIN_SEL), BIT_I2C2_PIN_SEL(num))
#define I2C3_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C3_PIN_EN, ctrl)
#define I2C3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C3_PIN_SEL << BIT_SHIFT_I2C3_PIN_SEL), BIT_I2C3_PIN_SEL(num))
//28C REG_I2S_MUX_CTRL
#define I2S0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_PIN_EN, ctrl)
#define I2S0_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_MCK_EN, ctrl)
#define I2S0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S0_PIN_SEL << BIT_SHIFT_I2S0_PIN_SEL), BIT_I2S0_PIN_SEL(num))
#define I2S1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_PIN_EN, ctrl)
#define I2S1_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_MCK_EN, ctrl)
#define I2S1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S1_PIN_SEL << BIT_SHIFT_I2S1_PIN_SEL), BIT_I2S1_PIN_SEL(num))
#define PCM0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM0_PIN_EN, ctrl)
#define PCM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM0_PIN_SEL << BIT_SHIFT_PCM0_PIN_SEL), BIT_PCM0_PIN_SEL(num))
#define PCM1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM1_PIN_EN, ctrl)
#define PCM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM1_PIN_SEL << BIT_SHIFT_PCM1_PIN_SEL), BIT_PCM1_PIN_SEL(num))
//2A0 HCI_PINMUX_CTRL
#define SDIOD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN, ctrl)
#define SDIOH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN, ctrl)
#define MII_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN, ctrl)
//2A4 WL_PINMUX_CTRL
#define LED_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_LED_PIN_EN, ctrl)
#define LED_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_WL_PINMUX_CTRL, (BIT_MASK_WL_LED_PIN_SEL << BIT_SHIFT_WL_LED_PIN_SEL), BIT_WL_LED_PIN_SEL(num))
#define ANT0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT0_PIN_EN, ctrl)
#define ANT1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT1_PIN_EN, ctrl)
#define BTCOEX_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCOEX_PIN_EN, ctrl)
#define BTCMD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCMD_PIN_EN, ctrl)
#define NFC_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_NFC_PIN_EN, ctrl)
//2AC PWM_PINMUX_CTRL
#define PWM0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM0_PIN_EN, ctrl)
#define PWM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM0_PIN_SEL << BIT_SHIFT_PWM0_PIN_SEL), BIT_PWM0_PIN_SEL(num))
#define PWM1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM1_PIN_EN, ctrl)
#define PWM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM1_PIN_SEL << BIT_SHIFT_PWM1_PIN_SEL), BIT_PWM1_PIN_SEL(num))
#define PWM2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM2_PIN_EN, ctrl)
#define PWM2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM2_PIN_SEL << BIT_SHIFT_PWM2_PIN_SEL), BIT_PWM2_PIN_SEL(num))
#define PWM3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM3_PIN_EN, ctrl)
#define PWM3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM3_PIN_SEL << BIT_SHIFT_PWM3_PIN_SEL), BIT_PWM3_PIN_SEL(num))
#define ETE0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE0_PIN_EN, ctrl)
#define ETE0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE0_PIN_SEL << BIT_SHIFT_ETE0_PIN_SEL), BIT_ETE0_PIN_SEL(num))
#define ETE1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE1_PIN_EN, ctrl)
#define ETE1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE1_PIN_SEL << BIT_SHIFT_ETE1_PIN_SEL), BIT_ETE1_PIN_SEL(num))
#define ETE2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE2_PIN_EN, ctrl)
#define ETE2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE2_PIN_SEL << BIT_SHIFT_ETE2_PIN_SEL), BIT_ETE2_PIN_SEL(num))
#define ETE3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE3_PIN_EN, ctrl)
#define ETE3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE3_PIN_SEL << BIT_SHIFT_ETE3_PIN_SEL), BIT_ETE3_PIN_SEL(num))
//2C0 CPU_PERIPHERAL_CTRL
#define SPI_FLASH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SPI_FLSH_PIN_EN, ctrl)
#define SPI_FLASH_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_CPU_PERIPHERAL_CTRL, (BIT_MASK_SPI_FLSH_PIN_SEL << BIT_SHIFT_SPI_FLSH_PIN_SEL), BIT_SPI_FLSH_PIN_SEL(num))
#define SDR_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SDR_PIN_EN, ctrl)
#define TRACE_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_TRACE_PIN_EN, ctrl)
#define LOG_UART_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_PIN_EN, ctrl)
#define LOG_UART_IR_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_IR_EN, ctrl)
//300 REG_PESOC_MEM_CTRL
#define SDR_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_SDR_DDL_CTRL << BIT_SHIFT_PESOC_SDR_DDL_CTRL), BIT_PESOC_SDR_DDL_CTRL(ctrl))
#define FLASH_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_FLASH_DDL_CTRL << BIT_SHIFT_PESOC_FLASH_DDL_CTRL), BIT_PESOC_FLASH_DDL_CTRL(ctrl))
//304 REG_PESOC_SOC_CTRL
#define SRAM_MUX_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_SRAM_MUX_CFG << BIT_SHIFT_PESOC_SRAM_MUX_CFG), BIT_PESOC_SRAM_MUX_CFG(num))
#define LX_WL_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_WL_SWAP_SEL, ctrl)
#define LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_MST_SWAP_SEL, ctrl)
#define LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_SLV_SWAP_SEL, ctrl)
#define MII_LX_WRAPPER_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_WRAPPER_EN, ctrl)
#define MII_LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_MST_SWAP_SEL, ctrl)
#define MII_LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_SLV_SWAP_SEL, ctrl)
#define GDMA_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_GDMA_CFG << BIT_SHIFT_PESOC_GDMA_CFG), BIT_PESOC_GDMA_CFG(num))
//308 PESOC_PERI_CTRL
#define SPI_RN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CTRL, BIT_SOC_FUNC_SPI_RN, ctrl)
//320 GPIO_SHTDN_CTRL
#define GPIO_GPA_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPA_SHTDN_N, ctrl)
#define GPIO_GPB_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPB_SHTDN_N, ctrl)
#define GPIO_GPC_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPC_SHTDN_N, ctrl)
#define GPIO_GPD_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPD_SHTDN_N, ctrl)
#define GPIO_GPE_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPE_SHTDN_N, ctrl)
#define GPIO_GPF_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPF_SHTDN_N, ctrl)
#define GPIO_GPG_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPG_SHTDN_N, ctrl)
#define GPIO_GPH_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPH_SHTDN_N, ctrl)
#define GPIO_GPI_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPI_SHTDN_N, ctrl)
#define GPIO_GPJ_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPJ_SHTDN_N, ctrl)
#define GPIO_GPK_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPK_SHTDN_N, ctrl)
//374
#define EGTIM_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PERI_EGTIM_CTRL, BIT_PERI_EGTIM_EN, ctrl)
#define EGTIM_RSIG_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_REF_SIG_SEL << BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL), BIT_PERI_EGTIM_REF_SIG_SEL(num))
#define EGTIME_PIN_G0_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP0_OPT_SEL(num))
#define EGTIME_PIN_G1_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP1_OPT_SEL(num))
#define EGTIME_PIN_G2_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP2_OPT_SEL(num))
#endif //_HAL_PERI_ON_H_

204
component/soc/realtek/8195a/fwlib/hal_platform.h
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@ -1,102 +1,102 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PLATFORM_
#define _HAL_PLATFORM_
#define ROMVERSION 0x03
#define ROMINFORMATION (ROMVERSION)
#define SYSTEM_CLK PLATFORM_CLOCK
#define SDR_SDRAM_BASE 0x30000000
#define SYSTEM_CTRL_BASE 0x40000000
#define PERI_ON_BASE 0x40000000
#define VENDOR_REG_BASE 0x40002800
#define SPI_FLASH_BASE 0x98000000
#define SDR_CTRL_BASE 0x40005000
#define PERIPHERAL_IRQ_STATUS 0x04
#define PERIPHERAL_IRQ_MODE 0x08
#define PERIPHERAL_IRQ_EN 0x0C
#define LP_PERI_EXT_IRQ_STATUS 0x24
#define LP_PERI_EXT_IRQ_MODE 0x28
#define LP_PERI_EXT_IRQ_EN 0x2C
#define PERIPHERAL_IRQ_ALL_LEVEL 0
#define TIMER_CLK 32*1000
//3 Peripheral IP Base Address
#define GPIO_REG_BASE 0x40001000
#define TIMER_REG_BASE 0x40002000
#define NFC_INTERFACE_BASE 0x40002400
#define LOG_UART_REG_BASE 0x40003000
#define I2C2_REG_BASE 0x40003400
#define I2C3_REG_BASE 0x40003800
#define SPI_FLASH_CTRL_BASE 0x40006000
#define ADC_REG_BASE 0x40010000
#define DAC_REG_BASE 0x40011000
#define UART0_REG_BASE 0x40040000
#define UART1_REG_BASE 0x40040400
#define UART2_REG_BASE 0x40040800
#define SPI0_REG_BASE 0x40042000
#define SPI1_REG_BASE 0x40042400
#define SPI2_REG_BASE 0x40042800
#define I2C0_REG_BASE 0x40044000
#define I2C1_REG_BASE 0x40044400
#define SDIO_DEVICE_REG_BASE 0x40050000
#define MII_REG_BASE 0x40050000
#define SDIO_HOST_REG_BASE 0x40058000
#define GDMA0_REG_BASE 0x40060000
#define GDMA1_REG_BASE 0x40061000
#define I2S0_REG_BASE 0x40062000
#define I2S1_REG_BASE 0x40063000
#define PCM0_REG_BASE 0x40064000
#define PCM1_REG_BASE 0x40065000
#define CRYPTO_REG_BASE 0x40070000
#define WIFI_REG_BASE 0x40080000
#define USB_OTG_REG_BASE 0x400C0000
#define GDMA1_REG_OFF 0x1000
#define I2S1_REG_OFF 0x1000
#define PCM1_REG_OFF 0x1000
#define SSI_REG_OFF 0x400
#define RUART_REG_OFF 0x400
#define CPU_CLK_TYPE_NO 6
enum _BOOT_TYPE_ {
BOOT_FROM_FLASH = 0,
BOOT_FROM_SDIO = 1,
BOOT_FROM_USB = 2,
BOOT_FROM_RSVD = 3,
};
enum _EFUSE_CPU_CLK_ {
#if 1
CLK_200M = 0,
CLK_100M = 1,
CLK_50M = 2,
CLK_25M = 3,
CLK_12_5M = 4,
CLK_4M = 5,
#else
CLK_25M = 0,
CLK_200M = 1,
CLK_100M = 2,
CLK_50M = 3,
CLK_12_5M = 4,
CLK_4M = 5,
#endif
};
#endif //_HAL_PLATFORM_
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PLATFORM_
#define _HAL_PLATFORM_
#define ROMVERSION 0x03
#define ROMINFORMATION (ROMVERSION)
#define SYSTEM_CLK PLATFORM_CLOCK
#define SDR_SDRAM_BASE 0x30000000
#define SYSTEM_CTRL_BASE 0x40000000
#define PERI_ON_BASE 0x40000000
#define VENDOR_REG_BASE 0x40002800
#define SPI_FLASH_BASE 0x98000000
#define SDR_CTRL_BASE 0x40005000
#define PERIPHERAL_IRQ_STATUS 0x04
#define PERIPHERAL_IRQ_MODE 0x08
#define PERIPHERAL_IRQ_EN 0x0C
#define LP_PERI_EXT_IRQ_STATUS 0x24
#define LP_PERI_EXT_IRQ_MODE 0x28
#define LP_PERI_EXT_IRQ_EN 0x2C
#define PERIPHERAL_IRQ_ALL_LEVEL 0
#define TIMER_CLK 32*1000
//3 Peripheral IP Base Address
#define GPIO_REG_BASE 0x40001000
#define TIMER_REG_BASE 0x40002000
#define NFC_INTERFACE_BASE 0x40002400
#define LOG_UART_REG_BASE 0x40003000
#define I2C2_REG_BASE 0x40003400
#define I2C3_REG_BASE 0x40003800
#define SPI_FLASH_CTRL_BASE 0x40006000
#define ADC_REG_BASE 0x40010000
#define DAC_REG_BASE 0x40011000
#define UART0_REG_BASE 0x40040000
#define UART1_REG_BASE 0x40040400
#define UART2_REG_BASE 0x40040800
#define SPI0_REG_BASE 0x40042000
#define SPI1_REG_BASE 0x40042400
#define SPI2_REG_BASE 0x40042800
#define I2C0_REG_BASE 0x40044000
#define I2C1_REG_BASE 0x40044400
#define SDIO_DEVICE_REG_BASE 0x40050000
#define MII_REG_BASE 0x40050000
#define SDIO_HOST_REG_BASE 0x40058000
#define GDMA0_REG_BASE 0x40060000
#define GDMA1_REG_BASE 0x40061000
#define I2S0_REG_BASE 0x40062000
#define I2S1_REG_BASE 0x40063000
#define PCM0_REG_BASE 0x40064000
#define PCM1_REG_BASE 0x40065000
#define CRYPTO_REG_BASE 0x40070000
#define WIFI_REG_BASE 0x40080000
#define USB_OTG_REG_BASE 0x400C0000
#define GDMA1_REG_OFF 0x1000
#define I2S1_REG_OFF 0x1000
#define PCM1_REG_OFF 0x1000
#define SSI_REG_OFF 0x400
#define RUART_REG_OFF 0x400
#define CPU_CLK_TYPE_NO 6
enum _BOOT_TYPE_ {
BOOT_FROM_FLASH = 0,
BOOT_FROM_SDIO = 1,
BOOT_FROM_USB = 2,
BOOT_FROM_RSVD = 3,
};
enum _EFUSE_CPU_CLK_ {
#if 1
CLK_200M = 0,
CLK_100M = 1,
CLK_50M = 2,
CLK_25M = 3,
CLK_12_5M = 4,
CLK_4M = 5,
#else
CLK_25M = 0,
CLK_200M = 1,
CLK_100M = 2,
CLK_50M = 3,
CLK_12_5M = 4,
CLK_4M = 5,
#endif
};
#endif //_HAL_PLATFORM_

116
component/soc/realtek/8195a/fwlib/hal_pwm.h
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@ -1,58 +1,58 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PWM_H_
#define _HAL_PWM_H_
#define MAX_PWM_CTRL_PIN 4
// the minimum tick time for G-timer is 61 us (clock source = 32768Hz, reload value=1 and reload takes extra 1T)
//#define GTIMER_TICK_US 31 // micro-second, 1000000/32768 ~= 30.5
#define MIN_GTIMER_TIMEOUT 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
#define PWM_GTIMER_TICK_TIME 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
typedef struct _HAL_PWM_ADAPTER_ {
u8 pwm_id; // the PWM ID, 0~3
u8 sel; // PWM Pin selection, 0~3
u8 gtimer_id; // using G-Timer ID, there are 7 G-timer, but we prefer to use timer 3~6
u8 enable; // is enabled
// u32 timer_value; // the G-Timer auto-reload value, source clock is 32768Hz, reload will takes extra 1 tick. To set the time of a tick of PWM
u32 tick_time; // the tick time for the G-timer
u32 period; // the period of a PWM control cycle, in PWM tick
u32 pulsewidth; // the pulse width in a period of a PWM control cycle, in PWM tick. To control the ratio
// float duty_ratio; // the dyty ratio = pulswidth/period
}HAL_PWM_ADAPTER, *PHAL_PWM_ADAPTER;
extern HAL_Status
HAL_Pwm_Init(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 pwm_id,
u32 sel
);
extern void
HAL_Pwm_Enable(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Disable(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_SetDuty(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PWM_H_
#define _HAL_PWM_H_
#define MAX_PWM_CTRL_PIN 4
// the minimum tick time for G-timer is 61 us (clock source = 32768Hz, reload value=1 and reload takes extra 1T)
//#define GTIMER_TICK_US 31 // micro-second, 1000000/32768 ~= 30.5
#define MIN_GTIMER_TIMEOUT 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
#define PWM_GTIMER_TICK_TIME 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
typedef struct _HAL_PWM_ADAPTER_ {
u8 pwm_id; // the PWM ID, 0~3
u8 sel; // PWM Pin selection, 0~3
u8 gtimer_id; // using G-Timer ID, there are 7 G-timer, but we prefer to use timer 3~6
u8 enable; // is enabled
// u32 timer_value; // the G-Timer auto-reload value, source clock is 32768Hz, reload will takes extra 1 tick. To set the time of a tick of PWM
u32 tick_time; // the tick time for the G-timer
u32 period; // the period of a PWM control cycle, in PWM tick
u32 pulsewidth; // the pulse width in a period of a PWM control cycle, in PWM tick. To control the ratio
// float duty_ratio; // the dyty ratio = pulswidth/period
}HAL_PWM_ADAPTER, *PHAL_PWM_ADAPTER;
extern HAL_Status
HAL_Pwm_Init(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 pwm_id,
u32 sel
);
extern void
HAL_Pwm_Enable(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Disable(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_SetDuty(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
#endif

178
component/soc/realtek/8195a/fwlib/hal_sdio_host.h
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@ -1,89 +1,89 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SDIO_HOST_H_
#define _HAL_SDIO_HOST_H_
#include "rtl8195a_sdio_host.h"
#define SDIO_HOST_WAIT_FOREVER 0xFFFFFFFF
typedef struct _HAL_SDIO_HOST_OP_ {
HAL_Status (*HalSdioHostInitHost) (VOID *Data);
HAL_Status (*HalSdioHostInitCard) (VOID *Data);
HAL_Status (*HalSdioHostDeInit) (VOID *Data);
HAL_Status (*HalSdioHostRegIrq) (VOID *Data);
HAL_Status (*HalSdioHostReadBlocksDma) (VOID *Data, u64 ReadAddr, u32 BlockCnt);
HAL_Status (*HalSdioHostWriteBlocksDma) (VOID *Data, u64 WriteAddr, u32 BlockCnt);
HAL_Status (*HalSdioHostStopTransfer) (VOID *Data);
HAL_Status (*HalSdioHostGetCardStatus) (VOID *Data);
HAL_Status (*HalSdioHostGetSdStatus) (VOID *Data);
HAL_Status (*HalSdioHostChangeSdClock) (VOID *Data, u8 Frequency);
HAL_Status (*HalSdioHostErase) (VOID *Data, u64 StartAddr, u64 EndAddr);
HAL_Status (*HalSdioHostGetWriteProtect) (VOID *Data);
HAL_Status (*HalSdioHostSetWriteProtect) (VOID *Data, u8 Setting);
}HAL_SDIO_HOST_OP, *PHAL_SDIO_HOST_OP;
typedef struct _HAL_SDIO_HOST_ADAPTER_{
IRQ_HANDLE IrqHandle; // Irq Handler
ADMA2_DESC_FMT *AdmaDescTbl;
u32 Response[4];
u32 CardOCR;
u32 CardStatus;
u32 IsWriteProtect;
u8 SdStatus[SD_STATUS_LEN];
u8 Csd[CSD_REG_LEN];
volatile u8 CmdCompleteFlg;
volatile u8 XferCompleteFlg;
volatile u8 ErrIntFlg;
volatile u8 CardCurState;
u8 IsSdhc;
u8 CurrSdClk;
u16 RCA;
u16 SdSpecVer;
VOID (*CardInsertCallBack)(VOID *pAdapter);
VOID (*CardRemoveCallBack)(VOID *pAdapter);
VOID *CardInsertCbPara;
VOID *CardRemoveCbPara;
}HAL_SDIO_HOST_ADAPTER, *PHAL_SDIO_HOST_ADAPTER;
extern HAL_Status
HalSdioHostInit(
IN VOID *Data
);
extern HAL_Status
HalSdioHostDeInit(
IN VOID *Data
);
extern HAL_Status
HalSdioHostEnable(
IN VOID *Data
);
extern HAL_Status
HalSdioHostDisable(
IN VOID *Data
);
extern VOID
HalSdioHostOpInit(
IN VOID *Data
);
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SDIO_HOST_H_
#define _HAL_SDIO_HOST_H_
#include "rtl8195a_sdio_host.h"
#define SDIO_HOST_WAIT_FOREVER 0xFFFFFFFF
typedef struct _HAL_SDIO_HOST_OP_ {
HAL_Status (*HalSdioHostInitHost) (VOID *Data);
HAL_Status (*HalSdioHostInitCard) (VOID *Data);
HAL_Status (*HalSdioHostDeInit) (VOID *Data);
HAL_Status (*HalSdioHostRegIrq) (VOID *Data);
HAL_Status (*HalSdioHostReadBlocksDma) (VOID *Data, u64 ReadAddr, u32 BlockCnt);
HAL_Status (*HalSdioHostWriteBlocksDma) (VOID *Data, u64 WriteAddr, u32 BlockCnt);
HAL_Status (*HalSdioHostStopTransfer) (VOID *Data);
HAL_Status (*HalSdioHostGetCardStatus) (VOID *Data);
HAL_Status (*HalSdioHostGetSdStatus) (VOID *Data);
HAL_Status (*HalSdioHostChangeSdClock) (VOID *Data, u8 Frequency);
HAL_Status (*HalSdioHostErase) (VOID *Data, u64 StartAddr, u64 EndAddr);
HAL_Status (*HalSdioHostGetWriteProtect) (VOID *Data);
HAL_Status (*HalSdioHostSetWriteProtect) (VOID *Data, u8 Setting);
}HAL_SDIO_HOST_OP, *PHAL_SDIO_HOST_OP;
typedef struct _HAL_SDIO_HOST_ADAPTER_{
IRQ_HANDLE IrqHandle; // Irq Handler
ADMA2_DESC_FMT *AdmaDescTbl;
u32 Response[4];
u32 CardOCR;
u32 CardStatus;
u32 IsWriteProtect;
u8 SdStatus[SD_STATUS_LEN];
u8 Csd[CSD_REG_LEN];
volatile u8 CmdCompleteFlg;
volatile u8 XferCompleteFlg;
volatile u8 ErrIntFlg;
volatile u8 CardCurState;
u8 IsSdhc;
u8 CurrSdClk;
u16 RCA;
u16 SdSpecVer;
VOID (*CardInsertCallBack)(VOID *pAdapter);
VOID (*CardRemoveCallBack)(VOID *pAdapter);
VOID *CardInsertCbPara;
VOID *CardRemoveCbPara;
}HAL_SDIO_HOST_ADAPTER, *PHAL_SDIO_HOST_ADAPTER;
extern HAL_Status
HalSdioHostInit(
IN VOID *Data
);
extern HAL_Status
HalSdioHostDeInit(
IN VOID *Data
);
extern HAL_Status
HalSdioHostEnable(
IN VOID *Data
);
extern HAL_Status
HalSdioHostDisable(
IN VOID *Data
);
extern VOID
HalSdioHostOpInit(
IN VOID *Data
);
#endif

704
component/soc/realtek/8195a/fwlib/hal_spi_flash.h
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@ -1,352 +1,352 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SPIFLASH__
#define _HAL_SPIFLASH__
//======================================================
// Header files
#define SPIC_CALIBRATION_IN_NVM 1 // if store the SPIC calibration data in the NVM
#ifndef CONFIG_IMAGE_SEPARATE // Store SPIC Calibration only for seprated image
#undef SPIC_CALIBRATION_IN_NVM
#define SPIC_CALIBRATION_IN_NVM 0
#endif
//======================================================
// Definition
#define HAL_SPI_WRITE32(addr, value32) HAL_WRITE32(SPI_FLASH_CTRL_BASE, addr, value32)
#define HAL_SPI_WRITE16(addr, value16) HAL_WRITE16(SPI_FLASH_CTRL_BASE, addr, value16)
#define HAL_SPI_WRITE8(addr, value8) HAL_WRITE8(SPI_FLASH_CTRL_BASE, addr, value8)
#define HAL_SPI_READ32(addr) HAL_READ32(SPI_FLASH_CTRL_BASE, addr)
#define HAL_SPI_READ16(addr) HAL_READ16(SPI_FLASH_CTRL_BASE, addr)
#define HAL_SPI_READ8(addr) HAL_READ8(SPI_FLASH_CTRL_BASE, addr)
typedef struct _SPIC_PARA_MODE_ {
u8 Valid:1; // valid
u8 CpuClk:3; // CPU clock
u8 BitMode:2; // Bit mode
u8 Reserved:2; // reserved
} SPIC_PARA_MODE, *PSPIC_PARA_MODE;
typedef struct _SPIC_INIT_PARA_ {
u8 BaudRate;
u8 RdDummyCyle;
u8 DelayLine;
union {
u8 Rsvd;
u8 Valid;
SPIC_PARA_MODE Mode;
};
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
u8 id[3];
u8 flashtype;
#endif
}SPIC_INIT_PARA, *PSPIC_INIT_PARA;
enum _SPIC_BIT_MODE_ {
SpicOneBitMode = 0,
SpicDualBitMode = 1,
SpicQuadBitMode = 2,
};
//======================================================
// Flash type used
#define FLASH_OTHERS 0
#define FLASH_MXIC 1
#define FLASH_MXIC_4IO 2
#define FLASH_WINBOND 3
#define FLASH_MICRON 4
#define FLASH_EON 5
//#define FLASH_MXIC_MX25L4006E 0
//#define FLASH_MXIC_MX25L8073E 0
//#define FLASH_MICRON_N25Q512A 1
// The below parts are based on the flash characteristics
//====== Flash Command Definition ======
//#if FLASH_MICRON_N25Q512A
/*Common command*/
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command 1-1-2
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command 1-2-2
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command 1-1-4
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command 1-4-4
#define FLASH_CMD_DPP 0xA2 // 1-1-2
#define FLASH_CMD_2PP 0xD2 // 1-2-2
#define FLASH_CMD_QPP 0x32 // 1-1-4
#define FLASH_CMD_4PP 0x38 //quad page program 1-4-4
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52)
#define FLASH_CMD_CE 0xC7 //Chip Erase(or 0xC7)
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
/*Micron Special command*/
#define FLASH_CMD_DE 0xC4
#define FLASH_CMD_4PP2 0x12
#define FLASH_CMD_RFSR 0x70
#define FLASH_CMD_CFSR 0x50
#define FLASH_CMD_RNCR 0xB5
#define FLASH_CMD_WNCR 0xB1
#define FLASH_CMD_RVCR 0x85
#define FLASH_CMD_WVCR 0x81
#define FLASH_CMD_REVCR 0x65
#define FLASH_CMD_WEVCR 0x61
#define FLASH_CMD_REAR 0xC8
#define FLASH_CMD_WEAR 0xC5
#define FLASH_CMD_ENQUAD 0x35
#define FLASH_CMD_EXQUAD 0xF5
/*MXIC Special command*/
#define FLASH_CMD_RDCR 0x15 //read configurate register
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
//#endif
#if 0
#if FLASH_MXIC_MX25L4006E
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52)
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_RDCR 0x15 //read configurate register
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#elif FLASH_MXIC_MX25L8073E
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0x52 //Block Erase
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#else
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0x52 //Block Erase
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#endif //#if FLASH_MXIC_MX25L4006E
#endif
// ============================
// ===== Flash Parameter Definition =====
//#if FLASH_MICRON_N25Q512A
#if 0
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 1
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 1
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 1
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 1
#endif
#define FLASH_DM_CYCLE_2O 0x08 // 1-1-2
#define FLASH_DM_CYCLE_2IO 0x04 // 1-2-2
#define FLASH_DM_CYCLE_4O 0x08 // 1-1-4
#define FLASH_DM_CYCLE_4IO 0x08 // 1-4-4
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_I)// 1-1-2
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_RD_QUAD_IO)// 1-4-4
#define FLASH_VLD_QUAD_CMDS2 (BIT_WR_BLOCKING | BIT_RD_QUAD_O)// 1-1-4
//#endif
#if 0
#if FLASH_MXIC_MX25L4006E
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x04 // 1-1-2
#define FLASH_DM_CYCLE_2IO 0x08 // 1-2-2
#define FLASH_DM_CYCLE_4O 0x04 // 1-1-4
#define FLASH_DM_CYCLE_4IO 0x08 // 1-4-4
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_WR_DUAL_II | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#elif FLASH_MXIC_MX25L8073E //This flash model is just for prototype, if you want to use it,
//the code MUST be rechecked according to the flash spec.
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_DM_CYCLE_2IO 0x04
#define FLASH_DM_CYCLE_4O 0x08
#define FLASH_DM_CYCLE_4IO 0x04
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#else
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_DM_CYCLE_2IO 0x04
#define FLASH_DM_CYCLE_4O 0x08
#define FLASH_DM_CYCLE_4IO 0x04
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#endif
#endif
#if 0
//======================================================
// Function prototype
BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
_LONG_CALL_
extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara);
// spi-flash controller initialization
_LONG_CALL_
extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode);
// wait sr[0] = 0, wait transmission done
_LONG_CALL_
extern VOID SpicWaitBusyDoneRtl8195A(VOID);
// wait spi-flash status register[0] = 0
//_LONG_CALL_
//extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara);
#endif
//======================================================
// ROM Function prototype
_LONG_CALL_ VOID SpiFlashAppV02(IN VOID *Data);
_LONG_CALL_ROM_ VOID SpicInitRtl8195AV02(IN u8 InitBaudRate,IN u8 SpicBitMode);
_LONG_CALL_ROM_ VOID SpicEraseFlashRtl8195AV02(VOID);
_LONG_CALL_ROM_ VOID SpicLoadInitParaFromClockRtl8195AV02(IN u8 CpuClkMode,IN u8 BaudRate,IN PSPIC_INIT_PARA pSpicInitPara);
VOID SpicBlockEraseFlashRtl8195A(IN u32 Address);
VOID SpicSectorEraseFlashRtl8195A(IN u32 Address);
VOID SpicDieEraseFlashRtl8195A(IN u32 Address);
VOID SpicWriteProtectFlashRtl8195A(IN u32 Protect);
VOID SpicWaitWipDoneRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicWaitOperationDoneRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicRxCmdRefinedRtl8195A(IN u8 cmd,IN SPIC_INIT_PARA SpicInitPara);
u8 SpicGetFlashStatusRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicInitRefinedRtl8195A(IN u8 InitBaudRate,IN u8 SpicBitMode);
u32 SpicWaitWipRtl8195A(VOID);
u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk);
VOID SpicDisableRtl8195A(VOID);
VOID SpicDeepPowerDownFlashRtl8195A(VOID);
VOID SpicUserProgramRtl8195A(IN u8 * data, IN SPIC_INIT_PARA SpicInitPara, IN u32 addr, IN u32 * LengthInfo);
VOID SpicUserReadRtl8195A(IN u32 Length, IN u32 addr, IN u8 * data, IN u8 BitMode);
VOID SpicUserReadFourByteRtl8195A(IN u32 Length, IN u32 addr, IN u32 * data, IN u8 BitMode);
VOID SpicReadIDRtl8195A(VOID);
VOID SpicSetFlashStatusRefinedRtl8195A(IN u32 data, IN SPIC_INIT_PARA SpicInitPara);
VOID SpicSetExtendAddrRtl8195A(IN u32 data, IN SPIC_INIT_PARA SpicInitPara);
u8 SpicGetExtendAddrRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
#if SPIC_CALIBRATION_IN_NVM
VOID SpicNVMCalLoad(u8 BitMode, u8 CpuClk);
VOID SpicNVMCalLoadAll(void);
VOID SpicNVMCalStore(u8 BitMode, u8 CpuClk);
#endif // #if SPIC_CALIBRATION_IN_NVM
#endif //_HAL_SPIFLASH__
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SPIFLASH__
#define _HAL_SPIFLASH__
//======================================================
// Header files
#define SPIC_CALIBRATION_IN_NVM 1 // if store the SPIC calibration data in the NVM
#ifndef CONFIG_IMAGE_SEPARATE // Store SPIC Calibration only for seprated image
#undef SPIC_CALIBRATION_IN_NVM
#define SPIC_CALIBRATION_IN_NVM 0
#endif
//======================================================
// Definition
#define HAL_SPI_WRITE32(addr, value32) HAL_WRITE32(SPI_FLASH_CTRL_BASE, addr, value32)
#define HAL_SPI_WRITE16(addr, value16) HAL_WRITE16(SPI_FLASH_CTRL_BASE, addr, value16)
#define HAL_SPI_WRITE8(addr, value8) HAL_WRITE8(SPI_FLASH_CTRL_BASE, addr, value8)
#define HAL_SPI_READ32(addr) HAL_READ32(SPI_FLASH_CTRL_BASE, addr)
#define HAL_SPI_READ16(addr) HAL_READ16(SPI_FLASH_CTRL_BASE, addr)
#define HAL_SPI_READ8(addr) HAL_READ8(SPI_FLASH_CTRL_BASE, addr)
typedef struct _SPIC_PARA_MODE_ {
u8 Valid:1; // valid
u8 CpuClk:3; // CPU clock
u8 BitMode:2; // Bit mode
u8 Reserved:2; // reserved
} SPIC_PARA_MODE, *PSPIC_PARA_MODE;
typedef struct _SPIC_INIT_PARA_ {
u8 BaudRate;
u8 RdDummyCyle;
u8 DelayLine;
union {
u8 Rsvd;
u8 Valid;
SPIC_PARA_MODE Mode;
};
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
u8 id[3];
u8 flashtype;
#endif
}SPIC_INIT_PARA, *PSPIC_INIT_PARA;
enum _SPIC_BIT_MODE_ {
SpicOneBitMode = 0,
SpicDualBitMode = 1,
SpicQuadBitMode = 2,
};
//======================================================
// Flash type used
#define FLASH_OTHERS 0
#define FLASH_MXIC 1
#define FLASH_MXIC_4IO 2
#define FLASH_WINBOND 3
#define FLASH_MICRON 4
#define FLASH_EON 5
//#define FLASH_MXIC_MX25L4006E 0
//#define FLASH_MXIC_MX25L8073E 0
//#define FLASH_MICRON_N25Q512A 1
// The below parts are based on the flash characteristics
//====== Flash Command Definition ======
//#if FLASH_MICRON_N25Q512A
/*Common command*/
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command 1-1-2
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command 1-2-2
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command 1-1-4
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command 1-4-4
#define FLASH_CMD_DPP 0xA2 // 1-1-2
#define FLASH_CMD_2PP 0xD2 // 1-2-2
#define FLASH_CMD_QPP 0x32 // 1-1-4
#define FLASH_CMD_4PP 0x38 //quad page program 1-4-4
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52)
#define FLASH_CMD_CE 0xC7 //Chip Erase(or 0xC7)
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
/*Micron Special command*/
#define FLASH_CMD_DE 0xC4
#define FLASH_CMD_4PP2 0x12
#define FLASH_CMD_RFSR 0x70
#define FLASH_CMD_CFSR 0x50
#define FLASH_CMD_RNCR 0xB5
#define FLASH_CMD_WNCR 0xB1
#define FLASH_CMD_RVCR 0x85
#define FLASH_CMD_WVCR 0x81
#define FLASH_CMD_REVCR 0x65
#define FLASH_CMD_WEVCR 0x61
#define FLASH_CMD_REAR 0xC8
#define FLASH_CMD_WEAR 0xC5
#define FLASH_CMD_ENQUAD 0x35
#define FLASH_CMD_EXQUAD 0xF5
/*MXIC Special command*/
#define FLASH_CMD_RDCR 0x15 //read configurate register
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
//#endif
#if 0
#if FLASH_MXIC_MX25L4006E
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52)
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_RDCR 0x15 //read configurate register
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#elif FLASH_MXIC_MX25L8073E
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0x52 //Block Erase
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#else
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0x52 //Block Erase
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#endif //#if FLASH_MXIC_MX25L4006E
#endif
// ============================
// ===== Flash Parameter Definition =====
//#if FLASH_MICRON_N25Q512A
#if 0
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 1
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 1
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 1
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 1
#endif
#define FLASH_DM_CYCLE_2O 0x08 // 1-1-2
#define FLASH_DM_CYCLE_2IO 0x04 // 1-2-2
#define FLASH_DM_CYCLE_4O 0x08 // 1-1-4
#define FLASH_DM_CYCLE_4IO 0x08 // 1-4-4
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_I)// 1-1-2
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_RD_QUAD_IO)// 1-4-4
#define FLASH_VLD_QUAD_CMDS2 (BIT_WR_BLOCKING | BIT_RD_QUAD_O)// 1-1-4
//#endif
#if 0
#if FLASH_MXIC_MX25L4006E
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x04 // 1-1-2
#define FLASH_DM_CYCLE_2IO 0x08 // 1-2-2
#define FLASH_DM_CYCLE_4O 0x04 // 1-1-4
#define FLASH_DM_CYCLE_4IO 0x08 // 1-4-4
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_WR_DUAL_II | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#elif FLASH_MXIC_MX25L8073E //This flash model is just for prototype, if you want to use it,
//the code MUST be rechecked according to the flash spec.
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_DM_CYCLE_2IO 0x04
#define FLASH_DM_CYCLE_4O 0x08
#define FLASH_DM_CYCLE_4IO 0x04
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#else
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_DM_CYCLE_2IO 0x04
#define FLASH_DM_CYCLE_4O 0x08
#define FLASH_DM_CYCLE_4IO 0x04
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#endif
#endif
#if 0
//======================================================
// Function prototype
BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
_LONG_CALL_
extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara);
// spi-flash controller initialization
_LONG_CALL_
extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode);
// wait sr[0] = 0, wait transmission done
_LONG_CALL_
extern VOID SpicWaitBusyDoneRtl8195A(VOID);
// wait spi-flash status register[0] = 0
//_LONG_CALL_
//extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara);
#endif
//======================================================
// ROM Function prototype
_LONG_CALL_ VOID SpiFlashAppV02(IN VOID *Data);
_LONG_CALL_ROM_ VOID SpicInitRtl8195AV02(IN u8 InitBaudRate,IN u8 SpicBitMode);
_LONG_CALL_ROM_ VOID SpicEraseFlashRtl8195AV02(VOID);
_LONG_CALL_ROM_ VOID SpicLoadInitParaFromClockRtl8195AV02(IN u8 CpuClkMode,IN u8 BaudRate,IN PSPIC_INIT_PARA pSpicInitPara);
VOID SpicBlockEraseFlashRtl8195A(IN u32 Address);
VOID SpicSectorEraseFlashRtl8195A(IN u32 Address);
VOID SpicDieEraseFlashRtl8195A(IN u32 Address);
VOID SpicWriteProtectFlashRtl8195A(IN u32 Protect);
VOID SpicWaitWipDoneRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicWaitOperationDoneRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicRxCmdRefinedRtl8195A(IN u8 cmd,IN SPIC_INIT_PARA SpicInitPara);
u8 SpicGetFlashStatusRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicInitRefinedRtl8195A(IN u8 InitBaudRate,IN u8 SpicBitMode);
u32 SpicWaitWipRtl8195A(VOID);
u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk);
VOID SpicDisableRtl8195A(VOID);
VOID SpicDeepPowerDownFlashRtl8195A(VOID);
VOID SpicUserProgramRtl8195A(IN u8 * data, IN SPIC_INIT_PARA SpicInitPara, IN u32 addr, IN u32 * LengthInfo);
VOID SpicUserReadRtl8195A(IN u32 Length, IN u32 addr, IN u8 * data, IN u8 BitMode);
VOID SpicUserReadFourByteRtl8195A(IN u32 Length, IN u32 addr, IN u32 * data, IN u8 BitMode);
VOID SpicReadIDRtl8195A(VOID);
VOID SpicSetFlashStatusRefinedRtl8195A(IN u32 data, IN SPIC_INIT_PARA SpicInitPara);
VOID SpicSetExtendAddrRtl8195A(IN u32 data, IN SPIC_INIT_PARA SpicInitPara);
u8 SpicGetExtendAddrRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
#if SPIC_CALIBRATION_IN_NVM
VOID SpicNVMCalLoad(u8 BitMode, u8 CpuClk);
VOID SpicNVMCalLoadAll(void);
VOID SpicNVMCalStore(u8 BitMode, u8 CpuClk);
#endif // #if SPIC_CALIBRATION_IN_NVM
#endif //_HAL_SPIFLASH__

672
component/soc/realtek/8195a/fwlib/hal_ssi.h
View file

@ -1,336 +1,336 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SSI_H_
#define _HAL_SSI_H_
#include "rtl8195a_ssi.h"
/**
* LOG Configurations
*/
extern u32 SSI_DBG_CONFIG;
extern uint8_t SPI0_IS_AS_SLAVE;
#define SSI_DBG_ENTRANCE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENTRANCE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE ANSI_COLOR_GREEN __VA_ARGS__ ANSI_COLOR_RESET); \
}while(0)
#define SSI_DBG_INIT(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INIT_V(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_V)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INIT_VV(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_VV)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_PINMUX(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_PINMUX)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_ENDIS(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENDIS)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_V(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_V)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_HNDLR(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_HNDLR)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_READ(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_READ)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_WRITE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_WRITE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_STATUS(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_STATUS)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_FIFO(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_FIFO)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_READ(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_READ)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_WRITE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_WRITE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_SLV_CTRL(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_SLV_CTRL)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
typedef enum _SSI_DBG_TYPE_LIST_ {
DBG_TYPE_ENTRANCE = 1 << 0,
DBG_TYPE_INIT = 1 << 1,
DBG_TYPE_INIT_V = 1 << 2,
DBG_TYPE_INIT_VV = 1 << 3,
DBG_TYPE_PINMUX = 1 << 4,
DBG_TYPE_ENDIS = 1 << 5,
DBG_TYPE_INT = 1 << 6,
DBG_TYPE_INT_V = 1 << 7,
DBG_TYPE_INT_HNDLR = 1 << 8,
DBG_TYPE_INT_READ = 1 << 9,
DBG_TYPE_INT_WRITE = 1 << 10,
DBG_TYPE_STATUS = 1 << 11,
DBG_TYPE_FIFO = 1 << 12,
DBG_TYPE_READ = 1 << 13,
DBG_TYPE_WRITE = 1 << 14,
DBG_TYPE_SLV_CTRL = 1 << 15
} SSI_DBG_TYPE_LIST, *PSSI_DBG_TYPE_LIST;
typedef struct _SSI_DMA_CONFIG_ {
VOID *pHalGdmaOp;
VOID *pTxHalGdmaAdapter;
VOID *pRxHalGdmaAdapter;
u8 RxDmaBurstSize;
u8 TxDmaBurstSize;
u8 RxDmaEnable;
u8 TxDmaEnable;
IRQ_HANDLE RxGdmaIrqHandle;
IRQ_HANDLE TxGdmaIrqHandle;
}SSI_DMA_CONFIG, *PSSI_DMA_CONFIG;
#ifdef CONFIG_GDMA_EN
typedef struct _HAL_SSI_DMA_MULTIBLK_ {
volatile GDMA_CH_LLI_ELE GdmaChLli[16];
struct GDMA_CH_LLI Lli[16];
struct BLOCK_SIZE_LIST BlockSizeList[16];
}SSI_DMA_MULTIBLK, *PSSI_DMA_MULTIBLK;
#endif
/**
* DesignWare SSI Configurations
*/
typedef struct _HAL_SSI_ADAPTOR_ {
SSI_DMA_CONFIG DmaConfig;
IRQ_HANDLE IrqHandle;
//
VOID (*RxCompCallback)(VOID *Para);
VOID *RxCompCbPara;
VOID *RxData;
VOID (*TxCompCallback)(VOID *Para);
VOID *TxCompCbPara;
VOID *TxData;
u32 DmaRxDataLevel;
u32 DmaTxDataLevel;
u32 InterruptPriority;
u32 RxLength;
u32 RxLengthRemainder;
u32 RxThresholdLevel;
u32 TxLength;
u32 TxThresholdLevel;
u32 SlaveSelectEnable;
//
u16 ClockDivider;
u16 DataFrameNumber;
//
u8 ControlFrameSize;
u8 DataFrameFormat;
u8 DataFrameSize;
u8 DmaControl;
u8 Index;
u8 InterruptMask;
u8 MicrowireDirection;
u8 MicrowireHandshaking;
u8 MicrowireTransferMode;
u8 PinmuxSelect;
u8 Role;
u8 SclkPhase;
u8 SclkPolarity;
u8 SlaveOutputEnable;
u8 TransferMode;
u8 TransferMechanism;
// Extend
u8 Reserve;
u8 HaveTxChannel;
u8 HaveRxChannel;
u8 DefaultRxThresholdLevel;
#ifdef CONFIG_GDMA_EN
SSI_DMA_MULTIBLK DmaTxMultiBlk, DmaRxMultiBlk;
#endif
u32 ReservedDummy;
VOID (*TxIdleCallback)(VOID *Para);
VOID *TxIdleCbPara;
}HAL_SSI_ADAPTOR, *PHAL_SSI_ADAPTOR;
typedef struct _HAL_SSI_OP_{
HAL_Status (*HalSsiPinmuxEnable)(VOID *Adaptor);
HAL_Status (*HalSsiPinmuxDisable)(VOID *Adaptor);
HAL_Status (*HalSsiEnable)(VOID *Adaptor);
HAL_Status (*HalSsiDisable)(VOID *Adaptor);
HAL_Status (*HalSsiInit)(VOID *Adaptor);
HAL_Status (*HalSsiSetSclkPolarity)(VOID *Adaptor);
HAL_Status (*HalSsiSetSclkPhase)(VOID *Adaptor);
HAL_Status (*HalSsiWrite)(VOID *Adaptor, u32 value);
HAL_Status (*HalSsiLoadSetting)(VOID *Adaptor, VOID *Setting);
HAL_Status (*HalSsiSetInterruptMask)(VOID *Adaptor);
HAL_Status (*HalSsiSetDeviceRole)(VOID *Adaptor, u32 Role);
HAL_Status (*HalSsiInterruptEnable)(VOID *Adaptor);
HAL_Status (*HalSsiInterruptDisable)(VOID *Adaptor);
HAL_Status (*HalSsiReadInterrupt)(VOID *Adaptor, VOID *RxData, u32 Length);
HAL_Status (*HalSsiSetRxFifoThresholdLevel)(VOID *Adaptor);
HAL_Status (*HalSsiSetTxFifoThresholdLevel)(VOID *Adaptor);
HAL_Status (*HalSsiWriteInterrupt)(VOID *Adaptor, u8 *TxData, u32 Length);
HAL_Status (*HalSsiSetSlaveEnableRegister)(VOID *Adaptor, u32 SlaveIndex);
u32 (*HalSsiBusy)(VOID *Adaptor);
u32 (*HalSsiReadable)(VOID *Adaptor);
u32 (*HalSsiWriteable)(VOID *Adaptor);
u32 (*HalSsiGetInterruptMask)(VOID *Adaptor);
u32 (*HalSsiGetRxFifoLevel)(VOID *Adaptor);
u32 (*HalSsiGetTxFifoLevel)(VOID *Adaptor);
u32 (*HalSsiGetStatus)(VOID *Adaptor);
u32 (*HalSsiGetInterruptStatus)(VOID *Adaptor);
u32 (*HalSsiRead)(VOID *Adaptor);
u32 (*HalSsiGetRawInterruptStatus)(VOID *Adaptor);
u32 (*HalSsiGetSlaveEnableRegister)(VOID *Adaptor);
}HAL_SSI_OP, *PHAL_SSI_OP;
typedef struct _DW_SSI_DEFAULT_SETTING_ {
VOID (*RxCompCallback)(VOID *Para);
VOID *RxCompCbPara;
VOID *RxData;
VOID (*TxCompCallback)(VOID *Para);
VOID *TxCompCbPara;
VOID *TxData;
u32 DmaRxDataLevel;
u32 DmaTxDataLevel;
u32 InterruptPriority;
u32 RxLength;
u32 RxLengthRemainder;
u32 RxThresholdLevel;
u32 TxLength;
u32 TxThresholdLevel;
u32 SlaveSelectEnable;
//
u16 ClockDivider;
u16 DataFrameNumber;
//
u8 ControlFrameSize;
u8 DataFrameFormat;
u8 DataFrameSize;
u8 DmaControl;
//u8 Index;
u8 InterruptMask;
u8 MicrowireDirection;
u8 MicrowireHandshaking;
u8 MicrowireTransferMode;
//u8 PinmuxSelect;
//u8 Role;
u8 SclkPhase;
u8 SclkPolarity;
u8 SlaveOutputEnable;
u8 TransferMode;
u8 TransferMechanism;
} DW_SSI_DEFAULT_SETTING, *PDW_SSI_DEFAULT_SETTING;
struct spi_s {
HAL_SSI_ADAPTOR spi_adp;
HAL_SSI_OP spi_op;
u32 irq_handler;
u32 irq_id;
u32 dma_en;
u32 state;
u8 sclk;
#ifdef CONFIG_GDMA_EN
HAL_GDMA_ADAPTER spi_gdma_adp_tx;
HAL_GDMA_ADAPTER spi_gdma_adp_rx;
#endif
u32 bus_tx_done_handler;
u32 bus_tx_done_irq_id;
};
VOID HalSsiOpInit(VOID *Adaptor);
static __inline__ VOID HalSsiSetSclk(
IN PHAL_SSI_ADAPTOR pHalSsiAdapter,
IN u32 ClkRate)
{
HalSsiSetSclkRtl8195a((VOID*)pHalSsiAdapter, ClkRate);
}
HAL_Status HalSsiInit(VOID * Data);
HAL_Status HalSsiDeInit(VOID * Data);
HAL_Status HalSsiEnable(VOID * Data);
HAL_Status HalSsiDisable(VOID * Data);
HAL_Status HalSsiEnterCritical(VOID * Data);
HAL_Status HalSsiExitCritical(VOID * Data);
HAL_Status HalSsiTimeout(u32 StartCount, u32 TimeoutCnt);
HAL_Status HalSsiStopRecv(VOID * Data);
HAL_Status HalSsiSetFormat(VOID * Data);
#ifdef CONFIG_GDMA_EN
HAL_Status HalSsiTxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
VOID HalSsiTxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
HAL_Status HalSsiRxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
VOID HalSsiRxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
HAL_Status HalSsiRxMultiBlkChnl(PHAL_SSI_ADAPTOR pHalSsiAdapter);
HAL_Status HalSsiDmaRecv(VOID * Adapter, u8 * pRxData, u32 Length);
HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length);
static __inline__ VOID
HalSsiDmaInit(
IN PHAL_SSI_ADAPTOR pHalSsiAdapter
)
{
#if CONFIG_CHIP_E_CUT
HalSsiDmaInitRtl8195a_V04((void *)pHalSsiAdapter);
#else
HalSsiDmaInitRtl8195a((void *)pHalSsiAdapter);
#endif
}
/*
static __inline__ HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length)
{
return (HalSsiDmaSendRtl8195a(Adapter, pTxData, Length));
}
static __inline__ HAL_Status HalSsiDmaRecv(VOID *Adapter, u8 *pRxData, u32 Length)
{
return (HalSsiDmaRecvRtl8195a(Adapter, pRxData, Length));
}
*/
#endif // end of "#ifdef CONFIG_GDMA_EN"
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SSI_H_
#define _HAL_SSI_H_
#include "rtl8195a_ssi.h"
/**
* LOG Configurations
*/
extern u32 SSI_DBG_CONFIG;
extern uint8_t SPI0_IS_AS_SLAVE;
#define SSI_DBG_ENTRANCE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENTRANCE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE ANSI_COLOR_GREEN __VA_ARGS__ ANSI_COLOR_RESET); \
}while(0)
#define SSI_DBG_INIT(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INIT_V(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_V)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INIT_VV(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_VV)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_PINMUX(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_PINMUX)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_ENDIS(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENDIS)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_V(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_V)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_HNDLR(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_HNDLR)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_READ(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_READ)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_WRITE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_WRITE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_STATUS(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_STATUS)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_FIFO(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_FIFO)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_READ(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_READ)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_WRITE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_WRITE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_SLV_CTRL(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_SLV_CTRL)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
typedef enum _SSI_DBG_TYPE_LIST_ {
DBG_TYPE_ENTRANCE = 1 << 0,
DBG_TYPE_INIT = 1 << 1,
DBG_TYPE_INIT_V = 1 << 2,
DBG_TYPE_INIT_VV = 1 << 3,
DBG_TYPE_PINMUX = 1 << 4,
DBG_TYPE_ENDIS = 1 << 5,
DBG_TYPE_INT = 1 << 6,
DBG_TYPE_INT_V = 1 << 7,
DBG_TYPE_INT_HNDLR = 1 << 8,
DBG_TYPE_INT_READ = 1 << 9,
DBG_TYPE_INT_WRITE = 1 << 10,
DBG_TYPE_STATUS = 1 << 11,
DBG_TYPE_FIFO = 1 << 12,
DBG_TYPE_READ = 1 << 13,
DBG_TYPE_WRITE = 1 << 14,
DBG_TYPE_SLV_CTRL = 1 << 15
} SSI_DBG_TYPE_LIST, *PSSI_DBG_TYPE_LIST;
typedef struct _SSI_DMA_CONFIG_ {
VOID *pHalGdmaOp;
VOID *pTxHalGdmaAdapter;
VOID *pRxHalGdmaAdapter;
u8 RxDmaBurstSize;
u8 TxDmaBurstSize;
u8 RxDmaEnable;
u8 TxDmaEnable;
IRQ_HANDLE RxGdmaIrqHandle;
IRQ_HANDLE TxGdmaIrqHandle;
}SSI_DMA_CONFIG, *PSSI_DMA_CONFIG;
#ifdef CONFIG_GDMA_EN
typedef struct _HAL_SSI_DMA_MULTIBLK_ {
volatile GDMA_CH_LLI_ELE GdmaChLli[16];
struct GDMA_CH_LLI Lli[16];
struct BLOCK_SIZE_LIST BlockSizeList[16];
}SSI_DMA_MULTIBLK, *PSSI_DMA_MULTIBLK;
#endif
/**
* DesignWare SSI Configurations
*/
typedef struct _HAL_SSI_ADAPTOR_ {
SSI_DMA_CONFIG DmaConfig;
IRQ_HANDLE IrqHandle;
//
VOID (*RxCompCallback)(VOID *Para);
VOID *RxCompCbPara;
VOID *RxData;
VOID (*TxCompCallback)(VOID *Para);
VOID *TxCompCbPara;
VOID *TxData;
u32 DmaRxDataLevel;
u32 DmaTxDataLevel;
u32 InterruptPriority;
u32 RxLength;
u32 RxLengthRemainder;
u32 RxThresholdLevel;
u32 TxLength;
u32 TxThresholdLevel;
u32 SlaveSelectEnable;
//
u16 ClockDivider;
u16 DataFrameNumber;
//
u8 ControlFrameSize;
u8 DataFrameFormat;
u8 DataFrameSize;
u8 DmaControl;
u8 Index;
u8 InterruptMask;
u8 MicrowireDirection;
u8 MicrowireHandshaking;
u8 MicrowireTransferMode;
u8 PinmuxSelect;
u8 Role;
u8 SclkPhase;
u8 SclkPolarity;
u8 SlaveOutputEnable;
u8 TransferMode;
u8 TransferMechanism;
// Extend
u8 Reserve;
u8 HaveTxChannel;
u8 HaveRxChannel;
u8 DefaultRxThresholdLevel;
#ifdef CONFIG_GDMA_EN
SSI_DMA_MULTIBLK DmaTxMultiBlk, DmaRxMultiBlk;
#endif
u32 ReservedDummy;
VOID (*TxIdleCallback)(VOID *Para);
VOID *TxIdleCbPara;
}HAL_SSI_ADAPTOR, *PHAL_SSI_ADAPTOR;
typedef struct _HAL_SSI_OP_{
HAL_Status (*HalSsiPinmuxEnable)(VOID *Adaptor);
HAL_Status (*HalSsiPinmuxDisable)(VOID *Adaptor);
HAL_Status (*HalSsiEnable)(VOID *Adaptor);
HAL_Status (*HalSsiDisable)(VOID *Adaptor);
HAL_Status (*HalSsiInit)(VOID *Adaptor);
HAL_Status (*HalSsiSetSclkPolarity)(VOID *Adaptor);
HAL_Status (*HalSsiSetSclkPhase)(VOID *Adaptor);
HAL_Status (*HalSsiWrite)(VOID *Adaptor, u32 value);
HAL_Status (*HalSsiLoadSetting)(VOID *Adaptor, VOID *Setting);
HAL_Status (*HalSsiSetInterruptMask)(VOID *Adaptor);
HAL_Status (*HalSsiSetDeviceRole)(VOID *Adaptor, u32 Role);
HAL_Status (*HalSsiInterruptEnable)(VOID *Adaptor);
HAL_Status (*HalSsiInterruptDisable)(VOID *Adaptor);
HAL_Status (*HalSsiReadInterrupt)(VOID *Adaptor, VOID *RxData, u32 Length);
HAL_Status (*HalSsiSetRxFifoThresholdLevel)(VOID *Adaptor);
HAL_Status (*HalSsiSetTxFifoThresholdLevel)(VOID *Adaptor);
HAL_Status (*HalSsiWriteInterrupt)(VOID *Adaptor, u8 *TxData, u32 Length);
HAL_Status (*HalSsiSetSlaveEnableRegister)(VOID *Adaptor, u32 SlaveIndex);
u32 (*HalSsiBusy)(VOID *Adaptor);
u32 (*HalSsiReadable)(VOID *Adaptor);
u32 (*HalSsiWriteable)(VOID *Adaptor);
u32 (*HalSsiGetInterruptMask)(VOID *Adaptor);
u32 (*HalSsiGetRxFifoLevel)(VOID *Adaptor);
u32 (*HalSsiGetTxFifoLevel)(VOID *Adaptor);
u32 (*HalSsiGetStatus)(VOID *Adaptor);
u32 (*HalSsiGetInterruptStatus)(VOID *Adaptor);
u32 (*HalSsiRead)(VOID *Adaptor);
u32 (*HalSsiGetRawInterruptStatus)(VOID *Adaptor);
u32 (*HalSsiGetSlaveEnableRegister)(VOID *Adaptor);
}HAL_SSI_OP, *PHAL_SSI_OP;
typedef struct _DW_SSI_DEFAULT_SETTING_ {
VOID (*RxCompCallback)(VOID *Para);
VOID *RxCompCbPara;
VOID *RxData;
VOID (*TxCompCallback)(VOID *Para);
VOID *TxCompCbPara;
VOID *TxData;
u32 DmaRxDataLevel;
u32 DmaTxDataLevel;
u32 InterruptPriority;
u32 RxLength;
u32 RxLengthRemainder;
u32 RxThresholdLevel;
u32 TxLength;
u32 TxThresholdLevel;
u32 SlaveSelectEnable;
//
u16 ClockDivider;
u16 DataFrameNumber;
//
u8 ControlFrameSize;
u8 DataFrameFormat;
u8 DataFrameSize;
u8 DmaControl;
//u8 Index;
u8 InterruptMask;
u8 MicrowireDirection;
u8 MicrowireHandshaking;
u8 MicrowireTransferMode;
//u8 PinmuxSelect;
//u8 Role;
u8 SclkPhase;
u8 SclkPolarity;
u8 SlaveOutputEnable;
u8 TransferMode;
u8 TransferMechanism;
} DW_SSI_DEFAULT_SETTING, *PDW_SSI_DEFAULT_SETTING;
struct spi_s {
HAL_SSI_ADAPTOR spi_adp;
HAL_SSI_OP spi_op;
u32 irq_handler;
u32 irq_id;
u32 dma_en;
u32 state;
u8 sclk;
#ifdef CONFIG_GDMA_EN
HAL_GDMA_ADAPTER spi_gdma_adp_tx;
HAL_GDMA_ADAPTER spi_gdma_adp_rx;
#endif
u32 bus_tx_done_handler;
u32 bus_tx_done_irq_id;
};
VOID HalSsiOpInit(VOID *Adaptor);
static __inline__ VOID HalSsiSetSclk(
IN PHAL_SSI_ADAPTOR pHalSsiAdapter,
IN u32 ClkRate)
{
HalSsiSetSclkRtl8195a((VOID*)pHalSsiAdapter, ClkRate);
}
HAL_Status HalSsiInit(VOID * Data);
HAL_Status HalSsiDeInit(VOID * Data);
HAL_Status HalSsiEnable(VOID * Data);
HAL_Status HalSsiDisable(VOID * Data);
HAL_Status HalSsiEnterCritical(VOID * Data);
HAL_Status HalSsiExitCritical(VOID * Data);
HAL_Status HalSsiTimeout(u32 StartCount, u32 TimeoutCnt);
HAL_Status HalSsiStopRecv(VOID * Data);
HAL_Status HalSsiSetFormat(VOID * Data);
#ifdef CONFIG_GDMA_EN
HAL_Status HalSsiTxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
VOID HalSsiTxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
HAL_Status HalSsiRxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
VOID HalSsiRxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
HAL_Status HalSsiRxMultiBlkChnl(PHAL_SSI_ADAPTOR pHalSsiAdapter);
HAL_Status HalSsiDmaRecv(VOID * Adapter, u8 * pRxData, u32 Length);
HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length);
static __inline__ VOID
HalSsiDmaInit(
IN PHAL_SSI_ADAPTOR pHalSsiAdapter
)
{
#if CONFIG_CHIP_E_CUT
HalSsiDmaInitRtl8195a_V04((void *)pHalSsiAdapter);
#else
HalSsiDmaInitRtl8195a((void *)pHalSsiAdapter);
#endif
}
/*
static __inline__ HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length)
{
return (HalSsiDmaSendRtl8195a(Adapter, pTxData, Length));
}
static __inline__ HAL_Status HalSsiDmaRecv(VOID *Adapter, u8 *pRxData, u32 Length)
{
return (HalSsiDmaRecvRtl8195a(Adapter, pRxData, Length));
}
*/
#endif // end of "#ifdef CONFIG_GDMA_EN"
#endif

192
component/soc/realtek/8195a/fwlib/hal_timer.h
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@ -1,96 +1,96 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_TIMER_H_
#define _HAL_TIMER_H_
#include "basic_types.h"
#include "hal_platform.h"
#include "rtl8195a_timer.h"
#define GTIMER_CLK_HZ (32768)
#define GTIMER_TICK_US (1000000/GTIMER_CLK_HZ)
typedef enum _TIMER_MODE_ {
FREE_RUN_MODE = 0,
USER_DEFINED = 1
}TIMER_MODE, *PTIMER_MODE;
typedef struct _TIMER_ADAPTER_ {
u32 TimerLoadValueUs;
u32 TimerIrqPriority;
TIMER_MODE TimerMode;
IRQ_HANDLE IrqHandle;
u8 TimerId;
u8 IrqDis;
}TIMER_ADAPTER, *PTIMER_ADAPTER;
typedef struct _HAL_TIMER_OP_ {
u32 (*HalGetTimerId)(u32 *TimerId);
BOOL (*HalTimerInit)(VOID *Data);
u32 (*HalTimerReadCount)(u32 TimerId);
VOID (*HalTimerIrqClear)(u32 TimerId);
VOID (*HalTimerDis)(u32 TimerId);
VOID (*HalTimerEn)(u32 TimerId);
VOID (*HalTimerDumpReg)(u32 TimerId);
}HAL_TIMER_OP, *PHAL_TIMER_OP;
#ifdef CONFIG_TIMER_MODULE
// This variable declared in ROM code
extern HAL_TIMER_OP HalTimerOp;
#endif
VOID HalTimerOpInit_Patch(
IN VOID *Data
);
//======================================================
// ROM Function prototype
_LONG_CALL_ VOID HalTimerOpInitV02(IN VOID *Data);
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#define HalTimerOpInit HalTimerOpInit_Patch
#endif
#ifdef CONFIG_RELEASE_BUILD_LIBRARIES
void HalTimerOpInit(
void *Data
);
HAL_Status
HalTimerInit(
void *Data
);
void
HalTimerEnable(
uint32_t TimerId
);
void
HalTimerDisable(
uint32_t TimerId
);
void
HalTimerReLoad(
uint32_t TimerId,
uint32_t LoadUs
);
void
HalTimerDeInit(
void *Data
);
#endif // #ifdef CONFIG_RELEASE_BUILD_LIBRARIES
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_TIMER_H_
#define _HAL_TIMER_H_
#include "basic_types.h"
#include "hal_platform.h"
#include "rtl8195a_timer.h"
#define GTIMER_CLK_HZ (32768)
#define GTIMER_TICK_US (1000000/GTIMER_CLK_HZ)
typedef enum _TIMER_MODE_ {
FREE_RUN_MODE = 0,
USER_DEFINED = 1
}TIMER_MODE, *PTIMER_MODE;
typedef struct _TIMER_ADAPTER_ {
u32 TimerLoadValueUs;
u32 TimerIrqPriority;
TIMER_MODE TimerMode;
IRQ_HANDLE IrqHandle;
u8 TimerId;
u8 IrqDis;
}TIMER_ADAPTER, *PTIMER_ADAPTER;
typedef struct _HAL_TIMER_OP_ {
u32 (*HalGetTimerId)(u32 *TimerId);
BOOL (*HalTimerInit)(VOID *Data);
u32 (*HalTimerReadCount)(u32 TimerId);
VOID (*HalTimerIrqClear)(u32 TimerId);
VOID (*HalTimerDis)(u32 TimerId);
VOID (*HalTimerEn)(u32 TimerId);
VOID (*HalTimerDumpReg)(u32 TimerId);
}HAL_TIMER_OP, *PHAL_TIMER_OP;
#ifdef CONFIG_TIMER_MODULE
// This variable declared in ROM code
extern HAL_TIMER_OP HalTimerOp;
#endif
VOID HalTimerOpInit_Patch(
IN VOID *Data
);
//======================================================
// ROM Function prototype
_LONG_CALL_ VOID HalTimerOpInitV02(IN VOID *Data);
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#define HalTimerOpInit HalTimerOpInit_Patch
#endif
#ifdef CONFIG_RELEASE_BUILD_LIBRARIES
void HalTimerOpInit(
void *Data
);
HAL_Status
HalTimerInit(
void *Data
);
void
HalTimerEnable(
uint32_t TimerId
);
void
HalTimerDisable(
uint32_t TimerId
);
void
HalTimerReLoad(
uint32_t TimerId,
uint32_t LoadUs
);
void
HalTimerDeInit(
void *Data
);
#endif // #ifdef CONFIG_RELEASE_BUILD_LIBRARIES
#endif

510
component/soc/realtek/8195a/fwlib/hal_uart.h
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@ -1,255 +1,255 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_UART_H_
#define _HAL_UART_H_
#include "rtl8195a_uart.h"
/**
* RUART Configurations
*/
#define UART_WAIT_FOREVER 0xffffffff
#define UART_DMA_MBLK_NUM 16 // maximum block number for each DMA transfer, it must <= 16
#define UART_DMA_BLOCK_SIZE 4092 // the block size of multiple block DMA, it cann0t over 4095
typedef struct _HAL_UART_DMA_MULTIBLK_ {
volatile GDMA_CH_LLI_ELE GdmaChLli[UART_DMA_MBLK_NUM];
struct GDMA_CH_LLI Lli[UART_DMA_MBLK_NUM];
struct BLOCK_SIZE_LIST BlockSizeList[UART_DMA_MBLK_NUM];
}UART_DMA_MULTIBLK, *PUART_DMA_MULTIBLK;
typedef struct _UART_DMA_CONFIG_ {
u8 TxDmaEnable;
u8 RxDmaEnable;
u8 TxDmaBurstSize;
u8 RxDmaBurstSize;
VOID *pHalGdmaOp;
VOID *pTxHalGdmaAdapter;
VOID *pRxHalGdmaAdapter;
IRQ_HANDLE TxGdmaIrqHandle;
IRQ_HANDLE RxGdmaIrqHandle;
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
UART_DMA_MULTIBLK *pTxDmaBlkList; // point to multi-block list
UART_DMA_MULTIBLK *pRxDmaBlkList; // point to multi-block list
u8 TxDmaMBChnl; // is using DMA multiple block channel
u8 RxDmaMBChnl; // is using DMA multiple block channel
#endif
}UART_DMA_CONFIG, *PUART_DMA_CONFIG;
typedef struct _HAL_RUART_ADAPTER_ {
u32 BaudRate;
u32 FlowControl;
u32 FifoControl;
u32 Interrupts;
u32 TxCount; // how many byte to TX
u32 RxCount; // how many bytes to RX
u8 *pTxBuf;
u8 *pRxBuf;
HAL_UART_State State; // UART state
u8 Status; // Transfer Status
u8 Locked; // is UART locked for operation
u8 UartIndex;
u8 WordLen; // word length select: 0 -> 7 bits, 1 -> 8 bits
u8 StopBit; // word length select: 0 -> 1 stop bit, 1 -> 2 stop bit
u8 Parity; // parity check enable
u8 ParityType; // parity check type
u8 StickParity;
u8 ModemStatus; // the modem status
u8 DmaEnable;
u8 TestCaseNumber;
u8 PinmuxSelect;
BOOL PullMode;
IRQ_HANDLE IrqHandle;
PUART_DMA_CONFIG DmaConfig;
VOID (*ModemStatusInd)(VOID *pAdapter); // modem status indication interrupt handler
VOID (*TxTDCallback)(VOID *pAdapter); // User Tx Done callback function
VOID (*RxDRCallback)(VOID *pAdapter); // User Rx Data ready callback function
VOID (*TxCompCallback)(VOID *para); // User Tx complete callback function
VOID (*RxCompCallback)(VOID *para); // User Rx complete callback function
VOID *TxTDCbPara; // the pointer agrument for TxTDCallback
VOID *RxDRCbPara; // the pointer agrument for RxDRCallback
VOID *TxCompCbPara; // the pointer argument for TxCompCbPara
VOID *RxCompCbPara; // the pointer argument for RxCompCallback
VOID (*EnterCritical)(void);
VOID (*ExitCritical)(void);
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
//1 New member only can be added below: members above must be fixed for ROM code
u32 *pDefaultBaudRateTbl; // point to the table of pre-defined baud rate
u8 *pDefaultOvsrRTbl; // point to the table of OVSR for pre-defined baud rate
u16 *pDefaultDivTbl; // point to the table of DIV for pre-defined baud rate
u8 *pDefOvsrAdjBitTbl_10; // point to the table of OVSR-Adj bits for 10 bits
u8 *pDefOvsrAdjBitTbl_9; // point to the table of OVSR-Adj bits for 9 bits
u8 *pDefOvsrAdjBitTbl_8; // point to the table of OVSR-Adj bits for 8 bits
u16 *pDefOvsrAdjTbl_10; // point to the table of OVSR-Adj for pre-defined baud rate
u16 *pDefOvsrAdjTbl_9; // point to the table of OVSR-Adj for pre-defined baud rate
u16 *pDefOvsrAdjTbl_8; // point to the table of OVSR-Adj for pre-defined baud rate
PUART_DMA_MULTIBLK pTxDMAMBlk; // point to the Link List Table of the DMA Multiple Block
PUART_DMA_MULTIBLK pRxDMAMBlk; // point to the Link List Table of the DMA Multiple Block
u32 BaudRateUsing; // Current using Baud-Rate
u8 WordLenUsing; // Current using Word Length
u8 ParityUsing; // Current using Parity check
u8 RTSCtrl; // Software RTS Control
#if 0//CONFIG_CHIP_E_CUT
u8 TxState;
u8 RxState;
u32 TxInitSize; // how many byte to TX at atart
u32 RxInitSize; // how many bytes to RX at start
VOID (*RuartEnterCritical)(VOID *para); // enter critical: disable UART interrupt
VOID (*RuartExitCritical)(VOID *para); // exit critical: re-enable UART interrupt
VOID (*TaskYield)(VOID *para); // User Task Yield: do a context switch while waitting
VOID *TaskYieldPara; // the agrument (pointer) for TaskYield
#endif // #if CONFIG_CHIP_E_CUT
#endif
}HAL_RUART_ADAPTER, *PHAL_RUART_ADAPTER;
typedef struct _HAL_RUART_OP_ {
VOID (*HalRuartAdapterLoadDef)(VOID *pAdp, u8 UartIdx); // Load UART adapter default setting
VOID (*HalRuartTxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load TX GDMA default setting
VOID (*HalRuartRxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load RX GDMA default setting
HAL_Status (*HalRuartResetRxFifo)(VOID *Data);
HAL_Status (*HalRuartInit)(VOID *Data);
VOID (*HalRuartDeInit)(VOID *Data);
HAL_Status (*HalRuartPutC)(VOID *Data, u8 TxData);
u32 (*HalRuartSend)(VOID *Data, u8 *pTxData, u32 Length, u32 Timeout);
HAL_Status (*HalRuartIntSend)(VOID *Data, u8 *pTxData, u32 Length);
HAL_Status (*HalRuartDmaSend)(VOID *Data, u8 *pTxData, u32 Length);
HAL_Status (*HalRuartStopSend)(VOID *Data);
HAL_Status (*HalRuartGetC)(VOID *Data, u8 *pRxByte);
u32 (*HalRuartRecv)(VOID *Data, u8 *pRxData, u32 Length, u32 Timeout);
HAL_Status (*HalRuartIntRecv)(VOID *Data, u8 *pRxData, u32 Length);
HAL_Status (*HalRuartDmaRecv)(VOID *Data, u8 *pRxData, u32 Length);
HAL_Status (*HalRuartStopRecv)(VOID *Data);
u8 (*HalRuartGetIMR)(VOID *Data);
VOID (*HalRuartSetIMR)(VOID *Data);
u32 (*HalRuartGetDebugValue)(VOID *Data, u32 DbgSel);
VOID (*HalRuartDmaInit)(VOID *Data);
VOID (*HalRuartRTSCtrl)(VOID *Data, BOOLEAN RtsCtrl);
VOID (*HalRuartRegIrq)(VOID *Data);
VOID (*HalRuartIntEnable)(VOID *Data);
VOID (*HalRuartIntDisable)(VOID *Data);
}HAL_RUART_OP, *PHAL_RUART_OP;
typedef struct _RUART_DATA_ {
PHAL_RUART_ADAPTER pHalRuartAdapter;
BOOL PullMode;
u8 BinaryData;
u8 SendBuffer;
u8 RecvBuffer;
}RUART_DATA, *PRUART_DATA;
typedef struct _RUART_ADAPTER_ {
PHAL_RUART_OP pHalRuartOp;
PHAL_RUART_ADAPTER pHalRuartAdapter;
PUART_DMA_CONFIG pHalRuartDmaCfg;
}RUART_ADAPTER, *PRUART_ADAPTER;
extern VOID
HalRuartOpInit(
IN VOID *Data
);
extern HAL_Status
HalRuartTxGdmaInit(
PHAL_RUART_ADAPTER pHalRuartAdapter,
PUART_DMA_CONFIG pUartGdmaConfig,
u8 IsMultiBlk
);
extern VOID
HalRuartTxGdmaDeInit(
PUART_DMA_CONFIG pUartGdmaConfig
);
extern HAL_Status
HalRuartRxGdmaInit(
PHAL_RUART_ADAPTER pHalRuartAdapter,
PUART_DMA_CONFIG pUartGdmaConfig,
u8 IsMultiBlk
);
extern VOID
HalRuartRxGdmaDeInit(
PUART_DMA_CONFIG pUartGdmaConfig
);
extern HAL_Status
HalRuartResetTxFifo(
VOID *Data
);
extern HAL_Status
HalRuartResetRxFifo(
IN VOID *Data
);
extern HAL_Status
HalRuartSetBaudRate(
IN VOID *Data
);
extern HAL_Status
HalRuartInit(
IN VOID *Data
);
extern VOID
HalRuartDeInit(
IN VOID *Data
);
extern HAL_Status
HalRuartDisable(
IN VOID *Data
);
extern HAL_Status
HalRuartEnable(
IN VOID *Data
);
HAL_Status
HalRuartFlowCtrl(
IN VOID *Data
);
VOID
HalRuartEnterCritical(
IN VOID *Data
);
VOID
HalRuartExitCritical(
IN VOID *Data
);
HAL_Status
HalRuartDmaSend(
IN VOID *Data,
IN u8 *pTxBuf,
IN u32 Length
);
HAL_Status
HalRuartDmaRecv(
IN VOID *Data,
IN u8 *pRxBuf,
IN u32 Length
);
extern const HAL_RUART_OP _HalRuartOp;
extern HAL_Status RuartLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
extern VOID RuartUnLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_UART_H_
#define _HAL_UART_H_
#include "rtl8195a_uart.h"
/**
* RUART Configurations
*/
#define UART_WAIT_FOREVER 0xffffffff
#define UART_DMA_MBLK_NUM 16 // maximum block number for each DMA transfer, it must <= 16
#define UART_DMA_BLOCK_SIZE 4092 // the block size of multiple block DMA, it cann0t over 4095
typedef struct _HAL_UART_DMA_MULTIBLK_ {
volatile GDMA_CH_LLI_ELE GdmaChLli[UART_DMA_MBLK_NUM];
struct GDMA_CH_LLI Lli[UART_DMA_MBLK_NUM];
struct BLOCK_SIZE_LIST BlockSizeList[UART_DMA_MBLK_NUM];
}UART_DMA_MULTIBLK, *PUART_DMA_MULTIBLK;
typedef struct _UART_DMA_CONFIG_ {
u8 TxDmaEnable;
u8 RxDmaEnable;
u8 TxDmaBurstSize;
u8 RxDmaBurstSize;
VOID *pHalGdmaOp;
VOID *pTxHalGdmaAdapter;
VOID *pRxHalGdmaAdapter;
IRQ_HANDLE TxGdmaIrqHandle;
IRQ_HANDLE RxGdmaIrqHandle;
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
UART_DMA_MULTIBLK *pTxDmaBlkList; // point to multi-block list
UART_DMA_MULTIBLK *pRxDmaBlkList; // point to multi-block list
u8 TxDmaMBChnl; // is using DMA multiple block channel
u8 RxDmaMBChnl; // is using DMA multiple block channel
#endif
}UART_DMA_CONFIG, *PUART_DMA_CONFIG;
typedef struct _HAL_RUART_ADAPTER_ {
u32 BaudRate;
u32 FlowControl;
u32 FifoControl;
u32 Interrupts;
u32 TxCount; // how many byte to TX
u32 RxCount; // how many bytes to RX
u8 *pTxBuf;
u8 *pRxBuf;
HAL_UART_State State; // UART state
u8 Status; // Transfer Status
u8 Locked; // is UART locked for operation
u8 UartIndex;
u8 WordLen; // word length select: 0 -> 7 bits, 1 -> 8 bits
u8 StopBit; // word length select: 0 -> 1 stop bit, 1 -> 2 stop bit
u8 Parity; // parity check enable
u8 ParityType; // parity check type
u8 StickParity;
u8 ModemStatus; // the modem status
u8 DmaEnable;
u8 TestCaseNumber;
u8 PinmuxSelect;
BOOL PullMode;
IRQ_HANDLE IrqHandle;
PUART_DMA_CONFIG DmaConfig;
VOID (*ModemStatusInd)(VOID *pAdapter); // modem status indication interrupt handler
VOID (*TxTDCallback)(VOID *pAdapter); // User Tx Done callback function
VOID (*RxDRCallback)(VOID *pAdapter); // User Rx Data ready callback function
VOID (*TxCompCallback)(VOID *para); // User Tx complete callback function
VOID (*RxCompCallback)(VOID *para); // User Rx complete callback function
VOID *TxTDCbPara; // the pointer agrument for TxTDCallback
VOID *RxDRCbPara; // the pointer agrument for RxDRCallback
VOID *TxCompCbPara; // the pointer argument for TxCompCbPara
VOID *RxCompCbPara; // the pointer argument for RxCompCallback
VOID (*EnterCritical)(void);
VOID (*ExitCritical)(void);
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
//1 New member only can be added below: members above must be fixed for ROM code
u32 *pDefaultBaudRateTbl; // point to the table of pre-defined baud rate
u8 *pDefaultOvsrRTbl; // point to the table of OVSR for pre-defined baud rate
u16 *pDefaultDivTbl; // point to the table of DIV for pre-defined baud rate
u8 *pDefOvsrAdjBitTbl_10; // point to the table of OVSR-Adj bits for 10 bits
u8 *pDefOvsrAdjBitTbl_9; // point to the table of OVSR-Adj bits for 9 bits
u8 *pDefOvsrAdjBitTbl_8; // point to the table of OVSR-Adj bits for 8 bits
u16 *pDefOvsrAdjTbl_10; // point to the table of OVSR-Adj for pre-defined baud rate
u16 *pDefOvsrAdjTbl_9; // point to the table of OVSR-Adj for pre-defined baud rate
u16 *pDefOvsrAdjTbl_8; // point to the table of OVSR-Adj for pre-defined baud rate
PUART_DMA_MULTIBLK pTxDMAMBlk; // point to the Link List Table of the DMA Multiple Block
PUART_DMA_MULTIBLK pRxDMAMBlk; // point to the Link List Table of the DMA Multiple Block
u32 BaudRateUsing; // Current using Baud-Rate
u8 WordLenUsing; // Current using Word Length
u8 ParityUsing; // Current using Parity check
u8 RTSCtrl; // Software RTS Control
#if 0//CONFIG_CHIP_E_CUT
u8 TxState;
u8 RxState;
u32 TxInitSize; // how many byte to TX at atart
u32 RxInitSize; // how many bytes to RX at start
VOID (*RuartEnterCritical)(VOID *para); // enter critical: disable UART interrupt
VOID (*RuartExitCritical)(VOID *para); // exit critical: re-enable UART interrupt
VOID (*TaskYield)(VOID *para); // User Task Yield: do a context switch while waitting
VOID *TaskYieldPara; // the agrument (pointer) for TaskYield
#endif // #if CONFIG_CHIP_E_CUT
#endif
}HAL_RUART_ADAPTER, *PHAL_RUART_ADAPTER;
typedef struct _HAL_RUART_OP_ {
VOID (*HalRuartAdapterLoadDef)(VOID *pAdp, u8 UartIdx); // Load UART adapter default setting
VOID (*HalRuartTxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load TX GDMA default setting
VOID (*HalRuartRxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load RX GDMA default setting
HAL_Status (*HalRuartResetRxFifo)(VOID *Data);
HAL_Status (*HalRuartInit)(VOID *Data);
VOID (*HalRuartDeInit)(VOID *Data);
HAL_Status (*HalRuartPutC)(VOID *Data, u8 TxData);
u32 (*HalRuartSend)(VOID *Data, u8 *pTxData, u32 Length, u32 Timeout);
HAL_Status (*HalRuartIntSend)(VOID *Data, u8 *pTxData, u32 Length);
HAL_Status (*HalRuartDmaSend)(VOID *Data, u8 *pTxData, u32 Length);
HAL_Status (*HalRuartStopSend)(VOID *Data);
HAL_Status (*HalRuartGetC)(VOID *Data, u8 *pRxByte);
u32 (*HalRuartRecv)(VOID *Data, u8 *pRxData, u32 Length, u32 Timeout);
HAL_Status (*HalRuartIntRecv)(VOID *Data, u8 *pRxData, u32 Length);
HAL_Status (*HalRuartDmaRecv)(VOID *Data, u8 *pRxData, u32 Length);
HAL_Status (*HalRuartStopRecv)(VOID *Data);
u8 (*HalRuartGetIMR)(VOID *Data);
VOID (*HalRuartSetIMR)(VOID *Data);
u32 (*HalRuartGetDebugValue)(VOID *Data, u32 DbgSel);
VOID (*HalRuartDmaInit)(VOID *Data);
VOID (*HalRuartRTSCtrl)(VOID *Data, BOOLEAN RtsCtrl);
VOID (*HalRuartRegIrq)(VOID *Data);
VOID (*HalRuartIntEnable)(VOID *Data);
VOID (*HalRuartIntDisable)(VOID *Data);
}HAL_RUART_OP, *PHAL_RUART_OP;
typedef struct _RUART_DATA_ {
PHAL_RUART_ADAPTER pHalRuartAdapter;
BOOL PullMode;
u8 BinaryData;
u8 SendBuffer;
u8 RecvBuffer;
}RUART_DATA, *PRUART_DATA;
typedef struct _RUART_ADAPTER_ {
PHAL_RUART_OP pHalRuartOp;
PHAL_RUART_ADAPTER pHalRuartAdapter;
PUART_DMA_CONFIG pHalRuartDmaCfg;
}RUART_ADAPTER, *PRUART_ADAPTER;
extern VOID
HalRuartOpInit(
IN VOID *Data
);
extern HAL_Status
HalRuartTxGdmaInit(
PHAL_RUART_ADAPTER pHalRuartAdapter,
PUART_DMA_CONFIG pUartGdmaConfig,
u8 IsMultiBlk
);
extern VOID
HalRuartTxGdmaDeInit(
PUART_DMA_CONFIG pUartGdmaConfig
);
extern HAL_Status
HalRuartRxGdmaInit(
PHAL_RUART_ADAPTER pHalRuartAdapter,
PUART_DMA_CONFIG pUartGdmaConfig,
u8 IsMultiBlk
);
extern VOID
HalRuartRxGdmaDeInit(
PUART_DMA_CONFIG pUartGdmaConfig
);
extern HAL_Status
HalRuartResetTxFifo(
VOID *Data
);
extern HAL_Status
HalRuartResetRxFifo(
IN VOID *Data
);
extern HAL_Status
HalRuartSetBaudRate(
IN VOID *Data
);
extern HAL_Status
HalRuartInit(
IN VOID *Data
);
extern VOID
HalRuartDeInit(
IN VOID *Data
);
extern HAL_Status
HalRuartDisable(
IN VOID *Data
);
extern HAL_Status
HalRuartEnable(
IN VOID *Data
);
HAL_Status
HalRuartFlowCtrl(
IN VOID *Data
);
VOID
HalRuartEnterCritical(
IN VOID *Data
);
VOID
HalRuartExitCritical(
IN VOID *Data
);
HAL_Status
HalRuartDmaSend(
IN VOID *Data,
IN u8 *pTxBuf,
IN u32 Length
);
HAL_Status
HalRuartDmaRecv(
IN VOID *Data,
IN u8 *pRxBuf,
IN u32 Length
);
extern const HAL_RUART_OP _HalRuartOp;
extern HAL_Status RuartLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
extern VOID RuartUnLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
#endif

106
component/soc/realtek/8195a/fwlib/hal_vector_table.h
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@ -1,53 +1,53 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_VECTOR_TABLE_H_
#define _HAL_VECTOR_TABLE_H_
extern _LONG_CALL_ROM_ VOID
VectorTableInitRtl8195A(
IN u32 StackP
);
extern _LONG_CALL_ROM_ VOID
VectorTableInitForOSRtl8195A(
IN VOID *PortSVC,
IN VOID *PortPendSVH,
IN VOID *PortSysTick
);
extern _LONG_CALL_ROM_ BOOL
VectorIrqRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ BOOL
VectorIrqUnRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
VectorIrqEnRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
VectorIrqDisRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
HalPeripheralIntrHandle(VOID);
#endif //_HAL_VECTOR_TABLE_H_
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_VECTOR_TABLE_H_
#define _HAL_VECTOR_TABLE_H_
extern _LONG_CALL_ROM_ VOID
VectorTableInitRtl8195A(
IN u32 StackP
);
extern _LONG_CALL_ROM_ VOID
VectorTableInitForOSRtl8195A(
IN VOID *PortSVC,
IN VOID *PortPendSVH,
IN VOID *PortSysTick
);
extern _LONG_CALL_ROM_ BOOL
VectorIrqRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ BOOL
VectorIrqUnRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
VectorIrqEnRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
VectorIrqDisRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
HalPeripheralIntrHandle(VOID);
#endif //_HAL_VECTOR_TABLE_H_

1188
component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_list.h
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164
component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_otg_adp.h
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@ -1,82 +1,82 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
* $Revision: #8 $
* $Date: 2013/04/09 $
* $Change: 2201932 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef __DWC_OTG_ADP_H__
#define __DWC_OTG_ADP_H__
/**
* @file
*
* This file contains the Attach Detect Protocol interfaces and defines
* (functions) and structures for Linux.
*
*/
#define DWC_OTG_ADP_UNATTACHED 0
#define DWC_OTG_ADP_ATTACHED 1
#define DWC_OTG_ADP_UNKOWN 2
#define HOST_RTIM_THRESHOLD 5
#define DEVICE_RTIM_THRESHOLD 3
typedef struct dwc_otg_adp {
uint32_t adp_started;
uint32_t initial_probe;
int32_t probe_timer_values[2];
uint32_t probe_enabled;
uint32_t sense_enabled;
dwc_timer_t *sense_timer;
uint32_t sense_timer_started;
dwc_timer_t *vbuson_timer;
uint32_t vbuson_timer_started;
uint32_t attached;
uint32_t probe_counter;
uint32_t gpwrdn;
} dwc_otg_adp_t;
/**
* Attach Detect Protocol functions
*/
extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
#endif //__DWC_OTG_ADP_H__
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
* $Revision: #8 $
* $Date: 2013/04/09 $
* $Change: 2201932 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef __DWC_OTG_ADP_H__
#define __DWC_OTG_ADP_H__
/**
* @file
*
* This file contains the Attach Detect Protocol interfaces and defines
* (functions) and structures for Linux.
*
*/
#define DWC_OTG_ADP_UNATTACHED 0
#define DWC_OTG_ADP_ATTACHED 1
#define DWC_OTG_ADP_UNKOWN 2
#define HOST_RTIM_THRESHOLD 5
#define DEVICE_RTIM_THRESHOLD 3
typedef struct dwc_otg_adp {
uint32_t adp_started;
uint32_t initial_probe;
int32_t probe_timer_values[2];
uint32_t probe_enabled;
uint32_t sense_enabled;
dwc_timer_t *sense_timer;
uint32_t sense_timer_started;
dwc_timer_t *vbuson_timer;
uint32_t vbuson_timer_started;
uint32_t attached;
uint32_t probe_counter;
uint32_t gpwrdn;
} dwc_otg_adp_t;
/**
* Attach Detect Protocol functions
*/
extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
#endif //__DWC_OTG_ADP_H__

172
component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_otg_attr.h
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@ -1,86 +1,86 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
* $Revision: #13 $
* $Date: 2010/06/21 $
* $Change: 1532021 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_ATTR_H__)
#define __DWC_OTG_ATTR_H__
#if 0
/** @file
* This file contains the interface to the Linux device attributes.
*/
extern struct device_attribute dev_attr_regoffset;
extern struct device_attribute dev_attr_regvalue;
extern struct device_attribute dev_attr_mode;
extern struct device_attribute dev_attr_hnpcapable;
extern struct device_attribute dev_attr_srpcapable;
extern struct device_attribute dev_attr_hnp;
extern struct device_attribute dev_attr_srp;
extern struct device_attribute dev_attr_buspower;
extern struct device_attribute dev_attr_bussuspend;
extern struct device_attribute dev_attr_mode_ch_tim_en;
extern struct device_attribute dev_attr_fr_interval;
extern struct device_attribute dev_attr_busconnected;
extern struct device_attribute dev_attr_gotgctl;
extern struct device_attribute dev_attr_gusbcfg;
extern struct device_attribute dev_attr_grxfsiz;
extern struct device_attribute dev_attr_gnptxfsiz;
extern struct device_attribute dev_attr_gpvndctl;
extern struct device_attribute dev_attr_ggpio;
extern struct device_attribute dev_attr_guid;
extern struct device_attribute dev_attr_gsnpsid;
extern struct device_attribute dev_attr_devspeed;
extern struct device_attribute dev_attr_enumspeed;
extern struct device_attribute dev_attr_hptxfsiz;
extern struct device_attribute dev_attr_hprt0;
#ifdef CONFIG_USB_DWC_OTG_LPM
extern struct device_attribute dev_attr_lpm_response;
extern struct device_attribute devi_attr_sleep_status;
#endif
void dwc_otg_attr_create(
#ifdef LM_INTERFACE
struct lm_device *dev
#elif PCI_INTERFACE
struct pci_dev *dev
#endif
);
void dwc_otg_attr_remove(
#ifdef LM_INTERFACE
struct lm_device *dev
#elif PCI_INTERFACE
struct pci_dev *dev
#endif
);
#endif
#endif
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
* $Revision: #13 $
* $Date: 2010/06/21 $
* $Change: 1532021 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_ATTR_H__)
#define __DWC_OTG_ATTR_H__
#if 0
/** @file
* This file contains the interface to the Linux device attributes.
*/
extern struct device_attribute dev_attr_regoffset;
extern struct device_attribute dev_attr_regvalue;
extern struct device_attribute dev_attr_mode;
extern struct device_attribute dev_attr_hnpcapable;
extern struct device_attribute dev_attr_srpcapable;
extern struct device_attribute dev_attr_hnp;
extern struct device_attribute dev_attr_srp;
extern struct device_attribute dev_attr_buspower;
extern struct device_attribute dev_attr_bussuspend;
extern struct device_attribute dev_attr_mode_ch_tim_en;
extern struct device_attribute dev_attr_fr_interval;
extern struct device_attribute dev_attr_busconnected;
extern struct device_attribute dev_attr_gotgctl;
extern struct device_attribute dev_attr_gusbcfg;
extern struct device_attribute dev_attr_grxfsiz;
extern struct device_attribute dev_attr_gnptxfsiz;
extern struct device_attribute dev_attr_gpvndctl;
extern struct device_attribute dev_attr_ggpio;
extern struct device_attribute dev_attr_guid;
extern struct device_attribute dev_attr_gsnpsid;
extern struct device_attribute dev_attr_devspeed;
extern struct device_attribute dev_attr_enumspeed;
extern struct device_attribute dev_attr_hptxfsiz;
extern struct device_attribute dev_attr_hprt0;
#ifdef CONFIG_USB_DWC_OTG_LPM
extern struct device_attribute dev_attr_lpm_response;
extern struct device_attribute devi_attr_sleep_status;
#endif
void dwc_otg_attr_create(
#ifdef LM_INTERFACE
struct lm_device *dev
#elif PCI_INTERFACE
struct pci_dev *dev
#endif
);
void dwc_otg_attr_remove(
#ifdef LM_INTERFACE
struct lm_device *dev
#elif PCI_INTERFACE
struct pci_dev *dev
#endif
);
#endif
#endif

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component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_otg_cil.h
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component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_otg_core_if.h
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component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_otg_driver.h
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@ -1,124 +1,124 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
* $Revision: #19 $
* $Date: 2010/11/15 $
* $Change: 1627671 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef __DWC_OTG_DRIVER_H__
#define __DWC_OTG_DRIVER_H__
/** @file
* This file contains the interface to the Linux driver.
*/
//#include "dwc_otg_os_dep.h"
#include "dwc_otg_core_if.h"
#include "osdep_service.h"
/* Type declarations */
struct dwc_otg_pcd;
struct dwc_otg_hcd;
/**
* This structure is a wrapper that encapsulates the driver components used to
* manage a single DWC_otg controller.
*/
typedef struct dwc_otg_device {
/** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE
* VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD
* require this. */
//struct os_dependent os_dep;
/** Base address returned from ioremap() */
void *base;
uint32_t reg_offset;
/** Pointer to the core interface structure. */
dwc_otg_core_if_t *core_if;
/** Pointer to the PCD structure. */
struct dwc_otg_pcd *pcd;
/** Pointer to the HCD structure. */
struct dwc_otg_hcd *hcd;
/** Flag to indicate whether the common IRQ handler is installed. */
uint8_t common_irq_installed;
} dwc_otg_device_t;
/*We must clear S3C24XX_EINTPEND external interrupt register
* because after clearing in this register trigerred IRQ from
* H/W core in kernel interrupt can be occured again before OTG
* handlers clear all IRQ sources of Core registers because of
* timing latencies and Low Level IRQ Type.
*/
#ifdef CONFIG_MACH_IPMATE
#define S3C2410X_CLEAR_EINTPEND() \
do { \
__raw_writel(1UL << 11,S3C24XX_EINTPEND); \
} while (0)
#else
#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
#endif
typedef struct USB_OTG_DRV_ADP {
dwc_otg_device_t *otgdev;
IRQ_HANDLE *pIrqHnd;
#if !TASK_SCHEDULER_DISABLED
#if defined(DWC_WITH_WLAN_OSDEP)
_sema Sema;
#else
_Sema Sema;
#endif
#else
u32 Sema;
#endif
#if !TASK_SCHEDULER_DISABLED
#if defined(DWC_WITH_WLAN_OSDEP)
struct task_struct OTGTask;
#else
xTaskHandle OTGTask;
#endif
#else
u32 OTGTask;
#endif
}USB_OTG_DRV_ADP,*PUSB_OTG_DRV_ADP;
typedef struct _DWC_OTG_ADAPTER_ {
u32 temp0;
dwc_otg_device_t *otgdev;
u8 TestItem;
}DWC_OTG_ADAPTER, *PDWC_OTG_ADAPTER;
void dwc_otg_disable_irq(IN VOID);
void dwc_otg_enable_irq(IN VOID);
#endif
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
* $Revision: #19 $
* $Date: 2010/11/15 $
* $Change: 1627671 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef __DWC_OTG_DRIVER_H__
#define __DWC_OTG_DRIVER_H__
/** @file
* This file contains the interface to the Linux driver.
*/
//#include "dwc_otg_os_dep.h"
#include "dwc_otg_core_if.h"
#include "osdep_service.h"
/* Type declarations */
struct dwc_otg_pcd;
struct dwc_otg_hcd;
/**
* This structure is a wrapper that encapsulates the driver components used to
* manage a single DWC_otg controller.
*/
typedef struct dwc_otg_device {
/** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE
* VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD
* require this. */
//struct os_dependent os_dep;
/** Base address returned from ioremap() */
void *base;
uint32_t reg_offset;
/** Pointer to the core interface structure. */
dwc_otg_core_if_t *core_if;
/** Pointer to the PCD structure. */
struct dwc_otg_pcd *pcd;
/** Pointer to the HCD structure. */
struct dwc_otg_hcd *hcd;
/** Flag to indicate whether the common IRQ handler is installed. */
uint8_t common_irq_installed;
} dwc_otg_device_t;
/*We must clear S3C24XX_EINTPEND external interrupt register
* because after clearing in this register trigerred IRQ from
* H/W core in kernel interrupt can be occured again before OTG
* handlers clear all IRQ sources of Core registers because of
* timing latencies and Low Level IRQ Type.
*/
#ifdef CONFIG_MACH_IPMATE
#define S3C2410X_CLEAR_EINTPEND() \
do { \
__raw_writel(1UL << 11,S3C24XX_EINTPEND); \
} while (0)
#else
#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
#endif
typedef struct USB_OTG_DRV_ADP {
dwc_otg_device_t *otgdev;
IRQ_HANDLE *pIrqHnd;
#if !TASK_SCHEDULER_DISABLED
#if defined(DWC_WITH_WLAN_OSDEP)
_sema Sema;
#else
_Sema Sema;
#endif
#else
u32 Sema;
#endif
#if !TASK_SCHEDULER_DISABLED
#if defined(DWC_WITH_WLAN_OSDEP)
struct task_struct OTGTask;
#else
xTaskHandle OTGTask;
#endif
#else
u32 OTGTask;
#endif
}USB_OTG_DRV_ADP,*PUSB_OTG_DRV_ADP;
typedef struct _DWC_OTG_ADAPTER_ {
u32 temp0;
dwc_otg_device_t *otgdev;
u8 TestItem;
}DWC_OTG_ADAPTER, *PDWC_OTG_ADAPTER;
void dwc_otg_disable_irq(IN VOID);
void dwc_otg_enable_irq(IN VOID);
#endif

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@ -1,412 +1,412 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
* $Revision: #12 $
* $Date: 2011/10/26 $
* $Change: 1873028 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_DEVICE_ONLY
#ifndef __DWC_HCD_IF_H__
#define __DWC_HCD_IF_H__
#include "dwc_otg_core_if.h"
/** @file
* This file defines DWC_OTG HCD Core API.
*/
struct dwc_otg_hcd;
typedef struct dwc_otg_hcd dwc_otg_hcd_t;
struct dwc_otg_hcd_urb;
typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
/** @name HCD Function Driver Callbacks */
/** @{ */
/** This function is called whenever core switches to host mode. */
typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
/** This function is called when device has been disconnected */
typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
void *urb_handle,
uint32_t * hub_addr,
uint32_t * port_addr);
/** Via this function HCD core gets device speed */
typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
void *urb_handle);
/** This function is called when urb is completed */
typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
void *urb_handle,
dwc_otg_hcd_urb_t * dwc_otg_urb,
int32_t status);
/** Via this function HCD core gets b_hnp_enable parameter */
typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
struct dwc_otg_hcd_function_ops {
dwc_otg_hcd_start_cb_t start;
dwc_otg_hcd_disconnect_cb_t disconnect;
dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
dwc_otg_hcd_speed_from_urb_cb_t speed;
dwc_otg_hcd_complete_urb_cb_t complete;
dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
};
/** @} */
/** @name HCD Core API */
/** @{ */
/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
extern _LONG_CALL_ dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
/** This function should be called to initiate HCD Core.
*
* @param hcd The HCD
* @param core_if The DWC_OTG Core
*
* Returns -DWC_E_NO_MEMORY if no enough memory.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
/** Frees HCD
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
/** This function should be called on every hardware interrupt.
*
* @param dwc_otg_hcd The HCD
*
* Returns non zero if interrupt is handled
* Return 0 if interrupt is not handled
*/
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
/**
* Returns private data set by
* dwc_otg_hcd_set_priv_data function.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
/**
* Set private data.
*
* @param hcd The HCD
* @param priv_data pointer to be stored in private data
*/
extern _LONG_CALL_ void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
/**
* This function initializes the HCD Core.
*
* @param hcd The HCD
* @param fops The Function Driver Operations data structure containing pointers to all callbacks.
*
* Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
struct dwc_otg_hcd_function_ops *fops);
/**
* Halts the DWC_otg host mode operations in a clean manner. USB transfers are
* stopped.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
/**
* Handles hub class-specific requests.
*
* @param dwc_otg_hcd The HCD
* @param typeReq Request Type
* @param wValue wValue from control request
* @param wIndex wIndex from control request
* @param buf data buffer
* @param wLength data buffer length
*
* Returns -DWC_E_INVALID if invalid argument is passed
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
uint16_t typeReq, uint16_t wValue,
uint16_t wIndex, uint8_t * buf,
uint16_t wLength);
/**
* Returns otg port number.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
/**
* Returns OTG version - either 1.3 or 2.0.
*
* @param core_if The core_if structure pointer
*/
extern _LONG_CALL_ uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
/**
* Returns 1 if currently core is acting as B host, and 0 otherwise.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
/**
* Returns current frame number.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
/**
* Dumps hcd state.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
/**
* Dump the average frame remaining at SOF. This can be used to
* determine average interrupt latency. Frame remaining is also shown for
* start transfer and two additional sample points.
* Currently this function is not implemented.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
/**
* Sends LPM transaction to the local device.
*
* @param hcd The HCD
* @param devaddr Device Address
* @param hird Host initiated resume duration
* @param bRemoteWake Value of bRemoteWake field in LPM transaction
*
* Returns negative value if sending LPM transaction was not succeeded.
* Returns 0 on success.
*/
extern _LONG_CALL_ int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
uint8_t hird, uint8_t bRemoteWake);
/* URB interface */
/**
* Allocates memory for dwc_otg_hcd_urb structure.
* Allocated memory should be freed by call of DWC_FREE.
*
* @param hcd The HCD
* @param iso_desc_count Count of ISOC descriptors
* @param atomic_alloc Specefies whether to perform atomic allocation.
*/
extern _LONG_CALL_ dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
int iso_desc_count,
int atomic_alloc);
/**
* Set pipe information in URB.
*
* @param hcd_urb DWC_OTG URB
* @param devaddr Device Address
* @param ep_num Endpoint Number
* @param ep_type Endpoint Type
* @param ep_dir Endpoint Direction
* @param mps Max Packet Size
*/
extern _LONG_CALL_ void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
uint8_t devaddr, uint8_t ep_num,
uint8_t ep_type, uint8_t ep_dir,
uint16_t mps);
/* Transfer flags */
#define URB_GIVEBACK_ASAP 0x1
#define URB_SEND_ZERO_PACKET 0x2
/**
* Sets dwc_otg_hcd_urb parameters.
*
* @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
* @param urb_handle Unique handle for request, this will be passed back
* to function driver in completion callback.
* @param buf The buffer for the data
* @param dma The DMA buffer for the data
* @param buflen Transfer length
* @param sp Buffer for setup data
* @param sp_dma DMA address of setup data buffer
* @param flags Transfer flags
* @param interval Polling interval for interrupt or isochronous transfers.
*/
extern _LONG_CALL_ void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
void *urb_handle, void *buf,
dwc_dma_t dma, uint32_t buflen, void *sp,
dwc_dma_t sp_dma, uint32_t flags,
uint16_t interval);
/** Gets status from dwc_otg_hcd_urb
*
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
/** Gets actual length from dwc_otg_hcd_urb
*
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
dwc_otg_urb);
/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
*
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
dwc_otg_urb);
/** Set ISOC descriptor offset and length
*
* @param dwc_otg_urb DWC_OTG URB
* @param desc_num ISOC descriptor number
* @param offset Offset from beginig of buffer.
* @param length Transaction length
*/
extern _LONG_CALL_ void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
int desc_num, uint32_t offset,
uint32_t length);
/** Get status of ISOC descriptor, specified by desc_num
*
* @param dwc_otg_urb DWC_OTG URB
* @param desc_num ISOC descriptor number
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
dwc_otg_urb, int desc_num);
/** Get actual length of ISOC descriptor, specified by desc_num
*
* @param dwc_otg_urb DWC_OTG URB
* @param desc_num ISOC descriptor number
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
dwc_otg_urb,
int desc_num);
/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
*
* @param dwc_otg_hcd The HCD
* @param dwc_otg_urb DWC_OTG URB
* @param ep_handle Out parameter for returning endpoint handle
* @param atomic_alloc Flag to do atomic allocation if needed
*
* Returns -DWC_E_NO_DEVICE if no device is connected.
* Returns -DWC_E_NO_MEMORY if there is no enough memory.
* Returns 0 on success.
*/
extern _LONG_CALL_ int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
dwc_otg_hcd_urb_t * dwc_otg_urb,
void **ep_handle, int atomic_alloc);
/** De-queue the specified URB
*
* @param dwc_otg_hcd The HCD
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
dwc_otg_hcd_urb_t * dwc_otg_urb);
/** Frees resources in the DWC_otg controller related to a given endpoint.
* Any URBs for the endpoint must already be dequeued.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
* @param retry Number of retries if there are queued transfers.
*
* Returns -DWC_E_INVALID if invalid arguments are passed.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
int retry);
/* Resets the data toggle in qh structure. This function can be called from
* usb_clear_halt routine.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
*
* Returns -DWC_E_INVALID if invalid arguments are passed.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
/** Returns 1 if status of specified port is changed and 0 otherwise.
*
* @param hcd The HCD
* @param port Port number
*/
extern _LONG_CALL_ int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
/** Call this function to check if bandwidth was allocated for specified endpoint.
* Only for ISOC and INTERRUPT endpoints.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle
*/
extern _LONG_CALL_ int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
void *ep_handle);
/** Call this function to check if bandwidth was freed for specified endpoint.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle
*/
extern _LONG_CALL_ int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
/** Returns bandwidth allocated for specified endpoint in microseconds.
* Only for ISOC and INTERRUPT endpoints.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle
*/
extern _LONG_CALL_ uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
void *ep_handle);
/** @} */
#endif /* __DWC_HCD_IF_H__ */
#endif /* DWC_DEVICE_ONLY */
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
* $Revision: #12 $
* $Date: 2011/10/26 $
* $Change: 1873028 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_DEVICE_ONLY
#ifndef __DWC_HCD_IF_H__
#define __DWC_HCD_IF_H__
#include "dwc_otg_core_if.h"
/** @file
* This file defines DWC_OTG HCD Core API.
*/
struct dwc_otg_hcd;
typedef struct dwc_otg_hcd dwc_otg_hcd_t;
struct dwc_otg_hcd_urb;
typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
/** @name HCD Function Driver Callbacks */
/** @{ */
/** This function is called whenever core switches to host mode. */
typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
/** This function is called when device has been disconnected */
typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
void *urb_handle,
uint32_t * hub_addr,
uint32_t * port_addr);
/** Via this function HCD core gets device speed */
typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
void *urb_handle);
/** This function is called when urb is completed */
typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
void *urb_handle,
dwc_otg_hcd_urb_t * dwc_otg_urb,
int32_t status);
/** Via this function HCD core gets b_hnp_enable parameter */
typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
struct dwc_otg_hcd_function_ops {
dwc_otg_hcd_start_cb_t start;
dwc_otg_hcd_disconnect_cb_t disconnect;
dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
dwc_otg_hcd_speed_from_urb_cb_t speed;
dwc_otg_hcd_complete_urb_cb_t complete;
dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
};
/** @} */
/** @name HCD Core API */
/** @{ */
/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
extern _LONG_CALL_ dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
/** This function should be called to initiate HCD Core.
*
* @param hcd The HCD
* @param core_if The DWC_OTG Core
*
* Returns -DWC_E_NO_MEMORY if no enough memory.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
/** Frees HCD
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
/** This function should be called on every hardware interrupt.
*
* @param dwc_otg_hcd The HCD
*
* Returns non zero if interrupt is handled
* Return 0 if interrupt is not handled
*/
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
/**
* Returns private data set by
* dwc_otg_hcd_set_priv_data function.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
/**
* Set private data.
*
* @param hcd The HCD
* @param priv_data pointer to be stored in private data
*/
extern _LONG_CALL_ void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
/**
* This function initializes the HCD Core.
*
* @param hcd The HCD
* @param fops The Function Driver Operations data structure containing pointers to all callbacks.
*
* Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
struct dwc_otg_hcd_function_ops *fops);
/**
* Halts the DWC_otg host mode operations in a clean manner. USB transfers are
* stopped.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
/**
* Handles hub class-specific requests.
*
* @param dwc_otg_hcd The HCD
* @param typeReq Request Type
* @param wValue wValue from control request
* @param wIndex wIndex from control request
* @param buf data buffer
* @param wLength data buffer length
*
* Returns -DWC_E_INVALID if invalid argument is passed
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
uint16_t typeReq, uint16_t wValue,
uint16_t wIndex, uint8_t * buf,
uint16_t wLength);
/**
* Returns otg port number.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
/**
* Returns OTG version - either 1.3 or 2.0.
*
* @param core_if The core_if structure pointer
*/
extern _LONG_CALL_ uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
/**
* Returns 1 if currently core is acting as B host, and 0 otherwise.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
/**
* Returns current frame number.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
/**
* Dumps hcd state.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
/**
* Dump the average frame remaining at SOF. This can be used to
* determine average interrupt latency. Frame remaining is also shown for
* start transfer and two additional sample points.
* Currently this function is not implemented.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
/**
* Sends LPM transaction to the local device.
*
* @param hcd The HCD
* @param devaddr Device Address
* @param hird Host initiated resume duration
* @param bRemoteWake Value of bRemoteWake field in LPM transaction
*
* Returns negative value if sending LPM transaction was not succeeded.
* Returns 0 on success.
*/
extern _LONG_CALL_ int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
uint8_t hird, uint8_t bRemoteWake);
/* URB interface */
/**
* Allocates memory for dwc_otg_hcd_urb structure.
* Allocated memory should be freed by call of DWC_FREE.
*
* @param hcd The HCD
* @param iso_desc_count Count of ISOC descriptors
* @param atomic_alloc Specefies whether to perform atomic allocation.
*/
extern _LONG_CALL_ dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
int iso_desc_count,
int atomic_alloc);
/**
* Set pipe information in URB.
*
* @param hcd_urb DWC_OTG URB
* @param devaddr Device Address
* @param ep_num Endpoint Number
* @param ep_type Endpoint Type
* @param ep_dir Endpoint Direction
* @param mps Max Packet Size
*/
extern _LONG_CALL_ void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
uint8_t devaddr, uint8_t ep_num,
uint8_t ep_type, uint8_t ep_dir,
uint16_t mps);
/* Transfer flags */
#define URB_GIVEBACK_ASAP 0x1
#define URB_SEND_ZERO_PACKET 0x2
/**
* Sets dwc_otg_hcd_urb parameters.
*
* @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
* @param urb_handle Unique handle for request, this will be passed back
* to function driver in completion callback.
* @param buf The buffer for the data
* @param dma The DMA buffer for the data
* @param buflen Transfer length
* @param sp Buffer for setup data
* @param sp_dma DMA address of setup data buffer
* @param flags Transfer flags
* @param interval Polling interval for interrupt or isochronous transfers.
*/
extern _LONG_CALL_ void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
void *urb_handle, void *buf,
dwc_dma_t dma, uint32_t buflen, void *sp,
dwc_dma_t sp_dma, uint32_t flags,
uint16_t interval);
/** Gets status from dwc_otg_hcd_urb
*
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
/** Gets actual length from dwc_otg_hcd_urb
*
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
dwc_otg_urb);
/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
*
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
dwc_otg_urb);
/** Set ISOC descriptor offset and length
*
* @param dwc_otg_urb DWC_OTG URB
* @param desc_num ISOC descriptor number
* @param offset Offset from beginig of buffer.
* @param length Transaction length
*/
extern _LONG_CALL_ void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
int desc_num, uint32_t offset,
uint32_t length);
/** Get status of ISOC descriptor, specified by desc_num
*
* @param dwc_otg_urb DWC_OTG URB
* @param desc_num ISOC descriptor number
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
dwc_otg_urb, int desc_num);
/** Get actual length of ISOC descriptor, specified by desc_num
*
* @param dwc_otg_urb DWC_OTG URB
* @param desc_num ISOC descriptor number
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
dwc_otg_urb,
int desc_num);
/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
*
* @param dwc_otg_hcd The HCD
* @param dwc_otg_urb DWC_OTG URB
* @param ep_handle Out parameter for returning endpoint handle
* @param atomic_alloc Flag to do atomic allocation if needed
*
* Returns -DWC_E_NO_DEVICE if no device is connected.
* Returns -DWC_E_NO_MEMORY if there is no enough memory.
* Returns 0 on success.
*/
extern _LONG_CALL_ int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
dwc_otg_hcd_urb_t * dwc_otg_urb,
void **ep_handle, int atomic_alloc);
/** De-queue the specified URB
*
* @param dwc_otg_hcd The HCD
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
dwc_otg_hcd_urb_t * dwc_otg_urb);
/** Frees resources in the DWC_otg controller related to a given endpoint.
* Any URBs for the endpoint must already be dequeued.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
* @param retry Number of retries if there are queued transfers.
*
* Returns -DWC_E_INVALID if invalid arguments are passed.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
int retry);
/* Resets the data toggle in qh structure. This function can be called from
* usb_clear_halt routine.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
*
* Returns -DWC_E_INVALID if invalid arguments are passed.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
/** Returns 1 if status of specified port is changed and 0 otherwise.
*
* @param hcd The HCD
* @param port Port number
*/
extern _LONG_CALL_ int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
/** Call this function to check if bandwidth was allocated for specified endpoint.
* Only for ISOC and INTERRUPT endpoints.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle
*/
extern _LONG_CALL_ int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
void *ep_handle);
/** Call this function to check if bandwidth was freed for specified endpoint.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle
*/
extern _LONG_CALL_ int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
/** Returns bandwidth allocated for specified endpoint in microseconds.
* Only for ISOC and INTERRUPT endpoints.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle
*/
extern _LONG_CALL_ uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
void *ep_handle);
/** @} */
#endif /* __DWC_HCD_IF_H__ */
#endif /* DWC_DEVICE_ONLY */

10
component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_otg_os_dep.h
View file

@ -1,5 +1,5 @@
#ifndef _DWC_OS_DEP_H_
#define _DWC_OS_DEP_H_
#include "errno.h"
#endif /* _DWC_OS_DEP_H_ */
#ifndef _DWC_OS_DEP_H_
#define _DWC_OS_DEP_H_
#include "errno.h"
#endif /* _DWC_OS_DEP_H_ */

542
component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_otg_pcd.h
View file

@ -1,271 +1,271 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
* $Revision: #49 $
* $Date: 2013/05/16 $
* $Change: 2231774 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_HOST_ONLY
#if !defined(__DWC_PCD_H__)
#define __DWC_PCD_H__
#include "dwc_otg_os_dep.h"
#include "usb.h"
#include "dwc_otg_cil.h"
#include "dwc_otg_pcd_if.h"
struct cfiobject;
/**
* @file
*
* This file contains the structures, constants, and interfaces for
* the Perpherial Contoller Driver (PCD).
*
* The Peripheral Controller Driver (PCD) for Linux will implement the
* Gadget API, so that the existing Gadget drivers can be used. For
* the Mass Storage Function driver the File-backed USB Storage Gadget
* (FBS) driver will be used. The FBS driver supports the
* Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
* transports.
*
*/
/** Invalid DMA Address */
#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0)
/** Max Transfer size for any EP */
#define DDMA_MAX_TRANSFER_SIZE 65535
/**
* Get the pointer to the core_if from the pcd pointer.
*/
#define GET_CORE_IF( _pcd ) (_pcd->core_if)
/**
* States of EP0.
*/
typedef enum ep0_state {
EP0_DISCONNECT, /* no host */
EP0_IDLE,
EP0_IN_DATA_PHASE,
EP0_OUT_DATA_PHASE,
EP0_IN_STATUS_PHASE,
EP0_OUT_STATUS_PHASE,
EP0_STALL,
} ep0state_e;
/** Fordward declaration.*/
struct dwc_otg_pcd;
/** DWC_otg iso request structure.
*
*/
typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
#ifdef DWC_UTE_PER_IO
XXX
/**
* This shall be the exact analogy of the same type structure defined in the
* usb_gadget.h. Each descriptor contains
*/
struct dwc_iso_pkt_desc_port {
uint32_t offset;
uint32_t length; /* expected length */
uint32_t actual_length;
uint32_t status;
};
struct dwc_iso_xreq_port {
/** transfer/submission flag */
uint32_t tr_sub_flags;
/** Start the request ASAP */
#define DWC_EREQ_TF_ASAP 0x00000002
/** Just enqueue the request w/o initiating a transfer */
#define DWC_EREQ_TF_ENQUEUE 0x00000004
/**
* count of ISO packets attached to this request - shall
* not exceed the pio_alloc_pkt_count
*/
uint32_t pio_pkt_count;
/** count of ISO packets allocated for this request */
uint32_t pio_alloc_pkt_count;
/** number of ISO packet errors */
uint32_t error_count;
/** reserved for future extension */
uint32_t res;
/** Will be allocated and freed in the UTE gadget and based on the CFC value */
struct dwc_iso_pkt_desc_port *per_io_frame_descs;
};
#endif
/** DWC_otg request structure.
* This structure is a list of requests.
*/
typedef struct dwc_otg_pcd_request {
void *priv;
void *buf;
dwc_dma_t dma;
uint32_t length;
uint32_t actual;
unsigned sent_zlp:1;
/**
* Used instead of original buffer if
* it(physical address) is not dword-aligned.
**/
uint8_t *dw_align_buf;
dwc_dma_t dw_align_buf_dma;
DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
#ifdef DWC_UTE_PER_IO
struct dwc_iso_xreq_port ext_req;
//void *priv_ereq_nport; /* */
#endif
} dwc_otg_pcd_request_t;
DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
/** PCD EP structure.
* This structure describes an EP, there is an array of EPs in the PCD
* structure.
*/
typedef struct dwc_otg_pcd_ep {
/** USB EP Descriptor */
const usb_endpoint_descriptor_t *desc;
/** queue of dwc_otg_pcd_requests. */
struct req_list queue;
unsigned stopped:1;
unsigned disabling:1;
unsigned dma:1;
unsigned queue_sof:1;
#ifdef DWC_EN_ISOC
/** ISOC req handle passed */
void *iso_req_handle;
#endif //_EN_ISOC_
/** DWC_otg ep data. */
dwc_ep_t dwc_ep;
/** Pointer to PCD */
struct dwc_otg_pcd *pcd;
void *priv;
} dwc_otg_pcd_ep_t;
/** DWC_otg PCD Structure.
* This structure encapsulates the data for the dwc_otg PCD.
*/
struct dwc_otg_pcd {
const struct dwc_otg_pcd_function_ops *fops;
/** The DWC otg device pointer */
struct dwc_otg_device *otg_dev;
/** Core Interface */
dwc_otg_core_if_t *core_if;
/** State of EP0 */
ep0state_e ep0state;
/** EP0 Request is pending */
unsigned ep0_pending:1;
/** Indicates when SET CONFIGURATION Request is in process */
unsigned request_config:1;
/** The state of the Remote Wakeup Enable. */
unsigned remote_wakeup_enable:1;
/** The state of the B-Device HNP Enable. */
unsigned b_hnp_enable:1;
/** The state of A-Device HNP Support. */
unsigned a_hnp_support:1;
/** The state of the A-Device Alt HNP support. */
unsigned a_alt_hnp_support:1;
/** Count of pending Requests */
unsigned request_pending;
/** SETUP packet for EP0
* This structure is allocated as a DMA buffer on PCD initialization
* with enough space for up to 3 setup packets.
*/
union {
usb_device_request_t req;
uint32_t d32[2];
} *setup_pkt;
dwc_dma_t setup_pkt_dma_handle;
/* Additional buffer and flag for CTRL_WR premature case */
uint8_t *backup_buf;
unsigned data_terminated;
/** 2-byte dma buffer used to return status from GET_STATUS */
uint16_t *status_buf;
dwc_dma_t status_buf_dma_handle;
/** EP0 */
dwc_otg_pcd_ep_t ep0;
/** Array of IN EPs. */
dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
/** Array of OUT EPs. */
dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
/** number of valid EPs in the above array. */
// unsigned num_eps : 4;
dwc_spinlock_t *lock;
/** Tasklet to defer starting of TEST mode transmissions until
* Status Phase has been completed.
*/
dwc_tasklet_t *test_mode_tasklet;
/** Tasklet to delay starting of xfer in DMA mode */
dwc_tasklet_t *start_xfer_tasklet;
/** The test mode to enter when the tasklet is executed. */
unsigned test_mode;
/** The cfi_api structure that implements most of the CFI API
* and OTG specific core configuration functionality
*/
#ifdef DWC_UTE_CFI
struct cfiobject *cfi;
#endif
};
//FIXME this functions should be static, and this prototypes should be removed
extern _LONG_CALL_ void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
extern _LONG_CALL_ void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
dwc_otg_pcd_request_t * req, int32_t status);
_LONG_CALL_ void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
void *req_handle);
extern _LONG_CALL_ void dwc_otg_pcd_start_iso_ddma(dwc_otg_core_if_t * core_if,
dwc_otg_pcd_ep_t * ep);
extern _LONG_CALL_ void do_test_mode(void *data);
extern _LONG_CALL_ void dwc_pcd_data_init(VOID);
#endif
#endif /* DWC_HOST_ONLY */
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
* $Revision: #49 $
* $Date: 2013/05/16 $
* $Change: 2231774 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_HOST_ONLY
#if !defined(__DWC_PCD_H__)
#define __DWC_PCD_H__
#include "dwc_otg_os_dep.h"
#include "usb.h"
#include "dwc_otg_cil.h"
#include "dwc_otg_pcd_if.h"
struct cfiobject;
/**
* @file
*
* This file contains the structures, constants, and interfaces for
* the Perpherial Contoller Driver (PCD).
*
* The Peripheral Controller Driver (PCD) for Linux will implement the
* Gadget API, so that the existing Gadget drivers can be used. For
* the Mass Storage Function driver the File-backed USB Storage Gadget
* (FBS) driver will be used. The FBS driver supports the
* Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
* transports.
*
*/
/** Invalid DMA Address */
#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0)
/** Max Transfer size for any EP */
#define DDMA_MAX_TRANSFER_SIZE 65535
/**
* Get the pointer to the core_if from the pcd pointer.
*/
#define GET_CORE_IF( _pcd ) (_pcd->core_if)
/**
* States of EP0.
*/
typedef enum ep0_state {
EP0_DISCONNECT, /* no host */
EP0_IDLE,
EP0_IN_DATA_PHASE,
EP0_OUT_DATA_PHASE,
EP0_IN_STATUS_PHASE,
EP0_OUT_STATUS_PHASE,
EP0_STALL,
} ep0state_e;
/** Fordward declaration.*/
struct dwc_otg_pcd;
/** DWC_otg iso request structure.
*
*/
typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
#ifdef DWC_UTE_PER_IO
XXX
/**
* This shall be the exact analogy of the same type structure defined in the
* usb_gadget.h. Each descriptor contains
*/
struct dwc_iso_pkt_desc_port {
uint32_t offset;
uint32_t length; /* expected length */
uint32_t actual_length;
uint32_t status;
};
struct dwc_iso_xreq_port {
/** transfer/submission flag */
uint32_t tr_sub_flags;
/** Start the request ASAP */
#define DWC_EREQ_TF_ASAP 0x00000002
/** Just enqueue the request w/o initiating a transfer */
#define DWC_EREQ_TF_ENQUEUE 0x00000004
/**
* count of ISO packets attached to this request - shall
* not exceed the pio_alloc_pkt_count
*/
uint32_t pio_pkt_count;
/** count of ISO packets allocated for this request */
uint32_t pio_alloc_pkt_count;
/** number of ISO packet errors */
uint32_t error_count;
/** reserved for future extension */
uint32_t res;
/** Will be allocated and freed in the UTE gadget and based on the CFC value */
struct dwc_iso_pkt_desc_port *per_io_frame_descs;
};
#endif
/** DWC_otg request structure.
* This structure is a list of requests.
*/
typedef struct dwc_otg_pcd_request {
void *priv;
void *buf;
dwc_dma_t dma;
uint32_t length;
uint32_t actual;
unsigned sent_zlp:1;
/**
* Used instead of original buffer if
* it(physical address) is not dword-aligned.
**/
uint8_t *dw_align_buf;
dwc_dma_t dw_align_buf_dma;
DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
#ifdef DWC_UTE_PER_IO
struct dwc_iso_xreq_port ext_req;
//void *priv_ereq_nport; /* */
#endif
} dwc_otg_pcd_request_t;
DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
/** PCD EP structure.
* This structure describes an EP, there is an array of EPs in the PCD
* structure.
*/
typedef struct dwc_otg_pcd_ep {
/** USB EP Descriptor */
const usb_endpoint_descriptor_t *desc;
/** queue of dwc_otg_pcd_requests. */
struct req_list queue;
unsigned stopped:1;
unsigned disabling:1;
unsigned dma:1;
unsigned queue_sof:1;
#ifdef DWC_EN_ISOC
/** ISOC req handle passed */
void *iso_req_handle;
#endif //_EN_ISOC_
/** DWC_otg ep data. */
dwc_ep_t dwc_ep;
/** Pointer to PCD */
struct dwc_otg_pcd *pcd;
void *priv;
} dwc_otg_pcd_ep_t;
/** DWC_otg PCD Structure.
* This structure encapsulates the data for the dwc_otg PCD.
*/
struct dwc_otg_pcd {
const struct dwc_otg_pcd_function_ops *fops;
/** The DWC otg device pointer */
struct dwc_otg_device *otg_dev;
/** Core Interface */
dwc_otg_core_if_t *core_if;
/** State of EP0 */
ep0state_e ep0state;
/** EP0 Request is pending */
unsigned ep0_pending:1;
/** Indicates when SET CONFIGURATION Request is in process */
unsigned request_config:1;
/** The state of the Remote Wakeup Enable. */
unsigned remote_wakeup_enable:1;
/** The state of the B-Device HNP Enable. */
unsigned b_hnp_enable:1;
/** The state of A-Device HNP Support. */
unsigned a_hnp_support:1;
/** The state of the A-Device Alt HNP support. */
unsigned a_alt_hnp_support:1;
/** Count of pending Requests */
unsigned request_pending;
/** SETUP packet for EP0
* This structure is allocated as a DMA buffer on PCD initialization
* with enough space for up to 3 setup packets.
*/
union {
usb_device_request_t req;
uint32_t d32[2];
} *setup_pkt;
dwc_dma_t setup_pkt_dma_handle;
/* Additional buffer and flag for CTRL_WR premature case */
uint8_t *backup_buf;
unsigned data_terminated;
/** 2-byte dma buffer used to return status from GET_STATUS */
uint16_t *status_buf;
dwc_dma_t status_buf_dma_handle;
/** EP0 */
dwc_otg_pcd_ep_t ep0;
/** Array of IN EPs. */
dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
/** Array of OUT EPs. */
dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
/** number of valid EPs in the above array. */
// unsigned num_eps : 4;
dwc_spinlock_t *lock;
/** Tasklet to defer starting of TEST mode transmissions until
* Status Phase has been completed.
*/
dwc_tasklet_t *test_mode_tasklet;
/** Tasklet to delay starting of xfer in DMA mode */
dwc_tasklet_t *start_xfer_tasklet;
/** The test mode to enter when the tasklet is executed. */
unsigned test_mode;
/** The cfi_api structure that implements most of the CFI API
* and OTG specific core configuration functionality
*/
#ifdef DWC_UTE_CFI
struct cfiobject *cfi;
#endif
};
//FIXME this functions should be static, and this prototypes should be removed
extern _LONG_CALL_ void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
extern _LONG_CALL_ void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
dwc_otg_pcd_request_t * req, int32_t status);
_LONG_CALL_ void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
void *req_handle);
extern _LONG_CALL_ void dwc_otg_pcd_start_iso_ddma(dwc_otg_core_if_t * core_if,
dwc_otg_pcd_ep_t * ep);
extern _LONG_CALL_ void do_test_mode(void *data);
extern _LONG_CALL_ void dwc_pcd_data_init(VOID);
#endif
#endif /* DWC_HOST_ONLY */

734
component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_otg_pcd_if.h
View file

@ -1,367 +1,367 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
* $Revision: #13 $
* $Date: 2012/12/12 $
* $Change: 2125019 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_HOST_ONLY
#if !defined(__DWC_PCD_IF_H__)
#define __DWC_PCD_IF_H__
//#include "dwc_os.h"
#include "dwc_otg_core_if.h"
/** @file
* This file defines DWC_OTG PCD Core API.
*/
struct dwc_otg_pcd;
typedef struct dwc_otg_pcd dwc_otg_pcd_t;
/** Maxpacket size for EP0 */
#define MAX_EP0_SIZE 64
/** Maxpacket size for any EP */
#define MAX_PACKET_SIZE 2048
/** @name Function Driver Callbacks */
/** @{ */
/** This function will be called whenever a previously queued request has
* completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a
* failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
* or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
* parameters. */
typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int32_t status,
uint32_t actual);
/**
* This function will be called whenever a previousle queued ISOC request has
* completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
* function.
* The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
* functions.
*/
typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int proc_buf_num);
/** This function should handle any SETUP request that cannot be handled by the
* PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
* class-specific requests, etc. The function must non-blocking.
*
* Returns 0 on success.
* Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
* Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
* Returns -DWC_E_SHUTDOWN on any other error. */
typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
/** This is called whenever the device has been disconnected. The function
* driver should take appropriate action to clean up all pending requests in the
* PCD Core, remove all endpoints (except ep0), and initialize back to reset
* state. */
typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called when device has been connected. */
typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
/** This function is called when device has been suspended */
typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called when device has received LPM tokens, i.e.
* device has been sent to sleep state. */
typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called when device has been resumed
* from suspend(L2) or L1 sleep state. */
typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called whenever hnp params has been changed.
* User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
* to get hnp parameters. */
typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called whenever USB RESET is detected. */
typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
/**
*
* @param ep_handle Void pointer to the usb_ep structure
* @param ereq_port Pointer to the extended request structure created in the
* portable part.
*/
typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int32_t status,
void *ereq_port);
/** Function Driver Ops Data Structure */
struct dwc_otg_pcd_function_ops {
dwc_connect_cb_t connect;
dwc_disconnect_cb_t disconnect;
dwc_setup_cb_t setup;
dwc_completion_cb_t complete;
dwc_isoc_completion_cb_t isoc_complete;
dwc_suspend_cb_t suspend;
dwc_sleep_cb_t sleep;
dwc_resume_cb_t resume;
dwc_reset_cb_t reset;
dwc_hnp_params_changed_cb_t hnp_changed;
cfi_setup_cb_t cfi_setup;
#ifdef DWC_UTE_PER_IO
xiso_completion_cb_t xisoc_complete;
#endif
};
/** @} */
/** @name Function Driver Functions */
/** @{ */
/** Call this function to get pointer on dwc_otg_pcd_t,
* this pointer will be used for all PCD API functions.
*
* @param core_if The DWC_OTG Core
*/
extern _LONG_CALL_ dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
/** Frees PCD allocated by dwc_otg_pcd_init
*
* @param pcd The PCD
*/
extern _LONG_CALL_ void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
/** Call this to bind the function driver to the PCD Core.
*
* @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
* @param fops The Function Driver Ops data structure containing pointers to all callbacks.
*/
extern _LONG_CALL_ void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
const struct dwc_otg_pcd_function_ops *fops);
/** Enables an endpoint for use. This function enables an endpoint in
* the PCD. The endpoint is described by the ep_desc which has the
* same format as a USB ep descriptor. The ep_handle parameter is used to refer
* to the endpoint from other API functions and in callbacks. Normally this
* should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
* core for that interface.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns 0 on success.
*
* @param pcd The PCD
* @param ep_desc Endpoint descriptor
* @param ep_handle Handle on endpoint, that will be used to identify endpoint.
*/
extern _LONG_CALL_ int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
const uint8_t * ep_desc, void *ep_handle);
/** Disable the endpoint referenced by ep_handle.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error occurred.
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
/** Queue a data transfer request on the endpoint referenced by ep_handle.
* After the transfer is completes, the complete callback will be called with
* the request status.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param buf The buffer for the data
* @param dma_buf The DMA buffer for the data
* @param buflen The length of the data transfer
* @param zero Specifies whether to send zero length last packet.
* @param req_handle Set this handle to any value to use to reference this
* request in the ep_dequeue function or from the complete callback
* @param atomic_alloc If driver need to perform atomic allocations
* for internal data structures.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf, dwc_dma_t dma_buf,
uint32_t buflen, int zero, void *req_handle,
int atomic_alloc);
#ifdef DWC_UTE_PER_IO
XXXX
/**
*
* @param ereq_nonport Pointer to the extended request part of the
* usb_request structure defined in usb_gadget.h file.
*/
extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf, dwc_dma_t dma_buf,
uint32_t buflen, int zero,
void *req_handle, int atomic_alloc,
void *ereq_nonport);
#endif
/** De-queue the specified data transfer that has not yet completed.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle);
/** Halt (STALL) an endpoint or clear it.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
/** This function should be called on every hardware interrupt */
extern _LONG_CALL_ int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
/** This function returns current frame number */
extern _LONG_CALL_ int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
/**
* Start isochronous transfers on the endpoint referenced by ep_handle.
* For isochronous transfers duble buffering is used.
* After processing each of buffers comlete callback will be called with
* status for each transaction.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param buf0 The virtual address of first data buffer
* @param buf1 The virtual address of second data buffer
* @param dma0 The DMA address of first data buffer
* @param dma1 The DMA address of second data buffer
* @param sync_frame Data pattern frame number
* @param dp_frame Data size for pattern frame
* @param data_per_frame Data size for regular frame
* @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
* @param buf_proc_intrvl Interval of ISOC Buffer processing
* @param req_handle Handle of ISOC request
* @param atomic_alloc Specefies whether to perform atomic allocation for
* internal data structures.
*
* Returns -DWC_E_NO_MEMORY if there is no enough memory.
* Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
* Returns -DW_E_SHUTDOWN for any other error.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf0, uint8_t * buf1,
dwc_dma_t dma0, dwc_dma_t dma1,
int sync_frame, int dp_frame,
int data_per_frame, int start_frame,
int buf_proc_intrvl, void *req_handle,
int atomic_alloc);
/** Stop ISOC transfers on endpoint referenced by ep_handle.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param req_handle Handle of ISOC request
*
* Returns -DWC_E_INVALID if incorrect arguments are passed to the function
* Returns 0 on success
*/
_LONG_CALL_ int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle);
/** Get ISOC packet status.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param iso_req_handle Isochronoush request handle
* @param packet Number of packet
* @param status Out parameter for returning status
* @param actual Out parameter for returning actual length
* @param offset Out parameter for returning offset
*
*/
extern _LONG_CALL_ void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
void *ep_handle,
void *iso_req_handle, int packet,
int *status, int *actual,
int *offset);
/** Get ISOC packet count.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param iso_req_handle
*/
extern _LONG_CALL_ int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
void *ep_handle,
void *iso_req_handle);
/** This function starts the SRP Protocol if no session is in progress. If
* a session is already in progress, but the device is suspended,
* remote wakeup signaling is started.
*/
extern _LONG_CALL_ int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
extern _LONG_CALL_ int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
/** This function returns 1 if LPM Errata support is enabled, and 0 otherwise. */
extern _LONG_CALL_ int dwc_otg_pcd_is_besl_enabled(dwc_otg_pcd_t * pcd);
/** This function returns baseline_besl module parametr. */
extern _LONG_CALL_ int dwc_otg_pcd_get_param_baseline_besl(dwc_otg_pcd_t * pcd);
/** This function returns deep_besl module parametr. */
extern _LONG_CALL_ int dwc_otg_pcd_get_param_deep_besl(dwc_otg_pcd_t * pcd);
/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
extern _LONG_CALL_ int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
/** Initiate SRP */
extern _LONG_CALL_ void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
/** Starts remote wakeup signaling. */
extern _LONG_CALL_ void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
/** Starts micorsecond soft disconnect. */
extern _LONG_CALL_ void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
/** This function returns whether device is dualspeed.*/
extern _LONG_CALL_ uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
/** This function returns whether device is otg. */
extern _LONG_CALL_ uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
/** These functions allow to get hnp parameters */
extern _LONG_CALL_ uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
extern _LONG_CALL_ uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
extern _LONG_CALL_ uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
/** CFI specific Interface functions */
/** Allocate a cfi buffer */
extern _LONG_CALL_ uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
dwc_dma_t * addr, size_t buflen,
int flags);
/******************************************************************************/
/** @} */
#endif /* __DWC_PCD_IF_H__ */
#endif /* DWC_HOST_ONLY */
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
* $Revision: #13 $
* $Date: 2012/12/12 $
* $Change: 2125019 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_HOST_ONLY
#if !defined(__DWC_PCD_IF_H__)
#define __DWC_PCD_IF_H__
//#include "dwc_os.h"
#include "dwc_otg_core_if.h"
/** @file
* This file defines DWC_OTG PCD Core API.
*/
struct dwc_otg_pcd;
typedef struct dwc_otg_pcd dwc_otg_pcd_t;
/** Maxpacket size for EP0 */
#define MAX_EP0_SIZE 64
/** Maxpacket size for any EP */
#define MAX_PACKET_SIZE 2048
/** @name Function Driver Callbacks */
/** @{ */
/** This function will be called whenever a previously queued request has
* completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a
* failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
* or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
* parameters. */
typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int32_t status,
uint32_t actual);
/**
* This function will be called whenever a previousle queued ISOC request has
* completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
* function.
* The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
* functions.
*/
typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int proc_buf_num);
/** This function should handle any SETUP request that cannot be handled by the
* PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
* class-specific requests, etc. The function must non-blocking.
*
* Returns 0 on success.
* Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
* Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
* Returns -DWC_E_SHUTDOWN on any other error. */
typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
/** This is called whenever the device has been disconnected. The function
* driver should take appropriate action to clean up all pending requests in the
* PCD Core, remove all endpoints (except ep0), and initialize back to reset
* state. */
typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called when device has been connected. */
typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
/** This function is called when device has been suspended */
typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called when device has received LPM tokens, i.e.
* device has been sent to sleep state. */
typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called when device has been resumed
* from suspend(L2) or L1 sleep state. */
typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called whenever hnp params has been changed.
* User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
* to get hnp parameters. */
typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called whenever USB RESET is detected. */
typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
/**
*
* @param ep_handle Void pointer to the usb_ep structure
* @param ereq_port Pointer to the extended request structure created in the
* portable part.
*/
typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int32_t status,
void *ereq_port);
/** Function Driver Ops Data Structure */
struct dwc_otg_pcd_function_ops {
dwc_connect_cb_t connect;
dwc_disconnect_cb_t disconnect;
dwc_setup_cb_t setup;
dwc_completion_cb_t complete;
dwc_isoc_completion_cb_t isoc_complete;
dwc_suspend_cb_t suspend;
dwc_sleep_cb_t sleep;
dwc_resume_cb_t resume;
dwc_reset_cb_t reset;
dwc_hnp_params_changed_cb_t hnp_changed;
cfi_setup_cb_t cfi_setup;
#ifdef DWC_UTE_PER_IO
xiso_completion_cb_t xisoc_complete;
#endif
};
/** @} */
/** @name Function Driver Functions */
/** @{ */
/** Call this function to get pointer on dwc_otg_pcd_t,
* this pointer will be used for all PCD API functions.
*
* @param core_if The DWC_OTG Core
*/
extern _LONG_CALL_ dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
/** Frees PCD allocated by dwc_otg_pcd_init
*
* @param pcd The PCD
*/
extern _LONG_CALL_ void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
/** Call this to bind the function driver to the PCD Core.
*
* @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
* @param fops The Function Driver Ops data structure containing pointers to all callbacks.
*/
extern _LONG_CALL_ void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
const struct dwc_otg_pcd_function_ops *fops);
/** Enables an endpoint for use. This function enables an endpoint in
* the PCD. The endpoint is described by the ep_desc which has the
* same format as a USB ep descriptor. The ep_handle parameter is used to refer
* to the endpoint from other API functions and in callbacks. Normally this
* should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
* core for that interface.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns 0 on success.
*
* @param pcd The PCD
* @param ep_desc Endpoint descriptor
* @param ep_handle Handle on endpoint, that will be used to identify endpoint.
*/
extern _LONG_CALL_ int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
const uint8_t * ep_desc, void *ep_handle);
/** Disable the endpoint referenced by ep_handle.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error occurred.
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
/** Queue a data transfer request on the endpoint referenced by ep_handle.
* After the transfer is completes, the complete callback will be called with
* the request status.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param buf The buffer for the data
* @param dma_buf The DMA buffer for the data
* @param buflen The length of the data transfer
* @param zero Specifies whether to send zero length last packet.
* @param req_handle Set this handle to any value to use to reference this
* request in the ep_dequeue function or from the complete callback
* @param atomic_alloc If driver need to perform atomic allocations
* for internal data structures.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf, dwc_dma_t dma_buf,
uint32_t buflen, int zero, void *req_handle,
int atomic_alloc);
#ifdef DWC_UTE_PER_IO
XXXX
/**
*
* @param ereq_nonport Pointer to the extended request part of the
* usb_request structure defined in usb_gadget.h file.
*/
extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf, dwc_dma_t dma_buf,
uint32_t buflen, int zero,
void *req_handle, int atomic_alloc,
void *ereq_nonport);
#endif
/** De-queue the specified data transfer that has not yet completed.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle);
/** Halt (STALL) an endpoint or clear it.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
/** This function should be called on every hardware interrupt */
extern _LONG_CALL_ int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
/** This function returns current frame number */
extern _LONG_CALL_ int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
/**
* Start isochronous transfers on the endpoint referenced by ep_handle.
* For isochronous transfers duble buffering is used.
* After processing each of buffers comlete callback will be called with
* status for each transaction.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param buf0 The virtual address of first data buffer
* @param buf1 The virtual address of second data buffer
* @param dma0 The DMA address of first data buffer
* @param dma1 The DMA address of second data buffer
* @param sync_frame Data pattern frame number
* @param dp_frame Data size for pattern frame
* @param data_per_frame Data size for regular frame
* @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
* @param buf_proc_intrvl Interval of ISOC Buffer processing
* @param req_handle Handle of ISOC request
* @param atomic_alloc Specefies whether to perform atomic allocation for
* internal data structures.
*
* Returns -DWC_E_NO_MEMORY if there is no enough memory.
* Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
* Returns -DW_E_SHUTDOWN for any other error.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf0, uint8_t * buf1,
dwc_dma_t dma0, dwc_dma_t dma1,
int sync_frame, int dp_frame,
int data_per_frame, int start_frame,
int buf_proc_intrvl, void *req_handle,
int atomic_alloc);
/** Stop ISOC transfers on endpoint referenced by ep_handle.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param req_handle Handle of ISOC request
*
* Returns -DWC_E_INVALID if incorrect arguments are passed to the function
* Returns 0 on success
*/
_LONG_CALL_ int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle);
/** Get ISOC packet status.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param iso_req_handle Isochronoush request handle
* @param packet Number of packet
* @param status Out parameter for returning status
* @param actual Out parameter for returning actual length
* @param offset Out parameter for returning offset
*
*/
extern _LONG_CALL_ void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
void *ep_handle,
void *iso_req_handle, int packet,
int *status, int *actual,
int *offset);
/** Get ISOC packet count.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param iso_req_handle
*/
extern _LONG_CALL_ int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
void *ep_handle,
void *iso_req_handle);
/** This function starts the SRP Protocol if no session is in progress. If
* a session is already in progress, but the device is suspended,
* remote wakeup signaling is started.
*/
extern _LONG_CALL_ int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
extern _LONG_CALL_ int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
/** This function returns 1 if LPM Errata support is enabled, and 0 otherwise. */
extern _LONG_CALL_ int dwc_otg_pcd_is_besl_enabled(dwc_otg_pcd_t * pcd);
/** This function returns baseline_besl module parametr. */
extern _LONG_CALL_ int dwc_otg_pcd_get_param_baseline_besl(dwc_otg_pcd_t * pcd);
/** This function returns deep_besl module parametr. */
extern _LONG_CALL_ int dwc_otg_pcd_get_param_deep_besl(dwc_otg_pcd_t * pcd);
/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
extern _LONG_CALL_ int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
/** Initiate SRP */
extern _LONG_CALL_ void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
/** Starts remote wakeup signaling. */
extern _LONG_CALL_ void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
/** Starts micorsecond soft disconnect. */
extern _LONG_CALL_ void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
/** This function returns whether device is dualspeed.*/
extern _LONG_CALL_ uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
/** This function returns whether device is otg. */
extern _LONG_CALL_ uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
/** These functions allow to get hnp parameters */
extern _LONG_CALL_ uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
extern _LONG_CALL_ uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
extern _LONG_CALL_ uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
/** CFI specific Interface functions */
/** Allocate a cfi buffer */
extern _LONG_CALL_ uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
dwc_dma_t * addr, size_t buflen,
int flags);
/******************************************************************************/
/** @} */
#endif /* __DWC_PCD_IF_H__ */
#endif /* DWC_HOST_ONLY */

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component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_otg_regs.h
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component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/errno.h
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@ -1,149 +1,149 @@
#ifndef _GENERIC_ERRNO_H
#define _GENERIC_ERRNO_H
#define EPERM 1 /* Operation not permitted */
#define ENOENT 2 /* No such file or directory */
#define ESRCH 3 /* No such process */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define E2BIG 7 /* Argument list too long */
#define ENOEXEC 8 /* Exec format error */
#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define ENOTBLK 15 /* Block device required */
#define EBUSY 16 /* Device or resource busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENFILE 23 /* File table overflow */
#define EMFILE 24 /* Too many open files */
#define ENOTTY 25 /* Not a typewriter */
#define ETXTBSY 26 /* Text file busy */
#define EFBIG 27 /* File too large */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read-only file system */
#define EMLINK 31 /* Too many links */
#define EPIPE 32 /* Broken pipe */
#define EDOM 33 /* Math argument out of domain of func */
#define ERANGE 34 /* Math result not representable */
#define EDEADLK 35 /* Resource deadlock would occur */
#define ENAMETOOLONG 36 /* File name too long */
#define ENOLCK 37 /* No record locks available */
#define ENOSYS 38 /* Function not implemented */
#define ENOTEMPTY 39 /* Directory not empty */
#define ELOOP 40 /* Too many symbolic links encountered */
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define ENOMSG 42 /* No message of desired type */
#define EIDRM 43 /* Identifier removed */
#define ECHRNG 44 /* Channel number out of range */
#define EL2NSYNC 45 /* Level 2 not synchronized */
#define EL3HLT 46 /* Level 3 halted */
#define EL3RST 47 /* Level 3 reset */
#define ELNRNG 48 /* Link number out of range */
#define EUNATCH 49 /* Protocol driver not attached */
#define ENOCSI 50 /* No CSI structure available */
#define EL2HLT 51 /* Level 2 halted */
#define EBADE 52 /* Invalid exchange */
#define EBADR 53 /* Invalid request descriptor */
#define EXFULL 54 /* Exchange full */
#define ENOANO 55 /* No anode */
#define EBADRQC 56 /* Invalid request code */
#define EBADSLT 57 /* Invalid slot */
#define EDEADLOCK EDEADLK
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define ETIME 62 /* Timer expired */
#define ENOSR 63 /* Out of streams resources */
#define ENONET 64 /* Machine is not on the network */
#define ENOPKG 65 /* Package not installed */
#define EREMOTE 66 /* Object is remote */
#define ENOLINK 67 /* Link has been severed */
#define EADV 68 /* Advertise error */
#define ESRMNT 69 /* Srmount error */
#define ECOMM 70 /* Communication error on send */
#define EPROTO 71 /* Protocol error */
#define EMULTIHOP 72 /* Multihop attempted */
#define EDOTDOT 73 /* RFS specific error */
#define EBADMSG 74 /* Not a data message */
#define EOVERFLOW 75 /* Value too large for defined data type */
#define ENOTUNIQ 76 /* Name not unique on network */
#define EBADFD 77 /* File descriptor in bad state */
#define EREMCHG 78 /* Remote address changed */
#define ELIBACC 79 /* Can not access a needed shared library */
#define ELIBBAD 80 /* Accessing a corrupted shared library */
#define ELIBSCN 81 /* .lib section in a.out corrupted */
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
#define EILSEQ 84 /* Illegal byte sequence */
#define ERESTART 85 /* Interrupted system call should be restarted */
#define ESTRPIPE 86 /* Streams pipe error */
#define EUSERS 87 /* Too many users */
#define ENOTSOCK 88 /* Socket operation on non-socket */
#define EDESTADDRREQ 89 /* Destination address required */
#define EMSGSIZE 90 /* Message too long */
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
#define ENOPROTOOPT 92 /* Protocol not available */
#define EPROTONOSUPPORT 93 /* Protocol not supported */
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
#define EPFNOSUPPORT 96 /* Protocol family not supported */
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
#define EADDRINUSE 98 /* Address already in use */
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
#define ENETDOWN 100 /* Network is down */
#define ENETUNREACH 101 /* Network is unreachable */
#define ENETRESET 102 /* Network dropped connection because of reset */
#define ECONNABORTED 103 /* Software caused connection abort */
#define ECONNRESET 104 /* Connection reset by peer */
#define ENOBUFS 105 /* No buffer space available */
#define EISCONN 106 /* Transport endpoint is already connected */
#define ENOTCONN 107 /* Transport endpoint is not connected */
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
#define ETIMEDOUT 110 /* Connection timed out */
#define ECONNREFUSED 111 /* Connection refused */
#define EHOSTDOWN 112 /* Host is down */
#define EHOSTUNREACH 113 /* No route to host */
#define EALREADY 114 /* Operation already in progress */
#define EINPROGRESS 115 /* Operation now in progress */
#define ESTALE 116 /* Stale NFS file handle */
#define EUCLEAN 117 /* Structure needs cleaning */
#define ENOTNAM 118 /* Not a XENIX named type file */
#define ENAVAIL 119 /* No XENIX semaphores available */
#define EISNAM 120 /* Is a named type file */
#define EREMOTEIO 121 /* Remote I/O error */
#define EDQUOT 122 /* Quota exceeded */
#define ENOMEDIUM 123 /* No medium found */
#define EMEDIUMTYPE 124 /* Wrong medium type */
#define ECANCELED 125 /* Operation Canceled */
#define ENOKEY 126 /* Required key not available */
#define EKEYEXPIRED 127 /* Key has expired */
#define EKEYREVOKED 128 /* Key has been revoked */
#define EKEYREJECTED 129 /* Key was rejected by service */
/* for robust mutexes */
#define EOWNERDEAD 130 /* Owner died */
#define ENOTRECOVERABLE 131 /* State not recoverable */
#define ERFKILL 132 /* Operation not possible due to RF-kill */
#define EHWPOISON 133 /* Memory page has hardware error */
#define ENOTSUPP 524 /* Operation is not supported */
#endif
#ifndef _GENERIC_ERRNO_H
#define _GENERIC_ERRNO_H
#define EPERM 1 /* Operation not permitted */
#define ENOENT 2 /* No such file or directory */
#define ESRCH 3 /* No such process */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define E2BIG 7 /* Argument list too long */
#define ENOEXEC 8 /* Exec format error */
#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define ENOTBLK 15 /* Block device required */
#define EBUSY 16 /* Device or resource busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENFILE 23 /* File table overflow */
#define EMFILE 24 /* Too many open files */
#define ENOTTY 25 /* Not a typewriter */
#define ETXTBSY 26 /* Text file busy */
#define EFBIG 27 /* File too large */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read-only file system */
#define EMLINK 31 /* Too many links */
#define EPIPE 32 /* Broken pipe */
#define EDOM 33 /* Math argument out of domain of func */
#define ERANGE 34 /* Math result not representable */
#define EDEADLK 35 /* Resource deadlock would occur */
#define ENAMETOOLONG 36 /* File name too long */
#define ENOLCK 37 /* No record locks available */
#define ENOSYS 38 /* Function not implemented */
#define ENOTEMPTY 39 /* Directory not empty */
#define ELOOP 40 /* Too many symbolic links encountered */
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define ENOMSG 42 /* No message of desired type */
#define EIDRM 43 /* Identifier removed */
#define ECHRNG 44 /* Channel number out of range */
#define EL2NSYNC 45 /* Level 2 not synchronized */
#define EL3HLT 46 /* Level 3 halted */
#define EL3RST 47 /* Level 3 reset */
#define ELNRNG 48 /* Link number out of range */
#define EUNATCH 49 /* Protocol driver not attached */
#define ENOCSI 50 /* No CSI structure available */
#define EL2HLT 51 /* Level 2 halted */
#define EBADE 52 /* Invalid exchange */
#define EBADR 53 /* Invalid request descriptor */
#define EXFULL 54 /* Exchange full */
#define ENOANO 55 /* No anode */
#define EBADRQC 56 /* Invalid request code */
#define EBADSLT 57 /* Invalid slot */
#define EDEADLOCK EDEADLK
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define ETIME 62 /* Timer expired */
#define ENOSR 63 /* Out of streams resources */
#define ENONET 64 /* Machine is not on the network */
#define ENOPKG 65 /* Package not installed */
#define EREMOTE 66 /* Object is remote */
#define ENOLINK 67 /* Link has been severed */
#define EADV 68 /* Advertise error */
#define ESRMNT 69 /* Srmount error */
#define ECOMM 70 /* Communication error on send */
#define EPROTO 71 /* Protocol error */
#define EMULTIHOP 72 /* Multihop attempted */
#define EDOTDOT 73 /* RFS specific error */
#define EBADMSG 74 /* Not a data message */
#define EOVERFLOW 75 /* Value too large for defined data type */
#define ENOTUNIQ 76 /* Name not unique on network */
#define EBADFD 77 /* File descriptor in bad state */
#define EREMCHG 78 /* Remote address changed */
#define ELIBACC 79 /* Can not access a needed shared library */
#define ELIBBAD 80 /* Accessing a corrupted shared library */
#define ELIBSCN 81 /* .lib section in a.out corrupted */
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
#define EILSEQ 84 /* Illegal byte sequence */
#define ERESTART 85 /* Interrupted system call should be restarted */
#define ESTRPIPE 86 /* Streams pipe error */
#define EUSERS 87 /* Too many users */
#define ENOTSOCK 88 /* Socket operation on non-socket */
#define EDESTADDRREQ 89 /* Destination address required */
#define EMSGSIZE 90 /* Message too long */
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
#define ENOPROTOOPT 92 /* Protocol not available */
#define EPROTONOSUPPORT 93 /* Protocol not supported */
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
#define EPFNOSUPPORT 96 /* Protocol family not supported */
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
#define EADDRINUSE 98 /* Address already in use */
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
#define ENETDOWN 100 /* Network is down */
#define ENETUNREACH 101 /* Network is unreachable */
#define ENETRESET 102 /* Network dropped connection because of reset */
#define ECONNABORTED 103 /* Software caused connection abort */
#define ECONNRESET 104 /* Connection reset by peer */
#define ENOBUFS 105 /* No buffer space available */
#define EISCONN 106 /* Transport endpoint is already connected */
#define ENOTCONN 107 /* Transport endpoint is not connected */
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
#define ETIMEDOUT 110 /* Connection timed out */
#define ECONNREFUSED 111 /* Connection refused */
#define EHOSTDOWN 112 /* Host is down */
#define EHOSTUNREACH 113 /* No route to host */
#define EALREADY 114 /* Operation already in progress */
#define EINPROGRESS 115 /* Operation now in progress */
#define ESTALE 116 /* Stale NFS file handle */
#define EUCLEAN 117 /* Structure needs cleaning */
#define ENOTNAM 118 /* Not a XENIX named type file */
#define ENAVAIL 119 /* No XENIX semaphores available */
#define EISNAM 120 /* Is a named type file */
#define EREMOTEIO 121 /* Remote I/O error */
#define EDQUOT 122 /* Quota exceeded */
#define ENOMEDIUM 123 /* No medium found */
#define EMEDIUMTYPE 124 /* Wrong medium type */
#define ECANCELED 125 /* Operation Canceled */
#define ENOKEY 126 /* Required key not available */
#define EKEYEXPIRED 127 /* Key has expired */
#define EKEYREVOKED 128 /* Key has been revoked */
#define EKEYREJECTED 129 /* Key was rejected by service */
/* for robust mutexes */
#define EOWNERDEAD 130 /* Owner died */
#define ENOTRECOVERABLE 131 /* State not recoverable */
#define ERFKILL 132 /* Operation not possible due to RF-kill */
#define EHWPOISON 133 /* Memory page has hardware error */
#define ENOTSUPP 524 /* Operation is not supported */
#endif

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component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/hal_otg.h
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_OTG_H_
#define _HAL_OTG_H_
#include "rtl8195a_otg.h"
#include "dwc_otg_regs.h"
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_OTG_H_
#define _HAL_OTG_H_
#include "rtl8195a_otg.h"
#include "dwc_otg_regs.h"
#endif

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component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/usb_ch9.h
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756
component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/usb_defs.h
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@ -1,378 +1,378 @@
/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Note: Part of this code has been derived from linux
*
*/
#ifndef _USB_DEFS_H_
#define _USB_DEFS_H_
/* USB constants */
/* Device and/or Interface Class codes */
#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */
#define USB_CLASS_AUDIO 1
#define USB_CLASS_COMM 2
#define USB_CLASS_HID 3
#define USB_CLASS_PHYSICAL 5
#define USB_CLASS_STILL_IMAGE 6
#define USB_CLASS_PRINTER 7
#define USB_CLASS_MASS_STORAGE 8
#define USB_CLASS_HUB 9
#define USB_CLASS_CDC_DATA 0x0a
#define USB_CLASS_DATA 10
#define USB_CLASS_CSCID 0x0b /* chip+ smart card */
#define USB_CLASS_CONTENT_SEC 0x0d /* content security */
#define USB_CLASS_VIDEO 0x0e
#define USB_CLASS_WIRELESS_CONTROLLER 0xe0
#define USB_CLASS_APP_SPEC 0xfe
#define USB_CLASS_VENDOR_SPEC 0xff
/* some HID sub classes */
#define USB_SUB_HID_NONE 0
#define USB_SUB_HID_BOOT 1
/* some UID Protocols */
#define USB_PROT_HID_NONE 0
#define USB_PROT_HID_KEYBOARD 1
#define USB_PROT_HID_MOUSE 2
/* Sub STORAGE Classes */
#define US_SC_RBC 1 /* Typically, flash devices */
#define US_SC_8020 2 /* CD-ROM */
#define US_SC_QIC 3 /* QIC-157 Tapes */
#define US_SC_UFI 4 /* Floppy */
#define US_SC_8070 5 /* Removable media */
#define US_SC_SCSI 6 /* Transparent */
#define US_SC_MIN US_SC_RBC
#define US_SC_MAX US_SC_SCSI
/* STORAGE Protocols */
#define US_PR_CB 1 /* Control/Bulk w/o interrupt */
#define US_PR_CBI 0 /* Control/Bulk/Interrupt */
#define US_PR_BULK 0x50 /* bulk only */
/* USB types */
#define USB_TYPE_STANDARD (0x00 << 5)
#define USB_TYPE_CLASS (0x01 << 5)
#define USB_TYPE_VENDOR (0x02 << 5)
#define USB_TYPE_RESERVED (0x03 << 5)
/* USB recipients */
#define USB_RECIP_DEVICE 0x00
#define USB_RECIP_INTERFACE 0x01
#define USB_RECIP_ENDPOINT 0x02
#define USB_RECIP_OTHER 0x03
#define USB_DT_CS_DEVICE 0x21
#define USB_DT_CS_CONFIG 0x22
#define USB_DT_CS_STRING 0x23
#define USB_DT_CS_INTERFACE 0x24
#define USB_DT_CS_ENDPOINT 0x25
/* USB directions */
#define USB_DIR_OUT 0 /* to device */
#define USB_DIR_IN 0x80 /* to host */
#if 0
enum usb_device_speed {
USB_SPEED_UNKNOWN = 0, /* enumerating */
USB_SPEED_LOW,
USB_SPEED_FULL, /* usb 1.1 */
USB_SPEED_HIGH, /* usb 2.0 */
};
#else
enum usb_device_speed {
USB_SPEED_UNKNOWN = 0, /* enumerating */
USB_SPEED_LOW, USB_SPEED_FULL, /* usb 1.1 */
USB_SPEED_HIGH, /* usb 2.0 */
USB_SPEED_VARIABLE, /* wireless (usb 2.5) */
};
#endif
/* Descriptor types */
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
#define USB_DT_STRING 0x03
#define USB_DT_INTERFACE 0x04
#define USB_DT_ENDPOINT 0x05
#define USB_DT_DEVICE_QUALIFIER 0x06
#define USB_DT_OTHER_SPEED_CONFIG 0x07
#define USB_DT_INTERFACE_POWER 0x08
/* these are from a minor usb 2.0 revision (ECN) */
#define USB_DT_OTG 0x09
#define USB_DT_DEBUG 0x0a
#define USB_DT_INTERFACE_ASSOCIATION 0x0b
/* these are from the Wireless USB spec */
#define USB_DT_SECURITY 0x0c
#define USB_DT_KEY 0x0d
#define USB_DT_ENCRYPTION_TYPE 0x0e
#define USB_DT_BOS 0x0f
#define USB_DT_DEVICE_CAPABILITY 0x10
#define USB_DT_WIRELESS_ENDPOINT_COMP 0x11
#define USB_DT_WIRE_ADAPTER 0x21
#define USB_DT_RPIPE 0x22
//#define USB_DT_INTERFACE_ASSOCIATION 0x0b
#define USB_DT_HID (USB_TYPE_CLASS | 0x01)
#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02)
#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03)
#define USB_DT_HUB (USB_TYPE_CLASS | 0x09)
/* Descriptor sizes per descriptor type */
#define USB_DT_DEVICE_SIZE 18
#define USB_DT_CONFIG_SIZE 9
#define USB_DT_INTERFACE_SIZE 9
#define USB_DT_ENDPOINT_SIZE 7
#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */
#define USB_DT_HUB_NONVAR_SIZE 7
#define USB_DT_HID_SIZE 9
/* Endpoints */
#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
#define USB_ENDPOINT_DIR_MASK 0x80
#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
#define USB_ENDPOINT_HALT 0 /* IN/OUT will STALL */
/* USB Packet IDs (PIDs) */
#define USB_PID_UNDEF_0 0xf0
#define USB_PID_OUT 0xe1
#define USB_PID_ACK 0xd2
#define USB_PID_DATA0 0xc3
#define USB_PID_UNDEF_4 0xb4
#define USB_PID_SOF 0xa5
#define USB_PID_UNDEF_6 0x96
#define USB_PID_UNDEF_7 0x87
#define USB_PID_UNDEF_8 0x78
#define USB_PID_IN 0x69
#define USB_PID_NAK 0x5a
#define USB_PID_DATA1 0x4b
#define USB_PID_PREAMBLE 0x3c
#define USB_PID_SETUP 0x2d
#define USB_PID_STALL 0x1e
#define USB_PID_UNDEF_F 0x0f
/* Standard requests */
#define USB_REQ_GET_STATUS 0x00
#define USB_REQ_CLEAR_FEATURE 0x01
#define USB_REQ_SET_FEATURE 0x03
#define USB_REQ_SET_ADDRESS 0x05
#define USB_REQ_GET_DESCRIPTOR 0x06
#define USB_REQ_SET_DESCRIPTOR 0x07
#define USB_REQ_GET_CONFIGURATION 0x08
#define USB_REQ_SET_CONFIGURATION 0x09
#define USB_REQ_GET_INTERFACE 0x0A
#define USB_REQ_SET_INTERFACE 0x0B
#define USB_REQ_SYNCH_FRAME 0x0C
/* HID requests */
#define USB_REQ_GET_REPORT 0x01
#define USB_REQ_GET_IDLE 0x02
#define USB_REQ_GET_PROTOCOL 0x03
#define USB_REQ_SET_REPORT 0x09
#define USB_REQ_SET_IDLE 0x0A
#define USB_REQ_SET_PROTOCOL 0x0B
/* "pipe" definitions */
#define PIPE_ISOCHRONOUS 0
#define PIPE_INTERRUPT 1
#define PIPE_CONTROL 2
#define PIPE_BULK 3
#define PIPE_DEVEP_MASK 0x0007ff00
#define USB_ISOCHRONOUS 0
#define USB_INTERRUPT 1
#define USB_CONTROL 2
#define USB_BULK 3
/* USB-status codes: */
#define USB_ST_ACTIVE 0x1 /* TD is active */
#define USB_ST_STALLED 0x2 /* TD is stalled */
#define USB_ST_BUF_ERR 0x4 /* buffer error */
#define USB_ST_BABBLE_DET 0x8 /* Babble detected */
#define USB_ST_NAK_REC 0x10 /* NAK Received*/
#define USB_ST_CRC_ERR 0x20 /* CRC/timeout Error */
#define USB_ST_BIT_ERR 0x40 /* Bitstuff error */
#define USB_ST_NOT_PROC 0x80000000L /* Not yet processed */
/*************************************************************************
* Hub defines
*/
/*
* Hub request types
*/
#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE)
#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER)
/*
* Hub Class feature numbers
*/
#define C_HUB_LOCAL_POWER 0
#define C_HUB_OVER_CURRENT 1
/*
* Port feature numbers
*/
#define USB_PORT_FEAT_CONNECTION 0
#define USB_PORT_FEAT_ENABLE 1
#define USB_PORT_FEAT_SUSPEND 2
#define USB_PORT_FEAT_OVER_CURRENT 3
#define USB_PORT_FEAT_RESET 4
#define USB_PORT_FEAT_POWER 8
#define USB_PORT_FEAT_LOWSPEED 9
#define USB_PORT_FEAT_HIGHSPEED 10
#define USB_PORT_FEAT_C_CONNECTION 16
#define USB_PORT_FEAT_C_ENABLE 17
#define USB_PORT_FEAT_C_SUSPEND 18
#define USB_PORT_FEAT_C_OVER_CURRENT 19
#define USB_PORT_FEAT_C_RESET 20
/* wPortStatus bits */
#define USB_PORT_STAT_CONNECTION 0x0001
#define USB_PORT_STAT_ENABLE 0x0002
#define USB_PORT_STAT_SUSPEND 0x0004
#define USB_PORT_STAT_OVERCURRENT 0x0008
#define USB_PORT_STAT_RESET 0x0010
#define USB_PORT_STAT_POWER 0x0100
#define USB_PORT_STAT_LOW_SPEED 0x0200
#define USB_PORT_STAT_HIGH_SPEED 0x0400 /* support for EHCI */
#define USB_PORT_STAT_SPEED \
(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
/* wPortChange bits */
#define USB_PORT_STAT_C_CONNECTION 0x0001
#define USB_PORT_STAT_C_ENABLE 0x0002
#define USB_PORT_STAT_C_SUSPEND 0x0004
#define USB_PORT_STAT_C_OVERCURRENT 0x0008
#define USB_PORT_STAT_C_RESET 0x0010
/* wHubCharacteristics (masks) */
#define HUB_CHAR_LPSM 0x0003
#define HUB_CHAR_COMPOUND 0x0004
#define HUB_CHAR_OCPM 0x0018
/*
*Hub Status & Hub Change bit masks
*/
#define HUB_STATUS_LOCAL_POWER 0x0001
#define HUB_STATUS_OVERCURRENT 0x0002
#define HUB_CHANGE_LOCAL_POWER 0x0001
#define HUB_CHANGE_OVERCURRENT 0x0002
/* Struct USB_HCD defination */
// for flags
#define HCD_FLAG_HW_ACCESSIBLE 0 /* at full power */
#define HCD_FLAG_POLL_RH 2 /* poll for rh status? */
#define HCD_FLAG_POLL_PENDING 3 /* status has changed? */
#define HCD_FLAG_WAKEUP_PENDING 4 /* root hub is resuming? */
#define HCD_FLAG_RH_RUNNING 5 /* root hub is running? */
#define HCD_FLAG_DEAD 6 /* controller has died? */
/* The flags can be tested using these macros; they are likely to
* be slightly faster than test_bit().
*/
#define HCD_HW_ACCESSIBLE(hcd) ((hcd)->flags & (1U << HCD_FLAG_HW_ACCESSIBLE))
#define HCD_POLL_RH(hcd) ((hcd)->flags & (1U << HCD_FLAG_POLL_RH))
#define HCD_POLL_PENDING(hcd) ((hcd)->flags & (1U << HCD_FLAG_POLL_PENDING))
#define HCD_WAKEUP_PENDING(hcd) ((hcd)->flags & (1U << HCD_FLAG_WAKEUP_PENDING))
#define HCD_RH_RUNNING(hcd) ((hcd)->flags & (1U << HCD_FLAG_RH_RUNNING))
#define HCD_DEAD(hcd) ((hcd)->flags & (1U << HCD_FLAG_DEAD))
// for state
#define __ACTIVE 0x01
#define __SUSPEND 0x04
#define __TRANSIENT 0x80
#define HC_STATE_HALT 0
#define HC_STATE_RUNNING (__ACTIVE)
#define HC_STATE_QUIESCING (__SUSPEND|__TRANSIENT|__ACTIVE)
#define HC_STATE_RESUMING (__SUSPEND|__TRANSIENT)
#define HC_STATE_SUSPENDED (__SUSPEND)
#define HC_IS_RUNNING(state) ((state) & __ACTIVE)
#define HC_IS_SUSPENDED(state) ((state) & __SUSPEND)
/*
* USB feature flags are written using USB_REQ_{CLEAR,SET}_FEATURE, and
* are read as a bit array returned by USB_REQ_GET_STATUS. (So there
* are at most sixteen features of each type.) Hubs may also support a
* new USB_REQ_TEST_AND_SET_FEATURE to put ports into L1 suspend.
*/
#define USB_DEVICE_SELF_POWERED 0 /* (read only) */
#define USB_DEVICE_REMOTE_WAKEUP 1 /* dev may initiate wakeup */
#define USB_DEVICE_TEST_MODE 2 /* (wired high speed only) */
#define USB_DEVICE_BATTERY 2 /* (wireless) */
#define USB_DEVICE_B_HNP_ENABLE 3 /* (otg) dev may initiate HNP */
#define USB_DEVICE_WUSB_DEVICE 3 /* (wireless)*/
#define USB_DEVICE_A_HNP_SUPPORT 4 /* (otg) RH port supports HNP */
#define USB_DEVICE_A_ALT_HNP_SUPPORT 5 /* (otg) other RH port does */
#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
#define DeviceRequest \
((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_DEVICE)<<8)
#define DeviceOutRequest \
((USB_DIR_OUT|USB_TYPE_STANDARD|USB_RECIP_DEVICE)<<8)
#define InterfaceRequest \
((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_INTERFACE)<<8)
#define EndpointRequest \
((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_INTERFACE)<<8)
#define EndpointOutRequest \
((USB_DIR_OUT|USB_TYPE_STANDARD|USB_RECIP_INTERFACE)<<8)
/* class requests from the USB 2.0 hub spec, table 11-15 */
/* GetBusState and SetHubDescriptor are optional, omitted */
#define ClearHubFeature (0x2000 | USB_REQ_CLEAR_FEATURE)
#define ClearPortFeature (0x2300 | USB_REQ_CLEAR_FEATURE)
#define GetHubDescriptor (0xa000 | USB_REQ_GET_DESCRIPTOR)
#define GetHubStatus (0xa000 | USB_REQ_GET_STATUS)
#define GetPortStatus (0xa300 | USB_REQ_GET_STATUS)
#define SetHubFeature (0x2000 | USB_REQ_SET_FEATURE)
#define SetPortFeature (0x2300 | USB_REQ_SET_FEATURE)
/* from config descriptor bmAttributes */
#define USB_CONFIG_ATT_ONE (1 << 7) /* must be set */
#define USB_CONFIG_ATT_SELFPOWER (1 << 6) /* self powered */
#define USB_CONFIG_ATT_WAKEUP (1 << 5) /* can wakeup */
#define USB_CONFIG_ATT_BATTERY (1 << 4) /* battery powered */
#endif /*_USB_DEFS_H_ */
/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Note: Part of this code has been derived from linux
*
*/
#ifndef _USB_DEFS_H_
#define _USB_DEFS_H_
/* USB constants */
/* Device and/or Interface Class codes */
#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */
#define USB_CLASS_AUDIO 1
#define USB_CLASS_COMM 2
#define USB_CLASS_HID 3
#define USB_CLASS_PHYSICAL 5
#define USB_CLASS_STILL_IMAGE 6
#define USB_CLASS_PRINTER 7
#define USB_CLASS_MASS_STORAGE 8
#define USB_CLASS_HUB 9
#define USB_CLASS_CDC_DATA 0x0a
#define USB_CLASS_DATA 10
#define USB_CLASS_CSCID 0x0b /* chip+ smart card */
#define USB_CLASS_CONTENT_SEC 0x0d /* content security */
#define USB_CLASS_VIDEO 0x0e
#define USB_CLASS_WIRELESS_CONTROLLER 0xe0
#define USB_CLASS_APP_SPEC 0xfe
#define USB_CLASS_VENDOR_SPEC 0xff
/* some HID sub classes */
#define USB_SUB_HID_NONE 0
#define USB_SUB_HID_BOOT 1
/* some UID Protocols */
#define USB_PROT_HID_NONE 0
#define USB_PROT_HID_KEYBOARD 1
#define USB_PROT_HID_MOUSE 2
/* Sub STORAGE Classes */
#define US_SC_RBC 1 /* Typically, flash devices */
#define US_SC_8020 2 /* CD-ROM */
#define US_SC_QIC 3 /* QIC-157 Tapes */
#define US_SC_UFI 4 /* Floppy */
#define US_SC_8070 5 /* Removable media */
#define US_SC_SCSI 6 /* Transparent */
#define US_SC_MIN US_SC_RBC
#define US_SC_MAX US_SC_SCSI
/* STORAGE Protocols */
#define US_PR_CB 1 /* Control/Bulk w/o interrupt */
#define US_PR_CBI 0 /* Control/Bulk/Interrupt */
#define US_PR_BULK 0x50 /* bulk only */
/* USB types */
#define USB_TYPE_STANDARD (0x00 << 5)
#define USB_TYPE_CLASS (0x01 << 5)
#define USB_TYPE_VENDOR (0x02 << 5)
#define USB_TYPE_RESERVED (0x03 << 5)
/* USB recipients */
#define USB_RECIP_DEVICE 0x00
#define USB_RECIP_INTERFACE 0x01
#define USB_RECIP_ENDPOINT 0x02
#define USB_RECIP_OTHER 0x03
#define USB_DT_CS_DEVICE 0x21
#define USB_DT_CS_CONFIG 0x22
#define USB_DT_CS_STRING 0x23
#define USB_DT_CS_INTERFACE 0x24
#define USB_DT_CS_ENDPOINT 0x25
/* USB directions */
#define USB_DIR_OUT 0 /* to device */
#define USB_DIR_IN 0x80 /* to host */
#if 0
enum usb_device_speed {
USB_SPEED_UNKNOWN = 0, /* enumerating */
USB_SPEED_LOW,
USB_SPEED_FULL, /* usb 1.1 */
USB_SPEED_HIGH, /* usb 2.0 */
};
#else
enum usb_device_speed {
USB_SPEED_UNKNOWN = 0, /* enumerating */
USB_SPEED_LOW, USB_SPEED_FULL, /* usb 1.1 */
USB_SPEED_HIGH, /* usb 2.0 */
USB_SPEED_VARIABLE, /* wireless (usb 2.5) */
};
#endif
/* Descriptor types */
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
#define USB_DT_STRING 0x03
#define USB_DT_INTERFACE 0x04
#define USB_DT_ENDPOINT 0x05
#define USB_DT_DEVICE_QUALIFIER 0x06
#define USB_DT_OTHER_SPEED_CONFIG 0x07
#define USB_DT_INTERFACE_POWER 0x08
/* these are from a minor usb 2.0 revision (ECN) */
#define USB_DT_OTG 0x09
#define USB_DT_DEBUG 0x0a
#define USB_DT_INTERFACE_ASSOCIATION 0x0b
/* these are from the Wireless USB spec */
#define USB_DT_SECURITY 0x0c
#define USB_DT_KEY 0x0d
#define USB_DT_ENCRYPTION_TYPE 0x0e
#define USB_DT_BOS 0x0f
#define USB_DT_DEVICE_CAPABILITY 0x10
#define USB_DT_WIRELESS_ENDPOINT_COMP 0x11
#define USB_DT_WIRE_ADAPTER 0x21
#define USB_DT_RPIPE 0x22
//#define USB_DT_INTERFACE_ASSOCIATION 0x0b
#define USB_DT_HID (USB_TYPE_CLASS | 0x01)
#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02)
#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03)
#define USB_DT_HUB (USB_TYPE_CLASS | 0x09)
/* Descriptor sizes per descriptor type */
#define USB_DT_DEVICE_SIZE 18
#define USB_DT_CONFIG_SIZE 9
#define USB_DT_INTERFACE_SIZE 9
#define USB_DT_ENDPOINT_SIZE 7
#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */
#define USB_DT_HUB_NONVAR_SIZE 7
#define USB_DT_HID_SIZE 9
/* Endpoints */
#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
#define USB_ENDPOINT_DIR_MASK 0x80
#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
#define USB_ENDPOINT_HALT 0 /* IN/OUT will STALL */
/* USB Packet IDs (PIDs) */
#define USB_PID_UNDEF_0 0xf0
#define USB_PID_OUT 0xe1
#define USB_PID_ACK 0xd2
#define USB_PID_DATA0 0xc3
#define USB_PID_UNDEF_4 0xb4
#define USB_PID_SOF 0xa5
#define USB_PID_UNDEF_6 0x96
#define USB_PID_UNDEF_7 0x87
#define USB_PID_UNDEF_8 0x78
#define USB_PID_IN 0x69
#define USB_PID_NAK 0x5a
#define USB_PID_DATA1 0x4b
#define USB_PID_PREAMBLE 0x3c
#define USB_PID_SETUP 0x2d
#define USB_PID_STALL 0x1e
#define USB_PID_UNDEF_F 0x0f
/* Standard requests */
#define USB_REQ_GET_STATUS 0x00
#define USB_REQ_CLEAR_FEATURE 0x01
#define USB_REQ_SET_FEATURE 0x03
#define USB_REQ_SET_ADDRESS 0x05
#define USB_REQ_GET_DESCRIPTOR 0x06
#define USB_REQ_SET_DESCRIPTOR 0x07
#define USB_REQ_GET_CONFIGURATION 0x08
#define USB_REQ_SET_CONFIGURATION 0x09
#define USB_REQ_GET_INTERFACE 0x0A
#define USB_REQ_SET_INTERFACE 0x0B
#define USB_REQ_SYNCH_FRAME 0x0C
/* HID requests */
#define USB_REQ_GET_REPORT 0x01
#define USB_REQ_GET_IDLE 0x02
#define USB_REQ_GET_PROTOCOL 0x03
#define USB_REQ_SET_REPORT 0x09
#define USB_REQ_SET_IDLE 0x0A
#define USB_REQ_SET_PROTOCOL 0x0B
/* "pipe" definitions */
#define PIPE_ISOCHRONOUS 0
#define PIPE_INTERRUPT 1
#define PIPE_CONTROL 2
#define PIPE_BULK 3
#define PIPE_DEVEP_MASK 0x0007ff00
#define USB_ISOCHRONOUS 0
#define USB_INTERRUPT 1
#define USB_CONTROL 2
#define USB_BULK 3
/* USB-status codes: */
#define USB_ST_ACTIVE 0x1 /* TD is active */
#define USB_ST_STALLED 0x2 /* TD is stalled */
#define USB_ST_BUF_ERR 0x4 /* buffer error */
#define USB_ST_BABBLE_DET 0x8 /* Babble detected */
#define USB_ST_NAK_REC 0x10 /* NAK Received*/
#define USB_ST_CRC_ERR 0x20 /* CRC/timeout Error */
#define USB_ST_BIT_ERR 0x40 /* Bitstuff error */
#define USB_ST_NOT_PROC 0x80000000L /* Not yet processed */
/*************************************************************************
* Hub defines
*/
/*
* Hub request types
*/
#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE)
#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER)
/*
* Hub Class feature numbers
*/
#define C_HUB_LOCAL_POWER 0
#define C_HUB_OVER_CURRENT 1
/*
* Port feature numbers
*/
#define USB_PORT_FEAT_CONNECTION 0
#define USB_PORT_FEAT_ENABLE 1
#define USB_PORT_FEAT_SUSPEND 2
#define USB_PORT_FEAT_OVER_CURRENT 3
#define USB_PORT_FEAT_RESET 4
#define USB_PORT_FEAT_POWER 8
#define USB_PORT_FEAT_LOWSPEED 9
#define USB_PORT_FEAT_HIGHSPEED 10
#define USB_PORT_FEAT_C_CONNECTION 16
#define USB_PORT_FEAT_C_ENABLE 17
#define USB_PORT_FEAT_C_SUSPEND 18
#define USB_PORT_FEAT_C_OVER_CURRENT 19
#define USB_PORT_FEAT_C_RESET 20
/* wPortStatus bits */
#define USB_PORT_STAT_CONNECTION 0x0001
#define USB_PORT_STAT_ENABLE 0x0002
#define USB_PORT_STAT_SUSPEND 0x0004
#define USB_PORT_STAT_OVERCURRENT 0x0008
#define USB_PORT_STAT_RESET 0x0010
#define USB_PORT_STAT_POWER 0x0100
#define USB_PORT_STAT_LOW_SPEED 0x0200
#define USB_PORT_STAT_HIGH_SPEED 0x0400 /* support for EHCI */
#define USB_PORT_STAT_SPEED \
(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
/* wPortChange bits */
#define USB_PORT_STAT_C_CONNECTION 0x0001
#define USB_PORT_STAT_C_ENABLE 0x0002
#define USB_PORT_STAT_C_SUSPEND 0x0004
#define USB_PORT_STAT_C_OVERCURRENT 0x0008
#define USB_PORT_STAT_C_RESET 0x0010
/* wHubCharacteristics (masks) */
#define HUB_CHAR_LPSM 0x0003
#define HUB_CHAR_COMPOUND 0x0004
#define HUB_CHAR_OCPM 0x0018
/*
*Hub Status & Hub Change bit masks
*/
#define HUB_STATUS_LOCAL_POWER 0x0001
#define HUB_STATUS_OVERCURRENT 0x0002
#define HUB_CHANGE_LOCAL_POWER 0x0001
#define HUB_CHANGE_OVERCURRENT 0x0002
/* Struct USB_HCD defination */
// for flags
#define HCD_FLAG_HW_ACCESSIBLE 0 /* at full power */
#define HCD_FLAG_POLL_RH 2 /* poll for rh status? */
#define HCD_FLAG_POLL_PENDING 3 /* status has changed? */
#define HCD_FLAG_WAKEUP_PENDING 4 /* root hub is resuming? */
#define HCD_FLAG_RH_RUNNING 5 /* root hub is running? */
#define HCD_FLAG_DEAD 6 /* controller has died? */
/* The flags can be tested using these macros; they are likely to
* be slightly faster than test_bit().
*/
#define HCD_HW_ACCESSIBLE(hcd) ((hcd)->flags & (1U << HCD_FLAG_HW_ACCESSIBLE))
#define HCD_POLL_RH(hcd) ((hcd)->flags & (1U << HCD_FLAG_POLL_RH))
#define HCD_POLL_PENDING(hcd) ((hcd)->flags & (1U << HCD_FLAG_POLL_PENDING))
#define HCD_WAKEUP_PENDING(hcd) ((hcd)->flags & (1U << HCD_FLAG_WAKEUP_PENDING))
#define HCD_RH_RUNNING(hcd) ((hcd)->flags & (1U << HCD_FLAG_RH_RUNNING))
#define HCD_DEAD(hcd) ((hcd)->flags & (1U << HCD_FLAG_DEAD))
// for state
#define __ACTIVE 0x01
#define __SUSPEND 0x04
#define __TRANSIENT 0x80
#define HC_STATE_HALT 0
#define HC_STATE_RUNNING (__ACTIVE)
#define HC_STATE_QUIESCING (__SUSPEND|__TRANSIENT|__ACTIVE)
#define HC_STATE_RESUMING (__SUSPEND|__TRANSIENT)
#define HC_STATE_SUSPENDED (__SUSPEND)
#define HC_IS_RUNNING(state) ((state) & __ACTIVE)
#define HC_IS_SUSPENDED(state) ((state) & __SUSPEND)
/*
* USB feature flags are written using USB_REQ_{CLEAR,SET}_FEATURE, and
* are read as a bit array returned by USB_REQ_GET_STATUS. (So there
* are at most sixteen features of each type.) Hubs may also support a
* new USB_REQ_TEST_AND_SET_FEATURE to put ports into L1 suspend.
*/
#define USB_DEVICE_SELF_POWERED 0 /* (read only) */
#define USB_DEVICE_REMOTE_WAKEUP 1 /* dev may initiate wakeup */
#define USB_DEVICE_TEST_MODE 2 /* (wired high speed only) */
#define USB_DEVICE_BATTERY 2 /* (wireless) */
#define USB_DEVICE_B_HNP_ENABLE 3 /* (otg) dev may initiate HNP */
#define USB_DEVICE_WUSB_DEVICE 3 /* (wireless)*/
#define USB_DEVICE_A_HNP_SUPPORT 4 /* (otg) RH port supports HNP */
#define USB_DEVICE_A_ALT_HNP_SUPPORT 5 /* (otg) other RH port does */
#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
#define DeviceRequest \
((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_DEVICE)<<8)
#define DeviceOutRequest \
((USB_DIR_OUT|USB_TYPE_STANDARD|USB_RECIP_DEVICE)<<8)
#define InterfaceRequest \
((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_INTERFACE)<<8)
#define EndpointRequest \
((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_INTERFACE)<<8)
#define EndpointOutRequest \
((USB_DIR_OUT|USB_TYPE_STANDARD|USB_RECIP_INTERFACE)<<8)
/* class requests from the USB 2.0 hub spec, table 11-15 */
/* GetBusState and SetHubDescriptor are optional, omitted */
#define ClearHubFeature (0x2000 | USB_REQ_CLEAR_FEATURE)
#define ClearPortFeature (0x2300 | USB_REQ_CLEAR_FEATURE)
#define GetHubDescriptor (0xa000 | USB_REQ_GET_DESCRIPTOR)
#define GetHubStatus (0xa000 | USB_REQ_GET_STATUS)
#define GetPortStatus (0xa300 | USB_REQ_GET_STATUS)
#define SetHubFeature (0x2000 | USB_REQ_SET_FEATURE)
#define SetPortFeature (0x2300 | USB_REQ_SET_FEATURE)
/* from config descriptor bmAttributes */
#define USB_CONFIG_ATT_ONE (1 << 7) /* must be set */
#define USB_CONFIG_ATT_SELFPOWER (1 << 6) /* self powered */
#define USB_CONFIG_ATT_WAKEUP (1 << 5) /* can wakeup */
#define USB_CONFIG_ATT_BATTERY (1 << 4) /* battery powered */
#endif /*_USB_DEFS_H_ */

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component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/usb_ulinker.h
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@ -1,74 +1,74 @@
#ifndef __LINUX_USB_ULINKER_H
#define __LINUX_USB_ULINKER_H
//#include "linux/autoconf.h"
//#ifndef CONFIG_RTL_ULINKER_CUSTOMIZATION
#if 1//ModifiedByJD
#define ULINKER_ETHER_VID 0x0BDA
#define ULINKER_ETHER_PID 0x8195
#define ULINKER_MANUFACTURER "Realtek Semicoonductor Corp."
#define ULINKER_WINTOOLS_GUID "1CACC490-055C-4035-A026-1DAB0BDA8196"
#define ULINKER_WINTOOLS_DISPLAY_NAME "Realtek RTL8196EU Universal Linker"
#define ULINKER_WINTOOLS_CONTACT "nicfae@realtek.com.tw"
#define ULINKER_WINTOOLS_DISPLAY_VERSION "v1.0.0.0"
#define ULINKER_WINTOOLS_HELP_LINK "http://www.realtek.com.tw"
#define ULINKER_WINTOOLS_PUBLISHER ULINKER_MANUFACTURER
#define ULINKER_WINTOOLS_TARGET_DIR ULINKER_WINTOOLS_DISPLAY_NAME
#else
#define ULINKER_ETHER_VID CONFIG_RTL_ULINKER_VID
#define ULINKER_ETHER_PID CONFIG_RTL_ULINKER_PID
#define ULINKER_STORAGE_VID CONFIG_RTL_ULINKER_VID_S
#define ULINKER_STORAGE_PID CONFIG_RTL_ULINKER_PID_S
#define ULINKER_MANUFACTURER CONFIG_RTL_ULINKER_MANUFACTURE
#define ULINKER_WINTOOLS_GUID CONFIG_RTL_ULINKER_WINTOOLS_GUID
#define ULINKER_WINTOOLS_DISPLAY_NAME CONFIG_RTL_ULINKER_WINTOOLS_DISPLAY_NAME
#define ULINKER_WINTOOLS_CONTACT CONFIG_RTL_ULINKER_WINTOOLS_CONTACT
#define ULINKER_WINTOOLS_DISPLAY_VERSION CONFIG_RTL_ULINKER_WINTOOLS_DISPLAY_VERSION
#define ULINKER_WINTOOLS_HELP_LINK CONFIG_RTL_ULINKER_WINTOOLS_HELP_LINK
#define ULINKER_WINTOOLS_PUBLISHER ULINKER_MANUFACTURER
#define ULINKER_WINTOOLS_TARGET_DIR ULINKER_WINTOOLS_DISPLAY_NAME
#endif
//------------------------------------------------
// if you don't have a specific PID for storage, don't change following define of storage mode.
//
// begin: don't change
#ifndef ULINKER_STORAGE_VID
#define ULINKER_STORAGE_VID 0x0BDA
#define ULINKER_STORAGE_PID 0x8197
#endif
#define ULINKER_STORAGE_VID_STR "USB Ether "
#define ULINKER_STORAGE_PID_DISK_STR "Driver DISC"
#define ULINKER_STORAGE_PID_CDROM_STR "Driver CDROM"
#define ULINKER_WINTOOLS_DRIVER_PATH "Driver"
// end: don't change
//------------------------------------------------
//----------------------------------------------------------------------
#if defined(CONFIG_RTL_ULINKER)
#define ULINKER_DEVINIT
#define ULINKER_DEVINITDATA
#define ULINKER_DEVINITCONST
#define ULINKER_DEVEXIT
#define ULINKER_DEVEXITDATA
#define ULINKER_DEVEXITCONST
#else
#define ULINKER_DEVINIT __devinit
#define ULINKER_DEVINITDATA __devinitdata
#define ULINKER_DEVINITCONST __devinitconst
#define ULINKER_DEVEXIT __devexit
#define ULINKER_DEVEXITDATA __devexitdata
#define ULINKER_DEVEXITCONST __devexitconst
#endif
#endif /* __LINUX_USB_ULINKER_H */
#ifndef __LINUX_USB_ULINKER_H
#define __LINUX_USB_ULINKER_H
//#include "linux/autoconf.h"
//#ifndef CONFIG_RTL_ULINKER_CUSTOMIZATION
#if 1//ModifiedByJD
#define ULINKER_ETHER_VID 0x0BDA
#define ULINKER_ETHER_PID 0x8195
#define ULINKER_MANUFACTURER "Realtek Semicoonductor Corp."
#define ULINKER_WINTOOLS_GUID "1CACC490-055C-4035-A026-1DAB0BDA8196"
#define ULINKER_WINTOOLS_DISPLAY_NAME "Realtek RTL8196EU Universal Linker"
#define ULINKER_WINTOOLS_CONTACT "nicfae@realtek.com.tw"
#define ULINKER_WINTOOLS_DISPLAY_VERSION "v1.0.0.0"
#define ULINKER_WINTOOLS_HELP_LINK "http://www.realtek.com.tw"
#define ULINKER_WINTOOLS_PUBLISHER ULINKER_MANUFACTURER
#define ULINKER_WINTOOLS_TARGET_DIR ULINKER_WINTOOLS_DISPLAY_NAME
#else
#define ULINKER_ETHER_VID CONFIG_RTL_ULINKER_VID
#define ULINKER_ETHER_PID CONFIG_RTL_ULINKER_PID
#define ULINKER_STORAGE_VID CONFIG_RTL_ULINKER_VID_S
#define ULINKER_STORAGE_PID CONFIG_RTL_ULINKER_PID_S
#define ULINKER_MANUFACTURER CONFIG_RTL_ULINKER_MANUFACTURE
#define ULINKER_WINTOOLS_GUID CONFIG_RTL_ULINKER_WINTOOLS_GUID
#define ULINKER_WINTOOLS_DISPLAY_NAME CONFIG_RTL_ULINKER_WINTOOLS_DISPLAY_NAME
#define ULINKER_WINTOOLS_CONTACT CONFIG_RTL_ULINKER_WINTOOLS_CONTACT
#define ULINKER_WINTOOLS_DISPLAY_VERSION CONFIG_RTL_ULINKER_WINTOOLS_DISPLAY_VERSION
#define ULINKER_WINTOOLS_HELP_LINK CONFIG_RTL_ULINKER_WINTOOLS_HELP_LINK
#define ULINKER_WINTOOLS_PUBLISHER ULINKER_MANUFACTURER
#define ULINKER_WINTOOLS_TARGET_DIR ULINKER_WINTOOLS_DISPLAY_NAME
#endif
//------------------------------------------------
// if you don't have a specific PID for storage, don't change following define of storage mode.
//
// begin: don't change
#ifndef ULINKER_STORAGE_VID
#define ULINKER_STORAGE_VID 0x0BDA
#define ULINKER_STORAGE_PID 0x8197
#endif
#define ULINKER_STORAGE_VID_STR "USB Ether "
#define ULINKER_STORAGE_PID_DISK_STR "Driver DISC"
#define ULINKER_STORAGE_PID_CDROM_STR "Driver CDROM"
#define ULINKER_WINTOOLS_DRIVER_PATH "Driver"
// end: don't change
//------------------------------------------------
//----------------------------------------------------------------------
#if defined(CONFIG_RTL_ULINKER)
#define ULINKER_DEVINIT
#define ULINKER_DEVINITDATA
#define ULINKER_DEVINITCONST
#define ULINKER_DEVEXIT
#define ULINKER_DEVEXITDATA
#define ULINKER_DEVEXITCONST
#else
#define ULINKER_DEVINIT __devinit
#define ULINKER_DEVINITDATA __devinitdata
#define ULINKER_DEVINITCONST __devinitconst
#define ULINKER_DEVEXIT __devexit
#define ULINKER_DEVEXITDATA __devexitdata
#define ULINKER_DEVEXITCONST __devexitconst
#endif
#endif /* __LINUX_USB_ULINKER_H */

1056
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gdma.h
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1720
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h
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2502
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h
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122
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h
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@ -1,61 +1,61 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_PWM_H_
#define _RTL8195A_PWM_H_
extern void
HAL_Pwm_SetDuty_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern HAL_Status
HAL_Pwm_Init_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Enable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Disable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
#ifdef CONFIG_CHIP_E_CUT
extern _LONG_CALL_ void
HAL_Pwm_SetDuty_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern _LONG_CALL_ HAL_Status
HAL_Pwm_Init_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern _LONG_CALL_ void
HAL_Pwm_Enable_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern _LONG_CALL_ void
HAL_Pwm_Disable_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
#endif
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_PWM_H_
#define _RTL8195A_PWM_H_
extern void
HAL_Pwm_SetDuty_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern HAL_Status
HAL_Pwm_Init_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Enable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Disable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
#ifdef CONFIG_CHIP_E_CUT
extern _LONG_CALL_ void
HAL_Pwm_SetDuty_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern _LONG_CALL_ HAL_Status
HAL_Pwm_Init_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern _LONG_CALL_ void
HAL_Pwm_Enable_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern _LONG_CALL_ void
HAL_Pwm_Disable_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
#endif
#endif

758
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdr.h
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@ -1,379 +1,379 @@
#ifndef _RTL8195A_SDR_H
#define _RTL8195A_SDR_H
#define MS_0_CTRL_BASE BSP_MS_I_DRAMC_0_BASE
#define MS_0_CTRL_PHY_BASE (BSP_MS_I_DRAMC_0_BASE)
#define MS_0_WRAP_BASE (MS_0_CTRL_BASE + 0x200)
#define MS_1_CTRL_BASE BSP_MS_I_DRAMC_1_BASE
#define MS_1_CTRL_PHY_BASE (BSP_MS_I_DRAMC_1_BASE)
#define MS_1_WRAP_BASE (MS_1_CTRL_BASE + 0x200)
#define MS_PCTL_CCR_OFFSET 0x000
#define MS_PCTL_DCR_OFFSET 0x004
#define MS_PCTL_IOCR_OFFSET 0x008
#define MS_PCTL_CSR_OFFSET 0x00c
#define MS_PCTL_DRR_OFFSET 0x010
#define MS_PCTL_TPR0_OFFSET 0x014
#define MS_PCTL_TPR1_OFFSET 0x018
#define MS_PCTL_TPR2_OFFSET 0x01c
#define MS_PCTL_MR_OFFSET 0x020
#define MS_PCTL_EMR1_OFFSET 0x024
#define MS_PCTL_EMR2_OFFSET 0x028
#define MS_PCTL_EMR3_OFFSET 0x02c
#define MS_PCTL_CSR2_OFFSET 0x030
#define MS_PCTL_SRST_OFFSET 0x034
#define MS_PCTL_DTR2_OFFSET 0x038
#define MS_PCTL_DTR3_OFFSET 0x03c
#define MS_PCTL_GDLLCR_OFFSET 0x040
#define MS_PCTL_DLLCR0_OFFSET 0x044
#define MS_PCTL_DLLCR1_OFFSET 0x048
#define MS_PCTL_DLLCR2_OFFSET 0x04c
#define MS_PCTL_DLLCR3_OFFSET 0x050
#define MS_PCTL_DLLCR4_OFFSET 0x054
#define MS_PCTL_DLLCR5_OFFSET 0x058
#define MS_PCTL_DLLCR6_OFFSET 0x05c
#define MS_PCTL_DLLCR7_OFFSET 0x060
#define MS_PCTL_DLLCR8_OFFSET 0x064
#define MS_PCTL_DQTR0_OFFSET 0x068
#define MS_PCTL_DQTR1_OFFSET 0x06c
#define MS_PCTL_DQTR2_OFFSET 0x070
#define MS_PCTL_DQTR3_OFFSET 0x074
#define MS_PCTL_DQTR4_OFFSET 0x078
#define MS_PCTL_DQTR5_OFFSET 0x07c
#define MS_PCTL_DQTR6_OFFSET 0x080
#define MS_PCTL_DQTR7_OFFSET 0x084
#define MS_PCTL_DQSTR_OFFSET 0x088
#define MS_PCTL_DQSBTR_OFFSET 0x08c
#define MS_PCTL_ODTCR_OFFSET 0x090
#define MS_PCTL_DTR0_OFFSET 0x094
#define MS_PCTL_DTR1_OFFSET 0x098
#define MS_PCTL_DTAR_OFFSET 0x09c
#define MS_PCTL_ZQCR0_OFFSET 0x0a0
#define MS_PCTL_ZQCR1_OFFSET 0x0a4
#define MS_PCTL_ZQSR_OFFSET 0x0a8
#define MS_PCTL_RSLR0_OFFSET 0x0ac
#define MS_PCTL_RSLR1_OFFSET 0x0b0
#define MS_PCTL_RSLR2_OFFSET 0x0b4
#define MS_PCTL_RSLR3_OFFSET 0x0b8
#define MS_PCTL_RDGR0_OFFSET 0x0bc
#define MS_PCTL_RDGR1_OFFSET 0x0c0
#define MS_PCTL_RDGR2_OFFSET 0x0c4
#define MS_PCTL_RDGR3_OFFSET 0x0c8
#define MS_PCTL_MXSL_OFFSET 0x0cc
#define MS_PCTL_BCR_OFFSET 0x0d0
#define MS_PCTL_BALR0_OFFSET 0x0d4
#define MS_PCTL_BALR1_OFFSET 0x0d8
#define MS_PCTL_BDR0_OFFSET 0x0dc
#define MS_PCTL_BDR1_OFFSET 0x0e0
#define MS_PCTL_BBR_OFFSET 0x0e4
#define MS_PCTL_BSR_OFFSET 0x0e8
#define MS_PCTL_BYR_OFFSET 0x0ec
#define MS_PCTL_BFA_OFFSET 0x0f0
#define MS_PCTL_IDR_OFFSET 0x0f8
#define MS_PCTL_ERR_OFFSET 0x0fc
#define MS_WRAP_SCR_OFFSET 0x224
#define MS_WRAP_QCR_OFFSET 0x230
#define MS_WRAP_PCR_OFFSET 0x234
#define MS_WRAP_QTR0_OFFSET 0x240
#define MS_WRAP_QTR1_OFFSET 0x244
#define MS_WRAP_QTR2_OFFSET 0x248
#define MS_WRAP_QTR3_OFFSET 0x24c
#define MS_WRAP_QTR4_OFFSET 0x250
#define MS_WRAP_QTR5_OFFSET 0x254
#define MS_WRAP_QTR6_OFFSET 0x258
#define MS_WRAP_QTR7_OFFSET 0x25c
#define MS_WRAP_QTR8_OFFSET 0x260
#define MS_WRAP_QTR9_OFFSET 0x264
#define MS_WRAP_QTR10_OFFSET 0x268
#define MS_WRAP_QTR11_OFFSET 0x26c
#define MS_WRAP_QTR12_OFFSET 0x270
#define MS_WRAP_QTR13_OFFSET 0x274
#define MS_WRAP_QTR14_OFFSET 0x278
#define MS_WRAP_QTR15_OFFSET 0x27c
#define MS_PHY_DLY0 0x100
#define MS_PHY_DLY1_RST 0x104
#define MS_PHY_DLY_CLK 0x108
#define MS_PHY_DLY_ST 0x10c
#define MS_PHY_DLY_NUM 0x100
#define PCTL_CCR_INIT_BFO 0
#define PCTL_CCR_INIT_BFW 1
#define PCTL_CCR_DTT_BFO 1
#define PCTL_CCR_DTT_BFW 1
#define PCTL_CCR_BTT_BFO 2
#define PCTL_CCR_BTT_BFW 1
#define PCTL_CCR_DPIT_BFO 3
#define PCTL_CCR_DPIT_BFW 1
#define PCTL_CCR_FLUSH_FIFO_BFO 8
#define PCTL_CCR_FLUSH_FIFO_BFW 1
#define PCTL_DCR_DDR3_BFO 0
#define PCTL_DCR_DDR3_BFW 1
#define PCTL_DCR_SDR_BFO 1
#define PCTL_DCR_SDR_BFW 1
#define PCTL_DCR_DQ32_BFO 4
#define PCTL_DCR_DQ32_BFW 1
#define PCTL_DCR_DFI_RATE_BFO 8
#define PCTL_DCR_DFI_RATE_BFW 3
#define PCTL_IOCR_RD_PIPE_BFO 8
#define PCTL_IOCR_RD_PIPE_BFW 4
#define PCTL_IOCR_TPHY_WD_BFO 12
#define PCTL_IOCR_TPHY_WD_BFW 5
#define PCTL_IOCR_TPHY_WL_BFO 17
#define PCTL_IOCR_TPHY_WL_BFW 3
#define PCTL_IOCR_TPHY_RD_EN_BFO 20
#define PCTL_IOCR_TPHY_RD_EN_BFW 5
#define PCTL_CSR_MEM_IDLE_BFO 8
#define PCTL_CSR_MEM_IDLE_BFW 1
#define PCTL_CSR_DT_IDLE_BFO 9
#define PCTL_CSR_DT_IDLE_BFW 1
#define PCTL_CSR_BIST_IDLE_BFO 10
#define PCTL_CSR_BIST_IDLE_BFW 1
#define PCTL_CSR_DT_FAIL_BFO 11
#define PCTL_CSR_DT_FAIL_BFW 1
#define PCTL_CSR_BT_FAIL_BFO 12
#define PCTL_CSR_BT_FAIL_BFW 1
#define PCTL_DRR_TRFC_BFO 0
#define PCTL_DRR_TRFC_BFW 7
#define PCTL_DRR_TREF_BFO 8
#define PCTL_DRR_TREF_BFW 24
#define PCTL_DRR_REF_NUM_BFO 24
#define PCTL_DRR_REF_NUM_BFW 4
#define PCTL_DRR_REF_DIS_BFO 28
#define PCTL_DRR_REF_DIS_BFW 1
#define PCTL_TPR0_TRP_BFO 0
#define PCTL_TPR0_TRP_BFW 4
#define PCTL_TPR0_TRAS_BFO 4
#define PCTL_TPR0_TRAS_BFW 5
#define PCTL_TPR0_TWR_BFO 9
#define PCTL_TPR0_TWR_BFW 4
#define PCTL_TPR0_TRTP_BFO 13
#define PCTL_TPR0_TRTP_BFW 3
#define PCTL_TPR1_TRRD_BFO 0
#define PCTL_TPR1_TRRD_BFW 4
#define PCTL_TPR1_TRC_BFO 4
#define PCTL_TPR1_TRC_BFW 6
#define PCTL_TPR1_TRCD_BFO 10
#define PCTL_TPR1_TRCD_BFW 4
#define PCTL_TPR1_TCCD_BFO 14
#define PCTL_TPR1_TCCD_BFW 3
#define PCTL_TPR1_TWTR_BFO 17
#define PCTL_TPR1_TWTR_BFW 3
#define PCTL_TPR1_TRTW_BFO 20
#define PCTL_TPR1_TRTW_BFW 4
#define PCTL_TPR2_INIT_REF_NUM_BFO 0
#define PCTL_TPR2_INIT_REF_NUM_BFW 4
#define PCTL_TPR2_INIT_NS_EN_BFO 4
#define PCTL_TPR2_INIT_NS_EN_BFW 1
#define PCTL_TPR2_TMRD_BFO 5
#define PCTL_TPR2_TMRD_BFW 2
#define PCTL_MR_BL_BFO 0
#define PCTL_MR_BL_BFW 3
#define PCTL_MR_BT_BFO 3
#define PCTL_MR_BT_BFW 1
#define PCTL_MR_CAS_BFO 4
#define PCTL_MR_CAS_BFW 3
#define PCTL_MR_OP_BFO 8
#define PCTL_MR_OP_BFW 12
#define PCTL_EMR1_ADDLAT_BFO 3
#define PCTL_EMR1_ADDLAT_BFW 3
#define PCTL_CMD_DPIN_RSTN_BFO 0
#define PCTL_CMD_DPIN_RSTN_BFW 1
#define PCTL_CMD_DPIN_CKE_BFO 1
#define PCTL_CMD_DPIN_CKE_BFW 1
#define PCTL_CMD_DPIN_ODT_BFO 2
#define PCTL_CMD_DPIN_ODT_BFW 1
#define PCTL_BCR_STOP_BFO 0
#define PCTL_BCR_STOP_BFW 1
#define PCTL_BCR_CMP_BFO 1
#define PCTL_BCR_CMP_BFW 1
#define PCTL_BCR_LOOP_BFO 2
#define PCTL_BCR_LOOP_BFW 1
#define PCTL_BCR_DIS_MASK_BFO 3
#define PCTL_BCR_DIS_MASK_BFW 1
#define PCTL_BCR_AT_STOP_BFO 4
#define PCTL_BCR_AT_STOP_BFW 1
#define PCTL_BCR_FLUSH_CMD_BFO 8
#define PCTL_BCR_FLUSH_CMD_BFW 1
#define PCTL_BCR_FLUSH_WD_BFO 9
#define PCTL_BCR_FLUSH_WD_BFW 1
#define PCTL_BCR_FLUSH_RGD_BFO 10
#define PCTL_BCR_FLUSH_RGD_BFW 1
#define PCTL_BCR_FLUSH_RD_BFO 11
#define PCTL_BCR_FLUSH_RD_BFW 1
#define PCTL_BCR_FLUSH_RD_EXPC_BFO 16
#define PCTL_BCR_FLUSH_RD_EXPC_BFW 14
#define PCTL_BST_ERR_FST_TH_BFO 0
#define PCTL_BST_ERR_FST_TH_BFW 12
#define PCTL_BST_ERR_CNT_BFO 16
#define PCTL_BST_ERR_CNT_BFW 14
#define PCTL_BSRAM0_CMD_LEVEL_BFO 0
#define PCTL_BSRAM0_CMD_LEVEL_BFW 12
#define PCTL_BSRAM0_WD_LEVEL_BFO 16
#define PCTL_BSRAM0_WD_LEVEL_BFW 14
#define PCTL_BSRAM1_RG_LEVEL_BFO 0
#define PCTL_BSRAM1_RG_LEVEL_BFW 14
#define PCTL_BSRAM1_RD_LEVEL_BFO 16
#define PCTL_BSRAM1_RD_LEVEL_BFW 14
#define WRAP_MISC_PAGE_SIZE_BFO 0
#define WRAP_MISC_PAGE_SIZE_BFW 4
#define WRAP_MISC_BANK_SIZE_BFO 4
#define WRAP_MISC_BANK_SIZE_BFW 2
#define WRAP_MISC_BST_SIZE_BFO 6
#define WRAP_MISC_BST_SIZE_BFW 2
#define WRAP_MISC_DDR_PARAL_BFO 8
#define WRAP_MISC_DDR_PARAL_BFW 1
struct ms_rxi310_portmap {
volatile unsigned int ccr; /* 0x000 */
volatile unsigned int dcr; /* 0x004 */
volatile unsigned int iocr; /* 0x008 */
volatile unsigned int csr; /* 0x00c */
volatile unsigned int drr; /* 0x010 */
volatile unsigned int tpr0; /* 0x014 */
volatile unsigned int tpr1; /* 0x018 */
volatile unsigned int tpr2; /* 0x01c */
volatile unsigned int mr; /* 0x020 */
volatile unsigned int emr1; /* 0x024 */
volatile unsigned int emr2; /* 0x028 */
volatile unsigned int emr3; /* 0x02c */
volatile unsigned int cdpin; /* 0x030 */
volatile unsigned int tdpin; /* 0x034 */
volatile unsigned int dtr2; /* 0x038 */
volatile unsigned int dtr3; /* 0x03c */
volatile unsigned int gdllcr; /* 0x040 */
volatile unsigned int dllcr0; /* 0x044 */
volatile unsigned int dllcr1; /* 0x048 */
volatile unsigned int dllcr2; /* 0x04c */
volatile unsigned int dllcr3; /* 0x050 */
volatile unsigned int dllcr4; /* 0x054 */
volatile unsigned int dllcr5; /* 0x058 */
volatile unsigned int dllcr6; /* 0x05c */
volatile unsigned int dllcr7; /* 0x060 */
volatile unsigned int dllcr8; /* 0x064 */
volatile unsigned int dqtr0; /* 0x068 */
volatile unsigned int dqtr1; /* 0x06c */
volatile unsigned int dqtr2; /* 0x070 */
volatile unsigned int dqtr3; /* 0x074 */
volatile unsigned int dqtr4; /* 0x078 */
volatile unsigned int dqtr5; /* 0x07c */
volatile unsigned int dqtr6; /* 0x080 */
volatile unsigned int dqtr7; /* 0x084 */
volatile unsigned int dqstr; /* 0x088 */
volatile unsigned int dqsbtr; /* 0x08c */
volatile unsigned int odtcr; /* 0x090 */
volatile unsigned int dtr0; /* 0x094 */
volatile unsigned int dtr1; /* 0x098 */
volatile unsigned int dtar; /* 0x09c */
volatile unsigned int zqcr0; /* 0x0a0 */
volatile unsigned int zqcr1; /* 0x0a4 */
volatile unsigned int zqsr; /* 0x0a8 */
volatile unsigned int rslr0; /* 0x0ac */
volatile unsigned int rslr1; /* 0x0b0 */
volatile unsigned int rslr2; /* 0x0b4 */
volatile unsigned int rslr3; /* 0x0b8 */
volatile unsigned int rdgr0; /* 0x0bc */
volatile unsigned int rdgr1; /* 0x0c0 */
volatile unsigned int rdgr2; /* 0x0c4 */
volatile unsigned int rdgr3; /* 0x0c8 */
volatile unsigned int mxsl; /* 0x0cc */
volatile unsigned int bcr; /* 0x0d0 */
volatile unsigned int bst; /* 0x0d4 */
volatile unsigned int bsram0; /* 0x0d8 */
volatile unsigned int bsram1; /* 0x0dc */
volatile unsigned int bdr1; /* 0x0e0 */
volatile unsigned int bbr; /* 0x0e4 */
volatile unsigned int bsr; /* 0x0e8 */
volatile unsigned int byr; /* 0x0ec */
volatile unsigned int bfa; /* 0x0f0 */
volatile unsigned int pctl_svn; /* 0x0f4 */
volatile unsigned int pctl_idr; /* 0x0f8 */
volatile unsigned int err; /* 0x0fc */
// SDR_PHY CONTROL REGISTER
volatile unsigned int phy_dly0; /* 0x100 */
volatile unsigned int phy_dly1_rst; /* 0x104 */
volatile unsigned int phy_dly_clk; /* 0x108 */
volatile unsigned int phy_dly_st; /* 0x10c */
volatile unsigned int phy_dly_num; /* 0x110 */
volatile unsigned int reserved0[68];
// WRAP CONTROL REGISTER
volatile unsigned int misc; /* 0x224 */
volatile unsigned int cq_ver; /* 0x228 */
volatile unsigned int cq_mon; /* 0x22c */
volatile unsigned int wq_ver; /* 0x230 */
volatile unsigned int wq_mon; /* 0x234 */
volatile unsigned int rq_ver; /* 0x240 */
volatile unsigned int rq_mon; /* 0x244 */
volatile unsigned int reserved1[22];
volatile unsigned int wwrap_idr; /* 0x2a0 */
volatile unsigned int wrap_svn; /* 0x2a4 */
}; //ms_rxi310_portmap
#define QFIFO_CMD_BANK_BFO (35 - QFIFO_CMD_WRRD_BFO) // [38:35]
#define QFIFO_CMD_BANK_BFW 4
#define QFIFO_CMD_PAGE_BFO (20 - QFIFO_CMD_WRRD_BFO) // [34:20]
#define QFIFO_CMD_PAGE_BFW 15
#define QFIFO_CMD_COLU_BFO (7 - QFIFO_CMD_WRRD_BFO) // [19: 7]
#define QFIFO_CMD_COLU_BFW 13 // [19: 7]
#define QFIFO_BST_LEN_BFO (3 - QFIFO_CMD_WRRD_BFO) // [6:3]
#define QFIFO_BST_LEN_BFW 4 // [6:3]
#define QFIFO_CMD_WRRD_BFO 2 // [2], remove bit[1:0]
#define QFIFO_CMD_WRRD_BFW 1 // [2], remove bit[1:0]
//====================================================//
#define REG_SDR_CCR 0x00
#define REG_SDR_DCR 0x04
#define REG_SDR_IOCR 0x08
#define REG_SDR_CSR 0x0C
#define REG_SDR_DRR 0x10
#define REG_SDR_TPR0 0x14
#define REG_SDR_TPR1 0x18
#define REG_SDR_TPR2 0x1C
#define REG_SDR_MR 0x20
#define REG_SDR_EMR1 0x24
#define REG_SDR_EMR2 0x28
#define REG_SDR_EMR3 0x2C
#define REG_SDR_CMD_DPIN 0x30
#define REG_SDR_TIE_DPIN 0x34
#define REG_SDR_BCR 0xD0
#define REG_SDR_BST 0xD4
#define REG_SDR_BSRAM0 0xD8
#define REG_SDR_BSRAM1 0xDC
#define REG_SDR_PCTL_SVN_ID 0xF4
#define REG_SDR_PCTL_IDR 0xF8
#define REG_SDR_DLY0 0x100
#define REG_SDR_DLY1 0x104
#define REG_SDR_DCM_RST 0x104
#define REG_SDR_DLY_CLK_PHA 0x108
#define REG_SDR_DLY_ST 0x10C
#define REG_SDR_MISC 0x224
#define REG_SDR_OCP_WRAP_IDR 0x2A0
#define REG_SDR_OCP_WRAP_VERSION 0x2A4
#endif // end of "#ifndef _RTL8195A_SDR_H"
#ifndef _RTL8195A_SDR_H
#define _RTL8195A_SDR_H
#define MS_0_CTRL_BASE BSP_MS_I_DRAMC_0_BASE
#define MS_0_CTRL_PHY_BASE (BSP_MS_I_DRAMC_0_BASE)
#define MS_0_WRAP_BASE (MS_0_CTRL_BASE + 0x200)
#define MS_1_CTRL_BASE BSP_MS_I_DRAMC_1_BASE
#define MS_1_CTRL_PHY_BASE (BSP_MS_I_DRAMC_1_BASE)
#define MS_1_WRAP_BASE (MS_1_CTRL_BASE + 0x200)
#define MS_PCTL_CCR_OFFSET 0x000
#define MS_PCTL_DCR_OFFSET 0x004
#define MS_PCTL_IOCR_OFFSET 0x008
#define MS_PCTL_CSR_OFFSET 0x00c
#define MS_PCTL_DRR_OFFSET 0x010
#define MS_PCTL_TPR0_OFFSET 0x014
#define MS_PCTL_TPR1_OFFSET 0x018
#define MS_PCTL_TPR2_OFFSET 0x01c
#define MS_PCTL_MR_OFFSET 0x020
#define MS_PCTL_EMR1_OFFSET 0x024
#define MS_PCTL_EMR2_OFFSET 0x028
#define MS_PCTL_EMR3_OFFSET 0x02c
#define MS_PCTL_CSR2_OFFSET 0x030
#define MS_PCTL_SRST_OFFSET 0x034
#define MS_PCTL_DTR2_OFFSET 0x038
#define MS_PCTL_DTR3_OFFSET 0x03c
#define MS_PCTL_GDLLCR_OFFSET 0x040
#define MS_PCTL_DLLCR0_OFFSET 0x044
#define MS_PCTL_DLLCR1_OFFSET 0x048
#define MS_PCTL_DLLCR2_OFFSET 0x04c
#define MS_PCTL_DLLCR3_OFFSET 0x050
#define MS_PCTL_DLLCR4_OFFSET 0x054
#define MS_PCTL_DLLCR5_OFFSET 0x058
#define MS_PCTL_DLLCR6_OFFSET 0x05c
#define MS_PCTL_DLLCR7_OFFSET 0x060
#define MS_PCTL_DLLCR8_OFFSET 0x064
#define MS_PCTL_DQTR0_OFFSET 0x068
#define MS_PCTL_DQTR1_OFFSET 0x06c
#define MS_PCTL_DQTR2_OFFSET 0x070
#define MS_PCTL_DQTR3_OFFSET 0x074
#define MS_PCTL_DQTR4_OFFSET 0x078
#define MS_PCTL_DQTR5_OFFSET 0x07c
#define MS_PCTL_DQTR6_OFFSET 0x080
#define MS_PCTL_DQTR7_OFFSET 0x084
#define MS_PCTL_DQSTR_OFFSET 0x088
#define MS_PCTL_DQSBTR_OFFSET 0x08c
#define MS_PCTL_ODTCR_OFFSET 0x090
#define MS_PCTL_DTR0_OFFSET 0x094
#define MS_PCTL_DTR1_OFFSET 0x098
#define MS_PCTL_DTAR_OFFSET 0x09c
#define MS_PCTL_ZQCR0_OFFSET 0x0a0
#define MS_PCTL_ZQCR1_OFFSET 0x0a4
#define MS_PCTL_ZQSR_OFFSET 0x0a8
#define MS_PCTL_RSLR0_OFFSET 0x0ac
#define MS_PCTL_RSLR1_OFFSET 0x0b0
#define MS_PCTL_RSLR2_OFFSET 0x0b4
#define MS_PCTL_RSLR3_OFFSET 0x0b8
#define MS_PCTL_RDGR0_OFFSET 0x0bc
#define MS_PCTL_RDGR1_OFFSET 0x0c0
#define MS_PCTL_RDGR2_OFFSET 0x0c4
#define MS_PCTL_RDGR3_OFFSET 0x0c8
#define MS_PCTL_MXSL_OFFSET 0x0cc
#define MS_PCTL_BCR_OFFSET 0x0d0
#define MS_PCTL_BALR0_OFFSET 0x0d4
#define MS_PCTL_BALR1_OFFSET 0x0d8
#define MS_PCTL_BDR0_OFFSET 0x0dc
#define MS_PCTL_BDR1_OFFSET 0x0e0
#define MS_PCTL_BBR_OFFSET 0x0e4
#define MS_PCTL_BSR_OFFSET 0x0e8
#define MS_PCTL_BYR_OFFSET 0x0ec
#define MS_PCTL_BFA_OFFSET 0x0f0
#define MS_PCTL_IDR_OFFSET 0x0f8
#define MS_PCTL_ERR_OFFSET 0x0fc
#define MS_WRAP_SCR_OFFSET 0x224
#define MS_WRAP_QCR_OFFSET 0x230
#define MS_WRAP_PCR_OFFSET 0x234
#define MS_WRAP_QTR0_OFFSET 0x240
#define MS_WRAP_QTR1_OFFSET 0x244
#define MS_WRAP_QTR2_OFFSET 0x248
#define MS_WRAP_QTR3_OFFSET 0x24c
#define MS_WRAP_QTR4_OFFSET 0x250
#define MS_WRAP_QTR5_OFFSET 0x254
#define MS_WRAP_QTR6_OFFSET 0x258
#define MS_WRAP_QTR7_OFFSET 0x25c
#define MS_WRAP_QTR8_OFFSET 0x260
#define MS_WRAP_QTR9_OFFSET 0x264
#define MS_WRAP_QTR10_OFFSET 0x268
#define MS_WRAP_QTR11_OFFSET 0x26c
#define MS_WRAP_QTR12_OFFSET 0x270
#define MS_WRAP_QTR13_OFFSET 0x274
#define MS_WRAP_QTR14_OFFSET 0x278
#define MS_WRAP_QTR15_OFFSET 0x27c
#define MS_PHY_DLY0 0x100
#define MS_PHY_DLY1_RST 0x104
#define MS_PHY_DLY_CLK 0x108
#define MS_PHY_DLY_ST 0x10c
#define MS_PHY_DLY_NUM 0x100
#define PCTL_CCR_INIT_BFO 0
#define PCTL_CCR_INIT_BFW 1
#define PCTL_CCR_DTT_BFO 1
#define PCTL_CCR_DTT_BFW 1
#define PCTL_CCR_BTT_BFO 2
#define PCTL_CCR_BTT_BFW 1
#define PCTL_CCR_DPIT_BFO 3
#define PCTL_CCR_DPIT_BFW 1
#define PCTL_CCR_FLUSH_FIFO_BFO 8
#define PCTL_CCR_FLUSH_FIFO_BFW 1
#define PCTL_DCR_DDR3_BFO 0
#define PCTL_DCR_DDR3_BFW 1
#define PCTL_DCR_SDR_BFO 1
#define PCTL_DCR_SDR_BFW 1
#define PCTL_DCR_DQ32_BFO 4
#define PCTL_DCR_DQ32_BFW 1
#define PCTL_DCR_DFI_RATE_BFO 8
#define PCTL_DCR_DFI_RATE_BFW 3
#define PCTL_IOCR_RD_PIPE_BFO 8
#define PCTL_IOCR_RD_PIPE_BFW 4
#define PCTL_IOCR_TPHY_WD_BFO 12
#define PCTL_IOCR_TPHY_WD_BFW 5
#define PCTL_IOCR_TPHY_WL_BFO 17
#define PCTL_IOCR_TPHY_WL_BFW 3
#define PCTL_IOCR_TPHY_RD_EN_BFO 20
#define PCTL_IOCR_TPHY_RD_EN_BFW 5
#define PCTL_CSR_MEM_IDLE_BFO 8
#define PCTL_CSR_MEM_IDLE_BFW 1
#define PCTL_CSR_DT_IDLE_BFO 9
#define PCTL_CSR_DT_IDLE_BFW 1
#define PCTL_CSR_BIST_IDLE_BFO 10
#define PCTL_CSR_BIST_IDLE_BFW 1
#define PCTL_CSR_DT_FAIL_BFO 11
#define PCTL_CSR_DT_FAIL_BFW 1
#define PCTL_CSR_BT_FAIL_BFO 12
#define PCTL_CSR_BT_FAIL_BFW 1
#define PCTL_DRR_TRFC_BFO 0
#define PCTL_DRR_TRFC_BFW 7
#define PCTL_DRR_TREF_BFO 8
#define PCTL_DRR_TREF_BFW 24
#define PCTL_DRR_REF_NUM_BFO 24
#define PCTL_DRR_REF_NUM_BFW 4
#define PCTL_DRR_REF_DIS_BFO 28
#define PCTL_DRR_REF_DIS_BFW 1
#define PCTL_TPR0_TRP_BFO 0
#define PCTL_TPR0_TRP_BFW 4
#define PCTL_TPR0_TRAS_BFO 4
#define PCTL_TPR0_TRAS_BFW 5
#define PCTL_TPR0_TWR_BFO 9
#define PCTL_TPR0_TWR_BFW 4
#define PCTL_TPR0_TRTP_BFO 13
#define PCTL_TPR0_TRTP_BFW 3
#define PCTL_TPR1_TRRD_BFO 0
#define PCTL_TPR1_TRRD_BFW 4
#define PCTL_TPR1_TRC_BFO 4
#define PCTL_TPR1_TRC_BFW 6
#define PCTL_TPR1_TRCD_BFO 10
#define PCTL_TPR1_TRCD_BFW 4
#define PCTL_TPR1_TCCD_BFO 14
#define PCTL_TPR1_TCCD_BFW 3
#define PCTL_TPR1_TWTR_BFO 17
#define PCTL_TPR1_TWTR_BFW 3
#define PCTL_TPR1_TRTW_BFO 20
#define PCTL_TPR1_TRTW_BFW 4
#define PCTL_TPR2_INIT_REF_NUM_BFO 0
#define PCTL_TPR2_INIT_REF_NUM_BFW 4
#define PCTL_TPR2_INIT_NS_EN_BFO 4
#define PCTL_TPR2_INIT_NS_EN_BFW 1
#define PCTL_TPR2_TMRD_BFO 5
#define PCTL_TPR2_TMRD_BFW 2
#define PCTL_MR_BL_BFO 0
#define PCTL_MR_BL_BFW 3
#define PCTL_MR_BT_BFO 3
#define PCTL_MR_BT_BFW 1
#define PCTL_MR_CAS_BFO 4
#define PCTL_MR_CAS_BFW 3
#define PCTL_MR_OP_BFO 8
#define PCTL_MR_OP_BFW 12
#define PCTL_EMR1_ADDLAT_BFO 3
#define PCTL_EMR1_ADDLAT_BFW 3
#define PCTL_CMD_DPIN_RSTN_BFO 0
#define PCTL_CMD_DPIN_RSTN_BFW 1
#define PCTL_CMD_DPIN_CKE_BFO 1
#define PCTL_CMD_DPIN_CKE_BFW 1
#define PCTL_CMD_DPIN_ODT_BFO 2
#define PCTL_CMD_DPIN_ODT_BFW 1
#define PCTL_BCR_STOP_BFO 0
#define PCTL_BCR_STOP_BFW 1
#define PCTL_BCR_CMP_BFO 1
#define PCTL_BCR_CMP_BFW 1
#define PCTL_BCR_LOOP_BFO 2
#define PCTL_BCR_LOOP_BFW 1
#define PCTL_BCR_DIS_MASK_BFO 3
#define PCTL_BCR_DIS_MASK_BFW 1
#define PCTL_BCR_AT_STOP_BFO 4
#define PCTL_BCR_AT_STOP_BFW 1
#define PCTL_BCR_FLUSH_CMD_BFO 8
#define PCTL_BCR_FLUSH_CMD_BFW 1
#define PCTL_BCR_FLUSH_WD_BFO 9
#define PCTL_BCR_FLUSH_WD_BFW 1
#define PCTL_BCR_FLUSH_RGD_BFO 10
#define PCTL_BCR_FLUSH_RGD_BFW 1
#define PCTL_BCR_FLUSH_RD_BFO 11
#define PCTL_BCR_FLUSH_RD_BFW 1
#define PCTL_BCR_FLUSH_RD_EXPC_BFO 16
#define PCTL_BCR_FLUSH_RD_EXPC_BFW 14
#define PCTL_BST_ERR_FST_TH_BFO 0
#define PCTL_BST_ERR_FST_TH_BFW 12
#define PCTL_BST_ERR_CNT_BFO 16
#define PCTL_BST_ERR_CNT_BFW 14
#define PCTL_BSRAM0_CMD_LEVEL_BFO 0
#define PCTL_BSRAM0_CMD_LEVEL_BFW 12
#define PCTL_BSRAM0_WD_LEVEL_BFO 16
#define PCTL_BSRAM0_WD_LEVEL_BFW 14
#define PCTL_BSRAM1_RG_LEVEL_BFO 0
#define PCTL_BSRAM1_RG_LEVEL_BFW 14
#define PCTL_BSRAM1_RD_LEVEL_BFO 16
#define PCTL_BSRAM1_RD_LEVEL_BFW 14
#define WRAP_MISC_PAGE_SIZE_BFO 0
#define WRAP_MISC_PAGE_SIZE_BFW 4
#define WRAP_MISC_BANK_SIZE_BFO 4
#define WRAP_MISC_BANK_SIZE_BFW 2
#define WRAP_MISC_BST_SIZE_BFO 6
#define WRAP_MISC_BST_SIZE_BFW 2
#define WRAP_MISC_DDR_PARAL_BFO 8
#define WRAP_MISC_DDR_PARAL_BFW 1
struct ms_rxi310_portmap {
volatile unsigned int ccr; /* 0x000 */
volatile unsigned int dcr; /* 0x004 */
volatile unsigned int iocr; /* 0x008 */
volatile unsigned int csr; /* 0x00c */
volatile unsigned int drr; /* 0x010 */
volatile unsigned int tpr0; /* 0x014 */
volatile unsigned int tpr1; /* 0x018 */
volatile unsigned int tpr2; /* 0x01c */
volatile unsigned int mr; /* 0x020 */
volatile unsigned int emr1; /* 0x024 */
volatile unsigned int emr2; /* 0x028 */
volatile unsigned int emr3; /* 0x02c */
volatile unsigned int cdpin; /* 0x030 */
volatile unsigned int tdpin; /* 0x034 */
volatile unsigned int dtr2; /* 0x038 */
volatile unsigned int dtr3; /* 0x03c */
volatile unsigned int gdllcr; /* 0x040 */
volatile unsigned int dllcr0; /* 0x044 */
volatile unsigned int dllcr1; /* 0x048 */
volatile unsigned int dllcr2; /* 0x04c */
volatile unsigned int dllcr3; /* 0x050 */
volatile unsigned int dllcr4; /* 0x054 */
volatile unsigned int dllcr5; /* 0x058 */
volatile unsigned int dllcr6; /* 0x05c */
volatile unsigned int dllcr7; /* 0x060 */
volatile unsigned int dllcr8; /* 0x064 */
volatile unsigned int dqtr0; /* 0x068 */
volatile unsigned int dqtr1; /* 0x06c */
volatile unsigned int dqtr2; /* 0x070 */
volatile unsigned int dqtr3; /* 0x074 */
volatile unsigned int dqtr4; /* 0x078 */
volatile unsigned int dqtr5; /* 0x07c */
volatile unsigned int dqtr6; /* 0x080 */
volatile unsigned int dqtr7; /* 0x084 */
volatile unsigned int dqstr; /* 0x088 */
volatile unsigned int dqsbtr; /* 0x08c */
volatile unsigned int odtcr; /* 0x090 */
volatile unsigned int dtr0; /* 0x094 */
volatile unsigned int dtr1; /* 0x098 */
volatile unsigned int dtar; /* 0x09c */
volatile unsigned int zqcr0; /* 0x0a0 */
volatile unsigned int zqcr1; /* 0x0a4 */
volatile unsigned int zqsr; /* 0x0a8 */
volatile unsigned int rslr0; /* 0x0ac */
volatile unsigned int rslr1; /* 0x0b0 */
volatile unsigned int rslr2; /* 0x0b4 */
volatile unsigned int rslr3; /* 0x0b8 */
volatile unsigned int rdgr0; /* 0x0bc */
volatile unsigned int rdgr1; /* 0x0c0 */
volatile unsigned int rdgr2; /* 0x0c4 */
volatile unsigned int rdgr3; /* 0x0c8 */
volatile unsigned int mxsl; /* 0x0cc */
volatile unsigned int bcr; /* 0x0d0 */
volatile unsigned int bst; /* 0x0d4 */
volatile unsigned int bsram0; /* 0x0d8 */
volatile unsigned int bsram1; /* 0x0dc */
volatile unsigned int bdr1; /* 0x0e0 */
volatile unsigned int bbr; /* 0x0e4 */
volatile unsigned int bsr; /* 0x0e8 */
volatile unsigned int byr; /* 0x0ec */
volatile unsigned int bfa; /* 0x0f0 */
volatile unsigned int pctl_svn; /* 0x0f4 */
volatile unsigned int pctl_idr; /* 0x0f8 */
volatile unsigned int err; /* 0x0fc */
// SDR_PHY CONTROL REGISTER
volatile unsigned int phy_dly0; /* 0x100 */
volatile unsigned int phy_dly1_rst; /* 0x104 */
volatile unsigned int phy_dly_clk; /* 0x108 */
volatile unsigned int phy_dly_st; /* 0x10c */
volatile unsigned int phy_dly_num; /* 0x110 */
volatile unsigned int reserved0[68];
// WRAP CONTROL REGISTER
volatile unsigned int misc; /* 0x224 */
volatile unsigned int cq_ver; /* 0x228 */
volatile unsigned int cq_mon; /* 0x22c */
volatile unsigned int wq_ver; /* 0x230 */
volatile unsigned int wq_mon; /* 0x234 */
volatile unsigned int rq_ver; /* 0x240 */
volatile unsigned int rq_mon; /* 0x244 */
volatile unsigned int reserved1[22];
volatile unsigned int wwrap_idr; /* 0x2a0 */
volatile unsigned int wrap_svn; /* 0x2a4 */
}; //ms_rxi310_portmap
#define QFIFO_CMD_BANK_BFO (35 - QFIFO_CMD_WRRD_BFO) // [38:35]
#define QFIFO_CMD_BANK_BFW 4
#define QFIFO_CMD_PAGE_BFO (20 - QFIFO_CMD_WRRD_BFO) // [34:20]
#define QFIFO_CMD_PAGE_BFW 15
#define QFIFO_CMD_COLU_BFO (7 - QFIFO_CMD_WRRD_BFO) // [19: 7]
#define QFIFO_CMD_COLU_BFW 13 // [19: 7]
#define QFIFO_BST_LEN_BFO (3 - QFIFO_CMD_WRRD_BFO) // [6:3]
#define QFIFO_BST_LEN_BFW 4 // [6:3]
#define QFIFO_CMD_WRRD_BFO 2 // [2], remove bit[1:0]
#define QFIFO_CMD_WRRD_BFW 1 // [2], remove bit[1:0]
//====================================================//
#define REG_SDR_CCR 0x00
#define REG_SDR_DCR 0x04
#define REG_SDR_IOCR 0x08
#define REG_SDR_CSR 0x0C
#define REG_SDR_DRR 0x10
#define REG_SDR_TPR0 0x14
#define REG_SDR_TPR1 0x18
#define REG_SDR_TPR2 0x1C
#define REG_SDR_MR 0x20
#define REG_SDR_EMR1 0x24
#define REG_SDR_EMR2 0x28
#define REG_SDR_EMR3 0x2C
#define REG_SDR_CMD_DPIN 0x30
#define REG_SDR_TIE_DPIN 0x34
#define REG_SDR_BCR 0xD0
#define REG_SDR_BST 0xD4
#define REG_SDR_BSRAM0 0xD8
#define REG_SDR_BSRAM1 0xDC
#define REG_SDR_PCTL_SVN_ID 0xF4
#define REG_SDR_PCTL_IDR 0xF8
#define REG_SDR_DLY0 0x100
#define REG_SDR_DLY1 0x104
#define REG_SDR_DCM_RST 0x104
#define REG_SDR_DLY_CLK_PHA 0x108
#define REG_SDR_DLY_ST 0x10C
#define REG_SDR_MISC 0x224
#define REG_SDR_OCP_WRAP_IDR 0x2A0
#define REG_SDR_OCP_WRAP_VERSION 0x2A4
#endif // end of "#ifndef _RTL8195A_SDR_H"

2286
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h
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1060
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_ssi.h
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File diff suppressed because it is too large Load diff

2186
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h
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514
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h
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@ -1,257 +1,257 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_TIMER_H_
#define _RTL8195A_TIMER_H_
#define TIMER_TICK_US 31
#define TIMER_LOAD_COUNT_OFF 0x00
#define TIMER_CURRENT_VAL_OFF 0x04
#define TIMER_CTL_REG_OFF 0x08
#define TIMER_EOI_OFF 0x0c
#define TIMER_INT_STATUS_OFF 0x10
#define TIMER_INTERVAL 0x14
#define TIMERS_INT_STATUS_OFF 0xa0
#define TIMERS_EOI_OFF 0xa4
#define TIMERS_RAW_INT_STATUS_OFF 0xa8
#define TIMERS_COMP_VER_OFF 0xac
#define MAX_TIMER_VECTOR_TABLE_NUM 6
#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value)
_LONG_CALL_ u32
HalGetTimerIdRtl8195a(
IN u32 *TimerID
);
_LONG_CALL_ BOOL
HalTimerInitRtl8195a(
IN VOID *Data
);
_LONG_CALL_ u32
HalTimerReadCountRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerIrqClearRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDisRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerEnRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDumpRegRtl8195a(
IN u32 TimerId
);
// ROM Code patch
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
);
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
);
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
);
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
);
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
__weak _LONG_CALL_
VOID
HalTimerIrq2To7HandleV02(
IN VOID *Data
);
__weak _LONG_CALL_ROM_
HAL_Status
HalTimerIrqRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
HAL_Status
HalTimerInitRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
u32
HalTimerReadCountRtl8195aV02(
IN u32 TimerId
);
__weak _LONG_CALL_
VOID
HalTimerReLoadRtl8195aV02(
IN u32 TimerId,
IN u32 LoadUs
);
__weak _LONG_CALL_ROM_
HAL_Status
HalTimerIrqUnRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
VOID
HalTimerDeInitRtl8195aV02(
IN VOID *Data
);
#endif // end of "#ifdef CONFIG_CHIP_C_CUT"
#ifdef CONFIG_CHIP_E_CUT
_LONG_CALL_ VOID
HalTimerReLoadRtl8195a_V04(
IN u32 TimerId,
IN u32 LoadUs
);
_LONG_CALL_ HAL_Status
HalTimerInitRtl8195a_V04(
IN VOID *Data
);
#endif // #ifdef CONFIG_CHIP_E_CUT
// HAL functions wrapper
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
static __inline HAL_Status
HalTimerInit(
IN VOID *Data
)
{
#ifdef CONFIG_CHIP_E_CUT
return (HalTimerInitRtl8195a_V04(Data));
#else
return (HalTimerInitRtl8195a_Patch(Data));
#endif
}
static __inline VOID
HalTimerEnable(
IN u32 TimerId
)
{
HalTimerIrqEnRtl8195a(TimerId);
HalTimerEnRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerDisable(
IN u32 TimerId
)
{
HalTimerDisRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerClearIsr(
IN u32 TimerId
)
{
HalTimerClearIsrRtl8195a(TimerId);
}
static __inline VOID
HalTimerReLoad(
IN u32 TimerId,
IN u32 LoadUs
)
{
#ifdef CONFIG_CHIP_E_CUT
HalTimerReLoadRtl8195a_V04(TimerId, LoadUs);
#else
HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs);
#endif
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195a_Patch(Data);
}
#else
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195aV02(Data);
}
#endif // end of "#ifndef CONFIG_CHIP_C_CUT"
#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#endif //_RTL8195A_TIMER_H_
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_TIMER_H_
#define _RTL8195A_TIMER_H_
#define TIMER_TICK_US 31
#define TIMER_LOAD_COUNT_OFF 0x00
#define TIMER_CURRENT_VAL_OFF 0x04
#define TIMER_CTL_REG_OFF 0x08
#define TIMER_EOI_OFF 0x0c
#define TIMER_INT_STATUS_OFF 0x10
#define TIMER_INTERVAL 0x14
#define TIMERS_INT_STATUS_OFF 0xa0
#define TIMERS_EOI_OFF 0xa4
#define TIMERS_RAW_INT_STATUS_OFF 0xa8
#define TIMERS_COMP_VER_OFF 0xac
#define MAX_TIMER_VECTOR_TABLE_NUM 6
#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value)
_LONG_CALL_ u32
HalGetTimerIdRtl8195a(
IN u32 *TimerID
);
_LONG_CALL_ BOOL
HalTimerInitRtl8195a(
IN VOID *Data
);
_LONG_CALL_ u32
HalTimerReadCountRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerIrqClearRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDisRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerEnRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDumpRegRtl8195a(
IN u32 TimerId
);
// ROM Code patch
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
);
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
);
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
);
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
);
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
__weak _LONG_CALL_
VOID
HalTimerIrq2To7HandleV02(
IN VOID *Data
);
__weak _LONG_CALL_ROM_
HAL_Status
HalTimerIrqRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
HAL_Status
HalTimerInitRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
u32
HalTimerReadCountRtl8195aV02(
IN u32 TimerId
);
__weak _LONG_CALL_
VOID
HalTimerReLoadRtl8195aV02(
IN u32 TimerId,
IN u32 LoadUs
);
__weak _LONG_CALL_ROM_
HAL_Status
HalTimerIrqUnRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
VOID
HalTimerDeInitRtl8195aV02(
IN VOID *Data
);
#endif // end of "#ifdef CONFIG_CHIP_C_CUT"
#ifdef CONFIG_CHIP_E_CUT
_LONG_CALL_ VOID
HalTimerReLoadRtl8195a_V04(
IN u32 TimerId,
IN u32 LoadUs
);
_LONG_CALL_ HAL_Status
HalTimerInitRtl8195a_V04(
IN VOID *Data
);
#endif // #ifdef CONFIG_CHIP_E_CUT
// HAL functions wrapper
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
static __inline HAL_Status
HalTimerInit(
IN VOID *Data
)
{
#ifdef CONFIG_CHIP_E_CUT
return (HalTimerInitRtl8195a_V04(Data));
#else
return (HalTimerInitRtl8195a_Patch(Data));
#endif
}
static __inline VOID
HalTimerEnable(
IN u32 TimerId
)
{
HalTimerIrqEnRtl8195a(TimerId);
HalTimerEnRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerDisable(
IN u32 TimerId
)
{
HalTimerDisRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerClearIsr(
IN u32 TimerId
)
{
HalTimerClearIsrRtl8195a(TimerId);
}
static __inline VOID
HalTimerReLoad(
IN u32 TimerId,
IN u32 LoadUs
)
{
#ifdef CONFIG_CHIP_E_CUT
HalTimerReLoadRtl8195a_V04(TimerId, LoadUs);
#else
HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs);
#endif
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195a_Patch(Data);
}
#else
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195aV02(Data);
}
#endif // end of "#ifndef CONFIG_CHIP_C_CUT"
#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#endif //_RTL8195A_TIMER_H_

172
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_wdt.h
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@ -1,86 +1,86 @@
/*
* Routines to access hardware
*
* Copyright (c) 2014 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_WDT_H_
#define _RTL8195A_WDT_H_
#define WDGTIMERELY (10*1024) //us
typedef struct _WDG_REG_ {
u16 WdgScalar;
u8 WdgEnByte;
u8 WdgClear:1;
u8 WdgCunLimit:4;
u8 Rsvd:1;
u8 WdgMode:1;
u8 WdgToISR:1;
}WDG_REG, *PWDG_REG;
typedef struct _WDG_ADAPTER_ {
WDG_REG Ctrl;
IRQ_HANDLE IrqHandle;
TIMER_ADAPTER WdgGTimer;
VOID (*UserCallback)(u32 callback_id); // User callback function
u32 callback_id;
}WDG_ADAPTER, *PWDG_ADAPTER;
typedef enum _WDG_CNTLMT_ {
CNT1H = 0,
CNT3H = 1,
CNT7H = 2,
CNTFH = 3,
CNT1FH = 4,
CNT3FH = 5,
CNT7FH = 6,
CNTFFH = 7,
CNT1FFH = 8,
CNT3FFH = 9,
CNT7FFH = 10,
CNTFFFH = 11
}WDG_CNTLMT, *PWDG_CNTLMT;
typedef enum _WDG_MODE_ {
INT_MODE = 0,
RESET_MODE = 1
}WDG_MODE, *PWDG_MODE;
extern VOID
WDGInitial(
IN u32 Period
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGStop(
VOID
);
extern VOID
WDGRefresh(
VOID
);
extern VOID
WDGIrqCallBackReg(
IN VOID *CallBack,
IN u32 Id
);
#endif //_RTL8195A_WDT_H_
/*
* Routines to access hardware
*
* Copyright (c) 2014 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_WDT_H_
#define _RTL8195A_WDT_H_
#define WDGTIMERELY (10*1024) //us
typedef struct _WDG_REG_ {
u16 WdgScalar;
u8 WdgEnByte;
u8 WdgClear:1;
u8 WdgCunLimit:4;
u8 Rsvd:1;
u8 WdgMode:1;
u8 WdgToISR:1;
}WDG_REG, *PWDG_REG;
typedef struct _WDG_ADAPTER_ {
WDG_REG Ctrl;
IRQ_HANDLE IrqHandle;
TIMER_ADAPTER WdgGTimer;
VOID (*UserCallback)(u32 callback_id); // User callback function
u32 callback_id;
}WDG_ADAPTER, *PWDG_ADAPTER;
typedef enum _WDG_CNTLMT_ {
CNT1H = 0,
CNT3H = 1,
CNT7H = 2,
CNTFH = 3,
CNT1FH = 4,
CNT3FH = 5,
CNT7FH = 6,
CNTFFH = 7,
CNT1FFH = 8,
CNT3FFH = 9,
CNT7FFH = 10,
CNTFFFH = 11
}WDG_CNTLMT, *PWDG_CNTLMT;
typedef enum _WDG_MODE_ {
INT_MODE = 0,
RESET_MODE = 1
}WDG_MODE, *PWDG_MODE;
extern VOID
WDGInitial(
IN u32 Period
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGStop(
VOID
);
extern VOID
WDGRefresh(
VOID
);
extern VOID
WDGIrqCallBackReg(
IN VOID *CallBack,
IN u32 Id
);
#endif //_RTL8195A_WDT_H_

582
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c
View file

@ -1,291 +1,291 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_gdma.h"
#include "hal_gdma.h"
#ifndef CONFIG_CHIP_E_CUT
BOOL
HalGdmaChBlockSetingRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pGdmaChLli;
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 ChEn = pHalGdmaAdapter->ChEn;
u8 GdmaChIsrBitmap = (ChEn & 0xFF);
u8 PendingIsrIndex;
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
//4 1) Check chanel is avaliable
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
//4 Disable Channel
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
HalGdmaChDisRtl8195a(Data);
}
//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
u32 PendRaw, PendStstus;
PendRaw = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
PendStstus = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
//4 Clear Pending Isr
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
(PendStstus & (GdmaChIsrBitmap))
);
}
}
//4 Fill in SARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChSar)
);
//4 Fill in DARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChDar)
);
//4 3) Process CTLx
CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
//4 Clear Config low register bits
CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
BIT_INVC_CTLX_LO_DST_TR_WIDTH &
BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
BIT_INVC_CTLX_LO_DINC &
BIT_INVC_CTLX_LO_SINC &
BIT_INVC_CTLX_LO_DEST_MSIZE &
BIT_INVC_CTLX_LO_SRC_MSIZE &
BIT_INVC_CTLX_LO_TT_FC &
BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
//4 Clear Config upper register bits
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
BIT_INVC_CTLX_UP_DONE);
CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
CtlxLow;
CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
CtlxUp;
//4 Fill in CTLx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
CtlxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
CtlxUp
);
//4 4) Program CFGx
CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
BIT_INVC_CFGX_LO_CH_SUSP &
BIT_INVC_CFGX_LO_HS_SEL_DST &
BIT_INVC_CFGX_LO_HS_SEL_SRC &
BIT_INVC_CFGX_LO_LOCK_CH_L &
BIT_INVC_CFGX_LO_LOCK_B_L &
BIT_INVC_CFGX_LO_LOCK_CH &
BIT_INVC_CFGX_LO_LOCK_B &
BIT_INVC_CFGX_LO_RELOAD_SRC &
BIT_INVC_CFGX_LO_RELOAD_DST);
CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
BIT_INVC_CFGX_UP_DS_UPD_EN &
BIT_INVC_CFGX_UP_SS_UPD_EN &
BIT_INVC_CFGX_UP_SRC_PER &
BIT_INVC_CFGX_UP_DEST_PER);
CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
CfgxLow;
CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
CfgxUp;
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
CfgxUp
);
//4 Check 4 Bytes Alignment
if ((u32)(pLliEle) & 0x3) {
DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n",
pHalGdmaAdapter->pLli);
return _FALSE;
}
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
pLliEle
);
//4 Update the first llp0
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
while (MultiBlockCount > 1) {
MultiBlockCount--;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pLliEle = pGdmaChLli->pLliEle;
if (NULL == pLliEle) {
DBG_GDMA_ERR("pLliEle Null Point!!!!!\n");
return _FALSE;
}
//4 Clear the last element llp enable bit
if (1 == MultiBlockCount) {
if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 1){
CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
}
}
//4 Update block size for transfer
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
//4 Update tje Lli and Block size list point to next llp
pGdmaChLli = pGdmaChLli->pNextLli;
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
//4 Updatethe Llpx context
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
}
return _TRUE;
}
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
if (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN) & (pHalGdmaAdapter->ChEn)) {
return 1;
} else {
return 0;
}
}
#endif
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_gdma.h"
#include "hal_gdma.h"
#ifndef CONFIG_CHIP_E_CUT
BOOL
HalGdmaChBlockSetingRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pGdmaChLli;
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 ChEn = pHalGdmaAdapter->ChEn;
u8 GdmaChIsrBitmap = (ChEn & 0xFF);
u8 PendingIsrIndex;
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
//4 1) Check chanel is avaliable
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
//4 Disable Channel
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
HalGdmaChDisRtl8195a(Data);
}
//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
u32 PendRaw, PendStstus;
PendRaw = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
PendStstus = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
//4 Clear Pending Isr
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
(PendStstus & (GdmaChIsrBitmap))
);
}
}
//4 Fill in SARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChSar)
);
//4 Fill in DARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChDar)
);
//4 3) Process CTLx
CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
//4 Clear Config low register bits
CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
BIT_INVC_CTLX_LO_DST_TR_WIDTH &
BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
BIT_INVC_CTLX_LO_DINC &
BIT_INVC_CTLX_LO_SINC &
BIT_INVC_CTLX_LO_DEST_MSIZE &
BIT_INVC_CTLX_LO_SRC_MSIZE &
BIT_INVC_CTLX_LO_TT_FC &
BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
//4 Clear Config upper register bits
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
BIT_INVC_CTLX_UP_DONE);
CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
CtlxLow;
CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
CtlxUp;
//4 Fill in CTLx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
CtlxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
CtlxUp
);
//4 4) Program CFGx
CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
BIT_INVC_CFGX_LO_CH_SUSP &
BIT_INVC_CFGX_LO_HS_SEL_DST &
BIT_INVC_CFGX_LO_HS_SEL_SRC &
BIT_INVC_CFGX_LO_LOCK_CH_L &
BIT_INVC_CFGX_LO_LOCK_B_L &
BIT_INVC_CFGX_LO_LOCK_CH &
BIT_INVC_CFGX_LO_LOCK_B &
BIT_INVC_CFGX_LO_RELOAD_SRC &
BIT_INVC_CFGX_LO_RELOAD_DST);
CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
BIT_INVC_CFGX_UP_DS_UPD_EN &
BIT_INVC_CFGX_UP_SS_UPD_EN &
BIT_INVC_CFGX_UP_SRC_PER &
BIT_INVC_CFGX_UP_DEST_PER);
CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
CfgxLow;
CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
CfgxUp;
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
CfgxUp
);
//4 Check 4 Bytes Alignment
if ((u32)(pLliEle) & 0x3) {
DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n",
pHalGdmaAdapter->pLli);
return _FALSE;
}
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
pLliEle
);
//4 Update the first llp0
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
while (MultiBlockCount > 1) {
MultiBlockCount--;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pLliEle = pGdmaChLli->pLliEle;
if (NULL == pLliEle) {
DBG_GDMA_ERR("pLliEle Null Point!!!!!\n");
return _FALSE;
}
//4 Clear the last element llp enable bit
if (1 == MultiBlockCount) {
if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 1){
CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
}
}
//4 Update block size for transfer
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
//4 Update tje Lli and Block size list point to next llp
pGdmaChLli = pGdmaChLli->pNextLli;
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
//4 Updatethe Llpx context
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
}
return _TRUE;
}
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
if (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN) & (pHalGdmaAdapter->ChEn)) {
return 1;
} else {
return 0;
}
}
#endif

718
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c
View file

@ -1,359 +1,359 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_pcm.h"
#include "hal_pcm.h"
extern void *
_memset( void *s, int c, SIZE_T n );
VOID
HalPcmOnOffRtl8195a (
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
//todo on off pcm
}
//default sampling rate 8khz, linear, 10ms frame size, time slot 0 , tx+rx
// master mode, enable endian swap
// Question: need local tx/rx page?
BOOL
HalPcmInitRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
_memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER));
//4 1) Initial PcmChCNR03 Register
pHalPcmAdapter->PcmChCNR03.CH0MuA = 0;
pHalPcmAdapter->PcmChCNR03.CH0Band = 0;
//4 1) Initial PcmTSR03 Register
pHalPcmAdapter->PcmTSR03.CH0TSA = 0;
//4 1) Initial PcmBSize03 Register
pHalPcmAdapter->PcmBSize03.CH0BSize = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte
//4 2) Initial Ctl Register
pHalPcmAdapter->PcmCtl.Pcm_En = 1;
pHalPcmAdapter->PcmCtl.SlaveMode = 0;
pHalPcmAdapter->PcmCtl.FsInv = 0;
pHalPcmAdapter->PcmCtl.LinearMode = 0;
pHalPcmAdapter->PcmCtl.LoopBack = 0;
pHalPcmAdapter->PcmCtl.EndianSwap = 1;
return _TRUE;
}
BOOL
HalPcmSettingRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03;
u32 Isr03;
PcmCh=0;
//4 1) Check Pcm index is avaliable
if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
//4 2) Check if there are the pending isr
Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03);
Isr03 &= 0xff000000;
//4 Clear Pending Isr
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03);
//}
//4 3) Process RegCtl
RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL);
//4 Clear Ctl register bits
RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL &
BIT_INV_CTLX_FSINV &
BIT_INV_CTLX_PCM_EN &
BIT_INV_CTLX_LINEARMODE &
BIT_INV_CTLX_LOOP_BACK &
BIT_INV_CTLX_ENDIAN_SWAP);
RegCtl = BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) |
BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) |
BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) |
BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) |
BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) |
BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) |
RegCtl;
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl);
//4 4) Program ChCNR03 Register
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE &
BIT_INV_CHCNR03_CH0TE &
BIT_INV_CHCNR03_CH0MUA &
BIT_INV_CHCNR03_CH0BAND);
RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) |
BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) |
BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) |
BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) |
RegChCNR03;
DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03);
// time slot
RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03);
RegTSR03 &= (BIT_INV_TSR03_CH0TSA);
RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) |
RegTSR03;
DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03);
// buffer size
RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03);
RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE);
RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) |
RegBSize03;
DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03);
return _TRUE;
}
BOOL
HalPcmEnRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 1;
//4 1) Check Pcm index is avaliable
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
if (RegChCNR03 & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25);
pHalPcmAdapter->PcmChCNR03.CH0RE = 1;
pHalPcmAdapter->PcmChCNR03.CH0TE = 1;
return _TRUE;
}
BOOL
HalPcmDisRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 0;
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25)));
pHalPcmAdapter->PcmChCNR03.CH0RE = 0;
pHalPcmAdapter->PcmChCNR03.CH0TE = 0;
return _TRUE;
}
BOOL
HalPcmIsrEnAndDisRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrMask, Addr, IsrCtrl;
u8 IsrTypeIndex = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
Addr = (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8);
IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr);
IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask):
((~pHalGdmaAdapter->ChEn) & IsrMask));
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
Addr,
IsrCtrl
);
}
}
*/
return _TRUE;
}
BOOL
HalPcmDumpRegRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
BOOL
HalPcmRtl8195a (
IN VOID *Data
)
{
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
~(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
/*
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrStatus;
u8 IsrTypeIndex = 0, IsrActBitMap = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8));
// DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus);
IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF));
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)),
(IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF))
);
IsrActBitMap |= BIT_(IsrTypeIndex);
}
}
return IsrActBitMap;
}
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
*/
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_pcm.h"
#include "hal_pcm.h"
extern void *
_memset( void *s, int c, SIZE_T n );
VOID
HalPcmOnOffRtl8195a (
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
//todo on off pcm
}
//default sampling rate 8khz, linear, 10ms frame size, time slot 0 , tx+rx
// master mode, enable endian swap
// Question: need local tx/rx page?
BOOL
HalPcmInitRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
_memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER));
//4 1) Initial PcmChCNR03 Register
pHalPcmAdapter->PcmChCNR03.CH0MuA = 0;
pHalPcmAdapter->PcmChCNR03.CH0Band = 0;
//4 1) Initial PcmTSR03 Register
pHalPcmAdapter->PcmTSR03.CH0TSA = 0;
//4 1) Initial PcmBSize03 Register
pHalPcmAdapter->PcmBSize03.CH0BSize = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte
//4 2) Initial Ctl Register
pHalPcmAdapter->PcmCtl.Pcm_En = 1;
pHalPcmAdapter->PcmCtl.SlaveMode = 0;
pHalPcmAdapter->PcmCtl.FsInv = 0;
pHalPcmAdapter->PcmCtl.LinearMode = 0;
pHalPcmAdapter->PcmCtl.LoopBack = 0;
pHalPcmAdapter->PcmCtl.EndianSwap = 1;
return _TRUE;
}
BOOL
HalPcmSettingRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03;
u32 Isr03;
PcmCh=0;
//4 1) Check Pcm index is avaliable
if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
//4 2) Check if there are the pending isr
Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03);
Isr03 &= 0xff000000;
//4 Clear Pending Isr
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03);
//}
//4 3) Process RegCtl
RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL);
//4 Clear Ctl register bits
RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL &
BIT_INV_CTLX_FSINV &
BIT_INV_CTLX_PCM_EN &
BIT_INV_CTLX_LINEARMODE &
BIT_INV_CTLX_LOOP_BACK &
BIT_INV_CTLX_ENDIAN_SWAP);
RegCtl = BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) |
BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) |
BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) |
BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) |
BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) |
BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) |
RegCtl;
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl);
//4 4) Program ChCNR03 Register
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE &
BIT_INV_CHCNR03_CH0TE &
BIT_INV_CHCNR03_CH0MUA &
BIT_INV_CHCNR03_CH0BAND);
RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) |
BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) |
BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) |
BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) |
RegChCNR03;
DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03);
// time slot
RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03);
RegTSR03 &= (BIT_INV_TSR03_CH0TSA);
RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) |
RegTSR03;
DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03);
// buffer size
RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03);
RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE);
RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) |
RegBSize03;
DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03);
return _TRUE;
}
BOOL
HalPcmEnRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 1;
//4 1) Check Pcm index is avaliable
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
if (RegChCNR03 & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25);
pHalPcmAdapter->PcmChCNR03.CH0RE = 1;
pHalPcmAdapter->PcmChCNR03.CH0TE = 1;
return _TRUE;
}
BOOL
HalPcmDisRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 0;
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25)));
pHalPcmAdapter->PcmChCNR03.CH0RE = 0;
pHalPcmAdapter->PcmChCNR03.CH0TE = 0;
return _TRUE;
}
BOOL
HalPcmIsrEnAndDisRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrMask, Addr, IsrCtrl;
u8 IsrTypeIndex = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
Addr = (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8);
IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr);
IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask):
((~pHalGdmaAdapter->ChEn) & IsrMask));
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
Addr,
IsrCtrl
);
}
}
*/
return _TRUE;
}
BOOL
HalPcmDumpRegRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
BOOL
HalPcmRtl8195a (
IN VOID *Data
)
{
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
~(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
/*
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrStatus;
u8 IsrTypeIndex = 0, IsrActBitMap = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8));
// DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus);
IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF));
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)),
(IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF))
);
IsrActBitMap |= BIT_(IsrTypeIndex);
}
}
return IsrActBitMap;
}
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
*/

3204
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
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File diff suppressed because it is too large Load diff

680
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_timer.c
View file

@ -1,340 +1,340 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_timer.h"
extern u32 gTimerRecord;
extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM];
#ifdef CONFIG_CHIP_A_CUT
HAL_RAM_BSS_SECTION u32 gTimerRecord;
#endif
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#else
u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#endif
VOID
HalTimerIrq2To7Handle_Patch(
IN VOID *Data
)
{
u32 TimerIrqStatus = 0, CheckIndex;
IRQ_FUN pHandler;
TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF);
DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus);
for (CheckIndex = 2; CheckIndex<8; CheckIndex++) {
//3 Check IRQ status bit and Timer X IRQ enable bit
if ((TimerIrqStatus & BIT_(CheckIndex)) &&
(HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) {
//3 Execute Timer callback function
pHandler = Timer2To7VectorTable[CheckIndex-2];
if (pHandler != NULL) {
pHandler((void*)Timer2To7HandlerData[CheckIndex-2]);
}
//3 Clear Timer ISR
HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF);
}
}
}
HAL_Status
HalTimerIrqRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
IRQ_HANDLE TimerIrqHandle;
//IRQ_FUN BackUpIrqFun = NULL;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
TimerIrqHandle.IrqNum = TIMER2_7_IRQ;
TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] =
(IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
Timer2To7HandlerData[pHalTimerAdap->TimerId-2] =
(uint32_t) pHalTimerAdap->IrqHandle.Data;
}
else {
TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
}
TimerIrqHandle.Data = (u32)pHalTimerAdap;
InterruptRegister(&TimerIrqHandle);
}
return HAL_OK;
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
// Patch for A/B Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
u32 ControlReg;
if ((gTimerRecord & (1<<pHalTimerAdap->TimerId)) != 0) {
DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_BUSY;
}
//4 1) Config Timer Setting
ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2);
/*
set TimerControlReg
0: Timer enable (0,disable; 1,enable)
1: Timer Mode (0, free-running mode; 1, user-defined count mode)
2: Timer Interrupt Mask (0, not masked; 1,masked)
*/
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
ControlReg);
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
else {
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF),
0xFFFFFFFF);
}
//4 2) Setting Timer IRQ
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
//4 2.1) Initial TimerIRQHandle
ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap);
if (HAL_OK != ret) {
DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return ret;
}
//4 2.2) Enable TimerIRQ for Platform
InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
}
else {
DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
}
//4 4) Enable Timer
// HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
// (ControlReg|0x1));
gTimerRecord |= (1<<pHalTimerAdap->TimerId);
return ret;
}
#elif defined(CONFIG_CHIP_C_CUT)
// Patch for C Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
ret = HalTimerInitRtl8195aV02(Data);
// Patch the Rom code to load the correct count value
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
return ret;
}
#endif
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
HAL_Status
HalTimerIrqUnRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
PIRQ_HANDLE pTimerIrqHandle;
u32 i;
pTimerIrqHandle = &pHalTimerAdap->IrqHandle;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
pTimerIrqHandle->IrqNum = TIMER2_7_IRQ;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL;
for (i=0;i<MAX_TIMER_VECTOR_TABLE_NUM;i++) {
if (Timer2To7VectorTable[i] != NULL) {
break;
}
}
if (i == MAX_TIMER_VECTOR_TABLE_NUM) {
// All timer UnRegister Interrupt
InterruptDis((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
InterruptUnRegister(pTimerIrqHandle);
}
}
else {
pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
InterruptUnRegister(pTimerIrqHandle);
}
}
return HAL_OK;
}
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
u32 timer_id;
timer_id = pHalTimerAdap->TimerId;
HalTimerDisRtl8195a (timer_id);
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap);
}
}
gTimerRecord &= ~(1<<pHalTimerAdap->TimerId);
}
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
)
{
u32 TimerCountOld;
u32 TimerCountNew;
u32 TimerRDCnt;
TimerRDCnt = 0;
TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
while(1) {
TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
if (TimerCountOld == TimerCountNew) {
return (u32)TimerCountOld;
}
else {
TimerRDCnt++;
TimerCountOld = TimerCountNew;
if (TimerRDCnt >= 2){
return (u32)TimerCountOld;
}
}
}
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
)
{
u32 LoadCount = 0;
u32 ms125; // how many 125ms
u32 remain_us;
ms125 = LoadUs/125000;
remain_us = LoadUs - (ms125*125000);
LoadCount = ms125 * (GTIMER_CLK_HZ/8);
LoadCount += (remain_us*GTIMER_CLK_HZ)/1000000;
if (LoadCount == 0) {
LoadCount = 1;
}
// DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount);
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF),
LoadCount);
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~(BIT2)));
}
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT2));
}
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_EOI_OFF);
}
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT0));
}
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
)
{
// Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~BIT0));
}
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_timer.h"
extern u32 gTimerRecord;
extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM];
#ifdef CONFIG_CHIP_A_CUT
HAL_RAM_BSS_SECTION u32 gTimerRecord;
#endif
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#else
u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#endif
VOID
HalTimerIrq2To7Handle_Patch(
IN VOID *Data
)
{
u32 TimerIrqStatus = 0, CheckIndex;
IRQ_FUN pHandler;
TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF);
DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus);
for (CheckIndex = 2; CheckIndex<8; CheckIndex++) {
//3 Check IRQ status bit and Timer X IRQ enable bit
if ((TimerIrqStatus & BIT_(CheckIndex)) &&
(HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) {
//3 Execute Timer callback function
pHandler = Timer2To7VectorTable[CheckIndex-2];
if (pHandler != NULL) {
pHandler((void*)Timer2To7HandlerData[CheckIndex-2]);
}
//3 Clear Timer ISR
HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF);
}
}
}
HAL_Status
HalTimerIrqRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
IRQ_HANDLE TimerIrqHandle;
//IRQ_FUN BackUpIrqFun = NULL;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
TimerIrqHandle.IrqNum = TIMER2_7_IRQ;
TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] =
(IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
Timer2To7HandlerData[pHalTimerAdap->TimerId-2] =
(uint32_t) pHalTimerAdap->IrqHandle.Data;
}
else {
TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
}
TimerIrqHandle.Data = (u32)pHalTimerAdap;
InterruptRegister(&TimerIrqHandle);
}
return HAL_OK;
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
// Patch for A/B Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
u32 ControlReg;
if ((gTimerRecord & (1<<pHalTimerAdap->TimerId)) != 0) {
DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_BUSY;
}
//4 1) Config Timer Setting
ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2);
/*
set TimerControlReg
0: Timer enable (0,disable; 1,enable)
1: Timer Mode (0, free-running mode; 1, user-defined count mode)
2: Timer Interrupt Mask (0, not masked; 1,masked)
*/
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
ControlReg);
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
else {
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF),
0xFFFFFFFF);
}
//4 2) Setting Timer IRQ
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
//4 2.1) Initial TimerIRQHandle
ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap);
if (HAL_OK != ret) {
DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return ret;
}
//4 2.2) Enable TimerIRQ for Platform
InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
}
else {
DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
}
//4 4) Enable Timer
// HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
// (ControlReg|0x1));
gTimerRecord |= (1<<pHalTimerAdap->TimerId);
return ret;
}
#elif defined(CONFIG_CHIP_C_CUT)
// Patch for C Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
ret = HalTimerInitRtl8195aV02(Data);
// Patch the Rom code to load the correct count value
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
return ret;
}
#endif
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
HAL_Status
HalTimerIrqUnRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
PIRQ_HANDLE pTimerIrqHandle;
u32 i;
pTimerIrqHandle = &pHalTimerAdap->IrqHandle;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
pTimerIrqHandle->IrqNum = TIMER2_7_IRQ;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL;
for (i=0;i<MAX_TIMER_VECTOR_TABLE_NUM;i++) {
if (Timer2To7VectorTable[i] != NULL) {
break;
}
}
if (i == MAX_TIMER_VECTOR_TABLE_NUM) {
// All timer UnRegister Interrupt
InterruptDis((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
InterruptUnRegister(pTimerIrqHandle);
}
}
else {
pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
InterruptUnRegister(pTimerIrqHandle);
}
}
return HAL_OK;
}
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
u32 timer_id;
timer_id = pHalTimerAdap->TimerId;
HalTimerDisRtl8195a (timer_id);
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap);
}
}
gTimerRecord &= ~(1<<pHalTimerAdap->TimerId);
}
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
)
{
u32 TimerCountOld;
u32 TimerCountNew;
u32 TimerRDCnt;
TimerRDCnt = 0;
TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
while(1) {
TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
if (TimerCountOld == TimerCountNew) {
return (u32)TimerCountOld;
}
else {
TimerRDCnt++;
TimerCountOld = TimerCountNew;
if (TimerRDCnt >= 2){
return (u32)TimerCountOld;
}
}
}
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
)
{
u32 LoadCount = 0;
u32 ms125; // how many 125ms
u32 remain_us;
ms125 = LoadUs/125000;
remain_us = LoadUs - (ms125*125000);
LoadCount = ms125 * (GTIMER_CLK_HZ/8);
LoadCount += (remain_us*GTIMER_CLK_HZ)/1000000;
if (LoadCount == 0) {
LoadCount = 1;
}
// DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount);
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF),
LoadCount);
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~(BIT2)));
}
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT2));
}
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_EOI_OFF);
}
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT0));
}
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
)
{
// Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~BIT0));
}

56
component/soc/realtek/8195a/fwlib/src/hal_pcm.c
View file

@ -1,28 +1,28 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "hal_pcm.h"
VOID HalPcmOpInit(
IN VOID *Data
)
{
PHAL_PCM_OP pHalPcmOp = (PHAL_PCM_OP) Data;
pHalPcmOp->HalPcmOnOff = HalPcmOnOffRtl8195a;
pHalPcmOp->HalPcmInit = HalPcmInitRtl8195a;
pHalPcmOp->HalPcmSetting = HalPcmSettingRtl8195a;
pHalPcmOp->HalPcmEn = HalPcmEnRtl8195a;
pHalPcmOp->HalPcmIsrEnAndDis= HalPcmIsrEnAndDisRtl8195a;
pHalPcmOp->HalPcmDumpReg= HalPcmDumpRegRtl8195a;
pHalPcmOp->HalPcm= HalPcmRtl8195a;
}
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "hal_pcm.h"
VOID HalPcmOpInit(
IN VOID *Data
)
{
PHAL_PCM_OP pHalPcmOp = (PHAL_PCM_OP) Data;
pHalPcmOp->HalPcmOnOff = HalPcmOnOffRtl8195a;
pHalPcmOp->HalPcmInit = HalPcmInitRtl8195a;
pHalPcmOp->HalPcmSetting = HalPcmSettingRtl8195a;
pHalPcmOp->HalPcmEn = HalPcmEnRtl8195a;
pHalPcmOp->HalPcmIsrEnAndDis= HalPcmIsrEnAndDisRtl8195a;
pHalPcmOp->HalPcmDumpReg= HalPcmDumpRegRtl8195a;
pHalPcmOp->HalPcm= HalPcmRtl8195a;
}

1370
component/soc/realtek/8195a/fwlib/src/hal_ssi.c
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