mirror of
https://github.com/rtlduino/RTL8710AF_GCC.git
synced 2024-11-22 17:24:16 +00:00
433 lines
13 KiB
C
433 lines
13 KiB
C
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _RTL8195A_USB_H_
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#define _RTL8195A_USB_H_
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// common command for USB
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#define USB_CMD_TX_ETH 0x83 // request to TX a 802.3 packet
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#define USB_CMD_TX_WLN 0x81 // request to TX a 802.11 packet
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#define USB_CMD_H2C 0x11 // H2C(host to device) command packet
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#define USB_CMD_MEMRD 0x51 // request to read a block of memory data
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#define USB_CMD_MEMWR 0x53 // request to write a block of memory
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#define USB_CMD_MEMST 0x55 // request to set a block of memory with a value
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#define USB_CMD_STARTUP 0x61 // request to jump to the start up function
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#define USB_CMD_RX_ETH 0x82 // indicate a RX 802.3 packet
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#define USB_CMD_RX_WLN 0x80 // indicate a RX 802.11 packet
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#define USB_CMD_C2H 0x10 // C2H(device to host) command packet
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#define USB_CMD_MEMRD_RSP 0x50 // response to memory block read command
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#define USB_CMD_MEMWR_RSP 0x52 // response to memory write command
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#define USB_CMD_MEMST_RSP 0x54 // response to memory set command
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#define USB_CMD_STARTED 0x60 // indicate the program has jumped to the given function
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// TODO: This data structer just for test, we should modify it for the normal driver
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typedef struct _USB_TX_DESC{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 txpktsize:16; // bit[15:0]
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u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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#else
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
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u32 txpktsize:16; // bit[15:0]
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the packet type
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u32 rsvd0:24;
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#else
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u32 rsvd0:24;
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u32 type:8; // bit[7:0], the packet type
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#endif
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// u4Byte 2
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u32 rsvd1;
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// u4Byte 3
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u32 rsvd2;
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// u4Byte 4
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u32 rsvd3;
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// u4Byte 5
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u32 rsvd4;
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} USB_TX_DESC, *PUSB_TX_DESC;
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#define SIZE_USB_TX_DESC sizeof(USB_TX_DESC)
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// TX Desc for Memory Write command
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typedef struct _USB_TX_DESC_MW{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 txpktsize:16; // bit[15:0]
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u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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#else
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
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u32 txpktsize:16; // bit[15:0]
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the packet type
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u32 reply:1; // bit[8], request to send a reply message
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u32 rsvd0:23;
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#else
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u32 rsvd0:23;
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u32 reply:1; // bit[8], request to send a reply message
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u32 type:8; // bit[7:0], the packet type
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#endif
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// u4Byte 2
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u32 start_addr; // memory write start address
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// u4Byte 3
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 write_len:16; // bit[15:0], the length to write
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u32 rsvd2:16; // bit[31:16]
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#else
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u32 rsvd2:16; // bit[31:16]
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u32 write_len:16; // bit[15:0], the length to write
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#endif
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// u4Byte 4
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u32 rsvd3;
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// u4Byte 5
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u32 rsvd4;
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} USB_TX_DESC_MW, *PUSB_TX_DESC_MW;
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// TX Desc for Memory Read command
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typedef struct _USB_TX_DESC_MR{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 txpktsize:16; // bit[15:0]
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u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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#else
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
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u32 txpktsize:16; // bit[15:0]
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the packet type
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u32 rsvd0:24;
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#else
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u32 rsvd0:24;
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u32 type:8; // bit[7:0], the packet type
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#endif
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// u4Byte 2
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u32 start_addr; // memory write start address
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// u4Byte 3
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 read_len:16; // bit[15:0], the length to read
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u32 rsvd2:16; // bit[31:16]
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#else
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u32 rsvd2:16; // bit[31:16]
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u32 read_len:16; // bit[15:0], the length to read
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#endif
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// u4Byte 4
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u32 rsvd3;
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// u4Byte 5
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u32 rsvd4;
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} USB_TX_DESC_MR, *PUSB_TX_DESC_MR;
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// TX Desc for Memory Set command
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typedef struct _USB_TX_DESC_MS{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 txpktsize:16; // bit[15:0]
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u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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#else
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
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u32 txpktsize:16; // bit[15:0]
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the packet type
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u32 data:8; // bit[8:15], the value to be written to the memory
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u32 reply:1; // bit[16], request to send a reply message
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u32 rsvd0:15;
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#else
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u32 rsvd0:15;
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u32 reply:1; // bit[16], request to send a reply message
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u32 data:8; // bit[8:15], the value to be written to the memory
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u32 type:8; // bit[7:0], the packet type
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#endif
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// u4Byte 2
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u32 start_addr; // memory write start address
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// u4Byte 3
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 write_len:16; // bit[15:0], the length to write
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u32 rsvd2:16; // bit[31:16]
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#else
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u32 rsvd2:16; // bit[31:16]
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u32 write_len:16; // bit[15:0], the length to write
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#endif
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// u4Byte 4
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u32 rsvd3;
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// u4Byte 5
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u32 rsvd4;
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} USB_TX_DESC_MS, *PUSB_TX_DESC_MS;
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// TX Desc for Jump to Start command
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typedef struct _USB_TX_DESC_JS{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 txpktsize:16; // bit[15:0]
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u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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#else
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u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
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u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
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u32 txpktsize:16; // bit[15:0]
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the packet type
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u32 rsvd0:24;
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#else
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u32 rsvd0:24;
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u32 type:8; // bit[7:0], the packet type
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#endif
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// u4Byte 2
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u32 start_fun; // the pointer of the startup function
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// u4Byte 3
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u32 rsvd2;
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// u4Byte 4
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u32 rsvd3;
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// u4Byte 5
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u32 rsvd4;
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} USB_TX_DESC_JS, *PUSB_TX_DESC_JS;
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typedef struct _USB_RX_DESC{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 pkt_len:16; // bit[15:0], the packet size
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u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
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u32 rsvd0:6; // bit[29:24]
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u32 icv:1; // bit[30], ICV error
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u32 crc:1; // bit[31], CRC error
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#else
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u32 crc:1; // bit[31], CRC error
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u32 icv:1; // bit[30], ICV error
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u32 rsvd0:6; // bit[29:24]
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u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
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u32 pkt_len:16; // bit[15:0], the packet size
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the type of this packet
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u32 rsvd1:24; // bit[31:8]
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#else
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u32 rsvd1:24; // bit[31:8]
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u32 type:8; // bit[7:0], the type of this packet
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#endif
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// u4Byte 2
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u32 rsvd2;
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// u4Byte 3
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u32 rsvd3;
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// u4Byte 4
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u32 rsvd4;
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// u4Byte 5
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u32 rsvd5;
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} USB_RX_DESC, *PUSB_RX_DESC;
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// For memory read command
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typedef struct _USB_RX_DESC_MR{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 pkt_len:16; // bit[15:0], the packet size
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u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
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u32 rsvd0:8; // bit[31:24]
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#else
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u32 rsvd0:8; // bit[31:24]
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u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
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u32 pkt_len:16; // bit[15:0], the packet size
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the type of this packet
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u32 rsvd1:24; // bit[31:8]
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#else
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u32 rsvd1:24; // bit[31:8]
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u32 type:8; // bit[7:0], the type of this packet
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#endif
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// u4Byte 2
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u32 start_addr;
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// u4Byte 3
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u32 rsvd2;
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// u4Byte 4
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u32 rsvd3;
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// u4Byte 5
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u32 rsvd4;
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} USB_RX_DESC_MR, *PUSB_RX_DESC_MR;
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// For memory write reply command
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typedef struct _USB_RX_DESC_MW{
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// u4Byte 0
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 pkt_len:16; // bit[15:0], the packet size
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u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
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u32 rsvd0:8; // bit[31:24]
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#else
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u32 rsvd0:8; // bit[31:24]
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u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
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u32 pkt_len:16; // bit[15:0], the packet size
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#endif
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// u4Byte 1
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 type:8; // bit[7:0], the type of this packet
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u32 rsvd1:24; // bit[31:8]
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#else
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u32 rsvd1:24; // bit[31:8]
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u32 type:8; // bit[7:0], the type of this packet
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#endif
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// u4Byte 2
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u32 start_addr;
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// u4Byte 3
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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u32 write_len:16; // bit[15:0], the type of this packet
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u32 result:8; // bit[23:16], the result of memory write command
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u32 rsvd2:8; // bit[31:24]
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#else
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u32 rsvd2:8; // bit[31:24]
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u32 result:8; // bit[23:16], the result of memory write command
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||
|
|
u32 write_len:16; // bit[15:0], the type of this packet
|
||
|
|
#endif
|
||
|
|
|
||
|
|
// u4Byte 4
|
||
|
|
u32 rsvd3;
|
||
|
|
|
||
|
|
// u4Byte 5
|
||
|
|
u32 rsvd4;
|
||
|
|
} USB_RX_DESC_MW, *PUSB_RX_DESC_MW;
|
||
|
|
|
||
|
|
// For memory set reply command
|
||
|
|
typedef struct _USB_RX_DESC_MS{
|
||
|
|
// u4Byte 0
|
||
|
|
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||
|
|
u32 pkt_len:16; // bit[15:0], the packet size
|
||
|
|
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||
|
|
u32 rsvd0:8; // bit[31:24]
|
||
|
|
#else
|
||
|
|
u32 rsvd0:8; // bit[31:24]
|
||
|
|
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||
|
|
u32 pkt_len:16; // bit[15:0], the packet size
|
||
|
|
#endif
|
||
|
|
|
||
|
|
// u4Byte 1
|
||
|
|
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||
|
|
u32 type:8; // bit[7:0], the type of this packet
|
||
|
|
u32 rsvd1:24; // bit[31:8]
|
||
|
|
#else
|
||
|
|
u32 rsvd1:24; // bit[31:8]
|
||
|
|
u32 type:8; // bit[7:0], the type of this packet
|
||
|
|
#endif
|
||
|
|
|
||
|
|
// u4Byte 2
|
||
|
|
u32 start_addr;
|
||
|
|
|
||
|
|
// u4Byte 3
|
||
|
|
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||
|
|
u32 write_len:16; // bit[15:0], the type of this packet
|
||
|
|
u32 result:8; // bit[23:16], the result of memory write command
|
||
|
|
u32 rsvd2:8; // bit[31:24]
|
||
|
|
#else
|
||
|
|
u32 rsvd2:8; // bit[31:24]
|
||
|
|
u32 result:8; // bit[23:16], the result of memory write command
|
||
|
|
u32 write_len:16; // bit[15:0], the type of this packet
|
||
|
|
#endif
|
||
|
|
|
||
|
|
// u4Byte 4
|
||
|
|
u32 rsvd3;
|
||
|
|
|
||
|
|
// u4Byte 5
|
||
|
|
u32 rsvd4;
|
||
|
|
} USB_RX_DESC_MS, *PUSB_RX_DESC_MS;
|
||
|
|
|
||
|
|
// For firmware ready reply command
|
||
|
|
typedef struct _USB_RX_DESC_FS{
|
||
|
|
// u4Byte 0
|
||
|
|
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||
|
|
u32 pkt_len:16; // bit[15:0], the packet size
|
||
|
|
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||
|
|
u32 rsvd0:8; // bit[31:24]
|
||
|
|
#else
|
||
|
|
u32 rsvd0:8; // bit[31:24]
|
||
|
|
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||
|
|
u32 pkt_len:16; // bit[15:0], the packet size
|
||
|
|
#endif
|
||
|
|
|
||
|
|
// u4Byte 1
|
||
|
|
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||
|
|
u32 type:8; // bit[7:0], the type of this packet
|
||
|
|
u32 rsvd1:24; // bit[31:8]
|
||
|
|
#else
|
||
|
|
u32 rsvd1:24; // bit[31:8]
|
||
|
|
u32 type:8; // bit[7:0], the type of this packet
|
||
|
|
#endif
|
||
|
|
|
||
|
|
// u4Byte 2
|
||
|
|
u32 rsvd2;
|
||
|
|
|
||
|
|
// u4Byte 3
|
||
|
|
u32 rsvd3;
|
||
|
|
|
||
|
|
// u4Byte 4
|
||
|
|
u32 rsvd4;
|
||
|
|
|
||
|
|
// u4Byte 5
|
||
|
|
u32 rsvd5;
|
||
|
|
} USB_RX_DESC_FS, *PUSB_RX_DESC_FS;
|
||
|
|
|
||
|
|
|
||
|
|
#define SIZE_USB_RX_DESC sizeof(USB_RX_DESC)
|
||
|
|
|
||
|
|
#endif // #ifndef _RTL8195A_USB_H_
|
||
|
|
|