2016-09-18 01:03:25 +00:00
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _HAL_IRQN_H_
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#define _HAL_IRQN_H_
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#define PERIPHERAL_IRQ_BASE_NUM 64
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typedef enum _IRQn_Type_ {
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#if 0
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/****** Cortex-M3 Processor Exceptions Numbers ********/
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NON_MASKABLE_INT_IRQ = -14,
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HARD_FAULT_IRQ = -13,
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MEM_MANAGE_FAULT_IRQ = -12,
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BUS_FAULT_IRQ = -11,
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USAGE_FAULT_IRQ = -10,
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SVCALL_IRQ = -5,
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DEBUG_MONITOR_IRQ = -4,
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PENDSVC_IRQ = -2,
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SYSTICK_IRQ = -1,
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#else
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/****** Cortex-M3 Processor Exceptions Numbers ********/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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#endif
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/****** RTL8195A Specific Interrupt Numbers ************/
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SYSTEM_ON_IRQ = 0,
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WDG_IRQ = 1,
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TIMER0_IRQ = 2,
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TIMER1_IRQ = 3,
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I2C3_IRQ = 4,
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TIMER2_7_IRQ = 5,
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SPI0_IRQ = 6,
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GPIO_IRQ = 7,
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UART0_IRQ = 8,
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SPI_FLASH_IRQ = 9,
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USB_OTG_IRQ = 10,
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SDIO_HOST_IRQ = 11,
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SDIO_DEVICE_IRQ = 12,
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I2S0_PCM0_IRQ = 13,
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I2S1_PCM1_IRQ = 14,
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WL_DMA_IRQ = 15,
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WL_PROTOCOL_IRQ = 16,
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CRYPTO_IRQ = 17,
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GMAC_IRQ = 18,
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PERIPHERAL_IRQ = 19,
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GDMA0_CHANNEL0_IRQ = 20,
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GDMA0_CHANNEL1_IRQ = 21,
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GDMA0_CHANNEL2_IRQ = 22,
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GDMA0_CHANNEL3_IRQ = 23,
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GDMA0_CHANNEL4_IRQ = 24,
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GDMA0_CHANNEL5_IRQ = 25,
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GDMA1_CHANNEL0_IRQ = 26,
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GDMA1_CHANNEL1_IRQ = 27,
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GDMA1_CHANNEL2_IRQ = 28,
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GDMA1_CHANNEL3_IRQ = 29,
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GDMA1_CHANNEL4_IRQ = 30,
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GDMA1_CHANNEL5_IRQ = 31,
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/****** RTL8195A Peripheral Interrupt Numbers ************/
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I2C0_IRQ = 64,// 0 + 64,
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I2C1_IRQ = 65,// 1 + 64,
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I2C2_IRQ = 66,// 2 + 64,
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SPI1_IRQ = 72,// 8 + 64,
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SPI2_IRQ = 73,// 9 + 64,
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UART1_IRQ = 80,// 16 + 64,
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UART2_IRQ = 81,// 17 + 64,
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UART_LOG_IRQ = 88,// 24 + 64,
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ADC_IRQ = 89,// 25 + 64,
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DAC0_IRQ = 91,// 27 + 64,
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DAC1_IRQ = 92,// 28 + 64,
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//RXI300_IRQ = 93// 29 + 64
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LP_EXTENSION_IRQ = 93,// 29+64
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PTA_TRX_IRQ = 95,// 31+64
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RXI300_IRQ = 96,// 0+32 + 64
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NFC_IRQ = 97// 1+32+64
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} IRQn_Type, *PIRQn_Type;
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typedef VOID (*HAL_VECTOR_FUN) (VOID);
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typedef enum _VECTOR_TABLE_TYPE_{
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DEDECATED_VECTRO_TABLE,
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PERIPHERAL_VECTOR_TABLE
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}VECTOR_TABLE_TYPE, *PVECTOR_TABLE_TYPE;
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typedef void (*IRQ_FUN)(VOID *Data);
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typedef struct _IRQ_HANDLE_ {
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IRQ_FUN IrqFun;
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IRQn_Type IrqNum;
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u32 Data;
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u32 Priority;
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}IRQ_HANDLE, *PIRQ_HANDLE;
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#endif //_HAL_IRQN_H_
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