mirror of
https://github.com/ADElectronics/RTL00_WEB_WS2812.git
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first release
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parent
9e39a46764
commit
8d743effde
63 changed files with 90030 additions and 93047 deletions
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@ -124,20 +124,20 @@ GenerateClassCluster=0
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DocumentUniqueId=TBYWGQNE
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[Parameter1]
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Name=GlobalProjectRevision
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Value=0
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Name=GlobalOrganizationName
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Value=A_D Electronics
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[Parameter2]
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Name=GlobalProjectNumber
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Value=A_D.000000.001
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[Parameter3]
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Name=GlobalProjectName
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Value=Ãëóïàÿ ãèðëÿíäà
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[Parameter3]
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Name=GlobalProjectNumber
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Value=A_D.000000.001
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[Parameter4]
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Name=GlobalOrganizationName
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Value=A_D Electronics
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Name=GlobalProjectRevision
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Value=0
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[Configuration1]
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Name=Default Configuration
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@ -231,6 +231,96 @@ OutputName6=XSpice Netlist
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OutputDocumentPath6=
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OutputVariantName6=
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OutputDefault6=0
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OutputType7=CadnetixNetlist
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OutputName7=Cadnetix Netlist
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OutputDocumentPath7=
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OutputVariantName7=
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OutputDefault7=0
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OutputType8=CalayNetlist
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OutputName8=Calay Netlist
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OutputDocumentPath8=
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OutputVariantName8=
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OutputDefault8=0
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OutputType9=EDIF
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OutputName9=EDIF for PCB
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OutputDocumentPath9=
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OutputVariantName9=
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OutputDefault9=0
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OutputType10=EESofNetlist
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OutputName10=EESof Netlist
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OutputDocumentPath10=
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OutputVariantName10=
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OutputDefault10=0
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OutputType11=IntergraphNetlist
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OutputName11=Intergraph Netlist
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OutputDocumentPath11=
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OutputVariantName11=
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OutputDefault11=0
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OutputType12=MentorBoardStationNetlist
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OutputName12=Mentor BoardStation Netlist
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OutputDocumentPath12=
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OutputVariantName12=
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OutputDefault12=0
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OutputType13=MultiWire
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OutputName13=MultiWire
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OutputDocumentPath13=
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OutputVariantName13=
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OutputDefault13=0
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OutputType14=OrCadPCB2Netlist
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OutputName14=Orcad/PCB2 Netlist
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OutputDocumentPath14=
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OutputVariantName14=
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OutputDefault14=0
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OutputType15=Pcad
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OutputName15=Pcad for PCB
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OutputDocumentPath15=
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OutputVariantName15=
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OutputDefault15=0
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OutputType16=PCADnltNetlist
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OutputName16=PCADnlt Netlist
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OutputDocumentPath16=
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OutputVariantName16=
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OutputDefault16=0
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OutputType17=Protel2Netlist
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OutputName17=Protel2 Netlist
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OutputDocumentPath17=
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OutputVariantName17=
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OutputDefault17=0
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OutputType18=ProtelNetlist
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OutputName18=Protel
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OutputDocumentPath18=
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OutputVariantName18=
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OutputDefault18=0
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OutputType19=RacalNetlist
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OutputName19=Racal Netlist
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OutputDocumentPath19=
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OutputVariantName19=
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OutputDefault19=0
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OutputType20=RINFNetlist
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OutputName20=RINF Netlist
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OutputDocumentPath20=
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OutputVariantName20=
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OutputDefault20=0
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OutputType21=SciCardsNetlist
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OutputName21=SciCards Netlist
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OutputDocumentPath21=
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OutputVariantName21=
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OutputDefault21=0
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OutputType22=TangoNetlist
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OutputName22=Tango Netlist
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OutputDocumentPath22=
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OutputVariantName22=
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OutputDefault22=0
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OutputType23=TelesisNetlist
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OutputName23=Telesis Netlist
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OutputDocumentPath23=
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OutputVariantName23=
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OutputDefault23=0
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OutputType24=WireListNetlist
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OutputName24=WireList Netlist
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OutputDocumentPath24=
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OutputVariantName24=
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OutputDefault24=0
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[OutputGroup2]
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Name=Simulator Outputs
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@ -260,10 +350,18 @@ TargetPrinter=Virtual Printer
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PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
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OutputType1=Composite
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OutputName1=Composite Drawing
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OutputDocumentPath1=
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OutputDocumentPath1=C:\Users\Andrew\Vector\USER\A_D\GitHub\RTL00_WEB_WS2812\Hardware\A_D.000000.001.PcbDoc
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OutputVariantName1=
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OutputDefault1=0
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PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
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PageOptions1=Record=PageOptions|CenterHorizontal=False|CenterVertical=False|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=2|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=1|PaperLength=2970|PaperWidth=2100|Scale=100|PaperSource=7|PrintQuality=600|MediaType=1|DitherType=10|PrintScaleMode=0|PaperKind=A4|PaperIndex=9
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Configuration1_Name1=OutputConfigurationParameter1
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Configuration1_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView
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Configuration1_Name2=OutputConfigurationParameter2
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Configuration1_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=True|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False
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Configuration1_Name3=OutputConfigurationParameter3
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Configuration1_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
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Configuration1_Name4=OutputConfigurationParameter4
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Configuration1_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
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OutputType2=PCB 3D Print
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OutputName2=PCB 3D Print
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OutputDocumentPath2=
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@ -785,6 +883,16 @@ OutputName3=AutoCAD dwg/dxf File Schematic
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OutputDocumentPath3=
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OutputVariantName3=
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OutputDefault3=0
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OutputType4=ExportIDF
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OutputName4=Export IDF
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OutputDocumentPath4=
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OutputVariantName4=
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OutputDefault4=0
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OutputType5=NetList Sch
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OutputName5=NetList Sch
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OutputDocumentPath5=
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OutputVariantName5=
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OutputDefault5=0
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[Modification Levels]
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Type1=1
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BIN
Hardware/_Outputs/A_D.000000.001 ЛУТ изм.0.PDF
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BIN
Hardware/_Outputs/A_D.000000.001 ЛУТ изм.0.PDF
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