RTL00_WEB_WS2812/Firmware/RTLGDB/Debug/RTLGDB.log

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Compile (Debug)
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Link (Debug)
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Build names map file
Debug/obj/Debug.nmap
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Create image1r (Debug/bin/ram_1.r.bin)
b:268438472 s:268438472 e:268446992
size 8520
append fw head b000
copy size 8520
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Create image2ns (Debug/bin/ram_2.ns.bin)
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b:268460032 s:268460032 e:268728976
size 268944
copy size 268944
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Create image3 (SDRAM, Debug/bin/sdram.p.bin)
30000000 30000000
b:805306368 s:805306368 e:805306368
size 0
copy size 0
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Make OTA image (Debug/bin/ota.bin)
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size = 268976
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checksum 1aa0f6e
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Create image2p (Debug/bin/ram_2.p.bin)
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b:268460032 s:268460032 e:268728976
size 268944
copy size 268944
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Make Flash image (Debug/bin/ram_all.bin)
total 44 k, padding data 0, name Debug/bin/ram_all.bin
Original size zd
Padding size zd
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Image (Debug/bin/ota.bin) size 268980 bytes
Image (Debug/bin/ram_all.bin) size 314032 bytes
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