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ADElectronics 2017-11-28 22:31:40 +03:00
parent 6a1f93f17b
commit 764b020238
1201 changed files with 527271 additions and 1 deletions
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196
RTLGDB/Project/driver/adc_drv.c Normal file
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/*
* Simple ADC DRV (adc_drv.c)
* Created on: 18 июн. 2017 г.
* Author: pvvx
*/
#include <platform_opts.h>
#include "platform_autoconf.h"
#include "diag.h"
#include "rtl8195a_adc.h"
#include "hal_adc.h"
#include "driver/adc_drv.h"
//------------------------------------------------------------------------------
void ADCIrqInit(IRQ_FUN IrqFunc, uint32_t IrqData, uint32_t intr_enable)
{
IRQ_HANDLE IrqHandle = {
.IrqNum = ADC_IRQ,
.Priority = 5
};
IrqHandle.Data = IrqData;
IrqHandle.IrqFun = IrqFunc;
InterruptRegister(&IrqHandle);
InterruptEn(&IrqHandle);
HAL_ADC_WRITE32(REG_ADC_INTR_EN, intr_enable);
}
void ADCIrqDeInit(void)
{
IRQ_HANDLE IrqHandle = {
.IrqNum = ADC_IRQ,
.Priority = 5,
.Data = (uint32_t)NULL,
.IrqFun = (IRQ_FUN) NULL
};
HAL_ADC_WRITE32(REG_ADC_INTR_EN, 0);
InterruptUnRegister(&IrqHandle);
}
void ADCEnable(void)
{
// Clear ADC Status
(void)HAL_ADC_READ32(REG_ADC_INTR_STS);
uint32_t AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat &= (~BIT_ADC_PWR_AUTO);
AdcTempDat |= 0x02;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
AdcTempDat |= 0x04;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
AdcTempDat &= (~0x08);
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, HAL_ADC_READ32(REG_ADC_ANAPAR_AD0) | BIT_ADC_EN_MANUAL);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, HAL_ADC_READ32(REG_ADC_ANAPAR_AD1) | BIT_ADC_EN_MANUAL);
}
void ADCDisable(void)
{
#if ADC_USE_IRQ
HAL_ADC_WRITE32(REG_ADC_INTR_EN, 0);
#endif
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, HAL_ADC_READ32(REG_ADC_ANAPAR_AD0) & (~BIT_ADC_EN_MANUAL));
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, HAL_ADC_READ32(REG_ADC_ANAPAR_AD1) & (~BIT_ADC_EN_MANUAL));
HAL_ADC_WRITE32(REG_ADC_POWER, HAL_ADC_READ32(REG_ADC_POWER) & (~(BIT_ADC_PWR_AUTO)));
}
#ifdef CONFIG_SOC_PS_MODULE
static void ADCEnablePS(void)
{
REG_POWER_STATE adcPwrState;
// To register a new peripheral device power state
adcPwrState.FuncIdx = ADC0;
adcPwrState.PwrState = ACT;
RegPowerState(adcPwrState);
}
#endif
void ADCInit(ADC_MODULE_SEL adc_idx)
{
// ADC Function and Clock Enable
// To release DAC delta sigma clock gating
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2) | BIT25);
// Turn on DAC active clock
ACTCK_ADC_CCTRL(ON);
// Enable DAC0 module
ADC0_FCTRL(ON);
// Enable ADC power cut ?
// ADCEnablePW();
// ADC Control register set-up
HAL_ADC_WRITE32(REG_ADC_CONTROL,
BIT_CTRL_ADC_COMP_ONLY(ADC_FEATURE_DISABLED) // compare mode only enable (without FIFO enable)
| BIT_CTRL_ADC_ONESHOT(ADC_FEATURE_DISABLED) // one-shot mode enable
| BIT_CTRL_ADC_OVERWRITE(ADC_FEATURE_DISABLED) // overwrite mode enable
| BIT_CTRL_ADC_ENDIAN(ADC_DATA_ENDIAN_LITTLE) // endian selection
| BIT_CTRL_ADC_BURST_SIZE(8) // DMA operation threshold
| BIT_CTRL_ADC_THRESHOLD(8) // one shot mode threshold
| BIT_CTRL_ADC_DBG_SEL(ADC_DBG_SEL_DISABLE));
#if 0
/* ADC compare value and compare method setting*/
switch (adc_idx)
{
case ADC0_SEL:
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L,
(HAL_ADC_READ32(REG_ADC_COMP_VALUE_L)
& (~(BIT_ADC_COMP_TH_0(0xFFFF))))
| BIT_CTRL_ADC_COMP_TH_0(0) // ADC compare mode threshold
);
break;
case ADC1_SEL:
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L,
(HAL_ADC_READ32(REG_ADC_COMP_VALUE_L)
& (~(BIT_ADC_COMP_TH_1(0xFFFF))))
| BIT_CTRL_ADC_COMP_TH_1(0) // ADC compare mode threshold
);
break;
case ADC2_SEL:
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H,
(HAL_ADC_READ32(REG_ADC_COMP_VALUE_H)
& (~(BIT_ADC_COMP_TH_2(0xFFFF))))
| BIT_CTRL_ADC_COMP_TH_2(0) // ADC compare mode threshold
);
break;
case ADC3_SEL:
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H,
(HAL_ADC_READ32(REG_ADC_COMP_VALUE_H)
& (~(BIT_ADC_COMP_TH_3(0xFFFF))))
| BIT_CTRL_ADC_COMP_TH_3(0) // ADC compare mode threshold
);
break;
}
/* ADC compare mode setting */
HAL_ADC_WRITE32(REG_ADC_COMP_SET,
HAL_ADC_READ32(REG_ADC_COMP_SET)
& (~(1 << adc_idx))); // compare mode control : less than the compare threshold
#endif
// ADC audio mode set-up
// ADC enable manually setting
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, HAL_ADC_READ32(REG_ADC_ANAPAR_AD0)
// & (~(BIT_ADC_AUDIO_EN)))
// & (~(BIT_ADC_EN_MANUAL))
| BIT_ADC_AUDIO_EN // ADC audio mode enable
| BIT_ADC_EN_MANUAL // ADC enable manually
);
// ADC analog parameter 0
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, (HAL_ADC_READ32(REG_ADC_ANAPAR_AD0)
// & (~BIT14) //ADC Input is internal?
| (BIT14))
& (~(BIT3|BIT2)));
// ADC analog parameter 1
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, (HAL_ADC_READ32(REG_ADC_ANAPAR_AD1) & (~BIT1)) | (BIT2|BIT0));
// ADC analog parameter 2
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD2, 0x67884400);
// ADC analog parameter 3
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD3, 0x77780039);
// ADC analog parameter 4
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD4, 0x0004d501);
// ADC analog parameter 5
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD5, 0x1E010800);
#ifdef CONFIG_SOC_PS_MODULE
ADCEnablePS();
#endif
}
void ADCDeInit(void)
{
#ifdef CONFIG_SOC_PS_MODULE
REG_POWER_STATE adcPwrState;
uint8_t HwState;
adcPwrState.FuncIdx = ADC0;
QueryRegPwrState(adcPwrState.FuncIdx, &(adcPwrState.PwrState), &HwState);
// if the power state isn't ACT, then switch the power state back to ACT first
if ((adcPwrState.PwrState != ACT) && (adcPwrState.PwrState != INACT))
{
ADCEnablePS();
QueryRegPwrState(adcPwrState.FuncIdx, &(adcPwrState.PwrState), &HwState);
}
if (adcPwrState.PwrState == ACT)
{
adcPwrState.PwrState = INACT;
RegPowerState(adcPwrState);
}
#endif
// Turn on DAC active clock
ACTCK_ADC_CCTRL(OFF);
// Enable DAC1 module
ADC0_FCTRL(OFF);
// To release DAC delta sigma clock gating
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2) & (~(BIT25)));
}

23
RTLGDB/Project/driver/adc_drv.h Normal file
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/*
* Simple ADC DRV (adc_drv.h)
*
* Created on: 19 июн. 2017 г.
* Author: pvvx
*/
#ifndef _DRIVER_ADC_DRV_H_
#define _DRIVER_ADC_DRV_H_
#include "rtl8195a.h"
#include "rtl8195a_adc.h"
void ADCIrqInit(IRQ_FUN IrqFunc, uint32_t IrqData, uint32_t intr_enable); // intr_enable = bits: REG_ADC_INTR_EN - BIT_ADC_FIFO_RD_ERROR_EN | BIT_ADC_FIFO_RD_REQ_EN | BIT_ADC_FIFO_FULL_EN ...
void ADCIrqDeInit(void);
void ADCInit(ADC_MODULE_SEL adc_idx); // RTL8711AM: adc_idx = ADC2_SEL = 2
void ADCDeInit(void);
void ADCEnable(void); // ADC Start
void ADCDisable(void); // ADC Stop
#endif /* _DRIVER_ADC_DRV_H_ */

570
RTLGDB/Project/driver/i2c_drv.c Normal file
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/*
* i2c_drv.c
*
* Created on: 02/05/2017.
* Author: pvvx
*/
#include "driver/i2c_drv.h"
#include "rtl_lib.h"
#if CONFIG_I2C_EN
#include "pinmap.h"
typedef struct {
unsigned char sda;
unsigned char scl;
unsigned char sel;
unsigned char id;
} PinMapI2C;
#define I2C_SEL(idx, ps) ((idx<<4) | ps)
static const PinMapI2C PinMap_I2C[] = {
// sda, scl, sel, id
// I2C0
{PD_4, PD_5, I2C_SEL(0, S0), I2C0},
{PH_1, PH_0, I2C_SEL(0, S1), I2C0},
{PC_8, PC_9, I2C_SEL(0, S2), I2C0},
{PE_7, PE_6, I2C_SEL(0, S3), I2C0},
// I2C1
{PC_4, PC_5, I2C_SEL(1, S0), I2C1},
{PH_3, PH_2, I2C_SEL(1, S1), I2C1},
{PD_7, PD_6, I2C_SEL(1, S2), I2C1},
// I2C2
{PB_7, PB_6, I2C_SEL(2, S0), I2C2},
{PE_1, PE_0, I2C_SEL(2, S1), I2C2},
{PC_7, PC_6, I2C_SEL(2, S2), I2C2},
// I2C3
{PB_3, PB_2, I2C_SEL(3, S0), I2C3},
{PE_3, PE_2, I2C_SEL(3, S1), I2C3},
{PE_5, PE_4, I2C_SEL(3, S2), I2C3},
{PD_9, PD_8, I2C_SEL(3, S3), I2C3},
{0xff, 0xff, 0, 0}
};
static void * i2c_base_reg[4] = {
(void *)I2C0_REG_BASE,
(void *)I2C1_REG_BASE,
(void *)I2C2_REG_BASE,
(void *)I2C3_REG_BASE
};
#if 1
#define test_printf(...)
#define i2c_dump_regs(p)
#else
#define test_printf rtl_printf
static int i2c_dump_regs(i2c_drv_t *pi2c)
{
uint32 *ptr = pi2c->base_regs;
test_printf("%s:", __func__);
for(int i = 0; i < (0xA0>>2); i++) {
if(!(i%4)) {
test_printf("\n%08x:", &ptr[i]);
}
test_printf("\t%08x", ptr[i]);
}
test_printf("\n");
}
#endif
#define i2c_reg(r) *((volatile uint32 *)(pi2c->base_regs + r))
// flg =0 write, =1 Read
static int i2c_ready(i2c_drv_t *pi2c, unsigned char flg)
{
test_printf("%s:\n", __func__);
// Test enable i2c
if(!(i2c_reg(REG_DW_I2C_IC_ENABLE) & BIT_IC_ENABLE)) {
error_printf("I2C%d disable!\n", pi2c->idx);
pi2c->status = DRV_I2C_IC_OFF;
return DRV_I2C_IC_OFF;
}
// Wait Receive FIFO is empty & Transmit FIFO Completely Empty
int poll_count = DRV_I2C_POOL_TIMEOUT;
do {
if(i2c_reg(REG_DW_I2C_IC_RAW_INTR_STAT) & BIT_IC_RAW_INTR_STAT_TX_ABRT) {
error_printf("I2C%d Abort!\n", pi2c->idx);
// Clear abort status.
(volatile uint32)i2c_reg(REG_DW_I2C_IC_CLR_TX_ABRT);
// Be sure that all interrupts flag are cleared.
// i2c_reg(REG_DW_I2C_IC_CLR_INTR);
pi2c->status = DRV_I2C_ABORT;
return DRV_I2C_ABORT;
}
if(flg) {
// Receive FIFO ready ?
if(i2c_reg(REG_DW_I2C_IC_STATUS) & (BIT_IC_STATUS_RFNE | BIT_IC_STATUS_RFF)) {
// pi2c->status = DRV_I2C_IC_ENABLE;
return DRV_I2C_OK;
}
}
else {
// Transmit FIFO is not full ?
if(i2c_reg(REG_DW_I2C_IC_STATUS) & BIT_IC_STATUS_TFNF) {
// pi2c->status = DRV_I2C_IC_ENABLE;
return DRV_I2C_OK;
}
}
} while(poll_count--);
error_printf("I2C%d Timeout!\n", pi2c->idx);
pi2c->status = DRV_I2C_TIMEOUT;
return DRV_I2C_TIMEOUT;
}
int _i2c_break(i2c_drv_t *pi2c)
{
test_printf("%s\n", __func__);
// i2c_reg(REG_DW_I2C_IC_CLR_INTR);
// ABORT operation
int poll_count = DRV_I2C_POOL_TIMEOUT;
i2c_reg(REG_DW_I2C_IC_ENABLE) |= 2;
// Wait until controller is disabled.
while(i2c_reg(REG_DW_I2C_IC_ENABLE) & 2) {
if(poll_count-- <= 0) {
error_printf("Error abort i2c%d\n", pi2c->idx);
pi2c->status = DRV_I2C_TIMEOUT;
return DRV_I2C_TIMEOUT;
};
};
pi2c->status = DRV_I2C_OFF;
// All interrupts flag are cleared.
(volatile uint32)i2c_reg(REG_DW_I2C_IC_CLR_INTR);
return DRV_I2C_OK;
}
/* (!) вызывать после _i2c_init */
int _i2c_set_speed(i2c_drv_t *pi2c, uint32 clk_hz)
{
test_printf("%s:\n", __func__);
if(clk_hz < 10000 || clk_hz > HalGetCpuClk()/16) {
error_printf("I2C%d Error clk!\n", pi2c->idx);
return DRV_I2C_ERR;
}
uint32 tmp;
uint32 CpuClkTmp = HalGetCpuClk()/clk_hz;
switch(pi2c->mode) {
case I2C_SS_MODE:
// Standard Speed Clock SCL High Count
tmp = (CpuClkTmp * I2C_SS_MIN_SCL_HTIME)/(I2C_SS_MIN_SCL_HTIME + I2C_SS_MIN_SCL_LTIME);
i2c_reg(REG_DW_I2C_IC_SS_SCL_HCNT) = BIT_CTRL_IC_SS_SCL_HCNT(tmp);
// Standard Speed Clock SCL Low Count
tmp = (CpuClkTmp * I2C_SS_MIN_SCL_LTIME)/(I2C_SS_MIN_SCL_HTIME + I2C_SS_MIN_SCL_LTIME);
i2c_reg(REG_DW_I2C_IC_SS_SCL_LCNT) = BIT_CTRL_IC_SS_SCL_LCNT(tmp);
break;
case I2C_HS_MODE:
// Standard Speed Clock SCL High Count
i2c_reg(REG_DW_I2C_IC_SS_SCL_HCNT) = BIT_CTRL_IC_SS_SCL_HCNT(400);
// Standard Speed Clock SCL Low Count
i2c_reg(REG_DW_I2C_IC_SS_SCL_LCNT) = BIT_CTRL_IC_SS_SCL_LCNT(470);
// Fast Speed Clock SCL High Count
i2c_reg(REG_DW_I2C_IC_FS_SCL_HCNT) = BIT_CTRL_IC_FS_SCL_HCNT(85);
// Fast Speed I2C Clock SCL Low Count
i2c_reg(REG_DW_I2C_IC_FS_SCL_LCNT) = BIT_CTRL_IC_FS_SCL_LCNT(105);
// High Speed I2C Clock SCL High Count
tmp = (CpuClkTmp * I2C_HS_MIN_SCL_HTIME_100)/(I2C_HS_MIN_SCL_HTIME_100 + I2C_HS_MIN_SCL_LTIME_100);
if (tmp > 8) tmp -= 3;
i2c_reg(REG_DW_I2C_IC_HS_SCL_HCNT) = BIT_CTRL_IC_HS_SCL_HCNT(tmp);
// High Speed I2C Clock SCL Low Count
tmp = (CpuClkTmp * I2C_HS_MIN_SCL_LTIME_100)/(I2C_HS_MIN_SCL_HTIME_100 + I2C_HS_MIN_SCL_LTIME_100);
if (tmp > 6) tmp -= 6;
i2c_reg(REG_DW_I2C_IC_HS_SCL_LCNT) = BIT_CTRL_IC_FS_SCL_LCNT(tmp);
break;
// case I2C_FS_MODE:
default:
pi2c->mode = I2C_FS_MODE;
// Fast Speed Clock SCL High Count
tmp = (CpuClkTmp * I2C_FS_MIN_SCL_HTIME)/(I2C_FS_MIN_SCL_HTIME + I2C_FS_MIN_SCL_LTIME);
if (tmp > 4) tmp -= 4;// this part is according to the fine-tune result
i2c_reg(REG_DW_I2C_IC_FS_SCL_HCNT) = BIT_CTRL_IC_FS_SCL_HCNT(tmp);
// Fast Speed I2C Clock SCL Low Count
tmp = (CpuClkTmp * I2C_FS_MIN_SCL_LTIME)/(I2C_FS_MIN_SCL_HTIME + I2C_FS_MIN_SCL_LTIME);
if (tmp > 3) tmp -= 3; // this part is according to the fine-tune result
i2c_reg(REG_DW_I2C_IC_FS_SCL_LCNT) = BIT_CTRL_IC_FS_SCL_LCNT(tmp);
}
return DRV_I2C_OK;
}
static int i2c_disable(i2c_drv_t *pi2c)
{
test_printf("%s:\n", __func__);
pi2c->status = DRV_I2C_IC_OFF;
if(i2c_reg(REG_DW_I2C_IC_ENABLE_STATUS) & BIT_IC_ENABLE_STATUS_IC_EN) {
test_printf("I2C%d Already disable!\n", pi2c->idx);
return DRV_I2C_OK;
}
// Disable controller.
int poll_count = DRV_I2C_POOL_TIMEOUT;
i2c_reg(REG_DW_I2C_IC_ENABLE) &= ~BIT_IC_ENABLE;
// Wait until controller is disabled.
while(i2c_reg(REG_DW_I2C_IC_ENABLE_STATUS) & BIT_IC_ENABLE_STATUS_IC_EN) {
if(poll_count-- <= 0) {
error_printf("I2C%d Error disable!\n", pi2c->idx);
pi2c->status = DRV_I2C_TIMEOUT;
return DRV_I2C_TIMEOUT;
};
};
return DRV_I2C_OK;
}
static int i2c_enable(i2c_drv_t *pi2c)
{
test_printf("%s:\n", __func__);
int poll_count = DRV_I2C_POOL_TIMEOUT;
if(!(i2c_reg(REG_DW_I2C_IC_ENABLE_STATUS) & BIT_IC_ENABLE_STATUS_IC_EN)) {
// Enable controller.
i2c_reg(REG_DW_I2C_IC_ENABLE) = BIT_IC_ENABLE;
// Wait until controller is enabled
while(!(i2c_reg(REG_DW_I2C_IC_ENABLE_STATUS) & BIT_IC_ENABLE_STATUS_IC_EN)) {
if(poll_count-- <= 0) {
error_printf("I2C%d Error enable\n", pi2c->idx);
pi2c->status = DRV_I2C_TIMEOUT;
return DRV_I2C_TIMEOUT;
};
};
};
// Be sure that all interrupts flag are cleared.
(volatile uint32)i2c_reg(REG_DW_I2C_IC_CLR_INTR);
pi2c->status = DRV_I2C_IC_ENABLE;
return DRV_I2C_OK;
}
// IC On & Enable CLK
static void _i2c_ic_on(i2c_drv_t *pi2c)
{
test_printf("%s:\n", __func__);
uint32 tmp = 1 << (pi2c->idx << 1);
HAL_PERI_ON_WRITE32(REG_PESOC_PERI_CLK_CTRL1,
HAL_PERI_ON_READ32(REG_PESOC_PERI_CLK_CTRL1) | tmp);
HAL_PERI_ON_WRITE32(REG_PESOC_PERI_CLK_CTRL1,
HAL_PERI_ON_READ32(REG_PESOC_PERI_CLK_CTRL1) | (tmp << 1));
tmp = BIT_PERI_I2C0_EN << pi2c->idx;
HAL_PERI_ON_WRITE32(REG_SOC_PERI_FUNC0_EN,
HAL_PERI_ON_READ32(REG_SOC_PERI_FUNC0_EN) & (~tmp));
HAL_PERI_ON_WRITE32(REG_SOC_PERI_FUNC0_EN,
HAL_PERI_ON_READ32(REG_SOC_PERI_FUNC0_EN) | tmp);
tmp = HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_SEL);
tmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_CLK_SEL, tmp);
HalPinCtrlRtl8195A(I2C0 + pi2c->idx, pi2c->io_sel, 1);
}
// IC Off & Disable CLK
void _i2c_ic_off(i2c_drv_t *pi2c)
{
test_printf("%s:\n", __func__);
if(pi2c->status) {
// mask all interrupts
i2c_reg(REG_DW_I2C_IC_INTR_MASK) = 0;
// Disable (Abort I2C Controller)
_i2c_break(pi2c);
i2c_disable(pi2c);
uint32 mask = BIT_PERI_I2C0_EN << pi2c->idx;
HAL_PERI_ON_WRITE32(REG_SOC_PERI_FUNC0_EN,
HAL_PERI_ON_READ32(REG_SOC_PERI_FUNC0_EN) & (~mask));
HalPinCtrlRtl8195A(I2C0 + pi2c->idx, pi2c->io_sel, 0);
#ifdef CONFIG_SOC_PS_MODULE
REG_POWER_STATE i2cPwrState;
// To register a new peripheral device power state
i2cPwrState.FuncIdx = I2C0 + pi2c->idx;
i2cPwrState.PwrState = INACT;
RegPowerState(i2cPwrState);
#endif
pi2c->status = DRV_I2C_OFF;
}
}
/* (!) вызывать до _i2c_init, если параметрв драйвера не заданы в i2c_drv_t */
int _i2c_setup(i2c_drv_t *pi2c, PinName sda, PinName scl, unsigned char mode)
{
test_printf("%s:\n", __func__);
if(mode < DRV_I2C_SS_MODE || mode > DRV_I2C_HS_MODE) {
error_printf("I2C Error mode!\n");
return DRV_I2C_ERR;
}
// Pins -> index
PinMapI2C *p = (PinMapI2C *)PinMap_I2C;
while(p->sda != 0xFF) {
if(p->sda == sda && p->scl == scl) {
pi2c->io_sel = RTL_GET_PERI_SEL(p->sel);
pi2c->idx = RTL_GET_PERI_IDX(p->sel);
pi2c->mode = mode;
return DRV_I2C_OK;
}
p++;
}
error_printf("I2C Error pins!\n");
return DRV_I2C_ERR;
}
/* (!) Использует заполненную структуру i2c_drv_t */
int _i2c_init(i2c_drv_t *pi2c)
{
test_printf("%s:\n", __func__);
// Set base address regs i2c
pi2c->base_regs = i2c_base_reg[pi2c->idx];
// IC On & Enable CLK
if(pi2c->status == DRV_I2C_OFF) _i2c_ic_on(pi2c);
// mask all interrupts
i2c_reg(REG_DW_I2C_IC_INTR_MASK) = 0;
// disable i2c
if(i2c_disable(pi2c)) return pi2c->status;
// Set Control Register:
// bit0: master enabled,
// bit1..2: fast mode (400 kbit/s), ...
// bit2: Slave Addressing Mode 7-bit
// bit4: Master Addressing Mode 7-bit
// bit5: Restart disable
// bit6: Slave Mode Disable
// bit7: STOP_DET_IFADDRESSED
// bit8: TX_EMPTY_CTRL
// bit9: RX_FIFO_FULL_HLD_CTRL
// Set MASTER_MODE
i2c_reg(REG_DW_I2C_IC_CON) =
BIT_CTRL_IC_CON_MASTER_MODE(1)
| BIT_IC_CON_SPEED(pi2c->mode)
| BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(0)
| BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(0)
| BIT_CTRL_IC_CON_IC_RESTART_EN(1)
| BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(1);
// Master Target Address
// i2c_reg(REG_DW_I2C_IC_TAR) = 0x40;
// Slave Address
// i2c_reg(REG_DW_I2C_IC_SAR) = 0x55;
// High Speed Master ID (00001xxx) bit0..2
// i2c_reg(REG_DW_I2C_IC_HS_MADDR) = BIT_CTRL_IC_HS_MADDR(0x4);
// Standard Speed Clock SCL High Count (100kHz)
i2c_reg(REG_DW_I2C_IC_SS_SCL_HCNT) = BIT_CTRL_IC_SS_SCL_HCNT(400);
// Standard Speed Clock SCL Low Count (100kHz)
i2c_reg(REG_DW_I2C_IC_SS_SCL_LCNT) = BIT_CTRL_IC_SS_SCL_LCNT(470);
// Fast Speed Clock SCL High Count (400kHz)
i2c_reg(REG_DW_I2C_IC_FS_SCL_HCNT) = BIT_CTRL_IC_FS_SCL_HCNT(80);
// Fast Speed I2C Clock SCL Low Count (400kHz)
i2c_reg(REG_DW_I2C_IC_FS_SCL_LCNT) = BIT_CTRL_IC_FS_SCL_LCNT(100);
// High Speed I2C Clock SCL High Count (1MHz)
i2c_reg(REG_DW_I2C_IC_HS_SCL_HCNT) = BIT_CTRL_IC_HS_SCL_HCNT(30);
// High Speed I2C Clock SCL Low Count (1MHz)
i2c_reg(REG_DW_I2C_IC_HS_SCL_LCNT) = BIT_CTRL_IC_FS_SCL_LCNT(40);
// SDA Hold (IC_CLK period, when I2C controller acts as a transmitter/receiver)
i2c_reg(REG_DW_I2C_IC_SDA_HOLD) = BIT_CTRL_IC_SDA_HOLD(10);
// General Call Ack
i2c_reg(REG_DW_I2C_IC_ACK_GENERAL_CALL) = BIT_CTRL_IC_ACK_GENERAL_CALL(1);
// Receive FIFO Threshold Level
// i2c_reg(REG_DW_I2C_IC_RX_TL) = 0x0;
// Transmit FIFO Threshold Level
// i2c_reg(REG_DW_I2C_IC_TX_TL) = 0x0;
// Transmit Abort Source
// i2c_reg(REG_DW_I2C_IC_TX_ABRT_SOURCE) = 0x0;
// DMA Transmit Data Level Register
// i2c_reg(REG_DW_I2C_IC_DMA_TDLR) = 0x09;
#ifdef CONFIG_SOC_PS_MODULE
REG_POWER_STATE i2cPwrState;
// To register a new peripheral device power state
i2cPwrState.FuncIdx = I2C0 + pi2c->idx;
i2cPwrState.PwrState = ACT;
RegPowerState(i2cPwrState);
#endif
i2c_dump_regs(pi2c);
// pi2c->status = DRV_I2C_IC_OFF;
return DRV_I2C_OK;
}
int _i2c_write(i2c_drv_t *pi2c, uint32 address, const char *data, int length, int stop)
{
test_printf("%s: [%d]%d\n", __func__, length, stop);
uint8_t *d = (uint8_t *)data;
// Write slave address to TAR.
// bit12: = 1 - 10-bit addressing mode when acting as a master
// bit11: = 1 - Special Command Enable
// bit10: = 1 - Special Command Type START BYTE
i2c_reg(REG_DW_I2C_IC_TAR) = address;
// Enable controller
if(i2c_enable(pi2c)) return pi2c->status;
while (length--) {
// Transmit FIFO is not full
if(i2c_ready(pi2c, 0)) return pi2c->status; // BIT_IC_STATUS_TFNF
// Fill IC_DATA_CMD[7:0] with the data.
// Send stop after last byte ?
if(length == 0 && stop) i2c_reg(REG_DW_I2C_IC_DATA_CMD) = *d | BIT_IC_DATA_CMD_STOP;
else i2c_reg(REG_DW_I2C_IC_DATA_CMD) = *d;
d++;
}
// Disable controller.
if(stop) {
if(i2c_disable(pi2c)) return pi2c->status;
}
return DRV_I2C_OK;
}
int _i2c_read(i2c_drv_t *pi2c, uint32 address, const char *data, int length, int stop)
{
test_printf("%s: [%d]%d\n", __func__, length, stop);
uint8_t *d = (uint8_t *)data;
int len = length;
// Write slave address to TAR.
// bit12: = 1 - 10-bit addressing mode when acting as a master
// bit11: = 1 - Special Command Enable
// bit10: = 1 - Special Command Type START BYTE
i2c_reg(REG_DW_I2C_IC_TAR) = address;
// Enable controller.
if(i2c_enable(pi2c)) return pi2c->status;
while (len--) {
// Transmit FIFO is not full
if(i2c_ready(pi2c, 0)) return pi2c->status; // BIT_IC_STATUS_TFE
// Send stop after last byte ?
if (len == 0 && stop) {
// bit10: = 1 - Restart Bit Control
// bit9: = 1 - Stop Bit Control
// bit8: = 1 - Command read / = 0 Command write
i2c_reg(REG_DW_I2C_IC_DATA_CMD) = BIT_IC_DATA_CMD_CMD | BIT_IC_DATA_CMD_STOP;
} else {
// Read command -IC_DATA_CMD[8] = 1.
i2c_reg(REG_DW_I2C_IC_DATA_CMD) = BIT_IC_DATA_CMD_CMD;
}
// Receive FIFO ready?
if(i2c_reg(REG_DW_I2C_IC_STATUS) & (BIT_IC_STATUS_RFNE | BIT_IC_STATUS_RFF)) {
// IC_DATA_CMD[7:0] contains received data.
if(length) {
*d++ = i2c_reg(REG_DW_I2C_IC_DATA_CMD);
length--;
}
else (volatile uint32)i2c_reg(REG_DW_I2C_IC_DATA_CMD);
};
}
while(length) {
// Receive FIFO ready?
if(i2c_ready(pi2c, 1)) return pi2c->status; // BIT_IC_STATUS_TFE
// IC_DATA_CMD[7:0] contains received data.
*d++ = i2c_reg(REG_DW_I2C_IC_DATA_CMD);
length--;
};
// Disable controller.
if(stop) {
if(i2c_disable(pi2c)) return pi2c->status;
}
return DRV_I2C_OK;
}
#if defined(USE_I2C_CONSOLE) && USE_I2C_CONSOLE
//extern void dump_bytes(uint32 addr, int size);
extern int print_hex_dump(uint8_t *buf, int len, unsigned char k);
extern uint32 hextoul(uint8 *s);
i2c_drv_t ti2c;
/* I2C Init:
* ati2c i [sda_pin [scl_pin [mode [speed]]]]
* I2C Deinit:
* ati2c d
* I2C Write:
* iati2c W address data1 [data2 ... [data8]...]
* I2C write + stop:
* iati2c w address data1 [data2 ... [data8]...]
* I2C Read:
* ati2c R address count
* I2C read + stop:
* ati2c r address count
*/
static void fATI2C(int argc, char *argv[])
{
i2c_drv_t *pi2c = &ti2c;
uint8 buf[32];
if(argc > 1) {
if(argv[1][0] == 'i') {
//
if(!pi2c->status) {
uint8 sda = 0;
uint8 scl = 0;
uint8 mode = 0;
uint32 speed = 0;
if(argc > 2) sda = hextoul(argv[2]);
else if(argc > 3) scl = hextoul(argv[3]);
else if(argc > 4) mode = hextoul(argv[4]);
else if(argc > 5) speed = hextoul(argv[5]);
if(!sda) sda = PC_4;
if(!scl) scl = PC_5;
if(!mode) mode = DRV_I2C_FS_MODE;
if(!speed) speed = 50000;
if(_i2c_setup(pi2c, sda, scl, mode) == DRV_I2C_OK
&& _i2c_init(pi2c) == DRV_I2C_OK
&& _i2c_set_speed(pi2c, speed) == DRV_I2C_OK) {
rtl_printf("I2C%d Init: %02x %02x %02x %08x\n", pi2c->idx, sda, scl, mode, speed);
};
} else {
rtl_printf("Already init!\n");
return;
};
} else if(argv[1][0] == '?') {
rtl_printf("I2C Init:\n\tati2c i [sda_pin [scl_pin [mode [speed]]]]\n");
rtl_printf("I2C Deinit:\n\tati2c d\n");
rtl_printf("I2C Write:\n\tati2c W address data1 [data2 ... [data8]...]\n");
rtl_printf("I2C write + stop:\n\tati2c w address data1 [data2 ... [data8]...]\n");
rtl_printf("I2C Read:\n\tati2c R address count\n");
rtl_printf("I2C read + stop:\n\tati2c r address count\n");
rtl_printf("I2C get:\n\tati2c g address wrcount wrdata1 [..wrdata6] rdcount\n");
} else {
if(pi2c->status) {
if(argv[1][0] == 'd') {
_i2c_ic_off(pi2c);
rtl_printf("I2C%d DeInit\n", pi2c->idx);
return;
};
int i;
for(i = 0; i + 2 < argc; i++) {
buf[i] = hextoul(argv[i+2]);
};
if(i) {
if(argv[1][0] == 'w' || argv[1][0] == 'W') {
// >ati2c w 40 2
// I2C1 write[1]: 40 02 00
// I2C1 drvStatus = 1
_i2c_write(pi2c, buf[0], &buf[1], i-1, argv[1][0] == 'w');
rtl_printf("I2C%d write[%d]: ", pi2c->idx, i-1);
print_hex_dump(buf, i, ' ');
rtl_printf("\n");
} else if(argv[1][0] == 'r' || argv[1][0] == 'R') {
// >ati2c r 40 2
// I2C1 read[2]: 40 07 d8
// I2C1 drvStatus = 1
i = buf[1];
if(i > sizeof(buf) - 1) i = sizeof(buf) - 1;
_i2c_read(pi2c, buf[0], &buf[1], i, argv[1][0] == 'r');
rtl_printf("I2C%d read[%d]: ", pi2c->idx, i);
print_hex_dump(buf, i+1, ' ');
rtl_printf("\n");
} else if(argv[1][0] == 'g') {
// >ati2c g 5a 1 6 3
// I2C1 get[3]: 5a 5e 3a 6c
// I2C1 drvStatus = 1
if (argc < 5 || buf[1] == 0 || buf[1] > sizeof(buf) - 2) {
rtl_printf("Error command string!\n");
return;
}
if(_i2c_write(pi2c, buf[0], &buf[2], buf[1], 0) >= 0) {
i = buf[buf[1] + 2]; // кол-во байт чтения
if(i == 0 || i > sizeof(buf) - 1) i = sizeof(buf) - 1;
_i2c_read(pi2c, buf[0], &buf[1], i, 1);
rtl_printf("I2C%d get[%d]: ", pi2c->idx, i);
print_hex_dump(buf, i+1, ' ');
}
rtl_printf("\n");
};
};
};
};
};
rtl_printf("I2C%d Status = %d\n", pi2c->idx, pi2c->status);
return;
}
MON_RAM_TAB_SECTION COMMAND_TABLE console_commands_i2c[] = {
{"ATI2C", 0, fATI2C, ": Test I2C, <i>nit, <d>einit, <w/W>rite, <r/R>ead"},
};
#endif // USE_I2C_CONSOLE
#endif // CONFIG_I2C_EN

55
RTLGDB/Project/driver/i2c_drv.h Normal file
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@ -0,0 +1,55 @@
/*
* i2c_drv.h
*
* Created on: 02/05/2017.
* Author: pvvx
*/
#ifndef PROJECT_INC_DRIVER_I2C_DRV_H_
#define PROJECT_INC_DRIVER_I2C_DRV_H_
#include "device.h"
typedef struct _I2C_HND_ {
signed char status; // _i2c_status_e
unsigned char idx; // Номер контроллера I2C
unsigned char io_sel; // Location Index(Pin Mux Selection): S0 -> PC_4, PC_5
unsigned char mode; // _i2c_mode_e, if(I2C_FIXED_SPEED_MODE != 0) user set -> i2c_mode_e
void * base_regs;
} i2c_drv_t, *i2c_drv_p;
typedef enum
{
DRV_I2C_OFF = 0, // IC I2C DeInit
DRV_I2C_OK = 0, // DRV ret Ok
DRV_I2C_IC_OFF = 1, // IC I2C Off
DRV_I2C_IC_ENABLE = 2, // IC I2C On
DRV_I2C_ERR = -1, // DRV ret err
DRV_I2C_ABORT = -1, // IC I2C Abort
DRV_I2C_TIMEOUT = -3 // IC I2C / DRV ret Timeout
} _i2c_status_e;
typedef enum
{
DRV_I2C_SS_MODE = 1, // Standard Mode (100 Kbps)
DRV_I2C_FS_MODE = 2, // Fast Mode (400 Kbps)
DRV_I2C_HS_MODE = 3 // Fast Mode Plus (1 Mbps)
} _i2c_mode_e;
#define DRV_I2C_POOL_TIMEOUT 16384
#define _i2c_deinit(p) _i2c_ic_off(p)
// Setup
int _i2c_setup(i2c_drv_t *pi2c, PinName sda, PinName scl, unsigned char mode); // _i2c_mode_e
int _i2c_set_speed(i2c_drv_t *pi2c, uint32 clk_hz);
// Work
int _i2c_init(i2c_drv_t *pi2c);
int _i2c_write(i2c_drv_t *pi2c, uint32 address, const char *data, int length, int stop);
int _i2c_read(i2c_drv_t *pi2c, uint32 address, const char *data, int length, int stop);
// Utils
int _i2c_break(i2c_drv_t *pi2c);
void _i2c_ic_off(i2c_drv_t *pi2c);
#endif /* PROJECT_INC_DRIVER_I2C_DRV_H_ */