j3d1/RTL00_WEB
1
0
Fork 0
mirror of https://github.com/pvvx/RTL00_WEB.git synced 2024-11-22 14:04:21 +00:00
Code Issues Projects Releases Packages Wiki Activity
RTL00_WEB/USDK/example_sources/uart_clock
History
pvvx 39f77eb92b update
2017-06-21 03:00:20 +03:00
..
src update 2017-06-21 03:00:20 +03:00
readme.txt update 2017-06-21 03:00:20 +03:00

readme.txt 

Example Description

This example describes how to use UART TX to simulate clock source

Required Components:
    Oscilloscope

Connect to PC
 - Connect Ground: connect to GND of oscilloscope
 - Use UART1
	GPIOA_6 as UART1_RX connect NOTHING
	GPIOA_7 as UART1_TX connect to probe of oscilloscope


This example shows: 
1. Clock signal output from UART1_TX to oscilloscope