first commit

flasher/ameba1.cfg

@@ -0,0 +1,124 @@
+# Main file for Ameba1 series Cortex-M3 parts
+#
+# !!!!!!
+#
+
+set CHIPNAME rtl8195a
+set CHIPSERIES ameba1
+
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	error "CHIPNAME not set. Please do not include ameba1.cfg directly."
+}
+
+if { [info exists CHIPSERIES] } {
+	# Validate chip series is supported
+	if { $CHIPSERIES != "ameba1" } {
+		error "Unsupported chip series specified."
+	}
+	set _CHIPSERIES $CHIPSERIES
+} else {
+	error "CHIPSERIES not set. Please do not include ameba1.cfg directly."
+}
+
+if { [info exists CPUTAPID] } {
+	# Allow user override
+	set _CPUTAPID $CPUTAPID
+} else {
+	# Ameba1 use a Cortex M3 core.
+	if { $_CHIPSERIES == "ameba1" } {
+		if { [using_jtag] } {
+			set _CPUTAPID 0x4ba00477
+		} {
+			set _CPUTAPID 0x2ba01477
+		}
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+
+
+# Run with *real slow* clock by default since the
+# boot rom could have been playing with the PLL, so
+# we have no idea what clock the target is running at.
+adapter_khz 1000
+
+# delays on reset lines
+adapter_nsrst_delay 200
+if {[using_jtag]} {
+ jtag_ntrst_delay 200
+}
+
+
+# Ameba1 (Cortex M3 core) support SYSRESETREQ
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {ameba1_init}
+
+# Ameba1 SDRAM enable
+proc ameba1_init { } {
+	# init System
+	mww 0x40000014 0x00000021
+	sleep 10
+	mww	0x40000304 0x1fc00002
+	sleep 10
+	mww 0x40000250 0x00000400
+	sleep 10
+	mww 0x40000340 0x00000000
+	sleep 10
+	mww 0x40000230 0x0000dcc4
+	sleep 10
+	mww 0x40000210 0x00011117
+	sleep 10
+	mww 0x40000210 0x00011157
+	sleep 10
+	mww 0x400002c0 0x00110011
+	sleep 10
+	mww 0x40000320 0xffffffff
+	sleep 10
+	# init SDRAM
+	mww 0x40000040 0x00fcc702
+	sleep 10
+	mdw 0x40000040
+	mww 0x40005224 0x00000001
+	sleep 10
+	mww 0x40005004 0x00000208
+	sleep 10
+	mww 0x40005008 0xffffd000
+	sleep 13
+	mww 0x40005020 0x00000022
+	sleep 13
+	mww 0x40005010 0x09006201
+	sleep 13
+	mww 0x40005014 0x00002611
+	sleep 13
+	mww 0x40005018 0x00068413
+	sleep 13
+	mww 0x4000501c 0x00000042
+	sleep 13
+	mww 0x4000500c 0x700 		;# set Idle
+	sleep 20
+	mww 0x40005000 0x1 			;# start init
+	sleep 100
+	mdw 0x40005000			
+	mww 0x4000500c 0x600		;# enter memory mode
+	sleep 30
+
+	mww 0x40005008 0x00000000	;# 0xf00
+	;# mww 0x40005008 0x00000f00
+	sleep 3
+	mww 0x40000300 0x0006005e	;# 0x5e
+	;# mww 0x40000300 0x0000005e
+	sleep 3
+}