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This commit is contained in:
Victor 2018-04-20 10:53:32 +03:00
parent 8529849a5a
commit d1e4ee31f1
70 changed files with 523 additions and 2274 deletions
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29
USDK/component/soc/realtek/8195a/fwlib/bitband_io.h
View file

@ -13,27 +13,27 @@
/*
* in hal_platform.h
#define BITBAND_REG_BASE 0x40001000
#define GPIO_REG_BASE 0x40001000
*/
/*
* in rtl8195a_gpio.h
*
#define BITBAND_PORTA_DR 0x00 // data register
#define BITBAND_PORTA_DDR 0x04 // data direction
#define BITBAND_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
#define REG_PORTA_DR 0x00 // data register
#define REG_PORTA_DDR 0x04 // data direction
#define REG_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
#define BITBAND_PORTB_DR 0x0c // data register
#define BITBAND_PORTB_DDR 0x10 // data direction
#define BITBAND_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
#define REG_PORTB_DR 0x0c // data register
#define REG_PORTB_DDR 0x10 // data direction
#define REG_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
#define BITBAND_PORTC_DR 0x18 // data register
#define BITBAND_PORTC_DDR 0x1c // data direction
#define BITBAND_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
#define REG_PORTC_DR 0x18 // data register
#define REG_PORTC_DDR 0x1c // data direction
#define REG_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
#define BITBAND_EXT_PORTA 0x50 // GPIO IN read or OUT read back
#define BITBAND_EXT_PORTB 0x54 // GPIO IN read or OUT read back
#define BITBAND_EXT_PORTC 0x58 // GPIO IN read or OUT read back
#define REG_EXT_PORTA 0x50 // GPIO IN read or OUT read back
#define REG_EXT_PORTB 0x54 // GPIO IN read or OUT read back
#define REG_EXT_PORTC 0x58 // GPIO IN read or OUT read back
*/
#define BITBAND_PERI_REF 0x40000000
@ -147,7 +147,8 @@
volatile uint8_t * BitBandAddr(void *addr, uint8_t bit);
volatile uint8_t * BitBandPeriAddr(void *addr, uint8_t bit);
volatile uint8_t * GetOutPinBitBandAddr(PinName pin);
#define GetDirPinBitBandAddr(pin) (GetOutPinBitBandAddr(pin) + 4*32)
volatile uint8_t * GetInPinBitBandAddr(PinName pin);
volatile uint8_t * HardSetPin(PinName pin, HAL_GPIO_PIN_MODE pmode, uint8_t val);
volatile uint8_t * HardSetPin(PinName pin, HAL_GPIO_PIN_MODE pmode, uint8_t val); /* return pointer bit out register */
#endif // _BITBAND_IO_H_

9
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
View file

@ -794,6 +794,15 @@ VOID HalSsiTxFIFOThresholdRtl8195a(VOID *Adaptor, u32 txftl)
HAL_SSI_WRITE32(Index, REG_DW_SSI_TXFTLR, TxftlrValue);
}
VOID HalSsiTModRtl8195a(VOID *Adaptor, SSI_CTRLR0_TMOD tmod)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor = (PHAL_SSI_ADAPTOR) Adaptor;
u8 Index = pHalSsiAdaptor->Index;
/* REG_DW_SSI_CTRLR0 */
u32 Ctrlr0Value = HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0) & BIT_INVC_CTRLR0_TMOD;
Ctrlr0Value |= BIT_CTRLR0_TMOD(pHalSsiAdaptor->TransferMode);
HAL_SSI_WRITE32(Index, REG_DW_SSI_CTRLR0, Ctrlr0Value);
}
HAL_Status
HalSsiIntWriteRtl8195a(

11
USDK/component/soc/realtek/8195a/fwlib/src/bitband_io.c
View file

@ -45,14 +45,15 @@ volatile uint8_t * HardSetPin(PinName pin, HAL_GPIO_PIN_MODE pmode, uint8_t val)
extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
}
if(_pHAL_Gpio_Adapter->Gpio_Func_En == 0) GPIO_FuncOn_8195a();
wait_us(100);
// delayMicroseconds(100);
if(_pHAL_Gpio_Adapter->Gpio_Func_En == 0) {
GPIO_FuncOn_8195a();
HalDelayUs(100); // delayMicroseconds(100); wait_us(100);
}
// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
#if CONFIG_DEBUG_LOG > 3
GpioFunctionChk(ippin, ENABLE);
#endif
GPIO_PullCtrl_8195a(ippin, HAL_GPIO_HIGHZ); // Make the pin pull control default as High-Z
GPIO_PullCtrl_8195a(pin, HAL_GPIO_HIGHZ); // Make the pin pull control default as High-Z
paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_PORTB_DR * (ippin >> 5)), ippin & 0x1f);
*paddr = val; // data register
HAL_GPIO_PIN gpio;
@ -61,7 +62,7 @@ volatile uint8_t * HardSetPin(PinName pin, HAL_GPIO_PIN_MODE pmode, uint8_t val)
HAL_GPIO_Init_8195a(&gpio);
*paddr = val; // data register
// paddr[(GPIO_PORTB_DDR - GPIO_PORTB_DR) * 32] = pmode == DOUT_PUSH_PULL; // data direction
// GPIO_PullCtrl_8195a(ippin, pmode); // set GPIO_PULL_CTRLx
// GPIO_PullCtrl_8195a(pin, pmode); // set GPIO_PULL_CTRLx
// paddr[(GPIO_PORTB_CTRL - GPIO_PORTB_DR) * 32] = 0; // data source control, we should keep it as default: data source from software
}
return paddr;

18
USDK/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_libgloss_retarget.c
View file

@ -2,9 +2,10 @@
* ram_libgloss_retarget.o
* pvvx 2016
*/
#ifdef SWO_DEBUG_OUT_ENA
#include "device.h"
#endif
#include "rtl_bios_data.h"
//-------------------------------------------------------------------------
// Function declarations
@ -86,6 +87,15 @@ char *ram_libgloss_sbrk(int incr) {
return prev_heap_end;
}
#ifdef SWO_DEBUG_OUT_ENA
//----- ram_libgloss_write()
int ram_libgloss_write(int file, const char *ptr, int len) {
int i;
for (i = 0; i < len; ++i)
ITM_SendChar(ptr[i]);
return len;
}
#else
//----- ram_libgloss_write()
int ram_libgloss_write(int file, const char *ptr, int len) {
int i;
@ -93,6 +103,7 @@ int ram_libgloss_write(int file, const char *ptr, int len) {
HalSerialPutcRtl8195a(ptr[i]);
return len;
}
#endif
//----- ram_libgloss_open()
int ram_libgloss_open(char *file, int flags, int mode) {
@ -115,6 +126,9 @@ int ram_libgloss_open(char *file, int flags, int mode) {
//----- init_rom_libgloss_ram_map()
void init_rom_libgloss_ram_map(void) {
#ifdef SWO_DEBUG_OUT_ENA
//#error @TODO: Not init SWO!
#endif
rom_libgloss_ram_map.libgloss_close = ram_libgloss_close;
rom_libgloss_ram_map.libgloss_fstat = ram_libgloss_fstat;
rom_libgloss_ram_map.libgloss_isatty = ram_libgloss_isatty;