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update -Wall

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pvvx 2017-09-06 14:34:28 +03:00
parent af72faa906
commit c98cbe6e00
86 changed files with 523 additions and 352 deletions
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14
USDK/component/soc/realtek/8195a/fwlib/src/bitband_io.c
View file

@ -1,8 +1,12 @@
#include "bitband_io.h"
//#include "rtl8195a_gpio.h"
#define BITBAND_ADDR(a,b) (0x02000000 + (a & 0xF0000000) + (a - (a & 0xF0000000)) * 32 + ((b) * 4)) // Convert address ?
volatile uint8_t * BitBandAddr(void *addr, uint8_t bit) {
return (volatile uint8_t *)(BITBAND_ADDR((u32)addr, bit));
uint32_t ret = BITBAND_ADDR((u32)addr, bit);
return (volatile uint8_t *) ret;
}
volatile uint8_t * BitBandPeriAddr(void *addr, uint8_t bit) {
@ -10,7 +14,7 @@ volatile uint8_t * BitBandPeriAddr(void *addr, uint8_t bit) {
}
volatile uint8_t * GetOutPinBitBandAddr(PinName pin) {
uint32_t paddr = NULL;
volatile uint8_t * paddr = 0;
uint32_t ippin = HAL_GPIO_GetIPPinName_8195a(pin);
if(ippin < 0xff) {
// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
@ -29,6 +33,9 @@ volatile uint8_t * GetInPinBitBandAddr(PinName pin) {
return paddr;
}
extern _LONG_CALL_ u32 GPIO_FuncOn_8195a(VOID);
extern void wait_us(int us);
volatile uint8_t * HardSetPin(PinName pin, HAL_GPIO_PIN_MODE pmode, uint8_t val)
{
volatile uint8_t *paddr = NULL;
@ -39,7 +46,8 @@ volatile uint8_t * HardSetPin(PinName pin, HAL_GPIO_PIN_MODE pmode, uint8_t val)
_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
}
if(_pHAL_Gpio_Adapter->Gpio_Func_En == 0) GPIO_FuncOn_8195a();
delayMicroseconds(100);
wait_us(100);
// delayMicroseconds(100);
// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
#if CONFIG_DEBUG_LOG > 3
GpioFunctionChk(ippin, ENABLE);

2
USDK/component/soc/realtek/8195a/fwlib/src/hal_misc.c
View file

@ -34,7 +34,7 @@ void HalReInitPlatformTimer(void)
TimerAdapter.IrqDis = 1;
TimerAdapter.TimerId = 1;
HalTimerOpInit_Patch(&HalTimerOp);
HAL_TIMER_OP x;
// HAL_TIMER_OP x;
HalTimerOp.HalTimerInit(&TimerAdapter);
HalTimerOp.HalTimerEn(1);
}

2
USDK/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c
View file

@ -1044,7 +1044,7 @@ Sdr_Rand2(
}
*/
extern __attribute__ ((long_call)) unsigned int Rand(void);
HAL_SDRC_TEXT_SECTION
s32
MemTest(

9
USDK/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c
View file

@ -541,7 +541,7 @@ VOID SleepPwrGatted(
u32 Rtemp = 0;
u32 ScaleTemp = 0;
u32 PeriodTemp = 0;
u32 CalTemp = 0;
//Backup CPU CLK
BackupCPUClk();
@ -553,7 +553,7 @@ VOID SleepPwrGatted(
//3 1.1 Set TU timer timescale
//0x4000_0090[21:16] = 6'h1F
//0x4000_0090[15] = 1'b0 => Disable timer
CalTemp = (CLKCal(ANACK) << 16);
u32 CalTemp = (CLKCal(ANACK) << 16);
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL)
& (~((BIT_MASK_SYS_DSTDY_TIM_SCAL << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) | (BIT_MASK_SYS_ANACK_TU_TIME << BIT_SHIFT_SYS_ANACK_TU_TIME))))
| ScaleTemp;
@ -608,7 +608,6 @@ DStandby(
u32 Rtemp = 0;
u32 ScaleTemp = 0;
u32 PeriodTemp = 0;
u32 CalTemp = 0;
//Backup CPU CLK
BackupCPUClk();
@ -621,7 +620,7 @@ DStandby(
//3 1.1 Set TU timer timescale
//0x4000_0090[21:16] = 6'h1F
//0x4000_0090[15] = 1'b0 => Disable timer
CalTemp = (CLKCal(ANACK) << 16);
u32 CalTemp = (CLKCal(ANACK) << 16);
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL)
& (~((BIT_MASK_SYS_DSTDY_TIM_SCAL << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) | (BIT_MASK_SYS_ANACK_TU_TIME << BIT_SHIFT_SYS_ANACK_TU_TIME))))
| ScaleTemp;
@ -679,7 +678,7 @@ DSleep(
u32 UTemp = 0;
u32 MaxTemp = 0;
u32 Reada335 = 0;
u32 Reada335;
//2 Deep Sleep mode:
//3 2.1 Set TU timer timescale