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pvvx 2017-06-28 07:09:45 +03:00
parent b8c699eb1c
commit 3a865fb51d
40 changed files with 293 additions and 463 deletions
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34
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h
View file

@ -45,11 +45,11 @@ IIR[3:0]:
typedef enum {
RU_IIR_MODEM_STATUS = 0, //Clear to send or data set ready or ring indicator or data carrier detect.
RU_IIR_NO_PENDING = 1,
RU_IIR_THR_EMPTY = 2, // TX FIFO level lower than threshold or FIFO empty
RU_IIR_RX_RDY = 4, // RX data ready
RU_IIR_RX_LINE_STATUS = 6, // Overrun/parity/framing errors or break interrupt
RU_IIR_THR_EMPTY = 2, // TX FIFO level lower than threshold or FIFO empty
RU_IIR_RX_RDY = 4, // RX data ready
RU_IIR_RX_LINE_STATUS = 6, // Overrun/parity/framing errors or break interrupt
RU_IIR_BUSY = 7,
RU_IIR_CHAR_TIMEOUT = 12 // timeout: Rx data ready but no read
RU_IIR_CHAR_TIMEOUT = 12 // timeout: Rx data ready but no read
} RUART_INT_ID;
#define RUART_IIR_INT_PEND 0x01
#define RUART_IIR_INT_ID (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0)
@ -57,17 +57,17 @@ typedef enum {
#define RUART_FIFO_CTL_REG_OFF 0x08 //[W]
// Define FIFO Control Register Bits
typedef enum {
RU_FCR_FIFO_EN = BIT0, // FIFO Enable.
RU_FCR_RST_RX = BIT1, // RCVR FIFO Reset, self clear
RU_FCR_RST_TX = BIT2, // XMIT FIFO Reset, self clear
RU_FCR_TX_TRIG_EMP = 0, // TX Empty Trigger: FIFO empty
RU_FCR_TX_TRIG_2CH = BIT4, // TX Empty Trigger: 2 characters in the FIFO
RU_FCR_TX_TRIG_QF = BIT5, // TX Empty Trigger: FIFO 1/4 full
RU_FCR_TX_TRIG_HF = (BIT5|BIT4), // TX Empty Trigger: FIFO 1/2 full
RU_FCR_TX_TRIG_MASK = (BIT5|BIT4), // TX Empty Trigger Bit Mask
RU_FCR_RX_TRIG_1CH = 0, // RCVR Trigger: 1 character in the FIFO
RU_FCR_RX_TRIG_QF = BIT6, // RCVR Trigger: FIFO 1/4 full
RU_FCR_RX_TRIG_HF = BIT7, // RCVR Trigger: FIFO 1/2 full
RU_FCR_FIFO_EN = BIT0, // FIFO Enable.
RU_FCR_RST_RX = BIT1, // RCVR FIFO Reset, self clear
RU_FCR_RST_TX = BIT2, // XMIT FIFO Reset, self clear
RU_FCR_TX_TRIG_EMP = 0, // TX Empty Trigger: FIFO empty
RU_FCR_TX_TRIG_2CH = BIT4, // TX Empty Trigger: 2 characters in the FIFO
RU_FCR_TX_TRIG_QF = BIT5, // TX Empty Trigger: FIFO 1/4 full
RU_FCR_TX_TRIG_HF = (BIT5|BIT4), // TX Empty Trigger: FIFO 1/2 full
RU_FCR_TX_TRIG_MASK = (BIT5|BIT4), // TX Empty Trigger Bit Mask
RU_FCR_RX_TRIG_1CH = 0, // RCVR Trigger: 1 character in the FIFO
RU_FCR_RX_TRIG_QF = BIT6, // RCVR Trigger: FIFO 1/4 full
RU_FCR_RX_TRIG_HF = BIT7, // RCVR Trigger: FIFO 1/2 full
RU_FCR_RX_TRIG_AF = (BIT7|BIT6), // RCVR Trigger: FIFO 2 less than full
RU_FCR_RX_TRIG_MASK = (BIT7|BIT6) // RCVR Trigger bits Mask
} RUART_FIFO_CTRL;
@ -92,7 +92,7 @@ typedef enum {
#define RUART_LINE_CTL_REG_OFF 0x0C
// Define Line Control Register Bits
typedef enum {
RU_LCR_DLS_5B = 0, // Data Length: 5 bits
RU_LCR_DLS_5B = 0, // Data Length: 5 bits
RU_LCR_DLS_6B = BIT0, // Data Length: 6 bits
RU_LCR_DLS_7B = BIT1, // Data Length: 7 bits
RU_LCR_DLS_8B = (BIT1|BIT0), // Data Length: 7 bits
@ -105,7 +105,7 @@ typedef enum {
RU_LCR_PARITY_EVEN = (BIT4|BIT3), // Parity Enable: 1, Even Parity: 1
RU_LCR_BC = BIT6, // Break Control Bit
RU_LCR_DLAB = BIT7 // Divisor Latch Access Bit
RU_LCR_DLAB = BIT7 // Divisor Latch Access Bit
} RUART_LINE_CTRL;
//*BIT6 Break Control Bit (BC)
//*BIT4 Even Parity Select (EPS)

4
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c
View file

@ -18,7 +18,7 @@ HalRuartGetChipVerRtl8195a(VOID)
{
u8 chip_ver;
chip_ver = (HAL_READ32(SYSTEM_CTRL_BASE, 0x01F0) >> 4) & 0x0f;
chip_ver = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSTEM_CFG0) >> 4) & 0x0f; // 0x400001F0 RTL8710AF = 0x41000220
return chip_ver;
}
@ -369,7 +369,7 @@ HalRuartSetBaudRateRtl8195a(
u8 chip_ver;
// get chip version
chip_ver = HalRuartGetChipVerRtl8195a();
chip_ver = HalRuartGetChipVerRtl8195a(); // RTL8710AF = 2
#endif
if (pHalRuartAdapter->WordLen == RUART_WLS_8BITS) {